diff options
Diffstat (limited to 'tests/quick')
78 files changed, 3633 insertions, 5026 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini index 08fd1ccfb..9a2e4ebac 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini @@ -287,7 +287,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.tsunami.pciconfig.pio master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma @@ -349,9 +349,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port[0] +master=system.bridge.slave system.physmem.port slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] @@ -406,7 +406,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout index 86d337feb..9d0955474 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:04 +gem5 compiled Jul 26 2012 21:20:05 +gem5 started Jul 26 2012 21:40:04 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 97861500 Exiting @ tick 1870335522500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt index 046013e55..98f92d27e 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.870336 # Nu sim_ticks 1870335522500 # Number of ticks simulated final_tick 1870335522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4061827 # Simulator instruction rate (inst/s) -host_op_rate 4061823 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 120292600618 # Simulator tick rate (ticks/s) -host_mem_usage 301032 # Number of bytes of host memory used -host_seconds 15.55 # Real time elapsed on the host +host_inst_rate 3051606 # Simulator instruction rate (inst/s) +host_op_rate 3051604 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90374561583 # Simulator tick rate (ticks/s) +host_mem_usage 305448 # Number of bytes of host memory used +host_seconds 20.70 # Real time elapsed on the host sim_insts 63154034 # Number of instructions simulated sim_ops 63154034 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 761216 # Number of bytes read from this memory @@ -50,9 +50,9 @@ system.physmem.bw_total::cpu1.data 357514 # To system.physmem.bw_total::total 42102084 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 1000626 # number of replacements system.l2c.tagsinuse 65381.922680 # Cycle average of tags in use -system.l2c.total_refs 2464692 # Total number of references to valid blocks. +system.l2c.total_refs 2464737 # Total number of references to valid blocks. system.l2c.sampled_refs 1065768 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.312597 # Average number of references to valid blocks. +system.l2c.avg_refs 2.312639 # Average number of references to valid blocks. system.l2c.warmup_cycle 838081000 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 56158.702580 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.inst 4894.236968 # Average occupied blocks per requestor @@ -66,31 +66,31 @@ system.l2c.occ_percent::cpu1.inst 0.002661 # Av system.l2c.occ_percent::cpu1.data 0.000305 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.997649 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 873086 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 763047 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 763077 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 101896 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 36724 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1774753 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 816766 # number of Writeback hits -system.l2c.Writeback_hits::total 816766 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1.data 36 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 169 # number of UpgradeReq hits +system.l2c.ReadReq_hits::cpu1.data 36734 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1774793 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 816653 # number of Writeback hits +system.l2c.Writeback_hits::total 816653 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 135 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1.data 37 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 172 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 14 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 9 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 23 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 166157 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 14260 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 180417 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 166234 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1.data 14285 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 180519 # number of ReadExReq hits system.l2c.demand_hits::cpu0.inst 873086 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 929204 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 929311 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 101896 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 50984 # number of demand (read+write) hits -system.l2c.demand_hits::total 1955170 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 51019 # number of demand (read+write) hits +system.l2c.demand_hits::total 1955312 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.inst 873086 # number of overall hits -system.l2c.overall_hits::cpu0.data 929204 # number of overall hits +system.l2c.overall_hits::cpu0.data 929311 # number of overall hits system.l2c.overall_hits::cpu1.inst 101896 # number of overall hits -system.l2c.overall_hits::cpu1.data 50984 # number of overall hits -system.l2c.overall_hits::total 1955170 # number of overall hits +system.l2c.overall_hits::cpu1.data 51019 # number of overall hits +system.l2c.overall_hits::total 1955312 # number of overall hits system.l2c.ReadReq_misses::cpu0.inst 11894 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.data 926761 # number of ReadReq misses system.l2c.ReadReq_misses::cpu1.inst 1734 # number of ReadReq misses @@ -116,55 +116,55 @@ system.l2c.overall_misses::cpu1.inst 1734 # nu system.l2c.overall_misses::cpu1.data 10570 # number of overall misses system.l2c.overall_misses::total 1066665 # number of overall misses system.l2c.ReadReq_accesses::cpu0.inst 884980 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 1689808 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 1689838 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 103630 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 37632 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2716050 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 816766 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 816766 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 2575 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 606 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 3181 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 37642 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2716090 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 816653 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 816653 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2577 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 607 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 3184 # number of UpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu0.data 79 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::cpu1.data 109 # number of SCUpgradeReq accesses(hits+misses) system.l2c.SCUpgradeReq_accesses::total 188 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 281863 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 23922 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 305785 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 281940 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 23947 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 305887 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu0.inst 884980 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 1971671 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 1971778 # number of demand (read+write) accesses system.l2c.demand_accesses::cpu1.inst 103630 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 61554 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 3021835 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 61589 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 3021977 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu0.inst 884980 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 1971671 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 1971778 # number of overall (read+write) accesses system.l2c.overall_accesses::cpu1.inst 103630 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 61554 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 3021835 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 61589 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 3021977 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu0.inst 0.013440 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.548442 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.548432 # miss rate for ReadReq accesses system.l2c.ReadReq_miss_rate::cpu1.inst 0.016733 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.024128 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.346568 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.948350 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.940594 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.946872 # miss rate for UpgradeReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.024122 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.346563 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.947614 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.939044 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.945980 # miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.822785 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.917431 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.877660 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.410504 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.403896 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.409987 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.410392 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.403474 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.409851 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.inst 0.013440 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.528723 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.528694 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.016733 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.171719 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.352986 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.171622 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.352969 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.inst 0.013440 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.528723 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.528694 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.016733 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.171719 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.352986 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.171622 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.352969 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -448,8 +448,6 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 95 # number of writebacks -system.cpu0.icache.writebacks::total 95 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 1978686 # number of replacements system.cpu0.dcache.tagsinuse 507.129778 # Cycle average of tags in use @@ -687,8 +685,6 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 18 # number of writebacks -system.cpu1.icache.writebacks::total 18 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 62044 # number of replacements system.cpu1.dcache.tagsinuse 421.562730 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini index 3950ce4a4..29a31b8cf 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini @@ -190,7 +190,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=system.tsunami.pciconfig.pio master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma @@ -252,9 +252,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port[0] +master=system.bridge.slave system.physmem.port slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] @@ -309,7 +309,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout index d842316f6..ed03a48be 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:05:18 -gem5 started Jun 28 2012 22:10:03 +gem5 compiled Jul 26 2012 21:20:05 +gem5 started Jul 26 2012 21:39:53 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 1829332258000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt index e2a65cb45..179af31f5 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 1.829332 # Nu sim_ticks 1829332258000 # Number of ticks simulated final_tick 1829332258000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 4017982 # Simulator instruction rate (inst/s) -host_op_rate 4017978 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 122425314574 # Simulator tick rate (ticks/s) -host_mem_usage 297960 # Number of bytes of host memory used -host_seconds 14.94 # Real time elapsed on the host +host_inst_rate 2962809 # Simulator instruction rate (inst/s) +host_op_rate 2962806 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 90274916526 # Simulator tick rate (ticks/s) +host_mem_usage 302384 # Number of bytes of host memory used +host_seconds 20.26 # Real time elapsed on the host sim_insts 60038305 # Number of instructions simulated sim_ops 60038305 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 857984 # Number of bytes read from this memory @@ -40,9 +40,9 @@ system.physmem.bw_total::tsunami.ide 1449867 # To system.physmem.bw_total::total 42507908 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 992301 # number of replacements system.l2c.tagsinuse 65424.374305 # Cycle average of tags in use -system.l2c.total_refs 2433195 # Total number of references to valid blocks. +system.l2c.total_refs 2433239 # Total number of references to valid blocks. system.l2c.sampled_refs 1057464 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.300972 # Average number of references to valid blocks. +system.l2c.avg_refs 2.301014 # Average number of references to valid blocks. system.l2c.warmup_cycle 614754000 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 56309.122439 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.inst 4867.329747 # Average occupied blocks per requestor @@ -52,20 +52,20 @@ system.l2c.occ_percent::cpu.inst 0.074270 # Av system.l2c.occ_percent::cpu.data 0.064818 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.998297 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu.inst 906797 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 811183 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1717980 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 833599 # number of Writeback hits -system.l2c.Writeback_hits::total 833599 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 1 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187125 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187125 # number of ReadExReq hits +system.l2c.ReadReq_hits::cpu.data 811229 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1718026 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 833491 # number of Writeback hits +system.l2c.Writeback_hits::total 833491 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 187229 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187229 # number of ReadExReq hits system.l2c.demand_hits::cpu.inst 906797 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 998308 # number of demand (read+write) hits -system.l2c.demand_hits::total 1905105 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 998458 # number of demand (read+write) hits +system.l2c.demand_hits::total 1905255 # number of demand (read+write) hits system.l2c.overall_hits::cpu.inst 906797 # number of overall hits -system.l2c.overall_hits::cpu.data 998308 # number of overall hits -system.l2c.overall_hits::total 1905105 # number of overall hits +system.l2c.overall_hits::cpu.data 998458 # number of overall hits +system.l2c.overall_hits::total 1905255 # number of overall hits system.l2c.ReadReq_misses::cpu.inst 13406 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.data 927640 # number of ReadReq misses system.l2c.ReadReq_misses::total 941046 # number of ReadReq misses @@ -80,33 +80,33 @@ system.l2c.overall_misses::cpu.inst 13406 # nu system.l2c.overall_misses::cpu.data 1044757 # number of overall misses system.l2c.overall_misses::total 1058163 # number of overall misses system.l2c.ReadReq_accesses::cpu.inst 920203 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1738823 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2659026 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 833599 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 833599 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 13 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304242 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304242 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1738869 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2659072 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 833491 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 833491 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 16 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 304346 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304346 # number of ReadExReq accesses(hits+misses) system.l2c.demand_accesses::cpu.inst 920203 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 2043065 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2963268 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 2043215 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2963418 # number of demand (read+write) accesses system.l2c.overall_accesses::cpu.inst 920203 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 2043065 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2963268 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 2043215 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2963418 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.014569 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.533487 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.353906 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.923077 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.923077 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.384947 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.384947 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.533473 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.353900 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.750000 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.750000 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.384815 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.384815 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.014569 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.511367 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.357093 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.511330 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.357075 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.014569 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.511367 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.357093 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.511330 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.357075 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,8 +385,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 108 # number of writebacks -system.cpu.icache.writebacks::total 108 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 2042702 # number of replacements system.cpu.dcache.tagsinuse 511.997802 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index b6c3eb879..e9608d5ae 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -343,7 +343,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port[0] +master=system.bridge.slave system.physmem.port slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout index e633d965f..3b87d756d 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout @@ -1,12 +1,13 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:09:26 +gem5 compiled Jul 26 2012 21:20:05 +gem5 started Jul 26 2012 21:40:05 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... info: Launching CPU 1 @ 573593000 -Exiting @ tick 1954209106000 because m5_exit instruction encountered +Exiting @ tick 1954209529000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt index e64aeb301..19b49bfc4 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.954209 # Number of seconds simulated -sim_ticks 1954209106000 # Number of ticks simulated -final_tick 1954209106000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.954210 # Number of seconds simulated +sim_ticks 1954209529000 # Number of ticks simulated +final_tick 1954209529000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1820229 # Simulator instruction rate (inst/s) -host_op_rate 1820228 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 59866957581 # Simulator tick rate (ticks/s) -host_mem_usage 296900 # Number of bytes of host memory used -host_seconds 32.64 # Real time elapsed on the host -sim_insts 59416827 # Number of instructions simulated -sim_ops 59416827 # Number of ops (including micro ops) simulated +host_inst_rate 1320479 # Simulator instruction rate (inst/s) +host_op_rate 1320478 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 43430338961 # Simulator tick rate (ticks/s) +host_mem_usage 301360 # Number of bytes of host memory used +host_seconds 45.00 # Real time elapsed on the host +sim_insts 59416773 # Number of instructions simulated +sim_ops 59416773 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 717056 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 23797184 # Number of bytes read from this memory system.physmem.bytes_read::tsunami.ide 2649344 # Number of bytes read from this memory @@ -31,90 +31,90 @@ system.physmem.num_reads::total 448972 # Nu system.physmem.num_writes::writebacks 121019 # Number of write requests responded to by this memory system.physmem.num_writes::total 121019 # Number of write requests responded to by this memory system.physmem.bw_read::cpu0.inst 366929 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 12177399 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::tsunami.ide 1355712 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 12177396 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::tsunami.ide 1355711 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 74637 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 729077 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14703753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 729076 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14703750 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 366929 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 74637 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 441566 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3963351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3963351 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3963351 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3963350 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3963350 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3963350 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 366929 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 12177399 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::tsunami.ide 1355712 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 12177396 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::tsunami.ide 1355711 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 74637 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 729077 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18667104 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 729076 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18667100 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 342059 # number of replacements -system.l2c.tagsinuse 65268.179703 # Cycle average of tags in use -system.l2c.total_refs 2559285 # Total number of references to valid blocks. -system.l2c.sampled_refs 407065 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.287165 # Average number of references to valid blocks. +system.l2c.tagsinuse 65268.160318 # Cycle average of tags in use +system.l2c.total_refs 2559182 # Total number of references to valid blocks. +system.l2c.sampled_refs 407064 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.286928 # Average number of references to valid blocks. system.l2c.warmup_cycle 7752825000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55637.656104 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3742.496714 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4175.529809 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 1176.827938 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 535.669138 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 55637.634903 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3742.497316 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4175.530834 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 1176.828105 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 535.669160 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.848963 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.057106 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.063714 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.017957 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.008174 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.995913 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 478629 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 342574 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 511941 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 491320 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1824464 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 858732 # number of Writeback hits -system.l2c.Writeback_hits::total 858732 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 137 # number of UpgradeReq hits +system.l2c.ReadReq_hits::cpu0.inst 478624 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 342590 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 511938 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 491329 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1824481 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 858650 # number of Writeback hits +system.l2c.Writeback_hits::total 858650 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 133 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::cpu1.data 95 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 232 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 228 # number of UpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu0.data 22 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 24 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 46 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 101383 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1.data 99295 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 200678 # number of ReadExReq hits -system.l2c.demand_hits::cpu0.inst 478629 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 443957 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 511941 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 590615 # 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number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 465201000 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1379588000 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1452699030 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1.data 729389000 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 2182088030 # number of overall MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0.data 914384000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 465175000 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1379559000 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0.data 1452696030 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 729363000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 2182059030 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.441300 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.441289 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.002459 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.135221 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.949502 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.135220 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.951013 # mshr miss rate for UpgradeReq accesses system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.833625 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.929354 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.930615 # mshr miss rate for UpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.794393 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.785714 # mshr miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.789954 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.500530 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.175208 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.379415 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.500258 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.175175 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.379262 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.456031 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.455961 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.036390 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.167675 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.036388 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.167666 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.inst 0.022873 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.456031 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.455961 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.004432 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.036390 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.167675 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.036388 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.167666 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40018.629730 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40369.942197 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.302647 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40040.372671 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40102.941176 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40050.131062 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.405887 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40037.815126 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40036.625245 # average UpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40223.529412 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average SCUpgradeReq mshr miss latency system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40109.826590 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736274 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40002.736167 # average ReadExReq mshr miss latency system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40001.801546 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575576 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40002.575492 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291203 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40014.291049 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40021.789813 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40014.971542 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40014.971396 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40026.686898 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291203 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40014.291049 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40001.755156 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40021.789813 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40014.971542 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40014.971396 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -345,14 +345,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41707 # number of replacements -system.iocache.tagsinuse 1.261560 # Cycle average of tags in use +system.iocache.tagsinuse 1.261563 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41723 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1747651126000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.261560 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.078847 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.078847 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 1.261563 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.078848 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.078848 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 176 # number of ReadReq misses system.iocache.ReadReq_misses::total 176 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -363,12 +363,12 @@ system.iocache.overall_misses::tsunami.ide 41728 # system.iocache.overall_misses::total 41728 # number of overall misses system.iocache.ReadReq_miss_latency::tsunami.ide 21013998 # number of ReadReq miss cycles system.iocache.ReadReq_miss_latency::total 21013998 # number of ReadReq miss cycles -system.iocache.WriteReq_miss_latency::tsunami.ide 7626020806 # number of WriteReq miss cycles -system.iocache.WriteReq_miss_latency::total 7626020806 # number of WriteReq miss cycles -system.iocache.demand_miss_latency::tsunami.ide 7647034804 # number of demand (read+write) miss cycles -system.iocache.demand_miss_latency::total 7647034804 # number of demand (read+write) miss cycles -system.iocache.overall_miss_latency::tsunami.ide 7647034804 # number of overall miss cycles -system.iocache.overall_miss_latency::total 7647034804 # number of overall miss cycles +system.iocache.WriteReq_miss_latency::tsunami.ide 7626285806 # number of WriteReq miss cycles +system.iocache.WriteReq_miss_latency::total 7626285806 # number of WriteReq miss cycles +system.iocache.demand_miss_latency::tsunami.ide 7647299804 # number of demand (read+write) miss cycles +system.iocache.demand_miss_latency::total 7647299804 # number of demand (read+write) miss cycles +system.iocache.overall_miss_latency::tsunami.ide 7647299804 # number of overall miss cycles +system.iocache.overall_miss_latency::total 7647299804 # number of overall miss cycles system.iocache.ReadReq_accesses::tsunami.ide 176 # number of ReadReq accesses(hits+misses) system.iocache.ReadReq_accesses::total 176 # number of ReadReq accesses(hits+misses) system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses) @@ -387,17 +387,17 @@ system.iocache.overall_miss_rate::tsunami.ide 1 system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses system.iocache.ReadReq_avg_miss_latency::tsunami.ide 119397.715909 # average ReadReq miss latency system.iocache.ReadReq_avg_miss_latency::total 119397.715909 # average ReadReq miss latency -system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183529.572728 # average WriteReq miss latency -system.iocache.WriteReq_avg_miss_latency::total 183529.572728 # average WriteReq miss latency -system.iocache.demand_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency -system.iocache.demand_avg_miss_latency::total 183259.077933 # average overall miss latency -system.iocache.overall_avg_miss_latency::tsunami.ide 183259.077933 # average overall miss latency -system.iocache.overall_avg_miss_latency::total 183259.077933 # average overall miss latency -system.iocache.blocked_cycles::no_mshrs 7245000 # number of cycles access was blocked +system.iocache.WriteReq_avg_miss_latency::tsunami.ide 183535.950279 # average WriteReq miss latency +system.iocache.WriteReq_avg_miss_latency::total 183535.950279 # average WriteReq miss latency +system.iocache.demand_avg_miss_latency::tsunami.ide 183265.428585 # average overall miss latency +system.iocache.demand_avg_miss_latency::total 183265.428585 # average overall miss latency +system.iocache.overall_avg_miss_latency::tsunami.ide 183265.428585 # average overall miss latency +system.iocache.overall_avg_miss_latency::total 183265.428585 # average overall miss latency +system.iocache.blocked_cycles::no_mshrs 7316000 # number of cycles access was blocked system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.iocache.blocked::no_mshrs 7076 # number of cycles access was blocked +system.iocache.blocked::no_mshrs 7050 # number of cycles access was blocked system.iocache.blocked::no_targets 0 # number of cycles access was blocked -system.iocache.avg_blocked_cycles::no_mshrs 1023.883550 # average number of cycles each access was blocked +system.iocache.avg_blocked_cycles::no_mshrs 1037.730496 # average number of cycles each access was blocked system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed @@ -413,12 +413,12 @@ system.iocache.overall_mshr_misses::tsunami.ide 41728 system.iocache.overall_mshr_misses::total 41728 # number of overall MSHR misses system.iocache.ReadReq_mshr_miss_latency::tsunami.ide 11861000 # number of ReadReq MSHR miss cycles system.iocache.ReadReq_mshr_miss_latency::total 11861000 # number of ReadReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5465163000 # number of WriteReq MSHR miss cycles -system.iocache.WriteReq_mshr_miss_latency::total 5465163000 # number of WriteReq MSHR miss cycles -system.iocache.demand_mshr_miss_latency::tsunami.ide 5477024000 # number of demand (read+write) MSHR miss cycles -system.iocache.demand_mshr_miss_latency::total 5477024000 # number of demand (read+write) MSHR miss cycles -system.iocache.overall_mshr_miss_latency::tsunami.ide 5477024000 # number of overall MSHR miss cycles -system.iocache.overall_mshr_miss_latency::total 5477024000 # number of overall MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 5465428000 # number of WriteReq MSHR miss cycles +system.iocache.WriteReq_mshr_miss_latency::total 5465428000 # number of WriteReq MSHR miss cycles +system.iocache.demand_mshr_miss_latency::tsunami.ide 5477289000 # number of demand (read+write) MSHR miss cycles +system.iocache.demand_mshr_miss_latency::total 5477289000 # number of demand (read+write) MSHR miss cycles +system.iocache.overall_mshr_miss_latency::tsunami.ide 5477289000 # number of overall MSHR miss cycles +system.iocache.overall_mshr_miss_latency::total 5477289000 # number of overall MSHR miss cycles system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses @@ -429,12 +429,12 @@ system.iocache.overall_mshr_miss_rate::tsunami.ide 1 system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 67392.045455 # average ReadReq mshr miss latency system.iocache.ReadReq_avg_mshr_miss_latency::total 67392.045455 # average ReadReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131525.871198 # average WriteReq mshr miss latency -system.iocache.WriteReq_avg_mshr_miss_latency::total 131525.871198 # average WriteReq mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency -system.iocache.demand_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131255.368098 # average overall mshr miss latency -system.iocache.overall_avg_mshr_miss_latency::total 131255.368098 # average overall mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 131532.248749 # average WriteReq mshr miss latency +system.iocache.WriteReq_avg_mshr_miss_latency::total 131532.248749 # average WriteReq mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 131261.718750 # average overall mshr miss latency +system.iocache.demand_avg_mshr_miss_latency::total 131261.718750 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 131261.718750 # average overall mshr miss latency +system.iocache.overall_avg_mshr_miss_latency::total 131261.718750 # average overall mshr miss latency system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). @@ -452,22 +452,22 @@ system.cpu0.dtb.fetch_hits 0 # IT system.cpu0.dtb.fetch_misses 0 # ITB misses system.cpu0.dtb.fetch_acv 0 # ITB acv system.cpu0.dtb.fetch_accesses 0 # ITB accesses -system.cpu0.dtb.read_hits 5733478 # DTB read hits +system.cpu0.dtb.read_hits 5733461 # DTB read hits system.cpu0.dtb.read_misses 7687 # DTB read misses system.cpu0.dtb.read_acv 174 # DTB read access violations system.cpu0.dtb.read_accesses 524201 # DTB read accesses -system.cpu0.dtb.write_hits 3961950 # DTB write hits +system.cpu0.dtb.write_hits 3961949 # DTB write hits system.cpu0.dtb.write_misses 798 # DTB write misses system.cpu0.dtb.write_acv 115 # DTB write access violations system.cpu0.dtb.write_accesses 195659 # DTB write accesses -system.cpu0.dtb.data_hits 9695428 # DTB hits +system.cpu0.dtb.data_hits 9695410 # DTB hits system.cpu0.dtb.data_misses 8485 # DTB misses system.cpu0.dtb.data_acv 289 # DTB access violations system.cpu0.dtb.data_accesses 719860 # DTB accesses -system.cpu0.itb.fetch_hits 3214168 # ITB hits +system.cpu0.itb.fetch_hits 3214179 # ITB hits system.cpu0.itb.fetch_misses 3841 # ITB misses system.cpu0.itb.fetch_acv 143 # ITB acv -system.cpu0.itb.fetch_accesses 3218009 # ITB accesses +system.cpu0.itb.fetch_accesses 3218020 # ITB accesses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.read_acv 0 # DTB read access violations @@ -480,55 +480,55 @@ system.cpu0.itb.data_hits 0 # DT system.cpu0.itb.data_misses 0 # DTB misses system.cpu0.itb.data_acv 0 # DTB access violations system.cpu0.itb.data_accesses 0 # DTB accesses -system.cpu0.numCycles 3908418212 # number of cpu cycles simulated +system.cpu0.numCycles 3908419058 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 36160823 # Number of instructions committed -system.cpu0.committedOps 36160823 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33648358 # Number of integer alu accesses +system.cpu0.committedInsts 36160769 # Number of instructions committed +system.cpu0.committedOps 36160769 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33648309 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 143029 # Number of float alu accesses -system.cpu0.num_func_calls 874754 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4239281 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33648358 # number of integer instructions +system.cpu0.num_func_calls 874750 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4239273 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33648309 # number of integer instructions system.cpu0.num_fp_insts 143029 # number of float instructions -system.cpu0.num_int_register_reads 46246578 # number of times the integer registers were read -system.cpu0.num_int_register_writes 25142775 # number of times the integer registers were written +system.cpu0.num_int_register_reads 46246517 # number of times the integer registers were read +system.cpu0.num_int_register_writes 25142738 # number of times the integer registers were written system.cpu0.num_fp_register_reads 70823 # number of times the floating registers were read system.cpu0.num_fp_register_writes 71471 # number of times the floating registers were written -system.cpu0.num_mem_refs 9726012 # number of memory refs -system.cpu0.num_load_insts 5755191 # Number of load instructions -system.cpu0.num_store_insts 3970821 # Number of store instructions -system.cpu0.num_idle_cycles 3741416410.998085 # Number of idle cycles -system.cpu0.num_busy_cycles 167001801.001915 # Number of busy cycles +system.cpu0.num_mem_refs 9725994 # number of memory refs +system.cpu0.num_load_insts 5755174 # Number of load instructions +system.cpu0.num_store_insts 3970820 # Number of store instructions +system.cpu0.num_idle_cycles 3741414636.998085 # Number of idle cycles +system.cpu0.num_busy_cycles 167004421.001915 # Number of busy cycles system.cpu0.not_idle_fraction 0.042729 # Percentage of non-idle cycles system.cpu0.idle_fraction 0.957271 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 4839 # number of quiesce instructions executed -system.cpu0.kern.inst.hwrei 129052 # number of hwrei instructions executed +system.cpu0.kern.inst.hwrei 129053 # number of hwrei instructions executed system.cpu0.kern.ipl_count::0 41012 38.31% 38.31% # number of times we switched to this ipl system.cpu0.kern.ipl_count::21 131 0.12% 38.43% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::22 1971 1.84% 40.28% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::22 1971 1.84% 40.27% # number of times we switched to this ipl system.cpu0.kern.ipl_count::30 17 0.02% 40.29% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::31 63918 59.71% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_count::total 107049 # number of times we switched to this ipl +system.cpu0.kern.ipl_count::31 63919 59.71% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_count::total 107050 # number of times we switched to this ipl system.cpu0.kern.ipl_good::0 40581 48.74% 48.74% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::21 131 0.16% 48.90% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::22 1971 2.37% 51.26% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::30 17 0.02% 51.28% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::31 40564 48.72% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good::total 83264 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_ticks::0 1905787793000 97.52% 97.52% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::21 88207500 0.00% 97.53% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::22 590484500 0.03% 97.56% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::0 1905788612000 97.52% 97.52% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::21 88224500 0.00% 97.53% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::22 590412500 0.03% 97.56% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks::30 12827000 0.00% 97.56% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::31 47728938000 2.44% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks::total 1954208250000 # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::31 47728597000 2.44% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks::total 1954208673000 # number of cycles we spent at this ipl system.cpu0.kern.ipl_used::0 0.989491 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::31 0.634626 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used::total 0.777812 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::31 0.634616 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used::total 0.777805 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.syscall::2 6 2.68% 2.68% # number of syscalls executed system.cpu0.kern.syscall::3 19 8.48% 11.16% # number of syscalls executed system.cpu0.kern.syscall::4 3 1.34% 12.50% # number of syscalls executed @@ -568,7 +568,7 @@ system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.08% # nu system.cpu0.kern.callpal::swpctx 1959 1.72% 1.80% # number of callpals executed system.cpu0.kern.callpal::tbi 44 0.04% 1.84% # number of callpals executed system.cpu0.kern.callpal::wrent 7 0.01% 1.84% # number of callpals executed -system.cpu0.kern.callpal::swpipl 101151 88.59% 90.44% # number of callpals executed +system.cpu0.kern.callpal::swpipl 101152 88.59% 90.44% # number of callpals executed system.cpu0.kern.callpal::rdps 6620 5.80% 96.24% # number of callpals executed system.cpu0.kern.callpal::wrkgp 1 0.00% 96.24% # number of callpals executed system.cpu0.kern.callpal::wrusp 4 0.00% 96.24% # number of callpals executed @@ -577,19 +577,19 @@ system.cpu0.kern.callpal::whami 2 0.00% 96.25% # nu system.cpu0.kern.callpal::rti 3778 3.31% 99.56% # number of callpals executed system.cpu0.kern.callpal::callsys 356 0.31% 99.87% # number of callpals executed system.cpu0.kern.callpal::imb 149 0.13% 100.00% # number of callpals executed -system.cpu0.kern.callpal::total 114173 # number of callpals executed +system.cpu0.kern.callpal::total 114174 # number of callpals executed system.cpu0.kern.mode_switch::kernel 5323 # number of protection mode switches -system.cpu0.kern.mode_switch::user 1230 # number of protection mode switches +system.cpu0.kern.mode_switch::user 1231 # number of protection mode switches system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches -system.cpu0.kern.mode_good::kernel 1229 -system.cpu0.kern.mode_good::user 1230 +system.cpu0.kern.mode_good::kernel 1230 +system.cpu0.kern.mode_good::user 1231 system.cpu0.kern.mode_good::idle 0 -system.cpu0.kern.mode_switch_good::kernel 0.230885 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good::kernel 0.231073 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good::total 0.375248 # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks::kernel 1950524029000 99.81% 99.81% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks::user 3684214000 0.19% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_switch_good::total 0.375496 # fraction of useful protection mode switches +system.cpu0.kern.mode_ticks::kernel 1950522760000 99.81% 99.81% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks::user 3685906000 0.19% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 1960 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA @@ -623,51 +623,51 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu0.icache.replacements 489211 # number of replacements -system.cpu0.icache.tagsinuse 508.795621 # Cycle average of tags in use -system.cpu0.icache.total_refs 35679745 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 489723 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 72.856993 # Average number of references to valid blocks. +system.cpu0.icache.replacements 489206 # number of replacements +system.cpu0.icache.tagsinuse 508.795620 # Cycle average of tags in use +system.cpu0.icache.total_refs 35679696 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 489718 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 72.857636 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 36113258000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 508.795621 # Average occupied blocks per requestor +system.cpu0.icache.occ_blocks::cpu0.inst 508.795620 # Average occupied blocks per requestor system.cpu0.icache.occ_percent::cpu0.inst 0.993741 # Average percentage of cache occupancy system.cpu0.icache.occ_percent::total 0.993741 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 35679745 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 35679745 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 35679745 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 35679745 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 35679745 # number of overall hits -system.cpu0.icache.overall_hits::total 35679745 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 489853 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 489853 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 489853 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 489853 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 489853 # number of overall misses -system.cpu0.icache.overall_misses::total 489853 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7462564000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 7462564000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 7462564000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 7462564000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 7462564000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 7462564000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 36169598 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 36169598 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 36169598 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 36169598 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 36169598 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 36169598 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_hits::cpu0.inst 35679696 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 35679696 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 35679696 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 35679696 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 35679696 # number of overall hits +system.cpu0.icache.overall_hits::total 35679696 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 489848 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 489848 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 489848 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 489848 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 489848 # number of overall misses +system.cpu0.icache.overall_misses::total 489848 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 7462315000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 7462315000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 7462315000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 7462315000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 7462315000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 7462315000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 36169544 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 36169544 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 36169544 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 36169544 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 36169544 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 36169544 # number of overall (read+write) accesses system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013543 # miss rate for ReadReq accesses system.cpu0.icache.ReadReq_miss_rate::total 0.013543 # miss rate for ReadReq accesses system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013543 # miss rate for demand accesses system.cpu0.icache.demand_miss_rate::total 0.013543 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013543 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.013543 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15234.292737 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 15234.292737 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 15234.292737 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15234.292737 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 15234.292737 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 15233.939916 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 15233.939916 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 15233.939916 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 15233.939916 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 15233.939916 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 15233.939916 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -676,114 +676,112 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 58 # number of writebacks -system.cpu0.icache.writebacks::total 58 # number of writebacks -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 489853 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 489853 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 489853 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 489853 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 489853 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 489853 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5992343500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 5992343500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5992343500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 5992343500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5992343500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 5992343500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 489848 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 489848 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 489848 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 489848 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 489848 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 489848 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 5992109500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 5992109500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 5992109500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 5992109500 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 5992109500 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 5992109500 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013543 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.013543 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013543 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.013543 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.942332 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.942332 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.942332 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12232.589497 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 12232.589497 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12232.589497 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 12232.589497 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 817835 # number of replacements -system.cpu0.dcache.tagsinuse 479.881432 # Cycle average of tags in use -system.cpu0.dcache.total_refs 8879650 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 818347 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 10.850715 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 817819 # number of replacements +system.cpu0.dcache.tagsinuse 479.881496 # Cycle average of tags in use +system.cpu0.dcache.total_refs 8879648 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 818331 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 10.850925 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 85697000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 479.881432 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.937268 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.937268 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 5008280 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 5008280 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 3627742 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 3627742 # number of WriteReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 479.881496 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.937269 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.937269 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 5008276 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 5008276 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3627744 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3627744 # number of WriteReq hits system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 117045 # number of LoadLockedReq hits system.cpu0.dcache.LoadLockedReq_hits::total 117045 # number of LoadLockedReq hits system.cpu0.dcache.StoreCondReq_hits::cpu0.data 122538 # number of StoreCondReq hits system.cpu0.dcache.StoreCondReq_hits::total 122538 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 8636022 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 8636022 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 8636022 # number of overall hits -system.cpu0.dcache.overall_hits::total 8636022 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 610615 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 610615 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 207039 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 207039 # number of WriteReq misses +system.cpu0.dcache.demand_hits::cpu0.data 8636020 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 8636020 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 8636020 # number of overall hits +system.cpu0.dcache.overall_hits::total 8636020 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 610602 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 610602 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 207036 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 207036 # number of WriteReq misses system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6562 # number of LoadLockedReq misses system.cpu0.dcache.LoadLockedReq_misses::total 6562 # number of LoadLockedReq misses system.cpu0.dcache.StoreCondReq_misses::cpu0.data 580 # number of StoreCondReq misses system.cpu0.dcache.StoreCondReq_misses::total 580 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 817654 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 817654 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 817654 # number of overall misses -system.cpu0.dcache.overall_misses::total 817654 # number of overall misses -system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19940488000 # number of ReadReq miss cycles -system.cpu0.dcache.ReadReq_miss_latency::total 19940488000 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7282919000 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 7282919000 # number of WriteReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92852000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.LoadLockedReq_miss_latency::total 92852000 # number of LoadLockedReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8304000 # number of StoreCondReq miss cycles -system.cpu0.dcache.StoreCondReq_miss_latency::total 8304000 # number of StoreCondReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 27223407000 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 27223407000 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 27223407000 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 27223407000 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 5618895 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 5618895 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 3834781 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 3834781 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_misses::cpu0.data 817638 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 817638 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 817638 # number of overall misses +system.cpu0.dcache.overall_misses::total 817638 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 19940652000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 19940652000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 7284412000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 7284412000 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 92857000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 92857000 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 8303000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 8303000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 27225064000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 27225064000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 27225064000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 27225064000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 5618878 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 5618878 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 3834780 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 3834780 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 123607 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.LoadLockedReq_accesses::total 123607 # number of LoadLockedReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 123118 # number of StoreCondReq accesses(hits+misses) system.cpu0.dcache.StoreCondReq_accesses::total 123118 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 9453676 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 9453676 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 9453676 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 9453676 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108672 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.108672 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.053990 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.053990 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 9453658 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 9453658 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 9453658 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 9453658 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.108670 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.108670 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.053989 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.053989 # miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053088 # miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053088 # miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.004711 # miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_miss_rate::total 0.004711 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086491 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.086491 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086491 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.086491 # miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32656.400514 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 32656.400514 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35176.556108 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 35176.556108 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14149.954282 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14149.954282 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14317.241379 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14317.241379 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33294.531672 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33294.531672 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33294.531672 # average overall miss latency +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.086489 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.086489 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.086489 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.086489 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 32657.364372 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 32657.364372 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 35184.277131 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 35184.277131 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 14150.716245 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14150.716245 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 14315.517241 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 14315.517241 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33297.209768 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33297.209768 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33297.209768 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33297.209768 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -792,62 +790,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 359699 # number of writebacks -system.cpu0.dcache.writebacks::total 359699 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 610615 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 610615 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 207039 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 207039 # number of WriteReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 359687 # number of writebacks +system.cpu0.dcache.writebacks::total 359687 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 610602 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 610602 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 207036 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 207036 # number of WriteReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 6562 # number of LoadLockedReq MSHR misses system.cpu0.dcache.LoadLockedReq_mshr_misses::total 6562 # number of LoadLockedReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 580 # number of StoreCondReq MSHR misses system.cpu0.dcache.StoreCondReq_mshr_misses::total 580 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 817654 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 817654 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 817654 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 817654 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 18108577524 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 18108577524 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 6661800002 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6661800002 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 73166000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 73166000 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 6564000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 6564000 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24770377526 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 24770377526 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24770377526 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 24770377526 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 601208500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 601208500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1014438500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1014438500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1615647000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1615647000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108672 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108672 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053990 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053990 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 817638 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 817638 # 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number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 24772082526 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 24772082526 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 24772082526 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 24772082526 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 601210500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 601210500 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1014423500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1014423500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 1615634000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 1615634000 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.108670 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.108670 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.053989 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.053989 # mshr miss rate for WriteReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.053088 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.053088 # mshr miss rate for LoadLockedReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.004711 # mshr miss rate for StoreCondReq accesses system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.004711 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.086491 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086491 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.086491 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29656.293285 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29656.293285 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32176.546457 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32176.546457 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11149.954282 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11149.954282 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11317.241379 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11317.241379 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30294.449151 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30294.449151 # average overall mshr miss latency +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.086489 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.086489 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.086489 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.086489 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 29657.257140 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 29657.257140 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 32184.267480 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 32184.267480 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11150.716245 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11150.716245 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 11315.517241 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11315.517241 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30297.127245 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30297.127245 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30297.127245 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30297.127245 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -887,7 +885,7 @@ system.cpu1.itb.data_hits 0 # DT system.cpu1.itb.data_misses 0 # DTB misses system.cpu1.itb.data_acv 0 # DTB access violations system.cpu1.itb.data_accesses 0 # DTB accesses -system.cpu1.numCycles 3908222380 # number of cpu cycles simulated +system.cpu1.numCycles 3908222400 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu1.committedInsts 23256004 # Number of instructions committed @@ -905,8 +903,8 @@ system.cpu1.num_fp_register_writes 97489 # nu system.cpu1.num_mem_refs 6725970 # number of memory refs system.cpu1.num_load_insts 3973767 # Number of load instructions system.cpu1.num_store_insts 2752203 # Number of store instructions -system.cpu1.num_idle_cycles 3808684025.637170 # Number of idle cycles -system.cpu1.num_busy_cycles 99538354.362830 # Number of busy cycles +system.cpu1.num_idle_cycles 3808683702.691761 # Number of idle cycles +system.cpu1.num_busy_cycles 99538697.308239 # Number of busy cycles system.cpu1.not_idle_fraction 0.025469 # Percentage of non-idle cycles system.cpu1.idle_fraction 0.974531 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed @@ -922,11 +920,11 @@ system.cpu1.kern.ipl_good::22 1966 2.41% 51.21% # nu system.cpu1.kern.ipl_good::30 91 0.11% 51.32% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::31 39692 48.68% 100.00% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good::total 81532 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks::0 1901560823500 97.31% 97.31% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::22 537428500 0.03% 97.34% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::0 1901560916500 97.31% 97.31% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::22 537337500 0.03% 97.34% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks::30 59036000 0.00% 97.34% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::31 51953872000 2.66% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks::total 1954111160000 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::31 51953880000 2.66% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks::total 1954111170000 # number of cycles we spent at this ipl system.cpu1.kern.ipl_used::0 0.976773 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl @@ -982,37 +980,37 @@ system.cpu1.kern.mode_switch_good::kernel 0.200282 # f system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::idle 0.026006 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good::total 0.210800 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks::kernel 72316980000 3.70% 3.70% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::user 1607803000 0.08% 3.78% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks::idle 1879348629000 96.22% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::kernel 72317077000 3.70% 3.70% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::user 1608073000 0.08% 3.78% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks::idle 1879348652000 96.22% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2293 # number of times the context was actually changed -system.cpu1.icache.replacements 513695 # number of replacements -system.cpu1.icache.tagsinuse 501.294136 # Cycle average of tags in use -system.cpu1.icache.total_refs 22744962 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 514207 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 44.233085 # Average number of references to valid blocks. +system.cpu1.icache.replacements 513692 # number of replacements +system.cpu1.icache.tagsinuse 501.294138 # Cycle average of tags in use +system.cpu1.icache.total_refs 22744965 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 514204 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 44.233349 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 96225204000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 501.294136 # Average occupied blocks per requestor +system.cpu1.icache.occ_blocks::cpu1.inst 501.294138 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.979090 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.979090 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 22744962 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 22744962 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 22744962 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 22744962 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 22744962 # number of overall hits -system.cpu1.icache.overall_hits::total 22744962 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 514232 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 514232 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 514232 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 514232 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 514232 # number of overall misses -system.cpu1.icache.overall_misses::total 514232 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7551962500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 7551962500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 7551962500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 7551962500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 7551962500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 7551962500 # number of overall miss cycles +system.cpu1.icache.ReadReq_hits::cpu1.inst 22744965 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 22744965 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 22744965 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 22744965 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 22744965 # number of overall hits +system.cpu1.icache.overall_hits::total 22744965 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 514229 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 514229 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 514229 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 514229 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 514229 # number of overall misses +system.cpu1.icache.overall_misses::total 514229 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7551928500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7551928500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7551928500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7551928500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7551928500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7551928500 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 23259194 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 23259194 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 23259194 # number of demand (read+write) accesses @@ -1025,12 +1023,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.022109 system.cpu1.icache.demand_miss_rate::total 0.022109 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.022109 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.022109 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.905389 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.905389 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.905389 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14685.905389 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.905389 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14685.905389 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14685.924948 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14685.924948 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14685.924948 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14685.924948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14685.924948 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14685.924948 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1039,78 +1037,76 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 11 # number of writebacks -system.cpu1.icache.writebacks::total 11 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 514232 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 514232 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 514232 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 514232 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 514232 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 514232 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6009201500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 6009201500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6009201500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 6009201500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6009201500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 6009201500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 514229 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 514229 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 514229 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 514229 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 514229 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 514229 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 6009175500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 6009175500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 6009175500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 6009175500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 6009175500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 6009175500 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022109 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.022109 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022109 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.022109 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.778987 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.778987 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.778987 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.778987 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11685.796600 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11685.796600 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11685.796600 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11685.796600 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 642543 # number of replacements -system.cpu1.dcache.tagsinuse 493.349744 # Cycle average of tags in use -system.cpu1.dcache.total_refs 6059288 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 642980 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 9.423758 # Average number of references to valid blocks. +system.cpu1.dcache.replacements 642542 # number of replacements +system.cpu1.dcache.tagsinuse 493.349728 # Cycle average of tags in use +system.cpu1.dcache.total_refs 6059289 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 642979 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 9.423774 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 54205321000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 493.349744 # Average occupied blocks per requestor +system.cpu1.dcache.occ_blocks::cpu1.data 493.349728 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.963574 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.963574 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 3370942 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 3370942 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 2541026 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 2541026 # number of WriteReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 3370941 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 3370941 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 2541028 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 2541028 # number of WriteReq hits system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 71125 # number of LoadLockedReq hits system.cpu1.dcache.LoadLockedReq_hits::total 71125 # number of LoadLockedReq hits system.cpu1.dcache.StoreCondReq_hits::cpu1.data 80221 # number of StoreCondReq hits system.cpu1.dcache.StoreCondReq_hits::total 80221 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 5911968 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 5911968 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 5911968 # number of overall hits -system.cpu1.dcache.overall_hits::total 5911968 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 513440 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 513440 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 122215 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 122215 # number of WriteReq misses +system.cpu1.dcache.demand_hits::cpu1.data 5911969 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 5911969 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 5911969 # number of overall hits +system.cpu1.dcache.overall_hits::total 5911969 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 513441 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 513441 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 122213 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 122213 # number of WriteReq misses system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 13103 # number of LoadLockedReq misses system.cpu1.dcache.LoadLockedReq_misses::total 13103 # number of LoadLockedReq misses system.cpu1.dcache.StoreCondReq_misses::cpu1.data 640 # number of StoreCondReq misses system.cpu1.dcache.StoreCondReq_misses::total 640 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 635655 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 635655 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 635655 # number of overall misses -system.cpu1.dcache.overall_misses::total 635655 # number of overall misses -system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7202447500 # number of ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 7202447500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2665469000 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2665469000 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 183740000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 183740000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.demand_misses::cpu1.data 635654 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 635654 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 635654 # number of overall misses +system.cpu1.dcache.overall_misses::total 635654 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 7202554500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 7202554500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2665634000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2665634000 # number of WriteReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 183727000 # number of LoadLockedReq miss cycles +system.cpu1.dcache.LoadLockedReq_miss_latency::total 183727000 # number of LoadLockedReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 8466000 # number of StoreCondReq miss cycles system.cpu1.dcache.StoreCondReq_miss_latency::total 8466000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 9867916500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 9867916500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 9867916500 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 9867916500 # number of overall miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 9868188500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 9868188500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 9868188500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 9868188500 # number of overall miss cycles system.cpu1.dcache.ReadReq_accesses::cpu1.data 3884382 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.ReadReq_accesses::total 3884382 # number of ReadReq accesses(hits+misses) system.cpu1.dcache.WriteReq_accesses::cpu1.data 2663241 # number of WriteReq accesses(hits+misses) @@ -1125,8 +1121,8 @@ system.cpu1.dcache.overall_accesses::cpu1.data 6547623 system.cpu1.dcache.overall_accesses::total 6547623 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.132181 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.132181 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045890 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.045890 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.045889 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.045889 # miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.155566 # miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.155566 # miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.007915 # miss rate for StoreCondReq accesses @@ -1135,18 +1131,18 @@ system.cpu1.dcache.demand_miss_rate::cpu1.data 0.097082 system.cpu1.dcache.demand_miss_rate::total 0.097082 # miss rate for demand accesses system.cpu1.dcache.overall_miss_rate::cpu1.data 0.097082 # miss rate for overall accesses system.cpu1.dcache.overall_miss_rate::total 0.097082 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14027.827010 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 14027.827010 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21809.671481 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 21809.671481 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14022.742883 # average LoadLockedReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14022.742883 # average LoadLockedReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 14028.008087 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 14028.008087 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 21811.378495 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 21811.378495 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14021.750744 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 14021.750744 # average LoadLockedReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 13228.125000 # average StoreCondReq miss latency system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 13228.125000 # average StoreCondReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 15524.013026 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.013026 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 15524.013026 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 15524.465354 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 15524.465354 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 15524.465354 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 15524.465354 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1155,44 +1151,44 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 498964 # number of writebacks -system.cpu1.dcache.writebacks::total 498964 # number of writebacks -system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 513440 # number of ReadReq MSHR misses -system.cpu1.dcache.ReadReq_mshr_misses::total 513440 # number of ReadReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 122215 # number of WriteReq MSHR misses -system.cpu1.dcache.WriteReq_mshr_misses::total 122215 # number of WriteReq MSHR misses +system.cpu1.dcache.writebacks::writebacks 498963 # number of writebacks +system.cpu1.dcache.writebacks::total 498963 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 513441 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 513441 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 122213 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 122213 # number of WriteReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 13103 # number of LoadLockedReq MSHR misses system.cpu1.dcache.LoadLockedReq_mshr_misses::total 13103 # number of LoadLockedReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 640 # number of StoreCondReq MSHR misses system.cpu1.dcache.StoreCondReq_mshr_misses::total 640 # number of StoreCondReq MSHR misses -system.cpu1.dcache.demand_mshr_misses::cpu1.data 635655 # number of demand (read+write) MSHR misses -system.cpu1.dcache.demand_mshr_misses::total 635655 # number of demand (read+write) MSHR misses -system.cpu1.dcache.overall_mshr_misses::cpu1.data 635655 # number of overall MSHR misses -system.cpu1.dcache.overall_mshr_misses::total 635655 # number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5662112010 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5662112010 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2298824000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2298824000 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 144431000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 144431000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_misses::cpu1.data 635654 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 635654 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 635654 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 635654 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 5662217009 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 5662217009 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 2298995000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 2298995000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 144418000 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 144418000 # number of LoadLockedReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 6549000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 6549000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 5000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 5000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7960936010 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 7960936010 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7960936010 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 7960936010 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 7961212009 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 7961212009 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 7961212009 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 7961212009 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 295035500 # number of ReadReq MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 295035500 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 516397500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 516397500 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 811433000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 811433000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 516366500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 516366500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 811402000 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 811402000 # number of overall MSHR uncacheable cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.132181 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.132181 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045890 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045890 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.045889 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.045889 # mshr miss rate for WriteReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.155566 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.155566 # mshr miss rate for LoadLockedReq accesses system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.007915 # mshr miss rate for StoreCondReq accesses @@ -1201,20 +1197,20 @@ system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.097082 system.cpu1.dcache.demand_mshr_miss_rate::total 0.097082 # mshr miss rate for demand accesses system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.097082 # mshr miss rate for overall accesses system.cpu1.dcache.overall_mshr_miss_rate::total 0.097082 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.796841 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.796841 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18809.671481 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18809.671481 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11022.742883 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11022.742883 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11027.979863 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11027.979863 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 18811.378495 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 18811.378495 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11021.750744 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11021.750744 # average LoadLockedReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 10232.812500 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 10232.812500 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12523.988657 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12523.988657 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12524.442557 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12524.442557 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12524.442557 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12524.442557 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index a60709d68..734887994 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -250,7 +250,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.physmem.port[0] +master=system.bridge.slave system.physmem.port slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout index c99186441..e4a5afde7 100755 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout @@ -1,11 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 08:30:56 -gem5 started Jul 2 2012 09:09:16 +gem5 compiled Jul 26 2012 21:20:05 +gem5 started Jul 26 2012 21:40:05 gem5 executing on zizzer -command line: build/ALPHA/gem5.fast -d build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/fast/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux + 0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1920852274000 because m5_exit instruction encountered +Exiting @ tick 1920853042000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt index 8d476d641..c7cd1312f 100644 --- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.920852 # Number of seconds simulated -sim_ticks 1920852274000 # Number of ticks simulated -final_tick 1920852274000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.920853 # Number of seconds simulated +sim_ticks 1920853042000 # Number of ticks simulated +final_tick 1920853042000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1904642 # Simulator instruction rate (inst/s) -host_op_rate 1904641 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 65112526106 # Simulator tick rate (ticks/s) -host_mem_usage 294856 # Number of bytes of host memory used -host_seconds 29.50 # Real time elapsed on the host +host_inst_rate 1381815 # Simulator instruction rate (inst/s) +host_op_rate 1381815 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47239093914 # Simulator tick rate (ticks/s) +host_mem_usage 299308 # Number of bytes of host memory used +host_seconds 40.66 # Real time elapsed on the host sim_insts 56187824 # Number of instructions simulated sim_ops 56187824 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 850688 # Number of bytes read from this memory @@ -26,113 +26,113 @@ system.physmem.num_reads::total 442978 # Nu system.physmem.num_writes::writebacks 115454 # Number of write requests responded to by this memory system.physmem.num_writes::total 115454 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 442870 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 12935691 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 12935686 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::tsunami.ide 1380820 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 14759382 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 14759376 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 442870 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 442870 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3846759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 3846759 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3846759 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 3846758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 3846758 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3846758 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 442870 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 12935691 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 12935686 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::tsunami.ide 1380820 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 18606141 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 18606133 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 336066 # number of replacements -system.l2c.tagsinuse 65311.816256 # Cycle average of tags in use -system.l2c.total_refs 2448229 # Total number of references to valid blocks. -system.l2c.sampled_refs 401229 # Sample count of references to valid blocks. -system.l2c.avg_refs 6.101825 # Average number of references to valid blocks. +system.l2c.tagsinuse 65311.806529 # Cycle average of tags in use +system.l2c.total_refs 2448197 # Total number of references to valid blocks. +system.l2c.sampled_refs 401228 # Sample count of references to valid blocks. +system.l2c.avg_refs 6.101760 # Average number of references to valid blocks. system.l2c.warmup_cycle 5946056000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 55675.740322 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 4768.394145 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 4867.681789 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 55675.727094 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 4768.395922 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 4867.683513 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.849544 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.inst 0.072760 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.data 0.074275 # Average percentage of cache occupancy system.l2c.occ_percent::total 0.996579 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.inst 916210 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 814879 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1731089 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 835223 # number of Writeback hits -system.l2c.Writeback_hits::total 835223 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu.data 6 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 6 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 187457 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 187457 # number of ReadExReq hits -system.l2c.demand_hits::cpu.inst 916210 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 1002336 # number of demand (read+write) hits -system.l2c.demand_hits::total 1918546 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.inst 916210 # number of overall hits -system.l2c.overall_hits::cpu.data 1002336 # number of overall hits -system.l2c.overall_hits::total 1918546 # number of overall hits +system.l2c.ReadReq_hits::cpu.inst 916208 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 814933 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1731141 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 835149 # number of Writeback hits +system.l2c.Writeback_hits::total 835149 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu.data 4 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 4 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu.data 187605 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 187605 # number of ReadExReq hits +system.l2c.demand_hits::cpu.inst 916208 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 1002538 # number of demand (read+write) hits +system.l2c.demand_hits::total 1918746 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.inst 916208 # number of overall hits +system.l2c.overall_hits::cpu.data 1002538 # number of overall hits +system.l2c.overall_hits::total 1918746 # number of overall hits system.l2c.ReadReq_misses::cpu.inst 13292 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.data 271915 # number of ReadReq misses system.l2c.ReadReq_misses::total 285207 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 8 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 8 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 116714 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 116714 # number of ReadExReq misses +system.l2c.UpgradeReq_misses::cpu.data 14 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 116718 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 116718 # number of ReadExReq misses system.l2c.demand_misses::cpu.inst 13292 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.data 388629 # number of demand (read+write) misses -system.l2c.demand_misses::total 401921 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.data 388633 # number of demand (read+write) misses +system.l2c.demand_misses::total 401925 # number of demand (read+write) misses system.l2c.overall_misses::cpu.inst 13292 # number of overall misses -system.l2c.overall_misses::cpu.data 388629 # number of overall misses -system.l2c.overall_misses::total 401921 # number of overall misses +system.l2c.overall_misses::cpu.data 388633 # number of overall misses +system.l2c.overall_misses::total 401925 # number of overall misses system.l2c.ReadReq_miss_latency::cpu.inst 691773000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu.data 14144855000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::total 14836628000 # number of ReadReq miss cycles system.l2c.UpgradeReq_miss_latency::cpu.data 320000 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_latency::total 320000 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu.data 6069807000 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 6069807000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu.data 6070015000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 6070015000 # number of ReadExReq miss cycles system.l2c.demand_miss_latency::cpu.inst 691773000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu.data 20214662000 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 20906435000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu.data 20214870000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 20906643000 # number of demand (read+write) miss cycles system.l2c.overall_miss_latency::cpu.inst 691773000 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu.data 20214662000 # number of overall miss cycles -system.l2c.overall_miss_latency::total 20906435000 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu.inst 929502 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 1086794 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 2016296 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 835223 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 835223 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 14 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 14 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 304171 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 304171 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.inst 929502 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 1390965 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 2320467 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.inst 929502 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 1390965 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 2320467 # number of overall (read+write) accesses +system.l2c.overall_miss_latency::cpu.data 20214870000 # number of overall miss cycles +system.l2c.overall_miss_latency::total 20906643000 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu.inst 929500 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 1086848 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 2016348 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 835149 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 835149 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 304323 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 304323 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.inst 929500 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 1391171 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 2320671 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.inst 929500 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 1391171 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 2320671 # number of overall (read+write) accesses system.l2c.ReadReq_miss_rate::cpu.inst 0.014300 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.250199 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.141451 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.571429 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.571429 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.383712 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.383712 # miss rate for ReadExReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.250187 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.141447 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.777778 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.777778 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.383533 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.383533 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu.inst 0.014300 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.279395 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.173207 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.279357 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.173193 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu.inst 0.014300 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.279395 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.173207 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.279357 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.173193 # miss rate for overall accesses system.l2c.ReadReq_avg_miss_latency::cpu.inst 52044.312368 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu.data 52019.399445 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::total 52020.560505 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu.data 40000 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 40000 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817640 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 52005.817640 # average ReadExReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu.data 22857.142857 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 22857.142857 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu.data 52005.817440 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 52005.817440 # average ReadExReq miss latency system.l2c.demand_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 52016.279319 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 52016.279157 # average overall miss latency system.l2c.overall_avg_miss_latency::cpu.inst 52044.312368 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu.data 52015.320524 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 52016.279319 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu.data 52015.320367 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 52016.279157 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -146,29 +146,29 @@ system.l2c.writebacks::total 73942 # nu system.l2c.ReadReq_mshr_misses::cpu.inst 13292 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::cpu.data 271915 # number of ReadReq MSHR misses system.l2c.ReadReq_mshr_misses::total 285207 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu.data 8 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 8 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu.data 116714 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 116714 # number of ReadExReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu.data 14 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 14 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu.data 116718 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 116718 # number of ReadExReq MSHR misses system.l2c.demand_mshr_misses::cpu.inst 13292 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu.data 388629 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 401921 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu.data 388633 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 401925 # number of demand (read+write) MSHR misses system.l2c.overall_mshr_misses::cpu.inst 13292 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu.data 388629 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 401921 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu.data 388633 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 401925 # number of overall MSHR misses system.l2c.ReadReq_mshr_miss_latency::cpu.inst 532266000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu.data 10881875000 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::total 11414141000 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 380000 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 380000 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669239000 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 4669239000 # number of ReadExReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu.data 620000 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 620000 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu.data 4669399000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4669399000 # number of ReadExReq MSHR miss cycles system.l2c.demand_mshr_miss_latency::cpu.inst 532266000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu.data 15551114000 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 16083380000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu.data 15551274000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 16083540000 # number of demand (read+write) MSHR miss cycles system.l2c.overall_mshr_miss_latency::cpu.inst 532266000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu.data 15551114000 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 16083380000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu.data 15551274000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 16083540000 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_uncacheable_latency::cpu.data 772639030 # number of ReadReq MSHR uncacheable cycles system.l2c.ReadReq_mshr_uncacheable_latency::total 772639030 # number of ReadReq MSHR uncacheable cycles system.l2c.WriteReq_mshr_uncacheable_latency::cpu.data 1072677000 # number of WriteReq MSHR uncacheable cycles @@ -176,31 +176,31 @@ system.l2c.WriteReq_mshr_uncacheable_latency::total 1072677000 system.l2c.overall_mshr_uncacheable_latency::cpu.data 1845316030 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_latency::total 1845316030 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250199 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.141451 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.571429 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.571429 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383712 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.383712 # mshr miss rate for ReadExReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.250187 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.141447 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.777778 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.777778 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.383533 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.383533 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.173207 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.173193 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.inst 0.014300 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.279395 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.173207 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.279357 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.173193 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40044.086669 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40019.399445 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::total 40020.549987 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 47500 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 47500 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817640 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817640 # average ReadExReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 44285.714286 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 44285.714286 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40005.817440 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40005.817440 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40044.086669 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320524 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40016.271854 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40015.320367 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40016.271692 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -209,14 +209,14 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu.data inf system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 41685 # number of replacements -system.iocache.tagsinuse 1.356962 # Cycle average of tags in use +system.iocache.tagsinuse 1.356968 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. system.iocache.sampled_refs 41701 # Sample count of references to valid blocks. system.iocache.avg_refs 0 # Average number of references to valid blocks. system.iocache.warmup_cycle 1753491316000 # Cycle when the warmup percentage was hit. -system.iocache.occ_blocks::tsunami.ide 1.356962 # Average occupied blocks per requestor -system.iocache.occ_percent::tsunami.ide 0.084810 # Average percentage of cache occupancy -system.iocache.occ_percent::total 0.084810 # Average percentage of cache occupancy +system.iocache.occ_blocks::tsunami.ide 1.356968 # Average occupied blocks per requestor +system.iocache.occ_percent::tsunami.ide 0.084811 # Average percentage of cache occupancy +system.iocache.occ_percent::total 0.084811 # Average percentage of cache occupancy system.iocache.ReadReq_misses::tsunami.ide 173 # number of ReadReq misses system.iocache.ReadReq_misses::total 173 # number of ReadReq misses system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses @@ -344,7 +344,7 @@ system.cpu.itb.data_hits 0 # DT system.cpu.itb.data_misses 0 # DTB misses system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses -system.cpu.numCycles 3841704548 # number of cpu cycles simulated +system.cpu.numCycles 3841706084 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 56187824 # Number of instructions committed @@ -362,10 +362,10 @@ system.cpu.num_fp_register_writes 166520 # nu system.cpu.num_mem_refs 15475451 # number of memory refs system.cpu.num_load_insts 9102635 # Number of load instructions system.cpu.num_store_insts 6372816 # Number of store instructions -system.cpu.num_idle_cycles 3589583028.998131 # Number of idle cycles -system.cpu.num_busy_cycles 252121519.001869 # Number of busy cycles -system.cpu.not_idle_fraction 0.065628 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.934372 # Percentage of idle cycles +system.cpu.num_idle_cycles 3589579952.998131 # Number of idle cycles +system.cpu.num_busy_cycles 252126131.001869 # Number of busy cycles +system.cpu.not_idle_fraction 0.065629 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.934371 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 6379 # number of quiesce instructions executed system.cpu.kern.inst.hwrei 212104 # number of hwrei instructions executed @@ -379,11 +379,11 @@ system.cpu.kern.ipl_good::21 131 0.09% 49.40% # nu system.cpu.kern.ipl_good::22 1936 1.30% 50.69% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::31 73562 49.31% 100.00% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good::total 149191 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks::0 1861395067500 96.90% 96.90% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::0 1861395652500 96.90% 96.90% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks::21 90398000 0.00% 96.91% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::22 587303500 0.03% 96.94% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::31 58778672000 3.06% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks::total 1920851441000 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::22 587366500 0.03% 96.94% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::31 58778792000 3.06% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks::total 1920852209000 # number of cycles we spent at this ipl system.cpu.kern.ipl_used::0 0.981756 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl @@ -447,9 +447,9 @@ system.cpu.kern.mode_switch_good::kernel 0.323061 # fr system.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::idle 0.081030 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good::total 0.391706 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks::kernel 46234544000 2.41% 2.41% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::user 5257252000 0.27% 2.68% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks::idle 1869359638000 97.32% 100.00% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::kernel 46234707000 2.41% 2.41% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::user 5259387000 0.27% 2.68% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks::idle 1869358108000 97.32% 100.00% # number of ticks spent at the given mode system.cpu.kern.swap_context 4178 # number of times the context was actually changed system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA @@ -482,33 +482,33 @@ system.tsunami.ethernet.totalRxOrn 0 # to system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU system.tsunami.ethernet.droppedPackets 0 # number of packets dropped -system.cpu.icache.replacements 928851 # number of replacements -system.cpu.icache.tagsinuse 508.732124 # Cycle average of tags in use -system.cpu.icache.total_refs 55270141 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 929362 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 59.471058 # Average number of references to valid blocks. +system.cpu.icache.replacements 928849 # number of replacements +system.cpu.icache.tagsinuse 508.732123 # Cycle average of tags in use +system.cpu.icache.total_refs 55270143 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 929360 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 59.471188 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 35877190000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 508.732124 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 508.732123 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.993617 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.993617 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 55270141 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 55270141 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 55270141 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 55270141 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 55270141 # number of overall hits -system.cpu.icache.overall_hits::total 55270141 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 929522 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 929522 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 929522 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 929522 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 929522 # number of overall misses -system.cpu.icache.overall_misses::total 929522 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854472500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13854472500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13854472500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13854472500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13854472500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13854472500 # number of overall miss cycles +system.cpu.icache.ReadReq_hits::cpu.inst 55270143 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 55270143 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 55270143 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 55270143 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 55270143 # number of overall hits +system.cpu.icache.overall_hits::total 55270143 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 929520 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 929520 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 929520 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 929520 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 929520 # number of overall misses +system.cpu.icache.overall_misses::total 929520 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 13854449500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 13854449500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 13854449500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 13854449500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 13854449500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 13854449500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 56199663 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 56199663 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 56199663 # number of demand (read+write) accesses @@ -521,12 +521,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.016540 system.cpu.icache.demand_miss_rate::total 0.016540 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.016540 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.016540 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.943078 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14904.943078 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14904.943078 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.943078 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14904.943078 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14904.950405 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14904.950405 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14904.950405 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14904.950405 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14904.950405 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -535,74 +535,72 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 85 # number of writebacks -system.cpu.icache.writebacks::total 85 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929522 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 929522 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 929522 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 929522 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 929522 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 929522 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065220000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11065220000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065220000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11065220000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065220000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11065220000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 929520 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 929520 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 929520 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 929520 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 929520 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 929520 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11065203000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 11065203000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11065203000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 11065203000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11065203000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 11065203000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.016540 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.016540 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.016540 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.016540 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.204527 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.204527 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.204527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.204527 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11904.211851 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11904.211851 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11904.211851 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11904.211851 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 1390643 # number of replacements +system.cpu.dcache.replacements 1390657 # number of replacements system.cpu.dcache.tagsinuse 511.983813 # Cycle average of tags in use -system.cpu.dcache.total_refs 14050710 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 1391155 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.100032 # Average number of references to valid blocks. +system.cpu.dcache.total_refs 14050696 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 1391169 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 10.099920 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 85768000 # Cycle when the warmup percentage was hit. system.cpu.dcache.occ_blocks::cpu.data 511.983813 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999968 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999968 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 7815347 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 7815347 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 5853082 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 5853082 # number of WriteReq hits +system.cpu.dcache.ReadReq_hits::cpu.data 7815339 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 7815339 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 5853076 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 5853076 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 182979 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 182979 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 199284 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 199284 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 13668429 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 13668429 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 13668429 # number of overall hits -system.cpu.dcache.overall_hits::total 13668429 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 1069514 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 1069514 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 304335 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 304335 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 13668415 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 13668415 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 13668415 # number of overall hits +system.cpu.dcache.overall_hits::total 13668415 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 1069522 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 1069522 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 304341 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 304341 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 17326 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 17326 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 1373849 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1373849 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1373849 # number of overall misses -system.cpu.dcache.overall_misses::total 1373849 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 26655510000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 26655510000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9230954000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9230954000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 1373863 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1373863 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1373863 # number of overall misses +system.cpu.dcache.overall_misses::total 1373863 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 26656014000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 26656014000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9232792000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9232792000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 248493000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 248493000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35886464000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35886464000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35886464000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35886464000 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 35888806000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 35888806000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 35888806000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 35888806000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 8884861 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 8884861 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 6157417 # number of WriteReq accesses(hits+misses) @@ -615,26 +613,26 @@ system.cpu.dcache.demand_accesses::cpu.data 15042278 # system.cpu.dcache.demand_accesses::total 15042278 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 15042278 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 15042278 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120375 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.120375 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049426 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.049426 # miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.120376 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.120376 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.049427 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.049427 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.086498 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.086498 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.091333 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.091333 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.091333 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.091333 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.011760 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.011760 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30331.555687 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 30331.555687 # average WriteReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24923.296575 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 24923.296575 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 30336.996987 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 30336.996987 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14342.202470 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14342.202470 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 26121.112291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 26121.112291 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 26121.112291 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 26122.550793 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 26122.550793 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 26122.550793 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -643,54 +641,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 835138 # number of writebacks -system.cpu.dcache.writebacks::total 835138 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069514 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 1069514 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304335 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 304335 # number of WriteReq MSHR misses +system.cpu.dcache.writebacks::writebacks 835149 # number of writebacks +system.cpu.dcache.writebacks::total 835149 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1069522 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 1069522 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 304341 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 304341 # number of WriteReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 17326 # number of LoadLockedReq MSHR misses system.cpu.dcache.LoadLockedReq_mshr_misses::total 17326 # number of LoadLockedReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 1373849 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 1373849 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 1373849 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 1373849 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23446923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 23446923000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8317949000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 8317949000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_misses::cpu.data 1373863 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 1373863 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 1373863 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 1373863 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 23447403000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 23447403000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8319769000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8319769000 # number of WriteReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 196515000 # number of LoadLockedReq MSHR miss cycles system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 196515000 # number of LoadLockedReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31764872000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 31764872000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31764872000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 31764872000 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 31767172000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 31767172000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 31767172000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 31767172000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 862831000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 862831000 # number of ReadReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 1190523500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 1190523500 # number of WriteReq MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 2053354500 # number of overall MSHR uncacheable cycles system.cpu.dcache.overall_mshr_uncacheable_latency::total 2053354500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120375 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120375 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049426 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049426 # mshr miss rate for WriteReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.120376 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.120376 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.049427 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.049427 # mshr miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.086498 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.086498 # mshr miss rate for LoadLockedReq accesses system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for demand accesses system.cpu.dcache.demand_mshr_miss_rate::total 0.091333 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.091333 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.091333 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21922.969685 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21922.969685 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27331.555687 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27331.555687 # average WriteReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 21923.254501 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 21923.254501 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27336.996987 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27336.996987 # average WriteReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11342.202470 # average LoadLockedReq mshr miss latency system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11342.202470 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23121.079536 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 23121.079536 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23122.518039 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 23122.518039 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index e2b1a3bea..cab94b1b5 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -306,7 +306,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -367,9 +367,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] @@ -780,7 +780,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 50982556e..638b19e04 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:36:18 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:55:21 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 911653589000 because m5_exit instruction encountered +Exiting @ tick 912096763500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index c0313feaf..492e0d099 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -1,16 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.911654 # Number of seconds simulated -sim_ticks 911653589000 # Number of ticks simulated -final_tick 911653589000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.912097 # Number of seconds simulated +sim_ticks 912096763500 # Number of ticks simulated +final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 2171864 # Simulator instruction rate (inst/s) -host_op_rate 2807005 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 32664627860 # Simulator tick rate (ticks/s) -host_mem_usage 382740 # Number of bytes of host memory used -host_seconds 27.91 # Real time elapsed on the host -sim_insts 60615585 # Number of instructions simulated -sim_ops 78342060 # Number of ops (including micro ops) simulated +host_inst_rate 1622636 # Simulator instruction rate (inst/s) +host_op_rate 2089140 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 24015838223 # Simulator tick rate (ticks/s) +host_mem_usage 388524 # Number of bytes of host memory used +host_seconds 37.98 # Real time elapsed on the host +sim_insts 61625970 # Number of instructions simulated +sim_ops 79343340 # Number of ops (including micro ops) simulated +system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6234996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory +system.physmem.bytes_read::total 49638308 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4195776 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1.data 3010088 # Number of bytes written to this memory +system.physmem.bytes_written::total 7222864 # Number of bytes written to this memory +system.physmem.num_reads::realview.clcd 4915200 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 97494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082797 # 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number of SCUpgradeReq accesses(hits+misses) -system.l2c.SCUpgradeReq_accesses::total 1394 # number of SCUpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 165376 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 83237 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 248613 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.dtb.walker 5303 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.itb.walker 2204 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.inst 495240 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 383310 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.dtb.walker 4300 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.itb.walker 1569 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 365119 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 218748 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1475793 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.dtb.walker 5303 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.itb.walker 2204 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 495240 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 383310 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.dtb.walker 4300 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.itb.walker 1569 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 365119 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 218748 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1475793 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000907 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.015142 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.029284 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.itb.walker 0.000637 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.009000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.038846 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.018284 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.883357 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 0.800426 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.854628 # miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.856476 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.901304 # miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_miss_rate::total 0.873745 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.567616 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 0.565025 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.566748 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.itb.walker 0.000907 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.inst 0.015142 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.261543 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.itb.walker 0.000637 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.009000 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.239065 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.110679 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000189 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.itb.walker 0.000907 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.inst 0.015142 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.261543 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000698 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.itb.walker 0.000637 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.009000 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.239065 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.110679 # miss rate for overall accesses +system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses +system.l2c.overall_misses::cpu1.data 53648 # number of overall misses +system.l2c.overall_misses::total 163287 # number of overall misses +system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu0.data 181580 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.dtb.walker 5334 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.itb.walker 1734 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.inst 433858 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1.data 174787 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1231560 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 567807 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 567807 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 5543 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1.data 4967 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 10510 # number of UpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu0.data 878 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::cpu1.data 521 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.SCUpgradeReq_accesses::total 1399 # number of SCUpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 150612 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 98584 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 249196 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0.dtb.walker 3875 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.itb.walker 1922 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.inst 428470 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu0.data 332192 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.dtb.walker 5334 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.itb.walker 1734 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.inst 433858 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1.data 273371 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1480756 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0.dtb.walker 3875 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.itb.walker 1922 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.inst 428470 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu0.data 332192 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.dtb.walker 5334 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.itb.walker 1734 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 433858 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 273371 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1480756 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.001561 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.017345 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.035202 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.007715 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.030185 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.018232 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0.data 0.889771 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1.data 0.866519 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.878782 # miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.613902 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.565150 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.297578 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.110273 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.297578 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.110273 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -269,8 +257,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 65563 # number of writebacks -system.l2c.writebacks::total 65563 # number of writebacks +system.l2c.writebacks::writebacks 65559 # number of writebacks +system.l2c.writebacks::total 65559 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -280,27 +268,27 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 9312139 # DTB read hits -system.cpu0.dtb.read_misses 5476 # DTB read misses -system.cpu0.dtb.write_hits 6895585 # DTB write hits -system.cpu0.dtb.write_misses 1137 # DTB write misses +system.cpu0.dtb.read_hits 7975768 # DTB read hits +system.cpu0.dtb.read_misses 3611 # DTB read misses +system.cpu0.dtb.write_hits 5966574 # DTB write hits +system.cpu0.dtb.write_misses 672 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.dtb.flush_entries 2449 # Number of entries that have been flushed from TLB +system.cpu0.dtb.flush_entries 2004 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 187 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 135 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu0.dtb.perms_faults 267 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 9317615 # DTB read accesses -system.cpu0.dtb.write_accesses 6896722 # DTB write accesses +system.cpu0.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions +system.cpu0.dtb.read_accesses 7979379 # DTB read accesses +system.cpu0.dtb.write_accesses 5967246 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 16207724 # DTB hits -system.cpu0.dtb.misses 6613 # DTB misses -system.cpu0.dtb.accesses 16214337 # DTB accesses -system.cpu0.itb.inst_hits 34683994 # ITB inst hits -system.cpu0.itb.inst_misses 3170 # ITB inst misses +system.cpu0.dtb.hits 13942342 # DTB hits +system.cpu0.dtb.misses 4283 # DTB misses +system.cpu0.dtb.accesses 13946625 # DTB accesses +system.cpu0.itb.inst_hits 30238804 # ITB inst hits +system.cpu0.itb.inst_misses 2175 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses system.cpu0.itb.write_hits 0 # DTB write hits @@ -309,74 +297,74 @@ system.cpu0.itb.flush_tlb 4 # Nu system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu0.itb.flush_entries 1558 # Number of entries that have been flushed from TLB +system.cpu0.itb.flush_entries 1499 # Number of entries that have been flushed from TLB system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 34687164 # ITB inst accesses -system.cpu0.itb.hits 34683994 # DTB hits -system.cpu0.itb.misses 3170 # DTB misses -system.cpu0.itb.accesses 34687164 # DTB accesses -system.cpu0.numCycles 1823259919 # number of cpu cycles simulated +system.cpu0.itb.inst_accesses 30240979 # ITB inst accesses +system.cpu0.itb.hits 30238804 # DTB hits +system.cpu0.itb.misses 2175 # DTB misses +system.cpu0.itb.accesses 30240979 # DTB accesses +system.cpu0.numCycles 1823633059 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 33900598 # Number of instructions committed -system.cpu0.committedOps 44786074 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 39685287 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 5074 # Number of float alu accesses -system.cpu0.num_func_calls 1436598 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4494112 # number of instructions that are conditional controls -system.cpu0.num_int_insts 39685287 # number of integer instructions -system.cpu0.num_fp_insts 5074 # number of float instructions -system.cpu0.num_int_register_reads 201262894 # number of times the integer registers were read -system.cpu0.num_int_register_writes 42034263 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 3706 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 1372 # number of times the floating registers were written -system.cpu0.num_mem_refs 16978573 # number of memory refs -system.cpu0.num_load_insts 9760184 # Number of load instructions -system.cpu0.num_store_insts 7218389 # Number of store instructions -system.cpu0.num_idle_cycles 1777623684.411826 # Number of idle cycles -system.cpu0.num_busy_cycles 45636234.588174 # Number of busy cycles -system.cpu0.not_idle_fraction 0.025030 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.974970 # Percentage of idle cycles +system.cpu0.committedInsts 29750005 # Number of instructions committed +system.cpu0.committedOps 39129633 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 34471201 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 5449 # Number of float alu accesses +system.cpu0.num_func_calls 1241903 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4025450 # number of instructions that are conditional controls +system.cpu0.num_int_insts 34471201 # number of integer instructions +system.cpu0.num_fp_insts 5449 # number of float instructions +system.cpu0.num_int_register_reads 175121947 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36551788 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 4535 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 916 # number of times the floating registers were written +system.cpu0.num_mem_refs 14626951 # number of memory refs +system.cpu0.num_load_insts 8357226 # Number of load instructions +system.cpu0.num_store_insts 6269725 # Number of store instructions +system.cpu0.num_idle_cycles 1783968822.941743 # Number of idle cycles +system.cpu0.num_busy_cycles 39664236.058257 # Number of busy cycles +system.cpu0.not_idle_fraction 0.021750 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 58955 # number of quiesce instructions executed -system.cpu0.icache.replacements 497178 # number of replacements -system.cpu0.icache.tagsinuse 511.019581 # Cycle average of tags in use -system.cpu0.icache.total_refs 34187980 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 497690 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.693323 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 64536851000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.019581 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998085 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998085 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 34187980 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 34187980 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 34187980 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 34187980 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 34187980 # number of overall hits -system.cpu0.icache.overall_hits::total 34187980 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 497690 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 497690 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 497690 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 497690 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 497690 # number of overall misses -system.cpu0.icache.overall_misses::total 497690 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 34685670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 34685670 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 34685670 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 34685670 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 34685670 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 34685670 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014349 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014349 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014349 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014349 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014349 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014349 # miss rate for overall accesses +system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed +system.cpu0.icache.replacements 428547 # number of replacements +system.cpu0.icache.tagsinuse 511.020000 # Cycle average of tags in use +system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 429059 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 69.480223 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 511.020000 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998086 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998086 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29811115 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29811115 # number of overall hits +system.cpu0.icache.overall_hits::total 29811115 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 429059 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 429059 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 429059 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 429059 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 429059 # number of overall misses +system.cpu0.icache.overall_misses::total 429059 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 30240174 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 30240174 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 30240174 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 30240174 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 30240174 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 30240174 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014188 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014188 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014188 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014188 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014188 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014188 # miss rate for overall accesses system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -385,66 +373,64 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.writebacks::writebacks 31457 # number of writebacks -system.cpu0.icache.writebacks::total 31457 # number of writebacks system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 380425 # number of replacements -system.cpu0.dcache.tagsinuse 495.308430 # Cycle average of tags in use -system.cpu0.dcache.total_refs 14671885 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 380937 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 38.515253 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 323609 # number of replacements +system.cpu0.dcache.tagsinuse 494.763091 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12467604 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 323981 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 38.482516 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 22115000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 495.308430 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.967399 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.967399 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 7779192 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 7779192 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 6519856 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 6519856 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 173153 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 173153 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 175464 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 175464 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 14299048 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 14299048 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 14299048 # number of overall hits -system.cpu0.dcache.overall_hits::total 14299048 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 237170 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 237170 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 185374 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 185374 # number of WriteReq misses -system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9761 # number of LoadLockedReq misses -system.cpu0.dcache.LoadLockedReq_misses::total 9761 # number of LoadLockedReq misses -system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7396 # number of StoreCondReq misses -system.cpu0.dcache.StoreCondReq_misses::total 7396 # number of StoreCondReq misses -system.cpu0.dcache.demand_misses::cpu0.data 422544 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 422544 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 422544 # number of overall misses -system.cpu0.dcache.overall_misses::total 422544 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 8016362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 8016362 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 6705230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 6705230 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 182914 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.LoadLockedReq_accesses::total 182914 # number of LoadLockedReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 182860 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.StoreCondReq_accesses::total 182860 # number of StoreCondReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 14721592 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 14721592 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 14721592 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 14721592 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029586 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.029586 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027646 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.027646 # miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.053364 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.053364 # miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.040446 # miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_miss_rate::total 0.040446 # miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.028702 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.028702 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.028702 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.028702 # miss rate for overall accesses +system.cpu0.dcache.occ_blocks::cpu0.data 494.763091 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.966334 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6512305 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6512305 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5630881 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5630881 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 151619 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 151619 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 153180 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 153180 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 12143186 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 12143186 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 12143186 # number of overall hits +system.cpu0.dcache.overall_hits::total 12143186 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 197167 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 197167 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 167342 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 167342 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9062 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9062 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7469 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7469 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 364509 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 364509 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 364509 # number of overall misses +system.cpu0.dcache.overall_misses::total 364509 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6709472 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6709472 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5798223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5798223 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 160681 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 160681 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 160649 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 160649 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12507695 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12507695 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12507695 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12507695 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.029386 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.029386 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.028861 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.028861 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.056397 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.056397 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.046493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.046493 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029143 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029143 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029143 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029143 # miss rate for overall accesses system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -453,32 +439,32 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 353901 # number of writebacks -system.cpu0.dcache.writebacks::total 353901 # number of writebacks +system.cpu0.dcache.writebacks::writebacks 300958 # number of writebacks +system.cpu0.dcache.writebacks::total 300958 # number of writebacks system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 6036043 # DTB read hits -system.cpu1.dtb.read_misses 1895 # DTB read misses -system.cpu1.dtb.write_hits 4565126 # DTB write hits -system.cpu1.dtb.write_misses 1147 # DTB write misses +system.cpu1.dtb.read_hits 7364781 # DTB read hits +system.cpu1.dtb.read_misses 3705 # DTB read misses +system.cpu1.dtb.write_hits 5489656 # DTB write hits +system.cpu1.dtb.write_misses 1595 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.dtb.flush_entries 1364 # Number of entries that have been flushed from TLB +system.cpu1.dtb.flush_entries 1788 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 95 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 145 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions -system.cpu1.dtb.perms_faults 185 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 6037938 # DTB read accesses -system.cpu1.dtb.write_accesses 4566273 # DTB write accesses +system.cpu1.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions +system.cpu1.dtb.read_accesses 7368486 # DTB read accesses +system.cpu1.dtb.write_accesses 5491251 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 10601169 # DTB hits -system.cpu1.dtb.misses 3042 # DTB misses -system.cpu1.dtb.accesses 10604211 # DTB accesses -system.cpu1.itb.inst_hits 26944447 # ITB inst hits -system.cpu1.itb.inst_misses 1203 # ITB inst misses +system.cpu1.dtb.hits 12854437 # DTB hits +system.cpu1.dtb.misses 5300 # DTB misses +system.cpu1.dtb.accesses 12859737 # DTB accesses +system.cpu1.itb.inst_hits 32412306 # ITB inst hits +system.cpu1.itb.inst_misses 2200 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses system.cpu1.itb.write_hits 0 # DTB write hits @@ -487,74 +473,74 @@ system.cpu1.itb.flush_tlb 4 # Nu system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu1.itb.flush_entries 1228 # Number of entries that have been flushed from TLB +system.cpu1.itb.flush_entries 1327 # Number of entries that have been flushed from TLB system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 26945650 # ITB inst accesses -system.cpu1.itb.hits 26944447 # DTB hits -system.cpu1.itb.misses 1203 # DTB misses -system.cpu1.itb.accesses 26945650 # DTB accesses -system.cpu1.numCycles 1822760078 # number of cpu cycles simulated +system.cpu1.itb.inst_accesses 32414506 # ITB inst accesses +system.cpu1.itb.hits 32412306 # DTB hits +system.cpu1.itb.misses 2200 # DTB misses +system.cpu1.itb.accesses 32414506 # DTB accesses +system.cpu1.numCycles 1824154149 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 26714987 # Number of instructions committed -system.cpu1.committedOps 33555986 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 30087808 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 5643 # Number of float alu accesses -system.cpu1.num_func_calls 761024 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3301562 # number of instructions that are conditional controls -system.cpu1.num_int_insts 30087808 # number of integer instructions -system.cpu1.num_fp_insts 5643 # number of float instructions -system.cpu1.num_int_register_reads 152234781 # number of times the integer registers were read -system.cpu1.num_int_register_writes 32495677 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 3915 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 1728 # number of times the floating registers were written -system.cpu1.num_mem_refs 11031013 # number of memory refs -system.cpu1.num_load_insts 6247466 # Number of load instructions -system.cpu1.num_store_insts 4783547 # Number of store instructions -system.cpu1.num_idle_cycles 1788952556.347001 # Number of idle cycles -system.cpu1.num_busy_cycles 33807521.652999 # Number of busy cycles -system.cpu1.not_idle_fraction 0.018547 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.981453 # Percentage of idle cycles +system.cpu1.committedInsts 31875965 # Number of instructions committed +system.cpu1.committedOps 40213707 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 35797832 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 4436 # Number of float alu accesses +system.cpu1.num_func_calls 955227 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 4028429 # number of instructions that are conditional controls +system.cpu1.num_int_insts 35797832 # number of integer instructions +system.cpu1.num_fp_insts 4436 # number of float instructions +system.cpu1.num_int_register_reads 181634271 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39007898 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 3022 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 1416 # number of times the floating registers were written +system.cpu1.num_mem_refs 13370713 # number of memory refs +system.cpu1.num_load_insts 7642673 # Number of load instructions +system.cpu1.num_store_insts 5728040 # Number of store instructions +system.cpu1.num_idle_cycles 1783362859.317266 # Number of idle cycles +system.cpu1.num_busy_cycles 40791289.682734 # Number of busy cycles +system.cpu1.not_idle_fraction 0.022362 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.977638 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 31471 # number of quiesce instructions executed -system.cpu1.icache.replacements 365832 # number of replacements -system.cpu1.icache.tagsinuse 475.430525 # Cycle average of tags in use -system.cpu1.icache.total_refs 26579068 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 366344 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 72.552213 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 69967043000 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 475.430525 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.928575 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.928575 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 26579068 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 26579068 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 26579068 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 26579068 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 26579068 # number of overall hits -system.cpu1.icache.overall_hits::total 26579068 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 366344 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 366344 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 366344 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 366344 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 366344 # number of overall misses -system.cpu1.icache.overall_misses::total 366344 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 26945412 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 26945412 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 26945412 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 26945412 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 26945412 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 26945412 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013596 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.013596 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013596 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.013596 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013596 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.013596 # miss rate for overall accesses +system.cpu1.kern.inst.quiesce 40379 # number of quiesce instructions executed +system.cpu1.icache.replacements 433942 # number of replacements +system.cpu1.icache.tagsinuse 475.447912 # Cycle average of tags in use +system.cpu1.icache.total_refs 31979125 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 434454 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 73.607620 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 69967763000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 475.447912 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.928609 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 31979125 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 31979125 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 31979125 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 31979125 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 31979125 # number of overall hits +system.cpu1.icache.overall_hits::total 31979125 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 434454 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 434454 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 434454 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 434454 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 434454 # number of overall misses +system.cpu1.icache.overall_misses::total 434454 # number of overall misses +system.cpu1.icache.ReadReq_accesses::cpu1.inst 32413579 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 32413579 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 32413579 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 32413579 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 32413579 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 32413579 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013403 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013403 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013403 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013403 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013403 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013403 # miss rate for overall accesses system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -563,66 +549,64 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 15197 # number of writebacks -system.cpu1.icache.writebacks::total 15197 # number of writebacks system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 236700 # number of replacements -system.cpu1.dcache.tagsinuse 447.071707 # Cycle average of tags in use -system.cpu1.dcache.total_refs 9515102 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 237061 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 40.137779 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 67292773000 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 447.071707 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.873187 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.873187 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 5742078 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 5742078 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 3635346 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 3635346 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 56591 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 56591 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 56639 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 56639 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 9377424 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 9377424 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 9377424 # number of overall hits -system.cpu1.dcache.overall_hits::total 9377424 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 159026 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 159026 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 108254 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 108254 # number of WriteReq misses -system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 10539 # number of LoadLockedReq misses -system.cpu1.dcache.LoadLockedReq_misses::total 10539 # number of LoadLockedReq misses -system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10435 # number of StoreCondReq misses -system.cpu1.dcache.StoreCondReq_misses::total 10435 # number of StoreCondReq misses -system.cpu1.dcache.demand_misses::cpu1.data 267280 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 267280 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 267280 # number of overall misses -system.cpu1.dcache.overall_misses::total 267280 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 5901104 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 5901104 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 3743600 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 3743600 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 67130 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.LoadLockedReq_accesses::total 67130 # number of LoadLockedReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 67074 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.StoreCondReq_accesses::total 67074 # number of StoreCondReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 9644704 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 9644704 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 9644704 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 9644704 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.026949 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.026949 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.028917 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.028917 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.156994 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.156994 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.155574 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.155574 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027713 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.027713 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027713 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.027713 # miss rate for overall accesses +system.cpu1.dcache.replacements 294289 # number of replacements +system.cpu1.dcache.tagsinuse 447.573682 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11707745 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 294801 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 39.714061 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 67293493000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 447.573682 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.874167 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 7002209 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 7002209 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4520313 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4520313 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 77954 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 77954 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 79030 # number of StoreCondReq hits +system.cpu1.dcache.StoreCondReq_hits::total 79030 # number of StoreCondReq hits +system.cpu1.dcache.demand_hits::cpu1.data 11522522 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 11522522 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 11522522 # number of overall hits +system.cpu1.dcache.overall_hits::total 11522522 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 198275 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 198275 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 125920 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 125920 # number of WriteReq misses +system.cpu1.dcache.LoadLockedReq_misses::cpu1.data 11251 # number of LoadLockedReq misses +system.cpu1.dcache.LoadLockedReq_misses::total 11251 # number of LoadLockedReq misses +system.cpu1.dcache.StoreCondReq_misses::cpu1.data 10139 # number of StoreCondReq misses +system.cpu1.dcache.StoreCondReq_misses::total 10139 # number of StoreCondReq misses +system.cpu1.dcache.demand_misses::cpu1.data 324195 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 324195 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 324195 # number of overall misses +system.cpu1.dcache.overall_misses::total 324195 # number of overall misses +system.cpu1.dcache.ReadReq_accesses::cpu1.data 7200484 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 7200484 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 4646233 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 4646233 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::cpu1.data 89205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.LoadLockedReq_accesses::total 89205 # number of LoadLockedReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::cpu1.data 89169 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.StoreCondReq_accesses::total 89169 # number of StoreCondReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 11846717 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 11846717 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 11846717 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 11846717 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.027536 # miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_miss_rate::total 0.027536 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.027102 # miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_miss_rate::total 0.027102 # miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.126125 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.126125 # miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.113705 # miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_miss_rate::total 0.113705 # miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.027366 # miss rate for demand accesses +system.cpu1.dcache.demand_miss_rate::total 0.027366 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.027366 # miss rate for overall accesses +system.cpu1.dcache.overall_miss_rate::total 0.027366 # miss rate for overall accesses system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -631,8 +615,8 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 212705 # number of writebacks -system.cpu1.dcache.writebacks::total 212705 # number of writebacks +system.cpu1.dcache.writebacks::writebacks 266849 # number of writebacks +system.cpu1.dcache.writebacks::total 266849 # number of writebacks system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini index f14835c6b..59476048e 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini @@ -191,7 +191,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.realview.uart.pio system.realview.realview_io.pio system.realview.timer0.pio system.realview.timer1.pio system.realview.clcd.pio system.realview.kmi0.pio system.realview.kmi1.pio system.realview.cf_ctrl.pio system.realview.cf_ctrl.config system.realview.dmac_fake.pio system.realview.uart1_fake.pio system.realview.uart2_fake.pio system.realview.uart3_fake.pio system.realview.smc_fake.pio system.realview.sp810_fake.pio system.realview.watchdog_fake.pio system.realview.gpio0_fake.pio system.realview.gpio1_fake.pio system.realview.gpio2_fake.pio system.realview.ssp_fake.pio system.realview.sci_fake.pio system.realview.aaci_fake.pio system.realview.mmc_fake.pio system.realview.rtc.pio system.realview.flash_fake.pio system.iocache.cpu_side slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma @@ -252,9 +252,9 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] @@ -665,7 +665,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 master=system.l2c.cpu_side slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout index 4dbfc774f..5f92f06af 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 28 2012 22:10:14 -gem5 started Jun 29 2012 00:35:36 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:54:29 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2332330037000 because m5_exit instruction encountered +Exiting @ tick 2332810264000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt index 176436ee7..e8bc29aac 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt @@ -1,54 +1,54 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.332330 # Number of seconds simulated -sim_ticks 2332330037000 # Number of ticks simulated -final_tick 2332330037000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.332810 # Number of seconds simulated +sim_ticks 2332810264000 # Number of ticks simulated +final_tick 2332810264000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1988795 # Simulator instruction rate (inst/s) -host_op_rate 2567201 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 78099767101 # Simulator tick rate (ticks/s) -host_mem_usage 382744 # Number of bytes of host memory used -host_seconds 29.86 # Real time elapsed on the host -sim_insts 59392246 # Number of instructions simulated -sim_ops 76665494 # Number of ops (including micro ops) simulated +host_inst_rate 1498673 # Simulator instruction rate (inst/s) +host_op_rate 1927201 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 57874436068 # Simulator tick rate (ticks/s) +host_mem_usage 388524 # Number of bytes of host memory used +host_seconds 40.31 # Real time elapsed on the host +sim_insts 60408639 # Number of instructions simulated +sim_ops 77681819 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 111673344 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9071568 # Number of bytes read from this memory -system.physmem.bytes_read::total 121450416 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704992 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3703040 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9071632 # Number of bytes read from this memory +system.physmem.bytes_read::total 121450608 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3703232 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3015816 # Number of bytes written to this memory -system.physmem.bytes_written::total 6718856 # Number of bytes written to this memory +system.physmem.bytes_written::total 6719048 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 13959168 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17218 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141777 # Number of read requests responded to by this memory -system.physmem.num_reads::total 14118171 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57860 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141778 # Number of read requests responded to by this memory +system.physmem.num_reads::total 14118174 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57863 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 753954 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811814 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47880592 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811817 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47870736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 137 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 82 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 302269 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3889487 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52072569 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 302269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 302269 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1587700 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1293049 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2880748 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1587700 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47880592 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 302262 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3888714 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52061931 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 302262 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1587455 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1292782 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2880238 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1587455 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47870736 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 137 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 82 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 302269 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 5182536 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 54953317 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 302262 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 5181496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 54942169 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory @@ -61,103 +61,103 @@ system.realview.nvmem.bw_inst_read::cpu.inst 9 system.realview.nvmem.bw_inst_read::total 9 # Instruction read bandwidth from this memory (bytes/s) system.realview.nvmem.bw_total::cpu.inst 9 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 9 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 62240 # number of replacements -system.l2c.tagsinuse 50004.786190 # Cycle average of tags in use -system.l2c.total_refs 1717775 # Total number of references to valid blocks. -system.l2c.sampled_refs 127625 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.459549 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2316513323500 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 36897.037256 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 2.960071 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.itb.walker 0.993930 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 7014.608709 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6089.186223 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.563004 # Average percentage of cache occupancy +system.l2c.replacements 62243 # number of replacements +system.l2c.tagsinuse 50007.272909 # Cycle average of tags in use +system.l2c.total_refs 1669922 # Total number of references to valid blocks. +system.l2c.sampled_refs 127628 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.084292 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2316901489000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 36899.582990 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 2.960148 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.itb.walker 0.993931 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.inst 7014.720482 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6089.015357 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.563043 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000045 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.107034 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.092914 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.763012 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 7534 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.itb.walker 3151 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 838895 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 364444 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1214024 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 642748 # number of Writeback hits -system.l2c.Writeback_hits::total 642748 # number of Writeback hits +system.l2c.occ_percent::cpu.inst 0.107036 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.092911 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.763050 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 7507 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.itb.walker 3129 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.inst 838871 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 366771 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1216278 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 592643 # number of Writeback hits +system.l2c.Writeback_hits::total 592643 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 113737 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 113737 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 7534 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.itb.walker 3151 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 838895 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 478181 # number of demand (read+write) hits -system.l2c.demand_hits::total 1327761 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 7534 # number of overall hits -system.l2c.overall_hits::cpu.itb.walker 3151 # number of overall hits -system.l2c.overall_hits::cpu.inst 838895 # number of overall hits -system.l2c.overall_hits::cpu.data 478181 # number of overall hits -system.l2c.overall_hits::total 1327761 # number of overall hits +system.l2c.ReadExReq_hits::cpu.data 113739 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 113739 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 7507 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.itb.walker 3129 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.inst 838871 # number of demand (read+write) hits +system.l2c.demand_hits::cpu.data 480510 # number of demand (read+write) hits +system.l2c.demand_hits::total 1330017 # number of demand (read+write) hits +system.l2c.overall_hits::cpu.dtb.walker 7507 # number of overall hits +system.l2c.overall_hits::cpu.itb.walker 3129 # number of overall hits +system.l2c.overall_hits::cpu.inst 838871 # number of overall hits +system.l2c.overall_hits::cpu.data 480510 # number of overall hits +system.l2c.overall_hits::total 1330017 # number of overall hits system.l2c.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses system.l2c.ReadReq_misses::cpu.itb.walker 3 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.inst 10602 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu.data 9870 # number of ReadReq misses -system.l2c.ReadReq_misses::total 20480 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu.data 2918 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 2918 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu.data 133469 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 133469 # number of ReadExReq misses +system.l2c.ReadReq_misses::cpu.inst 10604 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu.data 9871 # number of ReadReq misses +system.l2c.ReadReq_misses::total 20483 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu.data 2919 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 2919 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu.data 133468 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 133468 # number of ReadExReq misses system.l2c.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses system.l2c.demand_misses::cpu.itb.walker 3 # number of demand (read+write) misses -system.l2c.demand_misses::cpu.inst 10602 # number of demand (read+write) misses +system.l2c.demand_misses::cpu.inst 10604 # number of demand (read+write) misses system.l2c.demand_misses::cpu.data 143339 # number of demand (read+write) misses -system.l2c.demand_misses::total 153949 # number of demand (read+write) misses +system.l2c.demand_misses::total 153951 # number of demand (read+write) misses system.l2c.overall_misses::cpu.dtb.walker 5 # number of overall misses system.l2c.overall_misses::cpu.itb.walker 3 # number of overall misses -system.l2c.overall_misses::cpu.inst 10602 # number of overall misses +system.l2c.overall_misses::cpu.inst 10604 # number of overall misses system.l2c.overall_misses::cpu.data 143339 # number of overall misses -system.l2c.overall_misses::total 153949 # number of overall misses -system.l2c.ReadReq_accesses::cpu.dtb.walker 7539 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.itb.walker 3154 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.inst 849497 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu.data 374314 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1234504 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 642748 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 642748 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu.data 2944 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 2944 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu.data 247206 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 247206 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu.dtb.walker 7539 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.itb.walker 3154 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.inst 849497 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu.data 621520 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1481710 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu.dtb.walker 7539 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.itb.walker 3154 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.inst 849497 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu.data 621520 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1481710 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000663 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000951 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.inst 0.012480 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu.data 0.026368 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.016590 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu.data 0.991168 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.991168 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu.data 0.539910 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.539910 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu.dtb.walker 0.000663 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.itb.walker 0.000951 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.inst 0.012480 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu.data 0.230627 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.103900 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu.dtb.walker 0.000663 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.itb.walker 0.000951 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.inst 0.012480 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu.data 0.230627 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.103900 # miss rate for overall accesses +system.l2c.overall_misses::total 153951 # number of overall misses +system.l2c.ReadReq_accesses::cpu.dtb.walker 7512 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.itb.walker 3132 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.inst 849475 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu.data 376642 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 1236761 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 592643 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 592643 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu.data 2945 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2945 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu.data 247207 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 247207 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu.dtb.walker 7512 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.itb.walker 3132 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.inst 849475 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu.data 623849 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 1483968 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu.dtb.walker 7512 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.itb.walker 3132 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.inst 849475 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu.data 623849 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 1483968 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu.dtb.walker 0.000666 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.itb.walker 0.000958 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.inst 0.012483 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu.data 0.026208 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.016562 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu.data 0.991171 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.991171 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu.data 0.539904 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.539904 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu.dtb.walker 0.000666 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.itb.walker 0.000958 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.inst 0.012483 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu.data 0.229766 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.103743 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu.dtb.walker 0.000666 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.itb.walker 0.000958 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.inst 0.012483 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu.data 0.229766 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.103743 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -166,8 +166,8 @@ system.l2c.avg_blocked_cycles::no_mshrs nan # av system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 57860 # number of writebacks -system.l2c.writebacks::total 57860 # number of writebacks +system.l2c.writebacks::writebacks 57863 # number of writebacks +system.l2c.writebacks::total 57863 # number of writebacks system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). @@ -177,26 +177,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14971229 # DTB read hits -system.cpu.dtb.read_misses 7293 # DTB read misses -system.cpu.dtb.write_hits 11217018 # DTB write hits +system.cpu.dtb.read_hits 14971214 # DTB read hits +system.cpu.dtb.read_misses 7294 # DTB read misses +system.cpu.dtb.write_hits 11217004 # DTB write hits system.cpu.dtb.write_misses 2181 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3492 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3496 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 174 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 14978522 # DTB read accesses -system.cpu.dtb.write_accesses 11219199 # DTB write accesses +system.cpu.dtb.read_accesses 14978508 # DTB read accesses +system.cpu.dtb.write_accesses 11219185 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26188247 # DTB hits -system.cpu.dtb.misses 9474 # DTB misses -system.cpu.dtb.accesses 26197721 # DTB accesses -system.cpu.itb.inst_hits 60403303 # ITB inst hits +system.cpu.dtb.hits 26188218 # DTB hits +system.cpu.dtb.misses 9475 # DTB misses +system.cpu.dtb.accesses 26197693 # DTB accesses +system.cpu.itb.inst_hits 61431840 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -213,67 +213,67 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60407774 # ITB inst accesses -system.cpu.itb.hits 60403303 # DTB hits +system.cpu.itb.inst_accesses 61436311 # ITB inst accesses +system.cpu.itb.hits 61431840 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60407774 # DTB accesses -system.cpu.numCycles 4664583062 # number of cpu cycles simulated +system.cpu.itb.accesses 61436311 # DTB accesses +system.cpu.numCycles 4665543516 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59392246 # Number of instructions committed -system.cpu.committedOps 76665494 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68281415 # Number of integer alu accesses +system.cpu.committedInsts 60408639 # Number of instructions committed +system.cpu.committedOps 77681819 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68795605 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2136013 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7647793 # number of instructions that are conditional controls -system.cpu.num_int_insts 68281415 # number of integer instructions +system.cpu.num_func_calls 2136008 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7904929 # number of instructions that are conditional controls +system.cpu.num_int_insts 68795605 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 345981857 # number of times the integer registers were read -system.cpu.num_int_register_writes 73062916 # number of times the integer registers were written +system.cpu.num_int_register_reads 349324274 # number of times the integer registers were read +system.cpu.num_int_register_writes 74103608 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27361692 # number of memory refs -system.cpu.num_load_insts 15639569 # Number of load instructions -system.cpu.num_store_insts 11722123 # Number of store instructions -system.cpu.num_idle_cycles 4586814358.980880 # Number of idle cycles -system.cpu.num_busy_cycles 77768703.019120 # Number of busy cycles -system.cpu.not_idle_fraction 0.016672 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.983328 # Percentage of idle cycles +system.cpu.num_mem_refs 27361637 # number of memory refs +system.cpu.num_load_insts 15639527 # Number of load instructions +system.cpu.num_store_insts 11722110 # Number of store instructions +system.cpu.num_idle_cycles 4586746360.692756 # Number of idle cycles +system.cpu.num_busy_cycles 78797155.307244 # Number of busy cycles +system.cpu.not_idle_fraction 0.016889 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.983111 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82795 # number of quiesce instructions executed -system.cpu.icache.replacements 850612 # number of replacements -system.cpu.icache.tagsinuse 511.678549 # Cycle average of tags in use -system.cpu.icache.total_refs 59554939 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 851124 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 69.972106 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 5708999000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 511.678549 # Average occupied blocks per requestor +system.cpu.icache.replacements 850590 # number of replacements +system.cpu.icache.tagsinuse 511.678593 # Cycle average of tags in use +system.cpu.icache.total_refs 60583498 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 851102 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 71.182418 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 5709383000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 511.678593 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.999372 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.999372 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59554939 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59554939 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59554939 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59554939 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59554939 # number of overall hits -system.cpu.icache.overall_hits::total 59554939 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 851124 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 851124 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 851124 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 851124 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 851124 # number of overall misses -system.cpu.icache.overall_misses::total 851124 # number of overall misses -system.cpu.icache.ReadReq_accesses::cpu.inst 60406063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60406063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60406063 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60406063 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60406063 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60406063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014090 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014090 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014090 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014090 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014090 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014090 # miss rate for overall accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60583498 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60583498 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60583498 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60583498 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60583498 # number of overall hits +system.cpu.icache.overall_hits::total 60583498 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 851102 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 851102 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 851102 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 851102 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 851102 # number of overall misses +system.cpu.icache.overall_misses::total 851102 # number of overall misses +system.cpu.icache.ReadReq_accesses::cpu.inst 61434600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61434600 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61434600 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61434600 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61434600 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61434600 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013854 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013854 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013854 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013854 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013854 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013854 # miss rate for overall accesses system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -282,58 +282,56 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 50093 # number of writebacks -system.cpu.icache.writebacks::total 50093 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 623347 # number of replacements -system.cpu.dcache.tagsinuse 511.997030 # Cycle average of tags in use -system.cpu.dcache.total_refs 23628362 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 623859 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.874523 # Average number of references to valid blocks. +system.cpu.dcache.replacements 623337 # number of replacements +system.cpu.dcache.tagsinuse 511.997031 # Cycle average of tags in use +system.cpu.dcache.total_refs 23628343 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 623849 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.875100 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 21763000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.997030 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.997031 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999994 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13180074 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13180074 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9962087 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9962087 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236035 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236035 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247222 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247222 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23142161 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23142161 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23142161 # number of overall hits -system.cpu.dcache.overall_hits::total 23142161 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 365465 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 365465 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 250150 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 250150 # number of WriteReq misses -system.cpu.dcache.LoadLockedReq_misses::cpu.data 11188 # number of LoadLockedReq misses -system.cpu.dcache.LoadLockedReq_misses::total 11188 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 615615 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 615615 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 615615 # number of overall misses -system.cpu.dcache.overall_misses::total 615615 # number of overall misses -system.cpu.dcache.ReadReq_accesses::cpu.data 13545539 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 13545539 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 10212237 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 10212237 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247223 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.LoadLockedReq_accesses::total 247223 # number of LoadLockedReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::cpu.data 247222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.StoreCondReq_accesses::total 247222 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 23757776 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 23757776 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 23757776 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 23757776 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_hits::cpu.data 13180066 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13180066 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9962072 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9962072 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236039 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236039 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 247221 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 247221 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 23142138 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 23142138 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 23142138 # number of overall hits +system.cpu.dcache.overall_hits::total 23142138 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 365459 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 365459 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 250152 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 250152 # number of WriteReq misses +system.cpu.dcache.LoadLockedReq_misses::cpu.data 11183 # number of LoadLockedReq misses +system.cpu.dcache.LoadLockedReq_misses::total 11183 # number of LoadLockedReq misses +system.cpu.dcache.demand_misses::cpu.data 615611 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 615611 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 615611 # number of overall misses +system.cpu.dcache.overall_misses::total 615611 # number of overall misses +system.cpu.dcache.ReadReq_accesses::cpu.data 13545525 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13545525 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10212224 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10212224 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247222 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247221 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247221 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23757749 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 23757749 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 23757749 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 23757749 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.026980 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024495 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.024495 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045255 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045255 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.045235 # miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_miss_rate::total 0.045235 # miss rate for LoadLockedReq accesses system.cpu.dcache.demand_miss_rate::cpu.data 0.025912 # miss rate for demand accesses system.cpu.dcache.demand_miss_rate::total 0.025912 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.025912 # miss rate for overall accesses @@ -346,8 +344,8 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 592655 # number of writebacks -system.cpu.dcache.writebacks::total 592655 # number of writebacks +system.cpu.dcache.writebacks::writebacks 592643 # number of writebacks +system.cpu.dcache.writebacks::total 592643 # number of writebacks system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index 363bd4c66..f88222537 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -361,7 +361,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 70032b595..3225b7372 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:21:03 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:58:01 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1171612619000 because m5_exit instruction encountered +Exiting @ tick 1172544977000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index bf3a52c45..2693ffabe 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,71 +1,71 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.171613 # Number of seconds simulated -sim_ticks 1171612619000 # Number of ticks simulated -final_tick 1171612619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.172545 # Number of seconds simulated +sim_ticks 1172544977000 # Number of ticks simulated +final_tick 1172544977000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 639669 # Simulator instruction rate (inst/s) -host_op_rate 818158 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12399663305 # Simulator tick rate (ticks/s) -host_mem_usage 384708 # Number of bytes of host memory used -host_seconds 94.49 # Real time elapsed on the host -sim_insts 60440687 # Number of instructions simulated -sim_ops 77305655 # Number of ops (including micro ops) simulated +host_inst_rate 706392 # Simulator instruction rate (inst/s) +host_op_rate 900233 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 13469238975 # Simulator tick rate (ticks/s) +host_mem_usage 389548 # Number of bytes of host memory used +host_seconds 87.05 # Real time elapsed on the host +sim_insts 61493926 # Number of instructions simulated +sim_ops 78368454 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 50331648 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 395940 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4717108 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 394788 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4717236 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 321948 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4794672 # Number of bytes read from this memory -system.physmem.bytes_read::total 60561764 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 395940 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 321948 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 717888 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4107520 # Number of bytes written to this memory +system.physmem.bytes_read::cpu1.inst 322588 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1.data 4794736 # Number of bytes read from this memory +system.physmem.bytes_read::total 60561444 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 394788 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::cpu1.inst 322588 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 717376 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4107264 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7134864 # Number of bytes written to this memory +system.physmem.bytes_written::total 7134608 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6291456 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12405 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73777 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12387 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73779 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 5112 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74943 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6457700 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 64180 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.inst 5122 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu1.data 74944 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6457695 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64176 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 821016 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 42959291 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821012 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 42925132 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 55 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 109 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 337944 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 4026167 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.dtb.walker 219 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 274790 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4092370 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51690945 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 337944 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 274790 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 612735 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3505869 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0.data 14510 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2569402 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6089781 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3505869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 42959291 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 336693 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 4023075 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.dtb.walker 218 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 275118 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4089170 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51649570 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 336693 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 275118 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 611811 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3502863 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0.data 14498 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2567359 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6084720 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3502863 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 42925132 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 55 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 109 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 337944 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 4040677 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.dtb.walker 219 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 274790 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6661772 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 57780726 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 336693 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4037573 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.dtb.walker 218 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 275118 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6656529 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 57734290 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory @@ -84,237 +84,237 @@ system.realview.nvmem.bw_inst_read::total 58 # I system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) system.realview.nvmem.bw_total::total 58 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 69306 # number of replacements -system.l2c.tagsinuse 52659.016481 # Cycle average of tags in use -system.l2c.total_refs 1685686 # Total number of references to valid blocks. -system.l2c.sampled_refs 134505 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.532516 # Average number of references to valid blocks. +system.l2c.replacements 69301 # number of replacements +system.l2c.tagsinuse 52667.431766 # Cycle average of tags in use +system.l2c.total_refs 1645571 # Total number of references to valid blocks. +system.l2c.sampled_refs 134500 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.234729 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39891.573384 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 39900.139395 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000282 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.itb.walker 0.001243 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3742.951187 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4216.912189 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.733680 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2750.765696 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2054.078820 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.608697 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.itb.walker 0.001242 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 3730.644795 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 4216.663550 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.dtb.walker 2.734150 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 2763.076938 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 2054.171414 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.608828 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.057113 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.064345 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.056925 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.064341 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000042 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.041973 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.031343 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.803513 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.dtb.walker 4104 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.itb.walker 1844 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.inst 401511 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 204865 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.dtb.walker 5725 # number of ReadReq hits +system.l2c.occ_percent::cpu1.inst 0.042161 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.031344 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.803641 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.dtb.walker 4102 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.itb.walker 1845 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.inst 402958 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 205810 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.dtb.walker 5738 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.itb.walker 1962 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 448415 # 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number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 163025407000 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1.data 152778471500 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 163057732999 # number of overall MSHR uncacheable cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036972 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.036813 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024809 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.018083 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.799863 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.861010 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.825228 # mshr miss rate for UpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.728682 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.825862 # mshr miss rate for SCUpgradeReq accesses -system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.770310 # mshr miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541912 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577444 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.559780 # mshr miss rate for ReadExReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.024649 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.018015 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.805765 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.859632 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.828292 # mshr miss rate for UpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu0.data 0.733850 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::cpu1.data 0.827243 # mshr miss rate for SCUpgradeReq accesses +system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.774709 # mshr miss rate for SCUpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 0.541889 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.577121 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.559610 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.109125 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.108805 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu0.dtb.walker 0.000244 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu0.itb.walker 0.001083 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014172 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu0.data 0.222857 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000698 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.014078 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.222234 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000697 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu1.inst 0.011082 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1.data 0.279216 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.109125 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.278174 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.108805 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40042.593770 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40037.757437 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40133.296764 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40100.201658 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40036.203942 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40064.570466 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40048.481166 # average UpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40058.510638 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40100.208768 # average SCUpgradeReq mshr miss latency -system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40077.660594 # average SCUpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40018.469716 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40066.829666 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40043.555680 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40135.216676 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40104.043393 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40031.090290 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40068.036656 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40047.125467 # average UpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 40052.816901 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 40066.265060 # average SCUpgradeReq mshr miss latency +system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 40059.099437 # average SCUpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40015.975583 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40062.463740 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40040.090571 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu0.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40116.424116 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40020.998547 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40102.015989 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40018.259120 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40147.860697 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40070.016702 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40051.364658 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40187.487587 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40065.952130 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40048.904347 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -498,9 +498,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7077919 # DTB read hits -system.cpu0.dtb.read_misses 3740 # DTB read misses -system.cpu0.dtb.write_hits 5661726 # DTB write hits +system.cpu0.dtb.read_hits 7082876 # DTB read hits +system.cpu0.dtb.read_misses 3736 # DTB read misses +system.cpu0.dtb.write_hits 5665319 # DTB write hits system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -511,13 +511,13 @@ system.cpu0.dtb.align_faults 0 # Nu system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7081659 # DTB read accesses -system.cpu0.dtb.write_accesses 5662530 # DTB write accesses +system.cpu0.dtb.read_accesses 7086612 # DTB read accesses +system.cpu0.dtb.write_accesses 5666123 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12739645 # DTB hits -system.cpu0.dtb.misses 4544 # DTB misses -system.cpu0.dtb.accesses 12744189 # DTB accesses -system.cpu0.itb.inst_hits 29451654 # ITB inst hits +system.cpu0.dtb.hits 12748195 # DTB hits +system.cpu0.dtb.misses 4540 # DTB misses +system.cpu0.dtb.accesses 12752735 # DTB accesses +system.cpu0.itb.inst_hits 29606138 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -534,79 +534,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29453859 # ITB inst accesses -system.cpu0.itb.hits 29451654 # DTB hits +system.cpu0.itb.inst_accesses 29608343 # ITB inst accesses +system.cpu0.itb.hits 29606138 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29453859 # DTB accesses -system.cpu0.numCycles 2343225238 # number of cpu cycles simulated +system.cpu0.itb.accesses 29608343 # DTB accesses +system.cpu0.numCycles 2345089954 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28759206 # Number of instructions committed -system.cpu0.committedOps 37112849 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33058293 # Number of integer alu accesses +system.cpu0.committedInsts 28907917 # Number of instructions committed +system.cpu0.committedOps 37265600 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33149705 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1242118 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4322812 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33058293 # number of integer instructions +system.cpu0.num_func_calls 1243107 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4358822 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33149705 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 189772382 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36110779 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190344582 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36275228 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13408219 # number of memory refs -system.cpu0.num_load_insts 7415624 # Number of load instructions -system.cpu0.num_store_insts 5992595 # Number of store instructions -system.cpu0.num_idle_cycles 2203054927.350120 # Number of idle cycles -system.cpu0.num_busy_cycles 140170310.649880 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059819 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940181 # Percentage of idle cycles +system.cpu0.num_mem_refs 13418689 # number of memory refs +system.cpu0.num_load_insts 7420825 # Number of load instructions +system.cpu0.num_store_insts 5997864 # Number of store instructions +system.cpu0.num_idle_cycles 2204555139.350120 # Number of idle cycles +system.cpu0.num_busy_cycles 140534814.649880 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059927 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940073 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46686 # number of quiesce instructions executed -system.cpu0.icache.replacements 408292 # number of replacements -system.cpu0.icache.tagsinuse 509.494086 # Cycle average of tags in use -system.cpu0.icache.total_refs 29042833 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 408804 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 71.043417 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 75128321000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.494086 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995106 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995106 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29042833 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29042833 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29042833 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29042833 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29042833 # number of overall hits -system.cpu0.icache.overall_hits::total 29042833 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 408804 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 408804 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 408804 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 408804 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 408804 # number of overall misses -system.cpu0.icache.overall_misses::total 408804 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 6099412500 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 6099412500 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 6099412500 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 6099412500 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 6099412500 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 6099412500 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29451637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29451637 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29451637 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29451637 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29451637 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29451637 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013881 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.013881 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013881 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.013881 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013881 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.013881 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14920.138991 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 14920.138991 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 14920.138991 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14920.138991 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 14920.138991 # average overall miss latency +system.cpu0.kern.inst.quiesce 46687 # number of quiesce instructions executed +system.cpu0.icache.replacements 408797 # number of replacements +system.cpu0.icache.tagsinuse 509.495989 # Cycle average of tags in use +system.cpu0.icache.total_refs 29196812 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 409309 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 71.331957 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 75128897000 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 509.495989 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995109 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995109 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29196812 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29196812 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29196812 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29196812 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29196812 # number of overall hits +system.cpu0.icache.overall_hits::total 29196812 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 409309 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 409309 # 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number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29606121 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29606121 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29606121 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29606121 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.013825 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.013825 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.013825 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.013825 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.013825 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.013825 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14923.131424 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 14923.131424 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 14923.131424 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14923.131424 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 14923.131424 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -615,122 +615,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # 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number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4872150503 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4872150503 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 409309 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 409309 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 409309 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 409309 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 409309 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 409309 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4879387500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4879387500 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4879387500 # 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mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.013881 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013881 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.013881 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11918.059762 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11918.059762 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11918.059762 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.013825 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.013825 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.013825 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.013825 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11921.036430 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11921.036430 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11921.036430 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330880 # number of replacements -system.cpu0.dcache.tagsinuse 457.764906 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12284019 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331392 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.067941 # 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miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15067.400655 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 15067.400655 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34695.548484 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 34695.548484 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10826.838196 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10826.838196 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9933.315551 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9933.315551 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 22590.030720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22590.030720 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 22590.030720 # average overall miss latency +system.cpu0.dcache.occ_blocks::cpu0.data 457.939353 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.894413 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.894413 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 6612408 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 6612408 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 5360091 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 5360091 # number of WriteReq hits +system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147992 # number of LoadLockedReq hits +system.cpu0.dcache.LoadLockedReq_hits::total 147992 # number of LoadLockedReq hits +system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149726 # number of StoreCondReq hits +system.cpu0.dcache.StoreCondReq_hits::total 149726 # number of StoreCondReq hits +system.cpu0.dcache.demand_hits::cpu0.data 11972499 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 11972499 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 11972499 # number of overall hits +system.cpu0.dcache.overall_hits::total 11972499 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 228125 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 228125 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 141749 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 141749 # number of WriteReq misses +system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 9279 # number of LoadLockedReq misses +system.cpu0.dcache.LoadLockedReq_misses::total 9279 # number of LoadLockedReq misses +system.cpu0.dcache.StoreCondReq_misses::cpu0.data 7492 # number of StoreCondReq misses +system.cpu0.dcache.StoreCondReq_misses::total 7492 # number of StoreCondReq misses +system.cpu0.dcache.demand_misses::cpu0.data 369874 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369874 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369874 # number of overall misses +system.cpu0.dcache.overall_misses::total 369874 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3443081500 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3443081500 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4917870500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4917870500 # number of WriteReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::cpu0.data 100339500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.LoadLockedReq_miss_latency::total 100339500 # number of LoadLockedReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::cpu0.data 74628000 # number of StoreCondReq miss cycles +system.cpu0.dcache.StoreCondReq_miss_latency::total 74628000 # number of StoreCondReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 8360952000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 8360952000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 8360952000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 8360952000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 6840533 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 6840533 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 5501840 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 5501840 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 157271 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.LoadLockedReq_accesses::total 157271 # number of LoadLockedReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 157218 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.StoreCondReq_accesses::total 157218 # number of StoreCondReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 12342373 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 12342373 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 12342373 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 12342373 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033349 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033349 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059000 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059000 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047654 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047654 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029968 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029968 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029968 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029968 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 15092.960000 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 15092.960000 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 34694.216538 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 34694.216538 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 10813.611381 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10813.611381 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 9961.025093 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 9961.025093 # average StoreCondReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 22604.865441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 22604.865441 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 22604.865441 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -739,62 +737,62 @@ system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.dcache.fast_writes 0 # number of fast writes performed system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 306522 # number of writebacks -system.cpu0.dcache.writebacks::total 306522 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228069 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 228069 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141727 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141727 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9289 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7492 # number of StoreCondReq MSHR misses -system.cpu0.dcache.StoreCondReq_mshr_misses::total 7492 # number of StoreCondReq MSHR misses -system.cpu0.dcache.demand_mshr_misses::cpu0.data 369796 # number of demand (read+write) MSHR misses -system.cpu0.dcache.demand_mshr_misses::total 369796 # number of demand (read+write) MSHR misses -system.cpu0.dcache.overall_mshr_misses::cpu0.data 369796 # number of overall MSHR misses -system.cpu0.dcache.overall_mshr_misses::total 369796 # number of overall MSHR misses -system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2751577168 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2751577168 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4491927564 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4491927564 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72683507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72683507 # number of LoadLockedReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 51983021 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 51983021 # number of StoreCondReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7243504732 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 7243504732 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7243504732 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 7243504732 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10423590500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10423590500 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819778500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819778500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11243369000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11243369000 # number of overall MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033365 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033365 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025777 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025777 # mshr miss rate for WriteReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059059 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059059 # mshr miss rate for LoadLockedReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047650 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047650 # mshr miss rate for StoreCondReq accesses -system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for demand accesses -system.cpu0.dcache.demand_mshr_miss_rate::total 0.029982 # mshr miss rate for demand accesses -system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029982 # mshr miss rate for overall accesses -system.cpu0.dcache.overall_mshr_miss_rate::total 0.029982 # mshr miss rate for overall accesses -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12064.669762 # average ReadReq mshr miss latency -system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12064.669762 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31694.225970 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31694.225970 # average WriteReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7824.685865 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7824.685865 # average LoadLockedReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6938.470502 # average StoreCondReq mshr miss latency -system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6938.470502 # average StoreCondReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19587.839598 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19587.839598 # average overall mshr miss latency +system.cpu0.dcache.writebacks::writebacks 306322 # number of writebacks +system.cpu0.dcache.writebacks::total 306322 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 228125 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 228125 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141749 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 141749 # number of WriteReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9279 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9279 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 7485 # number of StoreCondReq MSHR misses +system.cpu0.dcache.StoreCondReq_mshr_misses::total 7485 # number of StoreCondReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 369874 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 369874 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 369874 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 369874 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 2758091164 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2758091164 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4492431566 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4492431566 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 72483506 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 72483506 # number of LoadLockedReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 52154019 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 52154019 # number of StoreCondReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 7250522730 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 7250522730 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 7250522730 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 7250522730 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 10425846000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 10425846000 # number of ReadReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 819721500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 819721500 # number of WriteReq MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 11245567500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 11245567500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033349 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033349 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059000 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059000 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047609 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047609 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029968 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029968 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029968 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 12090.262637 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12090.262637 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 31692.862496 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 31692.862496 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7811.564393 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7811.564393 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 6967.804810 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 6967.804810 # average StoreCondReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 19602.682887 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19602.682887 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -804,9 +802,9 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8311872 # DTB read hits -system.cpu1.dtb.read_misses 3663 # DTB read misses -system.cpu1.dtb.write_hits 5828412 # DTB write hits +system.cpu1.dtb.read_hits 8314117 # DTB read hits +system.cpu1.dtb.read_misses 3669 # DTB read misses +system.cpu1.dtb.write_hits 5830380 # DTB write hits system.cpu1.dtb.write_misses 1436 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -817,13 +815,13 @@ system.cpu1.dtb.align_faults 0 # Nu system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8315535 # DTB read accesses -system.cpu1.dtb.write_accesses 5829848 # DTB write accesses +system.cpu1.dtb.read_accesses 8317786 # DTB read accesses +system.cpu1.dtb.write_accesses 5831816 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14140284 # DTB hits -system.cpu1.dtb.misses 5099 # DTB misses -system.cpu1.dtb.accesses 14145383 # DTB accesses -system.cpu1.itb.inst_hits 32285286 # ITB inst hits +system.cpu1.dtb.hits 14144497 # DTB hits +system.cpu1.dtb.misses 5105 # DTB misses +system.cpu1.dtb.accesses 14149602 # DTB accesses +system.cpu1.itb.inst_hits 33196626 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -840,79 +838,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 32287457 # ITB inst accesses -system.cpu1.itb.hits 32285286 # DTB hits +system.cpu1.itb.inst_accesses 33198797 # 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number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3487066 # number of instructions that are conditional controls -system.cpu1.num_int_insts 36864445 # number of integer instructions +system.cpu1.num_func_calls 962171 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3714570 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37326288 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 210742691 # number of times the integer registers were read -system.cpu1.num_int_register_writes 38544620 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213739964 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39466250 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # 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number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 31830341 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 31830341 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 31830341 # number of overall hits -system.cpu1.icache.overall_hits::total 31830341 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 454941 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 454941 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 454941 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 454941 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 454941 # number of overall misses -system.cpu1.icache.overall_misses::total 454941 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6716097000 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6716097000 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6716097000 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6716097000 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6716097000 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6716097000 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 32285282 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 32285282 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 32285282 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 32285282 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 32285282 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 32285282 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014091 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014091 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014091 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014091 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014091 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014091 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14762.567014 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 14762.567014 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14762.567014 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 14762.567014 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14762.567014 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 14762.567014 # average overall miss latency +system.cpu1.kern.inst.quiesce 43921 # number of quiesce instructions executed +system.cpu1.icache.replacements 454393 # number of replacements +system.cpu1.icache.tagsinuse 478.384673 # Cycle average of tags in use +system.cpu1.icache.total_refs 32741717 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 454905 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 71.974845 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92994898000 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.384673 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.934345 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.934345 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 32741717 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32741717 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32741717 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32741717 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32741717 # number of overall hits +system.cpu1.icache.overall_hits::total 32741717 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 454905 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 454905 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 454905 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 454905 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 454905 # number of overall misses +system.cpu1.icache.overall_misses::total 454905 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6718353500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6718353500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6718353500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6718353500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6718353500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6718353500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33196622 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33196622 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33196622 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33196622 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33196622 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33196622 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.013703 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.013703 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.013703 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.013703 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.013703 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.013703 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 14768.695662 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 14768.695662 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 14768.695662 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 14768.695662 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 14768.695662 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -921,122 +919,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.writebacks::writebacks 23436 # number of writebacks -system.cpu1.icache.writebacks::total 23436 # number of writebacks -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454941 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 454941 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 454941 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 454941 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 454941 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 454941 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5350372502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5350372502 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5350372502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5350372502 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5350372502 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5350372502 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 454905 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 454905 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 454905 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 454905 # 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number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 5250000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 5250000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014091 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014091 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014091 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014091 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11760.585443 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11760.585443 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11760.585443 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11760.585443 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.013703 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.013703 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.013703 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.013703 # 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average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 23422.060587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23422.060587 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 23422.060587 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1045,62 +1041,62 @@ system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.dcache.fast_writes 0 # number of fast writes performed system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.writebacks::writebacks 266082 # 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number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 73165002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 73165002 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 58182011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 58182011 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6555140807 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6555140807 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6555140807 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6555140807 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 136477204500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 136477204500 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 39709759000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 39709759000 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 176186963500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 176186963500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023984 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030173 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030173 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119575 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108423 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108423 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026531 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026531 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026531 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10906.460484 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10906.460484 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 31230.662895 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 31230.662895 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6584.323434 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6584.323434 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5779.478593 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5779.478593 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 20419.409102 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 20419.409102 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1122,10 +1118,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550047772786 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 550047772786 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550047772786 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 550047772786 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 550791407487 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 550791407487 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 550791407487 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 550791407487 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index b0e885f8a..adf32d590 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -20,7 +20,7 @@ kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.realview.nvmem system.physmem +memories=system.physmem system.realview.nvmem midr_regval=890224640 multi_proc=true num_work_ids=16 @@ -250,7 +250,7 @@ header_cycles=1 use_default_range=false width=8 default=system.membus.badaddr_responder.pio -master=system.bridge.slave system.realview.nvmem.port[0] system.physmem.port[0] system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio +master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio slave=system.system_port system.iocache.mem_side system.l2c.mem_side [system.membus.badaddr_responder] diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index a0fa03c1d..a561bb329 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 2 2012 09:08:16 -gem5 started Jul 2 2012 15:20:44 +gem5 compiled Jul 26 2012 21:40:00 +gem5 started Jul 27 2012 00:56:10 gem5 executing on zizzer -command line: build/ARM/gem5.fast -d build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/fast/quick/fs/10.linux-boot/arm/linux/realview-simple-timing +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2593402521000 because m5_exit instruction encountered +Exiting @ tick 2594327510000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 5473fafb1..724af2042 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,201 +1,201 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.593403 # Number of seconds simulated -sim_ticks 2593402521000 # Number of ticks simulated -final_tick 2593402521000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.594328 # Number of seconds simulated +sim_ticks 2594327510000 # Number of ticks simulated +final_tick 2594327510000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 766927 # Simulator instruction rate (inst/s) -host_op_rate 979485 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 33608362861 # Simulator tick rate (ticks/s) -host_mem_usage 384708 # Number of bytes of host memory used -host_seconds 77.17 # Real time elapsed on the host -sim_insts 59180230 # Number of instructions simulated -sim_ops 75582343 # Number of ops (including micro ops) simulated -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 600896 # Simulator instruction rate (inst/s) +host_op_rate 764626 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 25897323777 # Simulator tick rate (ticks/s) +host_mem_usage 390576 # Number of bytes of host memory used +host_seconds 100.18 # Real time elapsed on the host +sim_insts 60196191 # Number of instructions simulated +sim_ops 76598245 # Number of ops (including micro ops) simulated system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704224 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9067536 # Number of bytes read from this memory -system.physmem.bytes_read::total 132455600 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704224 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704224 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3695808 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 704288 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9067216 # Number of bytes read from this memory +system.physmem.bytes_read::total 132455344 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 704288 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 704288 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3695616 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6711880 # Number of bytes written to this memory +system.physmem.bytes_written::total 6711688 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17206 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141714 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494351 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57747 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17207 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141709 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494347 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57744 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811765 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47305958 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811762 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47289092 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 271544 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3496386 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 51074062 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 271544 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271544 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1425081 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1162979 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2588059 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1425081 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47305958 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 271472 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3495016 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 51055753 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 271472 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 271472 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1424499 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1162564 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 2587063 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1424499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47289092 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 271544 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4659365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53662121 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 62163 # number of replacements -system.l2c.tagsinuse 51413.022429 # Cycle average of tags in use -system.l2c.total_refs 1730961 # Total number of references to valid blocks. -system.l2c.sampled_refs 127547 # Sample count of references to valid blocks. -system.l2c.avg_refs 13.571162 # Average number of references to valid blocks. -system.l2c.warmup_cycle 2544159444000 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 38018.047073 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.dtb.walker 3.884744 # Average occupied blocks per requestor +system.physmem.bw_total::cpu.inst 271472 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4657580 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53642816 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 62159 # number of replacements +system.l2c.tagsinuse 51417.185894 # Cycle average of tags in use +system.l2c.total_refs 1682923 # Total number of references to valid blocks. +system.l2c.sampled_refs 127542 # Sample count of references to valid blocks. +system.l2c.avg_refs 13.195049 # Average number of references to valid blocks. +system.l2c.warmup_cycle 2544924960000 # Cycle when the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 38023.288706 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.dtb.walker 3.884784 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.000558 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.inst 7004.232123 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu.data 6386.857931 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.580109 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu.inst 7004.395748 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu.data 6385.616098 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.580189 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy system.l2c.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.inst 0.106876 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu.data 0.097456 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784500 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu.dtb.walker 8759 # number of ReadReq hits +system.l2c.occ_percent::cpu.inst 0.106879 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu.data 0.097437 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.784564 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu.dtb.walker 8754 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.itb.walker 3544 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.inst 843511 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu.data 367799 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1223613 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 646378 # number of Writeback hits -system.l2c.Writeback_hits::total 646378 # number of Writeback hits +system.l2c.ReadReq_hits::cpu.inst 843519 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu.data 370124 # number of ReadReq hits +system.l2c.ReadReq_hits::total 1225941 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 596001 # number of Writeback hits +system.l2c.Writeback_hits::total 596001 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 26 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu.data 114402 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 114402 # number of ReadExReq hits -system.l2c.demand_hits::cpu.dtb.walker 8759 # number of demand (read+write) hits +system.l2c.ReadExReq_hits::cpu.data 114391 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 114391 # number of ReadExReq hits +system.l2c.demand_hits::cpu.dtb.walker 8754 # number of demand (read+write) hits system.l2c.demand_hits::cpu.itb.walker 3544 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.inst 843511 # number of demand (read+write) hits -system.l2c.demand_hits::cpu.data 482201 # number of demand (read+write) hits -system.l2c.demand_hits::total 1338015 # number of demand (read+write) hits -system.l2c.overall_hits::cpu.dtb.walker 8759 # number of overall hits +system.l2c.demand_hits::cpu.inst 843519 # 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mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.016749 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991056 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.991056 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.537701 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.537701 # mshr miss rate for ReadExReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.inst 0.012400 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu.data 0.026939 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.016719 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu.data 0.991050 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.991050 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu.data 0.537721 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.537721 # mshr miss rate for ReadExReq accesses system.l2c.demand_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for demand accesses system.l2c.demand_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.inst 0.012399 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu.data 0.229106 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.103159 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.inst 0.012400 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu.data 0.228259 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.102998 # mshr miss rate for demand accesses system.l2c.overall_mshr_miss_rate::cpu.dtb.walker 0.000571 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu.itb.walker 0.000564 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.inst 0.012399 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu.data 0.229106 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.103159 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.inst 0.012400 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu.data 0.228259 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.102998 # mshr miss rate for overall accesses system.l2c.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 40000 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40144.381492 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40070.362057 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 40107.944732 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40099.618188 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40099.618188 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40041.807893 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 40041.807893 # average ReadExReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.inst 40143.706921 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu.data 40067.629550 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 40106.260494 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu.data 40071.205280 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 40071.205280 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu.data 40036.592790 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 40036.592790 # average ReadExReq mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.demand_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40144.381492 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu.data 40043.849611 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 40050.765082 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.inst 40143.706921 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu.data 40038.812053 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 40046.028693 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.dtb.walker 40000 # average overall mshr miss latency system.l2c.overall_avg_mshr_miss_latency::cpu.itb.walker 40000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40144.381492 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu.data 40043.849611 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 40050.765082 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.inst 40143.706921 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu.data 40038.812053 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 40046.028693 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -307,26 +307,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995175 # DTB read hits -system.cpu.dtb.read_misses 7360 # DTB read misses -system.cpu.dtb.write_hits 11229808 # DTB write hits +system.cpu.dtb.read_hits 14995137 # DTB read hits +system.cpu.dtb.read_misses 7357 # DTB read misses +system.cpu.dtb.write_hits 11229787 # DTB write hits system.cpu.dtb.write_misses 2205 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID -system.cpu.dtb.flush_entries 3488 # Number of entries that have been flushed from TLB +system.cpu.dtb.flush_entries 3485 # Number of entries that have been flushed from TLB system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions system.cpu.dtb.prefetch_faults 182 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002535 # DTB read accesses -system.cpu.dtb.write_accesses 11232013 # DTB write accesses +system.cpu.dtb.read_accesses 15002494 # DTB read accesses +system.cpu.dtb.write_accesses 11231992 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26224983 # DTB hits -system.cpu.dtb.misses 9565 # DTB misses -system.cpu.dtb.accesses 26234548 # DTB accesses -system.cpu.itb.inst_hits 60461981 # ITB inst hits +system.cpu.dtb.hits 26224924 # DTB hits +system.cpu.dtb.misses 9562 # DTB misses +system.cpu.dtb.accesses 26234486 # DTB accesses +system.cpu.itb.inst_hits 61490084 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -343,79 +343,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 60466452 # ITB inst accesses -system.cpu.itb.hits 60461981 # DTB hits +system.cpu.itb.inst_accesses 61494555 # ITB inst accesses +system.cpu.itb.hits 61490084 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 60466452 # DTB accesses -system.cpu.numCycles 5186805042 # number of cpu cycles simulated +system.cpu.itb.accesses 61494555 # DTB accesses +system.cpu.numCycles 5188655020 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 59180230 # Number of instructions committed -system.cpu.committedOps 75582343 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68351784 # Number of integer alu accesses +system.cpu.committedInsts 60196191 # Number of instructions committed +system.cpu.committedOps 76598245 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68865648 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139562 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7653493 # number of instructions that are conditional controls -system.cpu.num_int_insts 68351784 # number of integer instructions +system.cpu.num_func_calls 2139540 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7910583 # number of instructions that are conditional controls +system.cpu.num_int_insts 68865648 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 391402858 # number of times the integer registers were read -system.cpu.num_int_register_writes 73137157 # number of times the integer registers were written +system.cpu.num_int_register_reads 394743471 # number of times the integer registers were read +system.cpu.num_int_register_writes 74177139 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27392171 # number of memory refs -system.cpu.num_load_insts 15659029 # Number of load instructions -system.cpu.num_store_insts 11733142 # Number of store instructions -system.cpu.num_idle_cycles 4570470450.554237 # Number of idle cycles -system.cpu.num_busy_cycles 616334591.445762 # Number of busy cycles -system.cpu.not_idle_fraction 0.118827 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.881173 # Percentage of idle cycles +system.cpu.num_mem_refs 27392126 # number of memory refs +system.cpu.num_load_insts 15659006 # Number of load instructions +system.cpu.num_store_insts 11733120 # Number of store instructions +system.cpu.num_idle_cycles 4570211154.554238 # Number of idle cycles +system.cpu.num_busy_cycles 618443865.445762 # Number of busy cycles +system.cpu.not_idle_fraction 0.119192 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.880808 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 82989 # number of quiesce instructions executed -system.cpu.icache.replacements 855209 # number of replacements -system.cpu.icache.tagsinuse 510.928777 # Cycle average of tags in use -system.cpu.icache.total_refs 59606260 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 855721 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 69.656185 # Average number of references to valid blocks. -system.cpu.icache.warmup_cycle 18855254000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.928777 # Average occupied blocks per requestor +system.cpu.icache.replacements 855220 # number of replacements +system.cpu.icache.tagsinuse 510.929118 # Cycle average of tags in use +system.cpu.icache.total_refs 60634352 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855732 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.856707 # Average number of references to valid blocks. +system.cpu.icache.warmup_cycle 18856022000 # Cycle when the warmup percentage was hit. +system.cpu.icache.occ_blocks::cpu.inst 510.929118 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.997908 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.997908 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 59606260 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 59606260 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 59606260 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 59606260 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 59606260 # number of overall hits -system.cpu.icache.overall_hits::total 59606260 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 855721 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 855721 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 855721 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 855721 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 855721 # number of overall misses -system.cpu.icache.overall_misses::total 855721 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 12570164500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 12570164500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 12570164500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 12570164500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 12570164500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 12570164500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 60461981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 60461981 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 60461981 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 60461981 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 60461981 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 60461981 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.014153 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.014153 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.014153 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14689.559448 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 14689.559448 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 14689.559448 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 14689.559448 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 14689.559448 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 14689.559448 # average overall miss latency +system.cpu.icache.ReadReq_hits::cpu.inst 60634352 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60634352 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60634352 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60634352 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60634352 # number of overall hits +system.cpu.icache.overall_hits::total 60634352 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855732 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855732 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855732 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855732 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855732 # number of overall misses +system.cpu.icache.overall_misses::total 855732 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 12556184500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 12556184500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 12556184500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 12556184500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 12556184500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 12556184500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61490084 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61490084 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61490084 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61490084 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61490084 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61490084 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013917 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.013917 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.013917 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.013917 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.013917 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.013917 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14673.033730 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 14673.033730 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 14673.033730 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 14673.033730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 14673.033730 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 14673.033730 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -424,114 +424,112 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 50294 # number of writebacks -system.cpu.icache.writebacks::total 50294 # number of writebacks -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855721 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 855721 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 855721 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 855721 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 855721 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 855721 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10001095500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10001095500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10001095500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10001095500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10001095500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10001095500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855732 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 855732 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 855732 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 855732 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 855732 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 855732 # 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average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11687.332086 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11687.332086 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013917 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.013917 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013917 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.013917 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11670.805229 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11670.805229 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11670.805229 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 11670.805229 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11670.805229 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 11670.805229 # average overall mshr miss latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 627384 # number of replacements -system.cpu.dcache.tagsinuse 511.875582 # Cycle average of tags in use -system.cpu.dcache.total_refs 23653412 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 627896 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 37.670907 # Average number of references to valid blocks. +system.cpu.dcache.replacements 627309 # number of replacements +system.cpu.dcache.tagsinuse 511.875626 # Cycle average of tags in use +system.cpu.dcache.total_refs 23653426 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 627821 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 37.675430 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 661351000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 511.875582 # Average occupied blocks per requestor +system.cpu.dcache.occ_blocks::cpu.data 511.875626 # Average occupied blocks per requestor system.cpu.dcache.occ_percent::cpu.data 0.999757 # Average percentage of cache occupancy system.cpu.dcache.occ_percent::total 0.999757 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 13194595 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 13194595 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 9972161 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 9972161 # number of WriteReq hits -system.cpu.dcache.LoadLockedReq_hits::cpu.data 236089 # number of LoadLockedReq hits -system.cpu.dcache.LoadLockedReq_hits::total 236089 # number of LoadLockedReq hits -system.cpu.dcache.StoreCondReq_hits::cpu.data 247660 # number of StoreCondReq hits -system.cpu.dcache.StoreCondReq_hits::total 247660 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 23166756 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 23166756 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 23166756 # number of overall hits -system.cpu.dcache.overall_hits::total 23166756 # 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miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.024492 # miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046725 # miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046725 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.026033 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.026033 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.026033 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.026033 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15513.716549 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 15513.716549 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36873.650997 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 36873.650997 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14875 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14875 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 24150.052242 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 24150.052242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 24150.052242 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 24150.052242 # average overall miss latency +system.cpu.dcache.ReadReq_hits::cpu.data 13194612 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 13194612 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 9972158 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 9972158 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 236094 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 236094 # 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number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14968153500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14968153500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 13563419 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 13563419 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 10222513 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 10222513 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247658 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 247658 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 247657 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 247657 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 23785932 # 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miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.026031 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.026031 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 15560.172394 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 15560.172394 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 36865.463042 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 36865.463042 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 14861.423383 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 14861.423383 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 24174.858115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 24174.858115 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 24174.858115 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -540,54 +538,54 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.writebacks::writebacks 596084 # number of writebacks -system.cpu.dcache.writebacks::total 596084 # number of writebacks -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368861 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 368861 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250370 # 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number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40324843500 # number of WriteReq MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187160444500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.overall_mshr_uncacheable_latency::total 187160444500 # number of overall MSHR uncacheable cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027195 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027195 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024492 # mshr miss rate for WriteReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046725 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046725 # mshr miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.026033 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026033 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.026033 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12510.586644 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12510.586644 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33873.339458 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33873.339458 # average WriteReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11874.870377 # average LoadLockedReq mshr miss latency -system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11874.870377 # average LoadLockedReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21148.061870 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 21148.061870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21148.061870 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 21148.061870 # average overall mshr miss latency +system.cpu.dcache.writebacks::writebacks 596001 # number of writebacks +system.cpu.dcache.writebacks::total 596001 # number of writebacks +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368807 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 368807 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250355 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 250355 # number of WriteReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11564 # number of LoadLockedReq MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11564 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619162 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619162 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619162 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619162 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4631124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4631124500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8478310000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8478310000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 137164000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 137164000 # number of LoadLockedReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13109434500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13109434500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13109434500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13109434500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 146832035500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 146832035500 # number of ReadReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 40357680500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 40357680500 # number of WriteReq MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 187189716000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 187189716000 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027191 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027191 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024491 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024491 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046693 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046693 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.026031 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026031 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.026031 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12557.040674 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12557.040674 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 33865.151485 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 33865.151485 # average WriteReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11861.293670 # average LoadLockedReq mshr miss latency +system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11861.293670 # average LoadLockedReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 21172.866713 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 21172.866713 # average overall mshr miss latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency @@ -609,10 +607,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1341484384445 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1341484384445 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1341484384445 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1341484384445 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1342178832750 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1342178832750 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1342178832750 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini index a4365933a..725aa519b 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=atomic memories=system.physmem @@ -934,7 +934,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -954,7 +954,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout index d8387d75d..7a86428b1 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simout -Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 08:05:39 -gem5 started Jul 22 2012 08:43:43 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jul 26 2012 21:30:36 +gem5 started Jul 26 2012 22:49:04 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5112043255000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt index 96f4e7d80..4f10e01e9 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.112043 # Nu sim_ticks 5112043255000 # Number of ticks simulated final_tick 5112043255000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1067695 # Simulator instruction rate (inst/s) -host_op_rate 2186181 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 27315912254 # Simulator tick rate (ticks/s) -host_mem_usage 409548 # Number of bytes of host memory used -host_seconds 187.15 # Real time elapsed on the host +host_inst_rate 1419112 # Simulator instruction rate (inst/s) +host_op_rate 2905734 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 36306590178 # Simulator tick rate (ticks/s) +host_mem_usage 362152 # Number of bytes of host memory used +host_seconds 140.80 # Real time elapsed on the host sim_insts 199813914 # Number of instructions simulated sim_ops 409133298 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2464768 # Number of bytes read from this memory @@ -48,9 +48,9 @@ system.physmem.bw_total::cpu.data 2073572 # To system.physmem.bw_total::total 4540656 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 106561 # number of replacements system.l2c.tagsinuse 64822.143261 # Cycle average of tags in use -system.l2c.total_refs 3457342 # Total number of references to valid blocks. +system.l2c.total_refs 3456533 # Total number of references to valid blocks. system.l2c.sampled_refs 170680 # Sample count of references to valid blocks. -system.l2c.avg_refs 20.256281 # Average number of references to valid blocks. +system.l2c.avg_refs 20.251541 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 51981.461987 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.dtb.walker 0.004954 # Average occupied blocks per requestor @@ -68,8 +68,8 @@ system.l2c.ReadReq_hits::cpu.itb.walker 2700 # nu system.l2c.ReadReq_hits::cpu.inst 777957 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.data 1275395 # number of ReadReq hits system.l2c.ReadReq_hits::total 2062630 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1538939 # number of Writeback hits -system.l2c.Writeback_hits::total 1538939 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 1538130 # number of Writeback hits +system.l2c.Writeback_hits::total 1538130 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 28 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 28 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu.data 179208 # number of ReadExReq hits @@ -108,8 +108,8 @@ system.l2c.ReadReq_accesses::cpu.itb.walker 2705 # system.l2c.ReadReq_accesses::cpu.inst 791299 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.data 1307579 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2108163 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1538939 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1538939 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1538130 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1538130 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 1824 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 1824 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 313585 # number of ReadExReq accesses(hits+misses) @@ -275,8 +275,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 809 # number of writebacks -system.cpu.icache.writebacks::total 809 # number of writebacks system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.itb_walker_cache.replacements 3335 # number of replacements system.cpu.itb_walker_cache.tagsinuse 3.026444 # Cycle average of tags in use diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini index 8535283af..ae091f3af 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini @@ -15,7 +15,7 @@ e820_table=system.e820_table init_param=0 intel_mp_pointer=system.intel_mp_pointer intel_mp_table=system.intel_mp_table -kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 load_addr_mask=18446744073709551615 mem_mode=timing memories=system.physmem @@ -930,7 +930,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks0.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img +image_file=/dist/m5/system/disks/linux-x86.img read_only=true [system.pc.south_bridge.ide.disks1] @@ -950,7 +950,7 @@ table_size=65536 [system.pc.south_bridge.ide.disks1.image.child] type=RawDiskImage -image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img +image_file=/dist/m5/system/disks/linux-bigswap2.img read_only=true [system.pc.south_bridge.int_lines0] diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout index 64807f302..4564af214 100755 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout @@ -1,15 +1,13 @@ -Redirecting stdout to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simout -Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 22 2012 08:05:39 -gem5 started Jul 22 2012 08:43:19 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jul 26 2012 21:30:36 +gem5 started Jul 26 2012 22:51:36 +gem5 executing on zizzer command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing warning: add_child('terminal'): child 'terminal' already has parent Global frequency set at 1000000000000 ticks per second -info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9 +info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9 0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 5191766314000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt index 49cb796d4..a4ae62a22 100644 --- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 5.191766 # Nu sim_ticks 5191766314000 # Number of ticks simulated final_tick 5191766314000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 672863 # Simulator instruction rate (inst/s) -host_op_rate 1291533 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25283717995 # Simulator tick rate (ticks/s) -host_mem_usage 405876 # Number of bytes of host memory used -host_seconds 205.34 # Real time elapsed on the host +host_inst_rate 787684 # Simulator instruction rate (inst/s) +host_op_rate 1511929 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 29598304712 # Simulator tick rate (ticks/s) +host_mem_usage 358992 # Number of bytes of host memory used +host_seconds 175.41 # Real time elapsed on the host sim_insts 138165780 # Number of instructions simulated sim_ops 265203824 # Number of ops (including micro ops) simulated system.physmem.bytes_read::pc.south_bridge.ide 2891072 # Number of bytes read from this memory @@ -44,9 +44,9 @@ system.physmem.bw_total::cpu.data 1721828 # To system.physmem.bw_total::total 3993388 # Total bandwidth to/from this memory (bytes/s) system.l2c.replacements 86221 # number of replacements system.l2c.tagsinuse 64766.656127 # Cycle average of tags in use -system.l2c.total_refs 3491043 # Total number of references to valid blocks. +system.l2c.total_refs 3490237 # Total number of references to valid blocks. system.l2c.sampled_refs 150947 # Sample count of references to valid blocks. -system.l2c.avg_refs 23.127608 # Average number of references to valid blocks. +system.l2c.avg_refs 23.122268 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.l2c.occ_blocks::writebacks 50170.355166 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu.itb.walker 0.141198 # Average occupied blocks per requestor @@ -62,8 +62,8 @@ system.l2c.ReadReq_hits::cpu.itb.walker 2757 # nu system.l2c.ReadReq_hits::cpu.inst 777565 # number of ReadReq hits system.l2c.ReadReq_hits::cpu.data 1279351 # number of ReadReq hits system.l2c.ReadReq_hits::total 2065979 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1542135 # number of Writeback hits -system.l2c.Writeback_hits::total 1542135 # number of Writeback hits +system.l2c.Writeback_hits::writebacks 1541329 # number of Writeback hits +system.l2c.Writeback_hits::total 1541329 # number of Writeback hits system.l2c.UpgradeReq_hits::cpu.data 319 # number of UpgradeReq hits system.l2c.UpgradeReq_hits::total 319 # number of UpgradeReq hits system.l2c.ReadExReq_hits::cpu.data 200451 # number of ReadExReq hits @@ -115,8 +115,8 @@ system.l2c.ReadReq_accesses::cpu.itb.walker 2762 # system.l2c.ReadReq_accesses::cpu.inst 790398 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu.data 1307724 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::total 2107190 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1542135 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1542135 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 1541329 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 1541329 # number of Writeback accesses(hits+misses) system.l2c.UpgradeReq_accesses::cpu.data 1665 # number of UpgradeReq accesses(hits+misses) system.l2c.UpgradeReq_accesses::total 1665 # number of UpgradeReq accesses(hits+misses) system.l2c.ReadExReq_accesses::cpu.data 312686 # number of ReadExReq accesses(hits+misses) @@ -431,8 +431,6 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.writebacks::writebacks 806 # number of writebacks -system.cpu.icache.writebacks::total 806 # number of writebacks system.cpu.icache.ReadReq_mshr_misses::cpu.inst 790411 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 790411 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 790411 # number of demand (read+write) MSHR misses diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini index 47099262f..3be58b836 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -155,30 +155,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -214,16 +204,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -260,76 +245,56 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=4 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 weight=1 [system.ruby.network.topology.int_links2] @@ -337,10 +302,26 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout index 1832a62b7..0c7f2991f 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 17:30:17 -gem5 started Jul 10 2012 17:30:49 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 13:42:35 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt index dc174d88f..bae589857 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000279 # Nu sim_ticks 279353 # Number of ticks simulated final_tick 279353 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 24575 # Simulator instruction rate (inst/s) -host_op_rate 24573 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1071866 # Simulator tick rate (ticks/s) -host_mem_usage 236072 # Number of bytes of host memory used -host_seconds 0.26 # Real time elapsed on the host +host_inst_rate 12119 # Simulator instruction rate (inst/s) +host_op_rate 12118 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 528605 # Simulator tick rate (ticks/s) +host_mem_usage 226340 # Number of bytes of host memory used +host_seconds 0.53 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory @@ -33,24 +33,6 @@ system.physmem.bw_write::total 23969673 # Wr system.physmem.bw_total::cpu.inst 91840789 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 55485354 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 147326143 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini index 81f78cde4..f0fb5fcd1 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -152,30 +152,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -210,16 +200,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -256,76 +241,56 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=4 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 weight=1 [system.ruby.network.topology.int_links2] @@ -333,10 +298,26 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout index aac08e2fa..691f6347c 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 17:36:02 -gem5 started Jul 10 2012 17:36:36 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:04 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 91d67e04f..ddb3e7d12 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000224 # Nu sim_ticks 223694 # Number of ticks simulated final_tick 223694 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 21381 # Simulator instruction rate (inst/s) -host_op_rate 21380 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 746759 # Simulator tick rate (ticks/s) -host_mem_usage 236312 # Number of bytes of host memory used -host_seconds 0.30 # Real time elapsed on the host +host_inst_rate 30014 # Simulator instruction rate (inst/s) +host_op_rate 30012 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1048235 # Simulator tick rate (ticks/s) +host_mem_usage 226460 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory @@ -33,24 +33,6 @@ system.physmem.bw_write::total 29933749 # Wr system.physmem.bw_total::cpu.inst 114692392 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 69291085 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 183983477 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini index 4e5ea8bc4..260fc7a89 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -161,30 +161,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -221,16 +211,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -267,76 +252,56 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=4 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 weight=1 [system.ruby.network.topology.int_links2] @@ -344,10 +309,26 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout index e3a769a26..63d892f7f 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 15:34:13 -gem5 started Jul 10 2012 17:45:14 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:12 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt index 7722b3fbe..9ad88fcd3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000232 # Nu sim_ticks 231701 # Number of ticks simulated final_tick 231701 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 36777 # Simulator instruction rate (inst/s) -host_op_rate 36773 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1330353 # Simulator tick rate (ticks/s) -host_mem_usage 234436 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 50012 # Simulator instruction rate (inst/s) +host_op_rate 50005 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1808952 # Simulator tick rate (ticks/s) +host_mem_usage 224692 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory @@ -33,24 +33,6 @@ system.physmem.bw_write::total 28899314 # Wr system.physmem.bw_total::cpu.inst 110728914 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 66896561 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 177625474 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini index 9fd0a4ee1..c7cccc96e 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -138,16 +138,11 @@ version=0 [system.dir_cntrl0.probeFilter] type=RubyCache assoc=4 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=1 replacement_policy=PSEUDO_LRU -resourceStalls=false size=1024 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0] type=L1Cache_Controller @@ -172,44 +167,29 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -262,64 +242,61 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 +children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=2 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers2 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers2 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout index 8fc46fbe9..f1ba4ed84 100755 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 15:16:15 -gem5 started Jul 10 2012 17:50:25 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:41:27 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt index a0796133c..842792d27 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000208 # Nu sim_ticks 208400 # Number of ticks simulated final_tick 208400 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 40149 # Simulator instruction rate (inst/s) -host_op_rate 40144 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1306231 # Simulator tick rate (ticks/s) -host_mem_usage 233684 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 52133 # Simulator instruction rate (inst/s) +host_op_rate 52125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1696034 # Simulator tick rate (ticks/s) +host_mem_usage 224184 # Number of bytes of host memory used +host_seconds 0.12 # Real time elapsed on the host sim_insts 6404 # Number of instructions simulated sim_ops 6404 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 25656 # Number of bytes read from this memory @@ -33,30 +33,6 @@ system.physmem.bw_write::total 32130518 # Wr system.physmem.bw_total::cpu.inst 123109405 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 74376200 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 197485605 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.dir_cntrl0.probeFilter.num_data_array_reads 0 # number of data array reads -system.dir_cntrl0.probeFilter.num_data_array_writes 0 # number of data array writes -system.dir_cntrl0.probeFilter.num_tag_array_reads 0 # number of tag array reads -system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes -system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array -system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini index bc15d1f8b..317cc6a7e 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -155,30 +155,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -214,16 +204,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -260,76 +245,56 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=4 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 weight=1 [system.ruby.network.topology.int_links2] @@ -337,10 +302,26 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout index d29f3759f..d8d70a93e 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 17:30:17 -gem5 started Jul 10 2012 17:31:25 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 13:42:35 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt index 20b3bd153..748d8a973 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000105 # Nu sim_ticks 104867 # Number of ticks simulated final_tick 104867 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 25231 # Simulator instruction rate (inst/s) -host_op_rate 25226 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1026377 # Simulator tick rate (ticks/s) -host_mem_usage 233832 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 4864 # Simulator instruction rate (inst/s) +host_op_rate 4864 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 197908 # Simulator tick rate (ticks/s) +host_mem_usage 224040 # Number of bytes of host memory used +host_seconds 0.53 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -33,24 +33,6 @@ system.physmem.bw_write::total 19624858 # Wr system.physmem.bw_total::cpu.inst 98601085 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 48385097 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 146986182 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini index 5b6cac45b..34c479e22 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -152,30 +152,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -210,16 +200,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -256,76 +241,56 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=4 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 weight=1 [system.ruby.network.topology.int_links2] @@ -333,10 +298,26 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout index 4b0921627..dc8b54148 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 17:36:02 -gem5 started Jul 10 2012 17:37:10 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:15 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt index 6d74d1d8c..07e9173f4 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000085 # Nu sim_ticks 85418 # Number of ticks simulated final_tick 85418 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 21617 # Simulator instruction rate (inst/s) -host_op_rate 21614 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 716318 # Simulator tick rate (ticks/s) -host_mem_usage 234076 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 30509 # Simulator instruction rate (inst/s) +host_op_rate 30502 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1010829 # Simulator tick rate (ticks/s) +host_mem_usage 224228 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -33,24 +33,6 @@ system.physmem.bw_write::total 24093282 # Wr system.physmem.bw_total::cpu.inst 121051769 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 59402000 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 180453769 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini index 2b2f5fcb6..ea15696c3 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -161,30 +161,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -221,16 +211,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -267,76 +252,56 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=4 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 weight=1 [system.ruby.network.topology.int_links2] @@ -344,10 +309,26 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout index 851a68508..3e1c7a0df 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 15:34:13 -gem5 started Jul 10 2012 17:45:47 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:22 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt index 0bb4f7ab2..0b4d202c9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000088 # Nu sim_ticks 87899 # Number of ticks simulated final_tick 87899 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 36684 # Simulator instruction rate (inst/s) -host_op_rate 36675 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1250644 # Simulator tick rate (ticks/s) -host_mem_usage 233044 # Number of bytes of host memory used -host_seconds 0.07 # Real time elapsed on the host +host_inst_rate 49141 # Simulator instruction rate (inst/s) +host_op_rate 49125 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1675041 # Simulator tick rate (ticks/s) +host_mem_usage 223232 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -33,24 +33,6 @@ system.physmem.bw_write::total 23413236 # Wr system.physmem.bw_total::cpu.inst 117635013 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 57725344 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 175360357 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini index d24ccea68..5531e80ff 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini @@ -78,7 +78,7 @@ egid=100 env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -138,16 +138,11 @@ version=0 [system.dir_cntrl0.probeFilter] type=RubyCache assoc=4 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=1 replacement_policy=PSEUDO_LRU -resourceStalls=false size=1024 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0] type=L1Cache_Controller @@ -172,44 +167,29 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -262,64 +242,61 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 +children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=2 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers2 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers2 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout index 2612c0b40..423daf7c7 100755 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 15:16:15 -gem5 started Jul 10 2012 17:50:59 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt index 17ceaae11..002b923d5 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000078 # Nu sim_ticks 78448 # Number of ticks simulated final_tick 78448 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_inst_rate 40059 # Simulator instruction rate (inst/s) -host_op_rate 40048 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1218818 # Simulator tick rate (ticks/s) -host_mem_usage 232472 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 9618 # Simulator instruction rate (inst/s) +host_op_rate 9618 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292754 # Simulator tick rate (ticks/s) +host_mem_usage 222892 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host sim_insts 2577 # Number of instructions simulated sim_ops 2577 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 10340 # Number of bytes read from this memory @@ -33,30 +33,6 @@ system.physmem.bw_write::total 26233938 # Wr system.physmem.bw_total::cpu.inst 131807057 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.data 64679788 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 196486845 # Total bandwidth to/from this memory (bytes/s) -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.dir_cntrl0.probeFilter.num_data_array_reads 0 # number of data array reads -system.dir_cntrl0.probeFilter.num_data_array_writes 0 # number of data array writes -system.dir_cntrl0.probeFilter.num_tag_array_reads 0 # number of tag array reads -system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes -system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array -system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini index 5b264ec2e..35cfc3441 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini @@ -14,7 +14,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing -memories=system.physmem system.funcmem +memories=system.funcmem system.physmem num_work_ids=16 readfile= symbolfile= @@ -249,30 +249,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -312,30 +302,20 @@ version=1 [system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.sequencer] type=RubySequencer @@ -375,30 +355,20 @@ version=2 [system.l1_cntrl2.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl2.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl2.sequencer] type=RubySequencer @@ -438,30 +408,20 @@ version=3 [system.l1_cntrl3.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl3.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl3.sequencer] type=RubySequencer @@ -501,30 +461,20 @@ version=4 [system.l1_cntrl4.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl4.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl4.sequencer] type=RubySequencer @@ -564,30 +514,20 @@ version=5 [system.l1_cntrl5.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl5.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl5.sequencer] type=RubySequencer @@ -627,30 +567,20 @@ version=6 [system.l1_cntrl6.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl6.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl6.sequencer] type=RubySequencer @@ -690,30 +620,20 @@ version=7 [system.l1_cntrl7.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl7.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl7.sequencer] type=RubySequencer @@ -749,16 +669,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -795,174 +710,119 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.ext_links9.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers00 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl1 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers01 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl2 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers02 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.ext_links3] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl3 -int_node=system.ruby.network.topology.ext_links3.int_node +int_node=system.ruby.network.topology.routers03 latency=1 link_id=3 weight=1 -[system.ruby.network.topology.ext_links3.int_node] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.ext_links4] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl4 -int_node=system.ruby.network.topology.ext_links4.int_node +int_node=system.ruby.network.topology.routers04 latency=1 link_id=4 weight=1 -[system.ruby.network.topology.ext_links4.int_node] -type=BasicRouter -router_id=4 - [system.ruby.network.topology.ext_links5] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl5 -int_node=system.ruby.network.topology.ext_links5.int_node +int_node=system.ruby.network.topology.routers05 latency=1 link_id=5 weight=1 -[system.ruby.network.topology.ext_links5.int_node] -type=BasicRouter -router_id=5 - [system.ruby.network.topology.ext_links6] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl6 -int_node=system.ruby.network.topology.ext_links6.int_node +int_node=system.ruby.network.topology.routers06 latency=1 link_id=6 weight=1 -[system.ruby.network.topology.ext_links6.int_node] -type=BasicRouter -router_id=6 - [system.ruby.network.topology.ext_links7] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl7 -int_node=system.ruby.network.topology.ext_links7.int_node +int_node=system.ruby.network.topology.routers07 latency=1 link_id=7 weight=1 -[system.ruby.network.topology.ext_links7.int_node] -type=BasicRouter -router_id=7 - [system.ruby.network.topology.ext_links8] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links8.int_node +int_node=system.ruby.network.topology.routers08 latency=1 link_id=8 weight=1 -[system.ruby.network.topology.ext_links8.int_node] -type=BasicRouter -router_id=8 - [system.ruby.network.topology.ext_links9] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links9.int_node +int_node=system.ruby.network.topology.routers09 latency=1 link_id=9 weight=1 -[system.ruby.network.topology.ext_links9.int_node] -type=BasicRouter -router_id=9 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=10 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers00 +node_b=system.ruby.network.topology.routers10 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=10 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=11 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers01 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links2] @@ -970,8 +830,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=12 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers02 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links3] @@ -979,8 +839,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=13 -node_a=system.ruby.network.topology.ext_links3.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers03 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links4] @@ -988,8 +848,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=14 -node_a=system.ruby.network.topology.ext_links4.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers04 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links5] @@ -997,8 +857,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=15 -node_a=system.ruby.network.topology.ext_links5.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers05 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links6] @@ -1006,8 +866,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=16 -node_a=system.ruby.network.topology.ext_links6.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers06 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links7] @@ -1015,8 +875,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=17 -node_a=system.ruby.network.topology.ext_links7.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers07 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links8] @@ -1024,8 +884,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=18 -node_a=system.ruby.network.topology.ext_links8.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers08 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links9] @@ -1033,10 +893,54 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=19 -node_a=system.ruby.network.topology.ext_links9.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers09 +node_b=system.ruby.network.topology.routers10 weight=1 +[system.ruby.network.topology.routers00] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers01] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers02] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers03] +type=BasicRouter +router_id=3 + +[system.ruby.network.topology.routers04] +type=BasicRouter +router_id=4 + +[system.ruby.network.topology.routers05] +type=BasicRouter +router_id=5 + +[system.ruby.network.topology.routers06] +type=BasicRouter +router_id=6 + +[system.ruby.network.topology.routers07] +type=BasicRouter +router_id=7 + +[system.ruby.network.topology.routers08] +type=BasicRouter +router_id=8 + +[system.ruby.network.topology.routers09] +type=BasicRouter +router_id=9 + +[system.ruby.network.topology.routers10] +type=BasicRouter +router_id=10 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout index bc0d86d72..4c179bc95 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 17:30:17 -gem5 started Jul 10 2012 17:31:57 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 14:40:22 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt index 3b11b4fe0..c7afc7b3a 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt @@ -4,111 +4,9 @@ sim_seconds 0.022495 # Nu sim_ticks 22495354 # Number of ticks simulated final_tick 22495354 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 170886 # Simulator tick rate (ticks/s) -host_mem_usage 380372 # Number of bytes of host memory used -host_seconds 131.64 # Real time elapsed on the host -system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl4.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl4.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl5.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl5.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl5.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl5.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl6.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl6.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl6.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl6.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl7.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl7.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl7.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl7.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl2.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl2.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl2.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl2.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl3.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl3.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl3.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl3.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +host_tick_rate 256726 # Simulator tick rate (ticks/s) +host_mem_usage 370452 # Number of bytes of host memory used +host_seconds 87.62 # Real time elapsed on the host system.cpu0.num_reads 99326 # number of read accesses completed system.cpu0.num_writes 53132 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini index ff00bba8d..e3b9d4def 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini @@ -246,30 +246,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -307,30 +297,20 @@ version=1 [system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.sequencer] type=RubySequencer @@ -368,30 +348,20 @@ version=2 [system.l1_cntrl2.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl2.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl2.sequencer] type=RubySequencer @@ -429,30 +399,20 @@ version=3 [system.l1_cntrl3.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl3.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl3.sequencer] type=RubySequencer @@ -490,30 +450,20 @@ version=4 [system.l1_cntrl4.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl4.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl4.sequencer] type=RubySequencer @@ -551,30 +501,20 @@ version=5 [system.l1_cntrl5.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl5.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl5.sequencer] type=RubySequencer @@ -612,30 +552,20 @@ version=6 [system.l1_cntrl6.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl6.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl6.sequencer] type=RubySequencer @@ -673,30 +603,20 @@ version=7 [system.l1_cntrl7.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl7.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl7.sequencer] type=RubySequencer @@ -731,16 +651,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -777,174 +692,119 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.ext_links9.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers00 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl1 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers01 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl2 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers02 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.ext_links3] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl3 -int_node=system.ruby.network.topology.ext_links3.int_node +int_node=system.ruby.network.topology.routers03 latency=1 link_id=3 weight=1 -[system.ruby.network.topology.ext_links3.int_node] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.ext_links4] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl4 -int_node=system.ruby.network.topology.ext_links4.int_node +int_node=system.ruby.network.topology.routers04 latency=1 link_id=4 weight=1 -[system.ruby.network.topology.ext_links4.int_node] -type=BasicRouter -router_id=4 - [system.ruby.network.topology.ext_links5] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl5 -int_node=system.ruby.network.topology.ext_links5.int_node +int_node=system.ruby.network.topology.routers05 latency=1 link_id=5 weight=1 -[system.ruby.network.topology.ext_links5.int_node] -type=BasicRouter -router_id=5 - [system.ruby.network.topology.ext_links6] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl6 -int_node=system.ruby.network.topology.ext_links6.int_node +int_node=system.ruby.network.topology.routers06 latency=1 link_id=6 weight=1 -[system.ruby.network.topology.ext_links6.int_node] -type=BasicRouter -router_id=6 - [system.ruby.network.topology.ext_links7] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl7 -int_node=system.ruby.network.topology.ext_links7.int_node +int_node=system.ruby.network.topology.routers07 latency=1 link_id=7 weight=1 -[system.ruby.network.topology.ext_links7.int_node] -type=BasicRouter -router_id=7 - [system.ruby.network.topology.ext_links8] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links8.int_node +int_node=system.ruby.network.topology.routers08 latency=1 link_id=8 weight=1 -[system.ruby.network.topology.ext_links8.int_node] -type=BasicRouter -router_id=8 - [system.ruby.network.topology.ext_links9] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links9.int_node +int_node=system.ruby.network.topology.routers09 latency=1 link_id=9 weight=1 -[system.ruby.network.topology.ext_links9.int_node] -type=BasicRouter -router_id=9 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=10 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers00 +node_b=system.ruby.network.topology.routers10 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=10 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=11 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers01 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links2] @@ -952,8 +812,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=12 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers02 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links3] @@ -961,8 +821,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=13 -node_a=system.ruby.network.topology.ext_links3.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers03 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links4] @@ -970,8 +830,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=14 -node_a=system.ruby.network.topology.ext_links4.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers04 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links5] @@ -979,8 +839,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=15 -node_a=system.ruby.network.topology.ext_links5.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers05 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links6] @@ -988,8 +848,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=16 -node_a=system.ruby.network.topology.ext_links6.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers06 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links7] @@ -997,8 +857,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=17 -node_a=system.ruby.network.topology.ext_links7.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers07 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links8] @@ -1006,8 +866,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=18 -node_a=system.ruby.network.topology.ext_links8.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers08 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links9] @@ -1015,10 +875,54 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=19 -node_a=system.ruby.network.topology.ext_links9.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers09 +node_b=system.ruby.network.topology.routers10 weight=1 +[system.ruby.network.topology.routers00] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers01] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers02] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers03] +type=BasicRouter +router_id=3 + +[system.ruby.network.topology.routers04] +type=BasicRouter +router_id=4 + +[system.ruby.network.topology.routers05] +type=BasicRouter +router_id=5 + +[system.ruby.network.topology.routers06] +type=BasicRouter +router_id=6 + +[system.ruby.network.topology.routers07] +type=BasicRouter +router_id=7 + +[system.ruby.network.topology.routers08] +type=BasicRouter +router_id=8 + +[system.ruby.network.topology.routers09] +type=BasicRouter +router_id=9 + +[system.ruby.network.topology.routers10] +type=BasicRouter +router_id=10 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout index 3dcad7574..ca77e3fc7 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 17:36:02 -gem5 started Jul 10 2012 17:37:43 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:41:26 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt index c85767a76..fcc191198 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt @@ -4,111 +4,9 @@ sim_seconds 0.019401 # Nu sim_ticks 19400856 # Number of ticks simulated final_tick 19400856 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 50488 # Simulator tick rate (ticks/s) -host_mem_usage 380584 # Number of bytes of host memory used -host_seconds 384.27 # Real time elapsed on the host -system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl4.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl4.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl5.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl5.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl5.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl5.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl6.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl6.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl6.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl6.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl7.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl7.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl7.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl7.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl2.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl2.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl2.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl2.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl3.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl3.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl3.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl3.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +host_tick_rate 79524 # Simulator tick rate (ticks/s) +host_mem_usage 370632 # Number of bytes of host memory used +host_seconds 243.96 # Real time elapsed on the host system.cpu0.num_reads 98844 # number of read accesses completed system.cpu0.num_writes 53478 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini index 93f57099a..4af9d9478 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini @@ -255,30 +255,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -322,30 +312,20 @@ version=1 [system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.sequencer] type=RubySequencer @@ -389,30 +369,20 @@ version=2 [system.l1_cntrl2.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl2.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl2.sequencer] type=RubySequencer @@ -456,30 +426,20 @@ version=3 [system.l1_cntrl3.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl3.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl3.sequencer] type=RubySequencer @@ -523,30 +483,20 @@ version=4 [system.l1_cntrl4.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl4.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl4.sequencer] type=RubySequencer @@ -590,30 +540,20 @@ version=5 [system.l1_cntrl5.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl5.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl5.sequencer] type=RubySequencer @@ -657,30 +597,20 @@ version=6 [system.l1_cntrl6.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl6.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl6.sequencer] type=RubySequencer @@ -724,30 +654,20 @@ version=7 [system.l1_cntrl7.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl7.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl7.sequencer] type=RubySequencer @@ -784,16 +704,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -830,174 +745,119 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 routers00 routers01 routers02 routers03 routers04 routers05 routers06 routers07 routers08 routers09 routers10 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.ext_links9.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers00 system.ruby.network.topology.routers01 system.ruby.network.topology.routers02 system.ruby.network.topology.routers03 system.ruby.network.topology.routers04 system.ruby.network.topology.routers05 system.ruby.network.topology.routers06 system.ruby.network.topology.routers07 system.ruby.network.topology.routers08 system.ruby.network.topology.routers09 system.ruby.network.topology.routers10 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers00 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl1 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers01 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl2 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers02 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.ext_links3] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl3 -int_node=system.ruby.network.topology.ext_links3.int_node +int_node=system.ruby.network.topology.routers03 latency=1 link_id=3 weight=1 -[system.ruby.network.topology.ext_links3.int_node] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.ext_links4] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl4 -int_node=system.ruby.network.topology.ext_links4.int_node +int_node=system.ruby.network.topology.routers04 latency=1 link_id=4 weight=1 -[system.ruby.network.topology.ext_links4.int_node] -type=BasicRouter -router_id=4 - [system.ruby.network.topology.ext_links5] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl5 -int_node=system.ruby.network.topology.ext_links5.int_node +int_node=system.ruby.network.topology.routers05 latency=1 link_id=5 weight=1 -[system.ruby.network.topology.ext_links5.int_node] -type=BasicRouter -router_id=5 - [system.ruby.network.topology.ext_links6] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl6 -int_node=system.ruby.network.topology.ext_links6.int_node +int_node=system.ruby.network.topology.routers06 latency=1 link_id=6 weight=1 -[system.ruby.network.topology.ext_links6.int_node] -type=BasicRouter -router_id=6 - [system.ruby.network.topology.ext_links7] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl7 -int_node=system.ruby.network.topology.ext_links7.int_node +int_node=system.ruby.network.topology.routers07 latency=1 link_id=7 weight=1 -[system.ruby.network.topology.ext_links7.int_node] -type=BasicRouter -router_id=7 - [system.ruby.network.topology.ext_links8] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links8.int_node +int_node=system.ruby.network.topology.routers08 latency=1 link_id=8 weight=1 -[system.ruby.network.topology.ext_links8.int_node] -type=BasicRouter -router_id=8 - [system.ruby.network.topology.ext_links9] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links9.int_node +int_node=system.ruby.network.topology.routers09 latency=1 link_id=9 weight=1 -[system.ruby.network.topology.ext_links9.int_node] -type=BasicRouter -router_id=9 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=10 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers00 +node_b=system.ruby.network.topology.routers10 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=10 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=11 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers01 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links2] @@ -1005,8 +865,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=12 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers02 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links3] @@ -1014,8 +874,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=13 -node_a=system.ruby.network.topology.ext_links3.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers03 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links4] @@ -1023,8 +883,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=14 -node_a=system.ruby.network.topology.ext_links4.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers04 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links5] @@ -1032,8 +892,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=15 -node_a=system.ruby.network.topology.ext_links5.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers05 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links6] @@ -1041,8 +901,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=16 -node_a=system.ruby.network.topology.ext_links6.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers06 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links7] @@ -1050,8 +910,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=17 -node_a=system.ruby.network.topology.ext_links7.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers07 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links8] @@ -1059,8 +919,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=18 -node_a=system.ruby.network.topology.ext_links8.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers08 +node_b=system.ruby.network.topology.routers10 weight=1 [system.ruby.network.topology.int_links9] @@ -1068,10 +928,54 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=19 -node_a=system.ruby.network.topology.ext_links9.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers09 +node_b=system.ruby.network.topology.routers10 weight=1 +[system.ruby.network.topology.routers00] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers01] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers02] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers03] +type=BasicRouter +router_id=3 + +[system.ruby.network.topology.routers04] +type=BasicRouter +router_id=4 + +[system.ruby.network.topology.routers05] +type=BasicRouter +router_id=5 + +[system.ruby.network.topology.routers06] +type=BasicRouter +router_id=6 + +[system.ruby.network.topology.routers07] +type=BasicRouter +router_id=7 + +[system.ruby.network.topology.routers08] +type=BasicRouter +router_id=8 + +[system.ruby.network.topology.routers09] +type=BasicRouter +router_id=9 + +[system.ruby.network.topology.routers10] +type=BasicRouter +router_id=10 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout index 096fa6972..4dc86aa94 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 15:34:13 -gem5 started Jul 10 2012 17:46:20 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:42:33 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt index 2de7fc80b..284e6ab5c 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt @@ -4,111 +4,9 @@ sim_seconds 0.019665 # Nu sim_ticks 19665440 # Number of ticks simulated final_tick 19665440 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 111694 # Simulator tick rate (ticks/s) -host_mem_usage 379960 # Number of bytes of host memory used -host_seconds 176.06 # Real time elapsed on the host -system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl4.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl4.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl5.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl5.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl5.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl5.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl6.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl6.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl6.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl6.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl7.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl7.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl7.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl7.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl2.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl2.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl2.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl2.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl3.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl3.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl3.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl3.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +host_tick_rate 168119 # Simulator tick rate (ticks/s) +host_mem_usage 370164 # Number of bytes of host memory used +host_seconds 116.97 # Real time elapsed on the host system.cpu0.num_reads 99534 # number of read accesses completed system.cpu0.num_writes 53920 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini index 9e9ce8534..34695a208 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini @@ -220,16 +220,11 @@ version=0 [system.dir_cntrl0.probeFilter] type=RubyCache assoc=4 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=1 replacement_policy=PSEUDO_LRU -resourceStalls=false size=1024 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.funcmem] type=SimpleMemory @@ -266,44 +261,29 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -344,44 +324,29 @@ version=1 [system.l1_cntrl1.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl1.sequencer] type=RubySequencer @@ -422,44 +387,29 @@ version=2 [system.l1_cntrl2.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl2.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl2.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl2.sequencer] type=RubySequencer @@ -500,44 +450,29 @@ version=3 [system.l1_cntrl3.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl3.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl3.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl3.sequencer] type=RubySequencer @@ -578,44 +513,29 @@ version=4 [system.l1_cntrl4.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl4.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl4.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl4.sequencer] type=RubySequencer @@ -656,44 +576,29 @@ version=5 [system.l1_cntrl5.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl5.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl5.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl5.sequencer] type=RubySequencer @@ -734,44 +639,29 @@ version=6 [system.l1_cntrl6.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl6.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl6.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl6.sequencer] type=RubySequencer @@ -812,44 +702,29 @@ version=7 [system.l1_cntrl7.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl7.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl7.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl7.sequencer] type=RubySequencer @@ -902,160 +777,110 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 routers0 routers1 routers2 routers3 routers4 routers5 routers6 routers7 routers8 routers9 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.ext_links3.int_node system.ruby.network.topology.ext_links4.int_node system.ruby.network.topology.ext_links5.int_node system.ruby.network.topology.ext_links6.int_node system.ruby.network.topology.ext_links7.int_node system.ruby.network.topology.ext_links8.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 system.ruby.network.topology.routers6 system.ruby.network.topology.routers7 system.ruby.network.topology.routers8 system.ruby.network.topology.routers9 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl1 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl2 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.ext_links3] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl3 -int_node=system.ruby.network.topology.ext_links3.int_node +int_node=system.ruby.network.topology.routers3 latency=1 link_id=3 weight=1 -[system.ruby.network.topology.ext_links3.int_node] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.ext_links4] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl4 -int_node=system.ruby.network.topology.ext_links4.int_node +int_node=system.ruby.network.topology.routers4 latency=1 link_id=4 weight=1 -[system.ruby.network.topology.ext_links4.int_node] -type=BasicRouter -router_id=4 - [system.ruby.network.topology.ext_links5] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl5 -int_node=system.ruby.network.topology.ext_links5.int_node +int_node=system.ruby.network.topology.routers5 latency=1 link_id=5 weight=1 -[system.ruby.network.topology.ext_links5.int_node] -type=BasicRouter -router_id=5 - [system.ruby.network.topology.ext_links6] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl6 -int_node=system.ruby.network.topology.ext_links6.int_node +int_node=system.ruby.network.topology.routers6 latency=1 link_id=6 weight=1 -[system.ruby.network.topology.ext_links6.int_node] -type=BasicRouter -router_id=6 - [system.ruby.network.topology.ext_links7] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl7 -int_node=system.ruby.network.topology.ext_links7.int_node +int_node=system.ruby.network.topology.routers7 latency=1 link_id=7 weight=1 -[system.ruby.network.topology.ext_links7.int_node] -type=BasicRouter -router_id=7 - [system.ruby.network.topology.ext_links8] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links8.int_node +int_node=system.ruby.network.topology.routers8 latency=1 link_id=8 weight=1 -[system.ruby.network.topology.ext_links8.int_node] -type=BasicRouter -router_id=8 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=9 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers9 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=9 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=10 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers9 weight=1 [system.ruby.network.topology.int_links2] @@ -1063,8 +888,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=11 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers9 weight=1 [system.ruby.network.topology.int_links3] @@ -1072,8 +897,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=12 -node_a=system.ruby.network.topology.ext_links3.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers3 +node_b=system.ruby.network.topology.routers9 weight=1 [system.ruby.network.topology.int_links4] @@ -1081,8 +906,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=13 -node_a=system.ruby.network.topology.ext_links4.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers4 +node_b=system.ruby.network.topology.routers9 weight=1 [system.ruby.network.topology.int_links5] @@ -1090,8 +915,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=14 -node_a=system.ruby.network.topology.ext_links5.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers5 +node_b=system.ruby.network.topology.routers9 weight=1 [system.ruby.network.topology.int_links6] @@ -1099,8 +924,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=15 -node_a=system.ruby.network.topology.ext_links6.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers6 +node_b=system.ruby.network.topology.routers9 weight=1 [system.ruby.network.topology.int_links7] @@ -1108,8 +933,8 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=16 -node_a=system.ruby.network.topology.ext_links7.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers7 +node_b=system.ruby.network.topology.routers9 weight=1 [system.ruby.network.topology.int_links8] @@ -1117,10 +942,50 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=17 -node_a=system.ruby.network.topology.ext_links8.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers8 +node_b=system.ruby.network.topology.routers9 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.network.topology.routers4] +type=BasicRouter +router_id=4 + +[system.ruby.network.topology.routers5] +type=BasicRouter +router_id=5 + +[system.ruby.network.topology.routers6] +type=BasicRouter +router_id=6 + +[system.ruby.network.topology.routers7] +type=BasicRouter +router_id=7 + +[system.ruby.network.topology.routers8] +type=BasicRouter +router_id=8 + +[system.ruby.network.topology.routers9] +type=BasicRouter +router_id=9 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout index cc01f71f1..bc60d72d3 100755 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 15:16:15 -gem5 started Jul 10 2012 17:51:31 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt index 75db37f25..7c588684e 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt @@ -4,159 +4,9 @@ sim_seconds 0.019129 # Nu sim_ticks 19129199 # Number of ticks simulated final_tick 19129199 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 120686 # Simulator tick rate (ticks/s) -host_mem_usage 379940 # Number of bytes of host memory used -host_seconds 158.50 # Real time elapsed on the host -system.l1_cntrl4.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl4.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl4.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl4.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl4.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl4.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl4.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl4.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl4.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl4.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl4.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl4.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl4.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl4.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl4.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl4.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl4.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl4.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl5.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl5.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl5.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl5.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl5.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl5.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl5.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl5.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl5.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl5.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl5.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl5.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl5.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl5.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl5.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl5.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl5.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl5.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl6.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl6.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl6.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl6.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl6.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl6.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl6.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl6.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl6.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl6.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl6.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl6.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl6.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl6.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl6.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl6.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl6.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl6.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl7.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl7.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl7.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl7.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl7.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl7.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl7.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl7.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl7.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl7.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl7.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl7.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl7.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl7.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl7.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl7.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl7.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl7.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl1.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl1.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl1.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl1.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl1.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl1.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl2.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl2.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl2.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl2.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl2.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl2.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl2.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl2.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl2.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl2.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl2.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl2.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl2.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl2.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl2.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl2.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl2.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl2.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl3.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl3.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl3.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl3.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl3.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl3.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl3.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl3.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl3.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl3.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl3.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl3.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl3.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl3.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl3.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl3.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl3.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl3.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.dir_cntrl0.probeFilter.num_data_array_reads 0 # number of data array reads -system.dir_cntrl0.probeFilter.num_data_array_writes 0 # number of data array writes -system.dir_cntrl0.probeFilter.num_tag_array_reads 0 # number of tag array reads -system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes -system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array -system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array +host_tick_rate 171697 # Simulator tick rate (ticks/s) +host_mem_usage 369968 # Number of bytes of host memory used +host_seconds 111.41 # Real time elapsed on the host system.cpu0.num_reads 100000 # number of read accesses completed system.cpu0.num_writes 53893 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini index f8c719b99..993287fd9 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini @@ -93,30 +93,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -152,16 +142,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -198,76 +183,56 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=4 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 weight=1 [system.ruby.network.topology.int_links2] @@ -275,10 +240,26 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout index a5b5eb0e5..bfa4f7e73 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 17:30:17 -gem5 started Jul 10 2012 17:34:42 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:53:20 +gem5 started Jun 4 2012 14:40:53 +gem5 executing on zizzer command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt index 3aa96ab1f..f6f4e6847 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt @@ -4,26 +4,8 @@ sim_seconds 0.000350 # Nu sim_ticks 349711 # Number of ticks simulated final_tick 349711 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1546655 # Simulator tick rate (ticks/s) -host_mem_usage 230968 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +host_tick_rate 2288501 # Simulator tick rate (ticks/s) +host_mem_usage 221264 # Number of bytes of host memory used +host_seconds 0.15 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini index dc2ecd66a..a92426643 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini @@ -90,30 +90,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=3 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -148,16 +138,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=15 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -194,76 +179,56 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=4 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 weight=1 [system.ruby.network.topology.int_links2] @@ -271,10 +236,26 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout index 3eb17b7ab..473ebc3b9 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 17:36:02 -gem5 started Jul 10 2012 17:44:41 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:54:55 +gem5 started Jun 4 2012 14:42:00 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt index da0ebfcc7..22e36183d 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt @@ -4,26 +4,8 @@ sim_seconds 0.000358 # Nu sim_ticks 357561 # Number of ticks simulated final_tick 357561 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 486616 # Simulator tick rate (ticks/s) -host_mem_usage 231064 # Number of bytes of host memory used -host_seconds 0.73 # Real time elapsed on the host -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +host_tick_rate 776030 # Simulator tick rate (ticks/s) +host_mem_usage 221440 # Number of bytes of host memory used +host_seconds 0.46 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini index ee2d6f075..529933d46 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini @@ -99,30 +99,20 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -159,16 +149,11 @@ version=0 [system.l2_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.physmem] type=SimpleMemory @@ -205,76 +190,56 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 routers0 routers1 routers2 routers3 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.ext_links2.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l2_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.ext_links2] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links2.int_node +int_node=system.ruby.network.topology.routers2 latency=1 link_id=2 weight=1 -[system.ruby.network.topology.ext_links2.int_node] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers3 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=3 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=4 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers3 weight=1 [system.ruby.network.topology.int_links2] @@ -282,10 +247,26 @@ type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=5 -node_a=system.ruby.network.topology.ext_links2.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers3 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout index f70cf8f6c..a79f03bf6 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 15:34:13 -gem5 started Jul 10 2012 17:49:52 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:56:32 +gem5 started Jun 4 2012 14:43:05 +gem5 executing on zizzer command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt index de9b59632..b667f4459 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt @@ -4,26 +4,8 @@ sim_seconds 0.000259 # Nu sim_ticks 259241 # Number of ticks simulated final_tick 259241 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1392990 # Simulator tick rate (ticks/s) -host_mem_usage 230820 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l2_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l2_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array +host_tick_rate 2053459 # Simulator tick rate (ticks/s) +host_mem_usage 221360 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini index 22a3e7356..c79554200 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini @@ -76,16 +76,11 @@ version=0 [system.dir_cntrl0.probeFilter] type=RubyCache assoc=4 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=1 replacement_policy=PSEUDO_LRU -resourceStalls=false size=1024 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0] type=L1Cache_Controller @@ -110,44 +105,29 @@ version=0 [system.l1_cntrl0.L1DcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L1IcacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=true latency=2 replacement_policy=PSEUDO_LRU -resourceStalls=false size=256 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.L2cacheMemory] type=RubyCache assoc=2 -dataAccessLatency=1 -dataArrayBanks=1 is_icache=false latency=10 replacement_policy=PSEUDO_LRU -resourceStalls=false size=512 start_index_bit=6 -tagAccessLatency=1 -tagArrayBanks=1 [system.l1_cntrl0.sequencer] type=RubySequencer @@ -200,64 +180,61 @@ topology=system.ruby.network.topology [system.ruby.network.topology] type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 +children=ext_links0 ext_links1 int_links0 int_links1 routers0 routers1 routers2 description=Crossbar ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 print_config=false -routers=system.ruby.network.topology.ext_links0.int_node system.ruby.network.topology.ext_links1.int_node system.ruby.network.topology.int_links0.node_b +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 [system.ruby.network.topology.ext_links0] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.l1_cntrl0 -int_node=system.ruby.network.topology.ext_links0.int_node +int_node=system.ruby.network.topology.routers0 latency=1 link_id=0 weight=1 -[system.ruby.network.topology.ext_links0.int_node] -type=BasicRouter -router_id=0 - [system.ruby.network.topology.ext_links1] type=SimpleExtLink -children=int_node bandwidth_factor=16 ext_node=system.dir_cntrl0 -int_node=system.ruby.network.topology.ext_links1.int_node +int_node=system.ruby.network.topology.routers1 latency=1 link_id=1 weight=1 -[system.ruby.network.topology.ext_links1.int_node] -type=BasicRouter -router_id=1 - [system.ruby.network.topology.int_links0] type=SimpleIntLink -children=node_b bandwidth_factor=16 latency=1 link_id=2 -node_a=system.ruby.network.topology.ext_links0.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers2 weight=1 -[system.ruby.network.topology.int_links0.node_b] -type=BasicRouter -router_id=2 - [system.ruby.network.topology.int_links1] type=SimpleIntLink bandwidth_factor=16 latency=1 link_id=3 -node_a=system.ruby.network.topology.ext_links1.int_node -node_b=system.ruby.network.topology.int_links0.node_b +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers2 weight=1 +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + [system.ruby.profiler] type=RubyProfiler all_instructions=false diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout index 4942a327e..4f76e711e 100755 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jul 10 2012 15:16:15 -gem5 started Jul 10 2012 17:54:42 -gem5 executing on sc2b0605 +gem5 compiled Jun 4 2012 11:51:44 +gem5 started Jun 4 2012 13:42:34 +gem5 executing on zizzer command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt index e6a46ea4d..863fa07d3 100644 --- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt +++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt @@ -4,32 +4,8 @@ sim_seconds 0.000206 # Nu sim_ticks 205611 # Number of ticks simulated final_tick 205611 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000 # Frequency of simulated ticks -host_tick_rate 1499366 # Simulator tick rate (ticks/s) -host_mem_usage 230800 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -system.l1_cntrl0.L1DcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1DcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1DcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1DcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1DcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L1IcacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L1IcacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L1IcacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L1IcacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L1IcacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.l1_cntrl0.L2cacheMemory.num_data_array_reads 0 # number of data array reads -system.l1_cntrl0.L2cacheMemory.num_data_array_writes 0 # number of data array writes -system.l1_cntrl0.L2cacheMemory.num_tag_array_reads 0 # number of tag array reads -system.l1_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes -system.l1_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array -system.l1_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array -system.dir_cntrl0.probeFilter.num_data_array_reads 0 # number of data array reads -system.dir_cntrl0.probeFilter.num_data_array_writes 0 # number of data array writes -system.dir_cntrl0.probeFilter.num_tag_array_reads 0 # number of tag array reads -system.dir_cntrl0.probeFilter.num_tag_array_writes 0 # number of tag array writes -system.dir_cntrl0.probeFilter.num_tag_array_stalls 0 # number of stalls caused by tag array -system.dir_cntrl0.probeFilter.num_data_array_stalls 0 # number of stalls caused by data array +host_tick_rate 2093129 # Simulator tick rate (ticks/s) +host_mem_usage 221128 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host ---------- End Simulation Statistics ---------- |