diff options
Diffstat (limited to 'tests/quick')
40 files changed, 8913 insertions, 0 deletions
diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini new file mode 100644 index 000000000..d40dd35ae --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/config.ini @@ -0,0 +1,231 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[2] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.membus.slave[1] +icache_port=system.membus.slave[0] + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/alpha/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.cpu.icache_port system.cpu.dcache_port system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout new file mode 100755 index 000000000..d203a5e33 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/simout @@ -0,0 +1,14 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:45:30 +gem5 started Jul 8 2015 14:46:17 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-simple + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 405501000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt new file mode 100644 index 000000000..caf16bc43 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-simple/stats.txt @@ -0,0 +1,394 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000406 # Number of seconds simulated +sim_ticks 405501000 # Number of ticks simulated +final_tick 405501000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 137975 # Simulator instruction rate (inst/s) +host_op_rate 137943 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8683882570 # Simulator tick rate (ticks/s) +host_mem_usage 670464 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +sim_insts 6440 # Number of instructions simulated +sim_ops 6440 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 25800 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 8828 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 34628 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 25800 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 25800 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_written::cpu.data 6696 # Number of bytes written to this memory +system.mem_ctrl.bytes_written::total 6696 # Number of bytes written to this memory +system.mem_ctrl.num_reads::cpu.inst 6450 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 1188 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 7638 # Number of read requests responded to by this memory +system.mem_ctrl.num_writes::cpu.data 865 # Number of write requests responded to by this memory +system.mem_ctrl.num_writes::total 865 # Number of write requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 63624997 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 21770600 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 85395597 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 63624997 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 63624997 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 16512906 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 16512906 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 63624997 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 38283506 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 101908503 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 7639 # Number of read requests accepted +system.mem_ctrl.writeReqs 865 # Number of write requests accepted +system.mem_ctrl.readBursts 7639 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 865 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 477632 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 11264 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 34632 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 6696 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 176 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 747 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 1736 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 393 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 768 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 787 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 776 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 293 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 6 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 26 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 257 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 578 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 167 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 1430 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 89 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 156 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 27 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 14 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 44 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 405425000 # Total gap between requests +system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 6620 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 1019 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 56 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 809 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 7463 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 775 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 623.649032 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 407.696259 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 407.140251 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 158 20.39% 20.39% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 63 8.13% 28.52% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 48 6.19% 34.71% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 41 5.29% 40.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 47 6.06% 46.06% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 28 3.61% 49.68% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 28 3.61% 53.29% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 33 4.26% 57.55% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 329 42.45% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 775 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1159.333333 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1053.861325 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 505.634519 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::512-575 1 16.67% 16.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::576-639 1 16.67% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1152-1215 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1344-1407 1 16.67% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1471 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1792-1855 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 26448250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 166379500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 37315000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3543.92 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 22293.92 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1177.88 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 15.15 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 85.41 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 16.51 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 9.32 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.20 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.12 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 23.37 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 6696 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 87 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.72 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 73.73 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 47674.62 # Average gap between requests +system.mem_ctrl.pageHitRate 89.47 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3439800 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1876875 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 37268400 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 213840 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 264293325 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 11250750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 344788110 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 851.023979 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 15542500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 13520000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 376096250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 2419200 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1320000 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 20888400 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 408240 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 26445120 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 228585105 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 42573750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 322639815 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 796.356403 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 69100250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 13520000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 322538500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1188 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1195 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2053 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2063 # DTB accesses +system.cpu.itb.fetch_hits 6451 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6468 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 405501 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6440 # Number of instructions committed +system.cpu.committedOps 6440 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls +system.cpu.num_int_insts 6368 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8380 # number of times the integer registers were read +system.cpu.num_int_register_writes 4614 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2063 # number of memory refs +system.cpu.num_load_insts 1195 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 405501 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1054 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction +system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6450 # Class of executed instruction +system.membus.trans_dist::ReadReq 7639 # Transaction distribution +system.membus.trans_dist::ReadResp 7638 # Transaction distribution +system.membus.trans_dist::WriteReq 865 # Transaction distribution +system.membus.trans_dist::WriteResp 865 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 12901 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4106 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 17007 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 25800 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 15524 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 41324 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 8504 # Request fanout histogram +system.membus.snoop_fanout::mean 0.758584 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.427967 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2053 24.14% 24.14% # Request fanout histogram +system.membus.snoop_fanout::1 6451 75.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 8504 # Request fanout histogram +system.membus.reqLayer0.occupancy 9369000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer0.occupancy 14662500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.6 # Layer utilization (%) +system.membus.respLayer1.occupancy 3576750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini new file mode 100644 index 000000000..e2c1a462b --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/config.ini @@ -0,0 +1,351 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=65536 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.l2bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=65536 + +[system.cpu.dtb] +type=AlphaTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=16384 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.l2bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=16384 + +[system.cpu.interrupts] +type=AlphaInterrupts +eventq_index=0 + +[system.cpu.isa] +type=AlphaISA +eventq_index=0 +system=system + +[system.cpu.itb] +type=AlphaTLB +eventq_index=0 +size=48 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/alpha/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2bus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=262144 +system=system +tags=system.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +cpu_side=system.l2bus.master[0] +mem_side=system.membus.slave[0] + +[system.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=262144 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.l2cache.mem_side system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout new file mode 100755 index 000000000..2fbfbfc77 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/simout @@ -0,0 +1,14 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:45:30 +gem5 started Jul 8 2015 14:46:17 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/ALPHA/tests/opt/quick/se/03.learning-gem5/alpha/linux/learning-gem5-p1-two-level + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello world! +Exiting @ tick 61608000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt new file mode 100644 index 000000000..849193946 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/alpha/linux/learning-gem5-p1-two-level/stats.txt @@ -0,0 +1,715 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000062 # Number of seconds simulated +sim_ticks 61608000 # Number of ticks simulated +final_tick 61608000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 214452 # Simulator instruction rate (inst/s) +host_op_rate 214360 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2049936831 # Simulator tick rate (ticks/s) +host_mem_usage 674692 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 6440 # Number of instructions simulated +sim_ops 6440 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 17792 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 10752 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 28544 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.mem_ctrl.num_reads::cpu.inst 278 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 168 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 446 # Number of read requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 288793663 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 174522789 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 463316452 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 288793663 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 288793663 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 288793663 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 174522789 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 463316452 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 446 # Number of read requests accepted +system.mem_ctrl.writeReqs 0 # Number of write requests accepted +system.mem_ctrl.readBursts 446 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 28544 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 28544 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 62 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 26 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 24 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 43 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 40 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 17 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 1 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 3 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 1 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 19 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 23 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 14 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 116 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 45 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 12 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 61358000 # Total gap between requests +system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 446 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 446 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 95 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 270.147368 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 180.864884 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 259.243949 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 27 28.42% 28.42% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 31 32.63% 61.05% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 11 11.58% 72.63% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 8 8.42% 81.05% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 6 6.32% 87.37% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 6 6.32% 93.68% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 1 1.05% 94.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 5 5.26% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 95 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3464500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11827000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 2230000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 7767.94 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 26517.94 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 463.32 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 463.32 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 3.62 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.62 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 340 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 76.23 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrl.avgGap 137573.99 # Average gap between requests +system.mem_ctrl.pageHitRate 76.23 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1583400 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 37159155 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 262500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 43032375 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 785.782110 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 256750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 52700750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 393120 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 214500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1489800 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 35929665 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1341000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 42928005 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 783.876287 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2295000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 51042000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.dtb.fetch_hits 0 # ITB hits +system.cpu.dtb.fetch_misses 0 # ITB misses +system.cpu.dtb.fetch_acv 0 # ITB acv +system.cpu.dtb.fetch_accesses 0 # ITB accesses +system.cpu.dtb.read_hits 1188 # DTB read hits +system.cpu.dtb.read_misses 7 # DTB read misses +system.cpu.dtb.read_acv 0 # DTB read access violations +system.cpu.dtb.read_accesses 1195 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits +system.cpu.dtb.write_misses 3 # DTB write misses +system.cpu.dtb.write_acv 0 # DTB write access violations +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2053 # DTB hits +system.cpu.dtb.data_misses 10 # DTB misses +system.cpu.dtb.data_acv 0 # DTB access violations +system.cpu.dtb.data_accesses 2063 # DTB accesses +system.cpu.itb.fetch_hits 6451 # ITB hits +system.cpu.itb.fetch_misses 17 # ITB misses +system.cpu.itb.fetch_acv 0 # ITB acv +system.cpu.itb.fetch_accesses 6468 # ITB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_acv 0 # DTB read access violations +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_acv 0 # DTB write access violations +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.data_hits 0 # DTB hits +system.cpu.itb.data_misses 0 # DTB misses +system.cpu.itb.data_acv 0 # DTB access violations +system.cpu.itb.data_accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 17 # Number of system calls +system.cpu.numCycles 61608 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 6440 # Number of instructions committed +system.cpu.committedOps 6440 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 6368 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 10 # Number of float alu accesses +system.cpu.num_func_calls 251 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 754 # number of instructions that are conditional controls +system.cpu.num_int_insts 6368 # number of integer instructions +system.cpu.num_fp_insts 10 # number of float instructions +system.cpu.num_int_register_reads 8380 # number of times the integer registers were read +system.cpu.num_int_register_writes 4614 # number of times the integer registers were written +system.cpu.num_fp_register_reads 8 # number of times the floating registers were read +system.cpu.num_fp_register_writes 2 # number of times the floating registers were written +system.cpu.num_mem_refs 2063 # number of memory refs +system.cpu.num_load_insts 1195 # Number of load instructions +system.cpu.num_store_insts 868 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 61608 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 1054 # Number of branches fetched +system.cpu.op_class::No_OpClass 19 0.29% 0.29% # Class of executed instruction +system.cpu.op_class::IntAlu 4365 67.67% 67.97% # Class of executed instruction +system.cpu.op_class::IntMult 1 0.02% 67.98% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 67.98% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.03% 68.02% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 68.02% # Class of executed instruction +system.cpu.op_class::MemRead 1195 18.53% 86.54% # Class of executed instruction +system.cpu.op_class::MemWrite 868 13.46% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 6450 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 104.300595 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1885 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.220238 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 104.300595 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.101856 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.101856 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 156 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.164062 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4274 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4274 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1093 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1093 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 792 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 792 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1885 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1885 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1885 # number of overall hits +system.cpu.dcache.overall_hits::total 1885 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 95 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 95 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 73 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 168 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 168 # number of overall misses +system.cpu.dcache.overall_misses::total 168 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9733000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9733000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 7588000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 7588000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17321000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17321000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17321000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17321000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1188 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1188 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2053 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2053 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2053 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2053 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.084393 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081831 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081831 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081831 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081831 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102452.631579 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 102452.631579 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 103945.205479 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 103945.205479 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 103101.190476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 103101.190476 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 103101.190476 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 9543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7442000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7442000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 16985000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 16985000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 16985000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 16985000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.079966 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.079966 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.081831 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.081831 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.081831 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100452.631579 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100452.631579 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 101945.205479 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 101945.205479 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101101.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 101101.190476 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 62 # number of replacements +system.cpu.icache.tags.tagsinuse 113.923956 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 6170 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 281 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 21.957295 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 113.923956 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.445015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.445015 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 219 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 52 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 167 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.855469 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 13183 # Number of tag accesses +system.cpu.icache.tags.data_accesses 13183 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 6170 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 6170 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 6170 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 6170 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 6170 # number of overall hits +system.cpu.icache.overall_hits::total 6170 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 281 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 281 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 281 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 281 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 281 # number of overall misses +system.cpu.icache.overall_misses::total 281 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28179000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28179000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28179000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28179000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28179000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28179000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 6451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 6451 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 6451 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 6451 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 6451 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 6451 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.043559 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.043559 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.043559 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.043559 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.043559 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.043559 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100281.138790 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100281.138790 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100281.138790 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100281.138790 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100281.138790 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 281 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 281 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 281 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 281 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 281 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 281 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27617000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27617000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27617000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27617000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.043559 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.043559 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.043559 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.043559 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98281.138790 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98281.138790 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98281.138790 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 98281.138790 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.trans_dist::ReadResp 376 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 62 # Transaction distribution +system.l2bus.trans_dist::ReadExReq 73 # Transaction distribution +system.l2bus.trans_dist::ReadExResp 73 # Transaction distribution +system.l2bus.trans_dist::ReadSharedReq 376 # Transaction distribution +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 17984 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size::total 28736 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.snoops 0 # Total snoops (count) +system.l2bus.snoop_fanout::samples 511 # Request fanout histogram +system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 511 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::total 511 # Request fanout histogram +system.l2bus.reqLayer0.occupancy 511000 # Layer occupancy (ticks) +system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.l2bus.respLayer0.occupancy 843000 # Layer occupancy (ticks) +system.l2bus.respLayer0.utilization 1.4 # Layer utilization (%) +system.l2bus.respLayer1.occupancy 504000 # Layer occupancy (ticks) +system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.l2cache.tags.replacements 0 # number of replacements +system.l2cache.tags.tagsinuse 185.387550 # Cycle average of tags in use +system.l2cache.tags.total_refs 65 # Total number of references to valid blocks. +system.l2cache.tags.sampled_refs 373 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.174263 # Average number of references to valid blocks. +system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2cache.tags.occ_blocks::cpu.inst 128.677366 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 56.710184 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031415 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.013845 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.045261 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 373 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 311 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.091064 # Percentage of cache occupancy per task id +system.l2cache.tags.tag_accesses 4534 # Number of tag accesses +system.l2cache.tags.data_accesses 4534 # Number of data accesses +system.l2cache.ReadSharedReq_hits::cpu.inst 3 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits +system.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits +system.l2cache.demand_hits::total 3 # number of demand (read+write) hits +system.l2cache.overall_hits::cpu.inst 3 # number of overall hits +system.l2cache.overall_hits::total 3 # number of overall hits +system.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses +system.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses +system.l2cache.ReadSharedReq_misses::cpu.inst 278 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::cpu.data 95 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::total 373 # number of ReadSharedReq misses +system.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses +system.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses +system.l2cache.demand_misses::total 446 # number of demand (read+write) misses +system.l2cache.overall_misses::cpu.inst 278 # number of overall misses +system.l2cache.overall_misses::cpu.data 168 # number of overall misses +system.l2cache.overall_misses::total 446 # number of overall misses +system.l2cache.ReadExReq_miss_latency::cpu.data 7223000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7223000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 26711000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 9258000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 35969000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 26711000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 16481000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 43192000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 26711000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 16481000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 43192000 # number of overall miss cycles +system.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.inst 281 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.data 95 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::total 376 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.demand_accesses::cpu.inst 281 # number of demand (read+write) accesses +system.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses +system.l2cache.demand_accesses::total 449 # number of demand (read+write) accesses +system.l2cache.overall_accesses::cpu.inst 281 # number of overall (read+write) accesses +system.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses +system.l2cache.overall_accesses::total 449 # number of overall (read+write) accesses +system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.989324 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::total 0.992021 # miss rate for ReadSharedReq accesses +system.l2cache.demand_miss_rate::cpu.inst 0.989324 # miss rate for demand accesses +system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.l2cache.demand_miss_rate::total 0.993318 # miss rate for demand accesses +system.l2cache.overall_miss_rate::cpu.inst 0.989324 # miss rate for overall accesses +system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.l2cache.overall_miss_rate::total 0.993318 # miss rate for overall accesses +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 98945.205479 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 98945.205479 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96082.733813 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97452.631579 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96431.635389 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96843.049327 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96082.733813 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 98101.190476 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96843.049327 # average overall miss latency +system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2cache.fast_writes 0 # number of fast writes performed +system.l2cache.cache_copies 0 # number of cache copies performed +system.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses +system.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 278 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.data 95 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::total 373 # number of ReadSharedReq MSHR misses +system.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::total 446 # number of demand (read+write) MSHR misses +system.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5763000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 5763000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 21151000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7358000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 28509000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 21151000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 13121000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 34272000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 21151000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 13121000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 34272000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.992021 # mshr miss rate for ReadSharedReq accesses +system.l2cache.demand_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::total 0.993318 # mshr miss rate for demand accesses +system.l2cache.overall_mshr_miss_rate::cpu.inst 0.989324 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::total 0.993318 # mshr miss rate for overall accesses +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 78945.205479 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 78945.205479 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76082.733813 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77452.631579 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76431.635389 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76082.733813 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78101.190476 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76843.049327 # average overall mshr miss latency +system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadResp 373 # Transaction distribution +system.membus.trans_dist::ReadExReq 73 # Transaction distribution +system.membus.trans_dist::ReadExResp 73 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 373 # Transaction distribution +system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 892 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28544 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 446 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 446 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 446 # Request fanout histogram +system.membus.reqLayer0.occupancy 446000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 2375000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini new file mode 100644 index 000000000..9250f1293 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/config.ini @@ -0,0 +1,328 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[2] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dstage2_mmu dtb interrupts isa istage2_mmu itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.membus.slave[1] +icache_port=system.membus.slave[0] + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/arm/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.cpu.icache_port system.cpu.dcache_port system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout new file mode 100755 index 000000000..0a8438e59 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/simout @@ -0,0 +1,13 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:23:26 +gem5 started Jul 8 2015 14:24:31 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-simple + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 325849000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt new file mode 100644 index 000000000..a106dd982 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-simple/stats.txt @@ -0,0 +1,480 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000326 # Number of seconds simulated +sim_ticks 325849000 # Number of ticks simulated +final_tick 325849000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 60983 # Simulator instruction rate (inst/s) +host_op_rate 70534 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3982742967 # Simulator tick rate (ticks/s) +host_mem_usage 686060 # Number of bytes of host memory used +host_seconds 0.08 # Real time elapsed on the host +sim_insts 4988 # Number of instructions simulated +sim_ops 5770 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 20108 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 4672 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 24780 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 20108 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 20108 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_written::cpu.data 3696 # Number of bytes written to this memory +system.mem_ctrl.bytes_written::total 3696 # Number of bytes written to this memory +system.mem_ctrl.num_reads::cpu.inst 5027 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 1061 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 6088 # Number of read requests responded to by this memory +system.mem_ctrl.num_writes::cpu.data 936 # Number of write requests responded to by this memory +system.mem_ctrl.num_writes::total 936 # Number of write requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 61709565 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 14337930 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 76047494 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 61709565 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 61709565 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 11342677 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 11342677 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 61709565 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 25680607 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 87390172 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 6089 # Number of read requests accepted +system.mem_ctrl.writeReqs 936 # Number of write requests accepted +system.mem_ctrl.readBursts 6089 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 936 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 384000 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 5696 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 3072 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 24784 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 3696 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 89 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 856 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 911 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 1454 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 724 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 364 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 505 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 303 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 487 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 206 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 42 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 155 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 194 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 431 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 108 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 36 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 80 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 13 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 30 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 325773000 # Total gap between requests +system.mem_ctrl.readPktSize::0 70 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 5858 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 160 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 16 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 920 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 5991 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 9 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 3 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 495 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 775.886869 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 648.412049 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 330.044561 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 19 3.84% 3.84% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 31 6.26% 10.10% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 37 7.47% 17.58% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 33 6.67% 24.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 20 4.04% 28.28% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 33 6.67% 34.95% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 27 5.45% 40.40% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 25 5.05% 45.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 270 54.55% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 495 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 3 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1299.666667 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1199.462709 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 577.403094 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-703 1 33.33% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1471 1 33.33% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1792-1855 1 33.33% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 3 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 3 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::16 3 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 3 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 17801000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 130301000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 30000000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 2966.83 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 21716.83 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1178.46 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 9.43 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 76.06 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 11.34 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 9.28 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.21 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.07 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 24.64 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5504 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 44 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 91.73 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 55.00 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 46373.38 # Average gap between requests +system.mem_ctrl.pageHitRate 91.25 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2782080 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1518000 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 37915800 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 212134050 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 5616000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 280816890 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 878.932981 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 6234500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 303655500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 922320 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 503250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 7932600 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 311040 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 20850960 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 182238975 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 31839000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 244598145 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 765.574385 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 52679500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 10660000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 256888500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.numCycles 325849 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 4988 # Number of instructions committed +system.cpu.committedOps 5770 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 215 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls +system.cpu.num_int_insts 4977 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 8084 # number of times the integer registers were read +system.cpu.num_int_register_writes 2992 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read +system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written +system.cpu.num_mem_refs 2035 # number of memory refs +system.cpu.num_load_insts 1085 # Number of load instructions +system.cpu.num_store_insts 950 # Number of store instructions +system.cpu.num_idle_cycles 0.001000 # Number of idle cycles +system.cpu.num_busy_cycles 325848.999000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 1107 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction +system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5831 # Class of executed instruction +system.membus.trans_dist::ReadReq 6078 # Transaction distribution +system.membus.trans_dist::ReadResp 6088 # Transaction distribution +system.membus.trans_dist::WriteReq 925 # Transaction distribution +system.membus.trans_dist::WriteResp 925 # Transaction distribution +system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondReq 11 # Transaction distribution +system.membus.trans_dist::StoreCondResp 11 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 14049 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 28476 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7025 # Request fanout histogram +system.membus.snoop_fanout::mean 0.715730 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.451098 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1997 28.43% 28.43% # Request fanout histogram +system.membus.snoop_fanout::1 5028 71.57% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 7025 # Request fanout histogram +system.membus.reqLayer0.occupancy 7961000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) +system.membus.respLayer0.occupancy 11411750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3326000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini new file mode 100644 index 000000000..b60a06c99 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/config.ini @@ -0,0 +1,448 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dcache dstage2_mmu dtb icache interrupts isa istage2_mmu itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dstage2_mmu=system.cpu.dstage2_mmu +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +istage2_mmu=system.cpu.istage2_mmu +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=65536 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.l2bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=65536 + +[system.cpu.dstage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.dtb + +[system.cpu.dstage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.dstage2_mmu.stage2_tlb.walker + +[system.cpu.dstage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.dtb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=16384 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.l2bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=16384 + +[system.cpu.interrupts] +type=ArmInterrupts +eventq_index=0 + +[system.cpu.isa] +type=ArmISA +eventq_index=0 +fpsid=1090793632 +id_aa64afr0_el1=0 +id_aa64afr1_el1=0 +id_aa64dfr0_el1=1052678 +id_aa64dfr1_el1=0 +id_aa64isar0_el1=0 +id_aa64isar1_el1=0 +id_aa64mmfr0_el1=15728642 +id_aa64mmfr1_el1=0 +id_aa64pfr0_el1=17 +id_aa64pfr1_el1=0 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=270536963 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=34611729 +id_pfr0=49 +id_pfr1=4113 +midr=1091551472 +pmu=Null +system=system + +[system.cpu.istage2_mmu] +type=ArmStage2MMU +children=stage2_tlb +eventq_index=0 +stage2_tlb=system.cpu.istage2_mmu.stage2_tlb +sys=system +tlb=system.cpu.itb + +[system.cpu.istage2_mmu.stage2_tlb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=true +size=32 +walker=system.cpu.istage2_mmu.stage2_tlb.walker + +[system.cpu.istage2_mmu.stage2_tlb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=true +num_squash_per_cycle=2 +sys=system + +[system.cpu.itb] +type=ArmTLB +children=walker +eventq_index=0 +is_stage2=false +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=ArmTableWalker +clk_domain=system.clk_domain +eventq_index=0 +is_stage2=false +num_squash_per_cycle=2 +sys=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/arm/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2bus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=262144 +system=system +tags=system.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +cpu_side=system.l2bus.master[0] +mem_side=system.membus.slave[0] + +[system.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=262144 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.l2cache.mem_side system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout new file mode 100755 index 000000000..cd1c56413 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/simout @@ -0,0 +1,13 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:23:26 +gem5 started Jul 8 2015 14:24:31 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/ARM/tests/opt/quick/se/03.learning-gem5/arm/linux/learning-gem5-p1-two-level + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 49855000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt new file mode 100644 index 000000000..dde0dd6ed --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/arm/linux/learning-gem5-p1-two-level/stats.txt @@ -0,0 +1,812 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000050 # Number of seconds simulated +sim_ticks 49855000 # Number of ticks simulated +final_tick 49855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 79800 # Simulator instruction rate (inst/s) +host_op_rate 92294 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 797317444 # Simulator tick rate (ticks/s) +host_mem_usage 690160 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +sim_insts 4988 # Number of instructions simulated +sim_ops 5770 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 14400 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 8064 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 22464 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory +system.mem_ctrl.num_reads::cpu.inst 225 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 126 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 351 # Number of read requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 288837629 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 161749072 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 450586701 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 288837629 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 288837629 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 288837629 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 161749072 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 450586701 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 351 # Number of read requests accepted +system.mem_ctrl.writeReqs 0 # Number of write requests accepted +system.mem_ctrl.readBursts 351 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 22464 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 22464 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 78 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 42 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 13 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 33 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 14 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 31 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 34 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 9 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 4 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 6 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 25 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 43 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 8 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 5 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 49757000 # Total gap between requests +system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 351 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 351 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 73 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 300.712329 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 214.051474 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 262.513782 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 14 19.18% 19.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 25 34.25% 53.42% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 13 17.81% 71.23% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 6 8.22% 79.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 7 9.59% 89.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 1 1.37% 90.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 2 2.74% 93.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 5 6.85% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 73 # Bytes accessed per row activation +system.mem_ctrl.totQLat 2542000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 9123250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 1755000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 7242.17 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 25992.17 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 450.59 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 450.59 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 3.52 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.52 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 274 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 78.06 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrl.avgGap 141757.83 # Average gap between requests +system.mem_ctrl.pageHitRate 78.06 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 347760 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 189750 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1825200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 31478535 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 573750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37466355 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 797.538290 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 1053000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 44628000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 189000 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 103125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 741000 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 30270420 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1633500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 35988405 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 766.077484 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2556000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 42875250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.dtb.walker.walks 0 # Table walker walks requested +system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.dtb.inst_hits 0 # ITB inst hits +system.cpu.dtb.inst_misses 0 # ITB inst misses +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.inst_accesses 0 # ITB inst accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits +system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses +system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits +system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses +system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits +system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses +system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses +system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses +system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses +system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits +system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses +system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses +system.cpu.itb.walker.walks 0 # Table walker walks requested +system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst +system.cpu.itb.inst_hits 0 # ITB inst hits +system.cpu.itb.inst_misses 0 # ITB inst misses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed +system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA +system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID +system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID +system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB +system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions +system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch +system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions +system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.inst_accesses 0 # ITB inst accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 13 # Number of system calls +system.cpu.numCycles 49855 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 4988 # Number of instructions committed +system.cpu.committedOps 5770 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4977 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses +system.cpu.num_func_calls 215 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 800 # number of instructions that are conditional controls +system.cpu.num_int_insts 4977 # number of integer instructions +system.cpu.num_fp_insts 16 # number of float instructions +system.cpu.num_int_register_reads 8084 # number of times the integer registers were read +system.cpu.num_int_register_writes 2992 # number of times the integer registers were written +system.cpu.num_fp_register_reads 16 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 20681 # number of times the CC registers were read +system.cpu.num_cc_register_writes 2647 # number of times the CC registers were written +system.cpu.num_mem_refs 2035 # number of memory refs +system.cpu.num_load_insts 1085 # Number of load instructions +system.cpu.num_store_insts 950 # Number of store instructions +system.cpu.num_idle_cycles 0.001000 # Number of idle cycles +system.cpu.num_busy_cycles 49854.999000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 1107 # Number of branches fetched +system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction +system.cpu.op_class::IntAlu 3789 64.98% 64.98% # Class of executed instruction +system.cpu.op_class::IntMult 4 0.07% 65.05% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% # Class of executed instruction +system.cpu.op_class::MemRead 1085 18.61% 83.71% # Class of executed instruction +system.cpu.op_class::MemWrite 950 16.29% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5831 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 84.307513 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1855 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.063380 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 84.307513 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.082332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.082332 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 19 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.138672 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4136 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4136 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 951 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 951 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 882 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 882 # number of WriteReq hits +system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits +system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits +system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits +system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits +system.cpu.dcache.demand_hits::cpu.data 1833 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1833 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1833 # number of overall hits +system.cpu.dcache.overall_hits::total 1833 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 99 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 99 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 142 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 142 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 142 # number of overall misses +system.cpu.dcache.overall_misses::total 142 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8771000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8771000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4421000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4421000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13192000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13192000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13192000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13192000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1050 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1050 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1975 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1975 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1975 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1975 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.094286 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.094286 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.046486 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.046486 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.071899 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.071899 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.071899 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.071899 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 88595.959596 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 88595.959596 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102813.953488 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102813.953488 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 92901.408451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 92901.408451 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 92901.408451 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 99 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 99 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8573000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8573000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4335000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4335000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12908000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12908000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12908000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12908000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.094286 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.094286 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046486 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046486 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.071899 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.071899 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.071899 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86595.959596 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86595.959596 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100813.953488 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100813.953488 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 90901.408451 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 90901.408451 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 70 # number of replacements +system.cpu.icache.tags.tagsinuse 96.491667 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4779 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 249 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 19.192771 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 96.491667 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.376921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.376921 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 179 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 125 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.699219 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 10305 # Number of tag accesses +system.cpu.icache.tags.data_accesses 10305 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4779 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4779 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4779 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4779 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4779 # number of overall hits +system.cpu.icache.overall_hits::total 4779 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 249 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 249 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 249 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 249 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 249 # number of overall misses +system.cpu.icache.overall_misses::total 249 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23407000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23407000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23407000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23407000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23407000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23407000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5028 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5028 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5028 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5028 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5028 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.049523 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.049523 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.049523 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.049523 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.049523 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.049523 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 94004.016064 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 94004.016064 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 94004.016064 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 94004.016064 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 94004.016064 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 249 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 249 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 249 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 249 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 249 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22909000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22909000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22909000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22909000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22909000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22909000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.049523 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.049523 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.049523 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.049523 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 92004.016064 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 92004.016064 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 92004.016064 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 92004.016064 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.trans_dist::ReadResp 348 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 60 # Transaction distribution +system.l2bus.trans_dist::ReadExReq 43 # Transaction distribution +system.l2bus.trans_dist::ReadExResp 43 # Transaction distribution +system.l2bus.trans_dist::ReadSharedReq 348 # Transaction distribution +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 558 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 842 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15936 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size::total 25024 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.snoops 0 # Total snoops (count) +system.l2bus.snoop_fanout::samples 461 # Request fanout histogram +system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 461 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::total 461 # Request fanout histogram +system.l2bus.reqLayer0.occupancy 461000 # Layer occupancy (ticks) +system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.l2bus.respLayer0.occupancy 747000 # Layer occupancy (ticks) +system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer1.occupancy 426000 # Layer occupancy (ticks) +system.l2bus.respLayer1.utilization 0.9 # Layer utilization (%) +system.l2cache.tags.replacements 0 # number of replacements +system.l2cache.tags.tagsinuse 156.235366 # Cycle average of tags in use +system.l2cache.tags.total_refs 100 # Total number of references to valid blocks. +system.l2cache.tags.sampled_refs 308 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.324675 # Average number of references to valid blocks. +system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2cache.tags.occ_blocks::cpu.inst 107.216430 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 49.018936 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026176 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.011968 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.038143 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 308 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 246 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.075195 # Percentage of cache occupancy per task id +system.l2cache.tags.tag_accesses 3959 # Number of tag accesses +system.l2cache.tags.data_accesses 3959 # Number of data accesses +system.l2cache.ReadSharedReq_hits::cpu.inst 24 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::cpu.data 16 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::total 40 # number of ReadSharedReq hits +system.l2cache.demand_hits::cpu.inst 24 # number of demand (read+write) hits +system.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits +system.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.l2cache.overall_hits::cpu.inst 24 # number of overall hits +system.l2cache.overall_hits::cpu.data 16 # number of overall hits +system.l2cache.overall_hits::total 40 # number of overall hits +system.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses +system.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses +system.l2cache.ReadSharedReq_misses::cpu.inst 225 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::cpu.data 83 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::total 308 # number of ReadSharedReq misses +system.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses +system.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses +system.l2cache.demand_misses::total 351 # number of demand (read+write) misses +system.l2cache.overall_misses::cpu.inst 225 # number of overall misses +system.l2cache.overall_misses::cpu.data 126 # number of overall misses +system.l2cache.overall_misses::total 351 # number of overall misses +system.l2cache.ReadExReq_miss_latency::cpu.data 4206000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 4206000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 21658000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 7940000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 29598000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 21658000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 12146000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 33804000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 21658000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 12146000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 33804000 # number of overall miss cycles +system.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.inst 249 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.data 99 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::total 348 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.demand_accesses::cpu.inst 249 # number of demand (read+write) accesses +system.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses +system.l2cache.demand_accesses::total 391 # number of demand (read+write) accesses +system.l2cache.overall_accesses::cpu.inst 249 # number of overall (read+write) accesses +system.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses +system.l2cache.overall_accesses::total 391 # number of overall (read+write) accesses +system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.903614 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.838384 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::total 0.885057 # miss rate for ReadSharedReq accesses +system.l2cache.demand_miss_rate::cpu.inst 0.903614 # miss rate for demand accesses +system.l2cache.demand_miss_rate::cpu.data 0.887324 # miss rate for demand accesses +system.l2cache.demand_miss_rate::total 0.897698 # miss rate for demand accesses +system.l2cache.overall_miss_rate::cpu.inst 0.903614 # miss rate for overall accesses +system.l2cache.overall_miss_rate::cpu.data 0.887324 # miss rate for overall accesses +system.l2cache.overall_miss_rate::total 0.897698 # miss rate for overall accesses +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97813.953488 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97813.953488 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96257.777778 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95662.650602 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96097.402597 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96307.692308 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96257.777778 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 96396.825397 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96307.692308 # average overall miss latency +system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2cache.fast_writes 0 # number of fast writes performed +system.l2cache.cache_copies 0 # number of cache copies performed +system.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses +system.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 225 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.data 83 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::total 308 # number of ReadSharedReq MSHR misses +system.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::cpu.data 126 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses +system.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::cpu.data 126 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::total 351 # number of overall MSHR misses +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3346000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 3346000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17158000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6280000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23438000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17158000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 9626000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 26784000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17158000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 9626000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 26784000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.838384 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.885057 # mshr miss rate for ReadSharedReq accesses +system.l2cache.demand_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::total 0.897698 # mshr miss rate for demand accesses +system.l2cache.overall_mshr_miss_rate::cpu.inst 0.903614 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::cpu.data 0.887324 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::total 0.897698 # mshr miss rate for overall accesses +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77813.953488 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77813.953488 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76257.777778 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75662.650602 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76097.402597 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76257.777778 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76396.825397 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76307.692308 # average overall mshr miss latency +system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadResp 308 # Transaction distribution +system.membus.trans_dist::ReadExReq 43 # Transaction distribution +system.membus.trans_dist::ReadExResp 43 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 308 # Transaction distribution +system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 702 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 702 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 22464 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 22464 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 351 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 351 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 351 # Request fanout histogram +system.membus.reqLayer0.occupancy 351000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 1865750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini new file mode 100644 index 000000000..d544c7127 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/config.ini @@ -0,0 +1,233 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[2] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.membus.slave[1] +icache_port=system.membus.slave[0] + +[system.cpu.dtb] +type=MipsTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=MipsInterrupts +eventq_index=0 + +[system.cpu.isa] +type=MipsISA +eventq_index=0 +num_threads=1 +num_vpes=1 +system=system + +[system.cpu.itb] +type=MipsTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/mips/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.cpu.icache_port system.cpu.dcache_port system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr new file mode 100755 index 000000000..b3b7d2ff9 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simerr @@ -0,0 +1,3 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections +warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout new file mode 100755 index 000000000..176599fd7 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/simout @@ -0,0 +1,14 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:37:59 +gem5 started Jul 8 2015 14:38:43 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-simple + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello World! +Exiting @ tick 367783000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt new file mode 100644 index 000000000..8c280514f --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-simple/stats.txt @@ -0,0 +1,378 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000368 # Number of seconds simulated +sim_ticks 367783000 # Number of ticks simulated +final_tick 367783000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 231595 # Simulator instruction rate (inst/s) +host_op_rate 231486 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15131443313 # Simulator tick rate (ticks/s) +host_mem_usage 668760 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +sim_insts 5624 # Number of instructions simulated +sim_ops 5624 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 22500 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 4289 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 26789 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 22500 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 22500 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_written::cpu.data 3601 # Number of bytes written to this memory +system.mem_ctrl.bytes_written::total 3601 # Number of bytes written to this memory +system.mem_ctrl.num_reads::cpu.inst 5625 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 1132 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 6757 # Number of read requests responded to by this memory +system.mem_ctrl.num_writes::cpu.data 901 # Number of write requests responded to by this memory +system.mem_ctrl.num_writes::total 901 # Number of write requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 61177379 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 11661768 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 72839147 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 61177379 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 61177379 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 9791100 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 9791100 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 61177379 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 21452868 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 82630247 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 6758 # Number of read requests accepted +system.mem_ctrl.writeReqs 901 # Number of write requests accepted +system.mem_ctrl.readBursts 6758 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 901 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 426368 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6144 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 4096 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 26793 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 3601 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 96 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 807 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 275 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 215 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 18 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 105 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 518 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 543 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 1211 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 899 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 346 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 677 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 396 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 1409 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 50 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 6 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 8 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 29 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 19 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 2 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 367707000 # Total gap between requests +system.mem_ctrl.readPktSize::0 79 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 1 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 6678 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 1 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 900 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 6662 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 5 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 4 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 842 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 509.263658 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 293.556275 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 414.582189 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 268 31.83% 31.83% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 81 9.62% 41.45% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 48 5.70% 47.15% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 49 5.82% 52.97% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 36 4.28% 57.24% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 49 5.82% 63.06% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 19 2.26% 65.32% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 21 2.49% 67.81% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 271 32.19% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 842 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 4 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1344.750000 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 1258.849963 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 502.036104 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-703 1 25.00% 25.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1216-1279 1 25.00% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1600-1663 1 25.00% 75.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1792-1855 1 25.00% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 4 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 4 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 4 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 27926000 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 152838500 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 33310000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 4191.83 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 22941.83 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1159.29 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 11.14 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 72.85 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 9.79 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 9.14 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.06 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.09 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 23.24 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5822 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 58 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 87.39 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 61.70 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 48009.79 # Average gap between requests +system.mem_ctrl.pageHitRate 87.03 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 1058400 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 577500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 8821800 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 38880 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 136778625 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 99747000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 270924525 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 739.798888 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 164402500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 189605000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 5299560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 2891625 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 42907800 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 375840 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 23902320 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 246879540 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 3167250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 325423935 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 888.617467 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 3404750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 12220000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 350602750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.numCycles 367783 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5624 # Number of instructions committed +system.cpu.committedOps 5624 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses +system.cpu.num_func_calls 190 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls +system.cpu.num_int_insts 4944 # number of integer instructions +system.cpu.num_fp_insts 2 # number of float instructions +system.cpu.num_int_register_reads 7054 # number of times the integer registers were read +system.cpu.num_int_register_writes 3281 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1 # number of times the floating registers were written +system.cpu.num_mem_refs 2034 # number of memory refs +system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_store_insts 902 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 367783 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 883 # Number of branches fetched +system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction +system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction +system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5625 # Class of executed instruction +system.membus.trans_dist::ReadReq 6758 # Transaction distribution +system.membus.trans_dist::ReadResp 6757 # Transaction distribution +system.membus.trans_dist::WriteReq 901 # Transaction distribution +system.membus.trans_dist::WriteResp 901 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11251 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4066 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 15317 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22500 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 7890 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 30390 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 7659 # Request fanout histogram +system.membus.snoop_fanout::mean 0.734561 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.441596 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2033 26.54% 26.54% # Request fanout histogram +system.membus.snoop_fanout::1 5626 73.46% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 7659 # Request fanout histogram +system.membus.reqLayer0.occupancy 8560000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer0.occupancy 12820000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.5 # Layer utilization (%) +system.membus.respLayer1.occupancy 3545250 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 1.0 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini new file mode 100644 index 000000000..f11778fb3 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/config.ini @@ -0,0 +1,353 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=65536 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.l2bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=65536 + +[system.cpu.dtb] +type=MipsTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=16384 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.l2bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=16384 + +[system.cpu.interrupts] +type=MipsInterrupts +eventq_index=0 + +[system.cpu.isa] +type=MipsISA +eventq_index=0 +num_threads=1 +num_vpes=1 +system=system + +[system.cpu.itb] +type=MipsTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/mips/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2bus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=262144 +system=system +tags=system.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +cpu_side=system.l2bus.master[0] +mem_side=system.membus.slave[0] + +[system.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=262144 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.l2cache.mem_side system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr new file mode 100755 index 000000000..b3b7d2ff9 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simerr @@ -0,0 +1,3 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections +warn: mmap failing: arguments not page-aligned: start 0x0 offset 0x7efefeff diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout new file mode 100755 index 000000000..2deebf5ec --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/simout @@ -0,0 +1,14 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:37:59 +gem5 started Jul 8 2015 14:38:43 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/MIPS/tests/opt/quick/se/03.learning-gem5/mips/linux/learning-gem5-p1-two-level + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +info: Increasing stack size by one page. +Hello World! +Exiting @ tick 58892000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt new file mode 100644 index 000000000..00ce95d37 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/mips/linux/learning-gem5-p1-two-level/stats.txt @@ -0,0 +1,701 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000059 # Number of seconds simulated +sim_ticks 58892000 # Number of ticks simulated +final_tick 58892000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 807198 # Simulator instruction rate (inst/s) +host_op_rate 805914 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8425106508 # Simulator tick rate (ticks/s) +host_mem_usage 672980 # Number of bytes of host memory used +host_seconds 0.01 # Real time elapsed on the host +sim_insts 5624 # Number of instructions simulated +sim_ops 5624 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 18752 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 27520 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory +system.mem_ctrl.num_reads::cpu.inst 293 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 430 # Number of read requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 318413367 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 148882701 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 467296067 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 318413367 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 318413367 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 318413367 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 148882701 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 467296067 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 430 # Number of read requests accepted +system.mem_ctrl.writeReqs 0 # Number of write requests accepted +system.mem_ctrl.readBursts 430 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 27520 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 27520 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 25 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 6 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 3 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 11 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 49 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 53 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 74 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 34 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 19 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 50 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 27 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 72 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 7 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 58762000 # Total gap between requests +system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 430 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 430 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 113 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 232.212389 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 169.054443 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 210.567831 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 30 26.55% 26.55% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 44 38.94% 65.49% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 17 15.04% 80.53% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 9 7.96% 88.50% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 5 4.42% 92.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 4 3.54% 96.46% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 1 0.88% 97.35% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.65% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 113 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3878500 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 11941000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 2150000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 9019.77 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 27769.77 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 467.30 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 467.30 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 3.65 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.65 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 313 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 72.79 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrl.avgGap 136655.81 # Average gap between requests +system.mem_ctrl.pageHitRate 72.79 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 196560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 107250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 678600 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 26204040 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 9872250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 40618620 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 741.706329 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 17140250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 36672750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 635040 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 346500 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 2425800 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 37227555 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 202500 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 44397315 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 810.706261 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 145000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 52812500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.dtb.read_hits 0 # DTB read hits +system.cpu.dtb.read_misses 0 # DTB read misses +system.cpu.dtb.read_accesses 0 # DTB read accesses +system.cpu.dtb.write_hits 0 # DTB write hits +system.cpu.dtb.write_misses 0 # DTB write misses +system.cpu.dtb.write_accesses 0 # DTB write accesses +system.cpu.dtb.hits 0 # DTB hits +system.cpu.dtb.misses 0 # DTB misses +system.cpu.dtb.accesses 0 # DTB accesses +system.cpu.itb.read_hits 0 # DTB read hits +system.cpu.itb.read_misses 0 # DTB read misses +system.cpu.itb.read_accesses 0 # DTB read accesses +system.cpu.itb.write_hits 0 # DTB write hits +system.cpu.itb.write_misses 0 # DTB write misses +system.cpu.itb.write_accesses 0 # DTB write accesses +system.cpu.itb.hits 0 # DTB hits +system.cpu.itb.misses 0 # DTB misses +system.cpu.itb.accesses 0 # DTB accesses +system.cpu.workload.num_syscalls 7 # Number of system calls +system.cpu.numCycles 58892 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5624 # Number of instructions committed +system.cpu.committedOps 5624 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses +system.cpu.num_func_calls 190 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls +system.cpu.num_int_insts 4944 # number of integer instructions +system.cpu.num_fp_insts 2 # number of float instructions +system.cpu.num_int_register_reads 7054 # number of times the integer registers were read +system.cpu.num_int_register_writes 3281 # number of times the integer registers were written +system.cpu.num_fp_register_reads 3 # number of times the floating registers were read +system.cpu.num_fp_register_writes 1 # number of times the floating registers were written +system.cpu.num_mem_refs 2034 # number of memory refs +system.cpu.num_load_insts 1132 # Number of load instructions +system.cpu.num_store_insts 902 # Number of store instructions +system.cpu.num_idle_cycles 0 # Number of idle cycles +system.cpu.num_busy_cycles 58892 # Number of busy cycles +system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu.idle_fraction 0 # Percentage of idle cycles +system.cpu.Branches 883 # Number of branches fetched +system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction +system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction +system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction +system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction +system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction +system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5625 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 86.277492 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 86.277492 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.084255 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.084255 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 6 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.133789 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits +system.cpu.dcache.overall_hits::total 1896 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses +system.cpu.dcache.overall_misses::total 137 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8910000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8910000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 5264000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 5264000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14174000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14174000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14174000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14174000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 102413.793103 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 102413.793103 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 105280 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 105280 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 103459.854015 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 103459.854015 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 103459.854015 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8736000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 8736000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5164000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 5164000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13900000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13900000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13900000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13900000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 100413.793103 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 100413.793103 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 103280 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 103280 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 101459.854015 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 101459.854015 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 94 # number of replacements +system.cpu.icache.tags.tagsinuse 110.157629 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5329 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 297 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 17.942761 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 110.157629 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.430303 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.430303 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 203 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 139 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.792969 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11549 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11549 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5329 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5329 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5329 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5329 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5329 # number of overall hits +system.cpu.icache.overall_hits::total 5329 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 297 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 297 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 297 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 297 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 297 # number of overall misses +system.cpu.icache.overall_misses::total 297 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 30270000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 30270000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 30270000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 30270000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 30270000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 30270000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052791 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052791 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052791 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052791 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052791 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052791 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101919.191919 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101919.191919 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101919.191919 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101919.191919 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101919.191919 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 297 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 297 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 297 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 297 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 297 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 297 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29676000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 29676000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29676000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 29676000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29676000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 29676000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052791 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052791 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052791 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052791 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99919.191919 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99919.191919 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99919.191919 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99919.191919 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.trans_dist::ReadResp 384 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 94 # Transaction distribution +system.l2bus.trans_dist::ReadExReq 50 # Transaction distribution +system.l2bus.trans_dist::ReadExResp 50 # Transaction distribution +system.l2bus.trans_dist::ReadSharedReq 384 # Transaction distribution +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 688 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 962 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 19008 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size::total 27776 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.snoops 0 # Total snoops (count) +system.l2bus.snoop_fanout::samples 528 # Request fanout histogram +system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 528 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::total 528 # Request fanout histogram +system.l2bus.reqLayer0.occupancy 528000 # Layer occupancy (ticks) +system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.l2bus.respLayer0.occupancy 891000 # Layer occupancy (ticks) +system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer1.occupancy 411000 # Layer occupancy (ticks) +system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.l2cache.tags.replacements 0 # number of replacements +system.l2cache.tags.tagsinuse 183.881600 # Cycle average of tags in use +system.l2cache.tags.total_refs 98 # Total number of references to valid blocks. +system.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.257895 # Average number of references to valid blocks. +system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2cache.tags.occ_blocks::cpu.inst 130.357827 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 53.523773 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.031826 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.013067 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.044893 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 77 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 303 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.092773 # Percentage of cache occupancy per task id +system.l2cache.tags.tag_accesses 4654 # Number of tag accesses +system.l2cache.tags.data_accesses 4654 # Number of data accesses +system.l2cache.ReadSharedReq_hits::cpu.inst 4 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::total 4 # number of ReadSharedReq hits +system.l2cache.demand_hits::cpu.inst 4 # number of demand (read+write) hits +system.l2cache.demand_hits::total 4 # number of demand (read+write) hits +system.l2cache.overall_hits::cpu.inst 4 # number of overall hits +system.l2cache.overall_hits::total 4 # number of overall hits +system.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses +system.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses +system.l2cache.ReadSharedReq_misses::cpu.inst 293 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::total 380 # number of ReadSharedReq misses +system.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses +system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses +system.l2cache.demand_misses::total 430 # number of demand (read+write) misses +system.l2cache.overall_misses::cpu.inst 293 # number of overall misses +system.l2cache.overall_misses::cpu.data 137 # number of overall misses +system.l2cache.overall_misses::total 430 # number of overall misses +system.l2cache.ReadExReq_miss_latency::cpu.data 5014000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 5014000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 28701000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 8475000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 37176000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 28701000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13489000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 42190000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 28701000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13489000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 42190000 # number of overall miss cycles +system.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.inst 297 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::total 384 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.demand_accesses::cpu.inst 297 # number of demand (read+write) accesses +system.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses +system.l2cache.demand_accesses::total 434 # number of demand (read+write) accesses +system.l2cache.overall_accesses::cpu.inst 297 # number of overall (read+write) accesses +system.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses +system.l2cache.overall_accesses::total 434 # number of overall (read+write) accesses +system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.986532 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::total 0.989583 # miss rate for ReadSharedReq accesses +system.l2cache.demand_miss_rate::cpu.inst 0.986532 # miss rate for demand accesses +system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.l2cache.demand_miss_rate::total 0.990783 # miss rate for demand accesses +system.l2cache.overall_miss_rate::cpu.inst 0.986532 # miss rate for overall accesses +system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.l2cache.overall_miss_rate::total 0.990783 # miss rate for overall accesses +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 100280 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 100280 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97955.631399 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 97413.793103 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 97831.578947 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98116.279070 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97955.631399 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 98459.854015 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98116.279070 # average overall miss latency +system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2cache.fast_writes 0 # number of fast writes performed +system.l2cache.cache_copies 0 # number of cache copies performed +system.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses +system.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 293 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::total 380 # number of ReadSharedReq MSHR misses +system.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses +system.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4014000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 4014000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 22841000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6735000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 29576000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 22841000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10749000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 33590000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 22841000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10749000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 33590000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.989583 # mshr miss rate for ReadSharedReq accesses +system.l2cache.demand_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::total 0.990783 # mshr miss rate for demand accesses +system.l2cache.overall_mshr_miss_rate::cpu.inst 0.986532 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::total 0.990783 # mshr miss rate for overall accesses +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 80280 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 80280 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77955.631399 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 77413.793103 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 77831.578947 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77955.631399 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 78459.854015 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78116.279070 # average overall mshr miss latency +system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadResp 380 # Transaction distribution +system.membus.trans_dist::ReadExReq 50 # Transaction distribution +system.membus.trans_dist::ReadExResp 50 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution +system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 430 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 430 # Request fanout histogram +system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 2299000 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini new file mode 100644 index 000000000..57a0de99e --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/config.ini @@ -0,0 +1,230 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[2] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.membus.slave[1] +icache_port=system.membus.slave[0] + +[system.cpu.dtb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.interrupts] +type=SparcInterrupts +eventq_index=0 + +[system.cpu.isa] +type=SparcISA +eventq_index=0 + +[system.cpu.itb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/sparc/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.cpu.icache_port system.cpu.dcache_port system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout new file mode 100755 index 000000000..2b9a57596 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:30:34 +gem5 started Jul 8 2015 14:31:17 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-simple + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 333033000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt new file mode 100644 index 000000000..9f000e805 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-simple/stats.txt @@ -0,0 +1,361 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000333 # Number of seconds simulated +sim_ticks 333033000 # Number of ticks simulated +final_tick 333033000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 184694 # Simulator instruction rate (inst/s) +host_op_rate 184612 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11077653777 # Simulator tick rate (ticks/s) +host_mem_usage 669088 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 5548 # Number of instructions simulated +sim_ops 5548 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 22364 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 4640 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 27004 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 22364 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 22364 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_written::cpu.data 5065 # Number of bytes written to this memory +system.mem_ctrl.bytes_written::total 5065 # Number of bytes written to this memory +system.mem_ctrl.num_reads::cpu.inst 5591 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 718 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 6309 # Number of read requests responded to by this memory +system.mem_ctrl.num_writes::cpu.data 673 # Number of write requests responded to by this memory +system.mem_ctrl.num_writes::total 673 # Number of write requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 67152504 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 13932553 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 81085058 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 67152504 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 67152504 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 15208703 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 15208703 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 67152504 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 29141256 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 96293761 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 6310 # Number of read requests accepted +system.mem_ctrl.writeReqs 673 # Number of write requests accepted +system.mem_ctrl.readBursts 6310 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 673 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 397376 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 6464 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 6144 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 27008 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 5065 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 101 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 551 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 220 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 84 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 2 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 199 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 1001 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 1555 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 876 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 710 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 348 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 99 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 623 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 56 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 158 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 200 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 78 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 14 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 37 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 27 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 5 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 4 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 9 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 332957000 # Total gap between requests +system.mem_ctrl.readPktSize::0 88 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 2 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 5711 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 509 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 13 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 2 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 54 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 604 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 6209 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 6 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 569 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 706.024605 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 523.041408 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 385.942790 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 49 8.61% 8.61% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 76 13.36% 21.97% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 38 6.68% 28.65% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 27 4.75% 33.39% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 21 3.69% 37.08% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 21 3.69% 40.77% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 15 2.64% 43.41% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 24 4.22% 47.63% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 298 52.37% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 569 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 6 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 772.166667 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 643.154197 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 524.176084 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::256-319 2 33.33% 33.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-703 1 16.67% 50.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::704-767 1 16.67% 66.67% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::896-959 1 16.67% 83.33% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1664-1727 1 16.67% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 6 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 6 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::16 6 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 6 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 19522250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 135941000 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 31045000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3144.19 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 21894.19 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1193.20 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 18.45 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 81.10 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 15.21 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 9.47 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.32 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.14 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 22.95 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 5646 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 86 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 90.93 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 70.49 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 47681.08 # Average gap between requests +system.mem_ctrl.pageHitRate 90.54 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 2676240 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1460250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 29983200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 505440 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 211046490 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 11241000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 278272140 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 850.250594 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 16881000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 10920000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 299495250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 1587600 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 866250 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 17604600 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 116640 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 21359520 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 163497375 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 52950750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 257982735 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 788.257041 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 88704750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 10920000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 229634250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 333033 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5548 # Number of instructions committed +system.cpu.committedOps 5548 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 146 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls +system.cpu.num_int_insts 4660 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 10977 # number of times the integer registers were read +system.cpu.num_int_register_writes 5062 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 1404 # number of memory refs +system.cpu.num_load_insts 726 # Number of load instructions +system.cpu.num_store_insts 678 # Number of store instructions +system.cpu.num_idle_cycles 0.001000 # Number of idle cycles +system.cpu.num_busy_cycles 333032.999000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 1187 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction +system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5591 # Class of executed instruction +system.membus.trans_dist::ReadReq 6310 # Transaction distribution +system.membus.trans_dist::ReadResp 6309 # Transaction distribution +system.membus.trans_dist::WriteReq 673 # Transaction distribution +system.membus.trans_dist::WriteResp 673 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 11183 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 2782 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 13965 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 22364 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 9705 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 32069 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 6983 # Request fanout histogram +system.membus.snoop_fanout::mean 0.800802 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.399426 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 1391 19.92% 19.92% # Request fanout histogram +system.membus.snoop_fanout::1 5592 80.08% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 6983 # Request fanout histogram +system.membus.reqLayer0.occupancy 7656000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.3 # Layer utilization (%) +system.membus.respLayer0.occupancy 12692250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.8 # Layer utilization (%) +system.membus.respLayer1.occupancy 2298500 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.7 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini new file mode 100644 index 000000000..a8ddc285e --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/config.ini @@ -0,0 +1,350 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=dcache dtb icache interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=65536 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.l2bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=65536 + +[system.cpu.dtb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=16384 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.l2bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=16384 + +[system.cpu.interrupts] +type=SparcInterrupts +eventq_index=0 + +[system.cpu.isa] +type=SparcISA +eventq_index=0 + +[system.cpu.itb] +type=SparcTLB +eventq_index=0 +size=64 + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/sparc/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2bus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=262144 +system=system +tags=system.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +cpu_side=system.l2bus.master[0] +mem_side=system.membus.slave[0] + +[system.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=262144 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[0] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.mem_ctrl.port +slave=system.l2cache.mem_side system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout new file mode 100755 index 000000000..01f8a1c56 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/simout @@ -0,0 +1,12 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 8 2015 14:30:34 +gem5 started Jul 8 2015 14:31:17 +gem5 executing on galapagos-15.cs.wisc.edu +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/SPARC/tests/opt/quick/se/03.learning-gem5/sparc/linux/learning-gem5-p1-two-level + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +Hello World!Exiting @ tick 53332000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt new file mode 100644 index 000000000..279d13e98 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/sparc/linux/learning-gem5-p1-two-level/stats.txt @@ -0,0 +1,691 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000053 # Number of seconds simulated +sim_ticks 53332000 # Number of ticks simulated +final_tick 53332000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 257745 # Simulator instruction rate (inst/s) +host_op_rate 257613 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2475242240 # Simulator tick rate (ticks/s) +host_mem_usage 673312 # Number of bytes of host memory used +host_seconds 0.02 # Real time elapsed on the host +sim_insts 5548 # Number of instructions simulated +sim_ops 5548 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 16448 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 8768 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 25216 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 16448 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 16448 # Number of instructions bytes read from this memory +system.mem_ctrl.num_reads::cpu.inst 257 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 137 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 394 # Number of read requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 308407710 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 164404110 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 472811820 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 308407710 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 308407710 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 308407710 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 164404110 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 472811820 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 394 # Number of read requests accepted +system.mem_ctrl.writeReqs 0 # Number of write requests accepted +system.mem_ctrl.readBursts 394 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 25216 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 25216 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 21 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 7 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 1 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 7 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 69 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 79 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 62 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 32 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 17 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 9 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 47 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 10 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 21 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 5 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 7 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 53236000 # Total gap between requests +system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 394 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 394 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 93 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 243.612903 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 174.394567 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 202.881901 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::64-127 29 31.18% 31.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-191 15 16.13% 47.31% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::192-255 11 11.83% 59.14% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-319 8 8.60% 67.74% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::320-383 6 6.45% 74.19% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-447 8 8.60% 82.80% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::448-511 2 2.15% 84.95% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-575 3 3.23% 88.17% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::576-639 6 6.45% 94.62% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-703 2 2.15% 96.77% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::704-767 1 1.08% 97.85% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-959 1 1.08% 98.92% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::960-1023 1 1.08% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 93 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3014250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10401750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 1970000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 7650.38 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 26400.38 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 472.81 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 472.81 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 3.69 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.69 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 295 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 74.87 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrl.avgGap 135116.75 # Average gap between requests +system.mem_ctrl.pageHitRate 74.87 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 385560 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 210375 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1622400 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 30542310 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 1395000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 37207005 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 792.017562 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 2172750 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 1560000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 43258500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 279720 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 152625 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1053000 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 3051360 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 29447910 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 2355000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 36339615 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 773.553616 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 4798500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1560000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 41660500 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 53332 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5548 # Number of instructions committed +system.cpu.committedOps 5548 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 4660 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 146 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 835 # number of instructions that are conditional controls +system.cpu.num_int_insts 4660 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 10977 # number of times the integer registers were read +system.cpu.num_int_register_writes 5062 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_mem_refs 1404 # number of memory refs +system.cpu.num_load_insts 726 # Number of load instructions +system.cpu.num_store_insts 678 # Number of store instructions +system.cpu.num_idle_cycles 0.001000 # Number of idle cycles +system.cpu.num_busy_cycles 53331.999000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 1187 # Number of branches fetched +system.cpu.op_class::No_OpClass 173 3.09% 3.09% # Class of executed instruction +system.cpu.op_class::IntAlu 4014 71.79% 74.89% # Class of executed instruction +system.cpu.op_class::IntMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::IntDiv 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 74.89% # Class of executed instruction +system.cpu.op_class::MemRead 726 12.99% 87.87% # Class of executed instruction +system.cpu.op_class::MemWrite 678 12.13% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 5591 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 83.742557 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1253 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 138 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 9.079710 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 83.742557 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.081780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.081780 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 138 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 10 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.134766 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 2920 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 2920 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 662 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 662 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 591 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 591 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1253 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1253 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1253 # number of overall hits +system.cpu.dcache.overall_hits::total 1253 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 82 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 82 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 138 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 138 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 138 # number of overall misses +system.cpu.dcache.overall_misses::total 138 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5532000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5532000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8433000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8433000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 13965000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 13965000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 13965000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 13965000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 718 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 718 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 673 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 1391 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 1391 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 1391 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 1391 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.077994 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.077994 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.121842 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.121842 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.099209 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.099209 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.099209 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.099209 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 98785.714286 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 98785.714286 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 102841.463415 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 102841.463415 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 101195.652174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 101195.652174 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 101195.652174 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 82 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 82 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8269000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8269000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13689000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13689000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13689000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13689000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.077994 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.077994 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.121842 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.121842 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.099209 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.099209 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.099209 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 96785.714286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 96785.714286 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 100841.463415 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 100841.463415 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 99195.652174 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 99195.652174 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 71 # number of replacements +system.cpu.icache.tags.tagsinuse 98.062197 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 5333 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 259 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 20.590734 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 98.062197 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.383055 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.383055 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 188 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 60 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.734375 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 11443 # Number of tag accesses +system.cpu.icache.tags.data_accesses 11443 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 5333 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5333 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5333 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5333 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5333 # number of overall hits +system.cpu.icache.overall_hits::total 5333 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 259 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 259 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 259 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 259 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 259 # number of overall misses +system.cpu.icache.overall_misses::total 259 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 26197000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 26197000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 26197000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 26197000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 26197000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 26197000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5592 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5592 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5592 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5592 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5592 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5592 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.046316 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.046316 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.046316 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.046316 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.046316 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.046316 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 101146.718147 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 101146.718147 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 101146.718147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 101146.718147 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 101146.718147 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 259 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 259 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 259 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 259 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 259 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25679000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 25679000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25679000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 25679000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25679000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 25679000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.046316 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.046316 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.046316 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.046316 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 99146.718147 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 99146.718147 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 99146.718147 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 99146.718147 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.trans_dist::ReadResp 315 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 70 # Transaction distribution +system.l2bus.trans_dist::ReadExReq 82 # Transaction distribution +system.l2bus.trans_dist::ReadExResp 82 # Transaction distribution +system.l2bus.trans_dist::ReadSharedReq 315 # Transaction distribution +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 16576 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.snoops 0 # Total snoops (count) +system.l2bus.snoop_fanout::samples 468 # Request fanout histogram +system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 468 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::total 468 # Request fanout histogram +system.l2bus.reqLayer0.occupancy 468000 # Layer occupancy (ticks) +system.l2bus.reqLayer0.utilization 0.9 # Layer utilization (%) +system.l2bus.respLayer0.occupancy 777000 # Layer occupancy (ticks) +system.l2bus.respLayer0.utilization 1.5 # Layer utilization (%) +system.l2bus.respLayer1.occupancy 414000 # Layer occupancy (ticks) +system.l2bus.respLayer1.utilization 0.8 # Layer utilization (%) +system.l2cache.tags.replacements 0 # number of replacements +system.l2cache.tags.tagsinuse 143.999291 # Cycle average of tags in use +system.l2cache.tags.total_refs 73 # Total number of references to valid blocks. +system.l2cache.tags.sampled_refs 312 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.233974 # Average number of references to valid blocks. +system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2cache.tags.occ_blocks::cpu.inst 117.698664 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 26.300627 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.028735 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.006421 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.035156 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 68 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 244 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.076172 # Percentage of cache occupancy per task id +system.l2cache.tags.tag_accesses 4130 # Number of tag accesses +system.l2cache.tags.data_accesses 4130 # Number of data accesses +system.l2cache.ReadSharedReq_hits::cpu.inst 2 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::cpu.data 1 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::total 3 # number of ReadSharedReq hits +system.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits +system.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits +system.l2cache.demand_hits::total 3 # number of demand (read+write) hits +system.l2cache.overall_hits::cpu.inst 2 # number of overall hits +system.l2cache.overall_hits::cpu.data 1 # number of overall hits +system.l2cache.overall_hits::total 3 # number of overall hits +system.l2cache.ReadExReq_misses::cpu.data 82 # number of ReadExReq misses +system.l2cache.ReadExReq_misses::total 82 # number of ReadExReq misses +system.l2cache.ReadSharedReq_misses::cpu.inst 257 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::cpu.data 55 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::total 312 # number of ReadSharedReq misses +system.l2cache.demand_misses::cpu.inst 257 # number of demand (read+write) misses +system.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses +system.l2cache.demand_misses::total 394 # number of demand (read+write) misses +system.l2cache.overall_misses::cpu.inst 257 # number of overall misses +system.l2cache.overall_misses::cpu.data 137 # number of overall misses +system.l2cache.overall_misses::total 394 # number of overall misses +system.l2cache.ReadExReq_miss_latency::cpu.data 8023000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 8023000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 24860000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 5231000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 30091000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 24860000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13254000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 38114000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 24860000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13254000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 38114000 # number of overall miss cycles +system.l2cache.ReadExReq_accesses::cpu.data 82 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadExReq_accesses::total 82 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.inst 259 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::total 315 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.demand_accesses::cpu.inst 259 # number of demand (read+write) accesses +system.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses +system.l2cache.demand_accesses::total 397 # number of demand (read+write) accesses +system.l2cache.overall_accesses::cpu.inst 259 # number of overall (read+write) accesses +system.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses +system.l2cache.overall_accesses::total 397 # number of overall (read+write) accesses +system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.992278 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.data 0.982143 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::total 0.990476 # miss rate for ReadSharedReq accesses +system.l2cache.demand_miss_rate::cpu.inst 0.992278 # miss rate for demand accesses +system.l2cache.demand_miss_rate::cpu.data 0.992754 # miss rate for demand accesses +system.l2cache.demand_miss_rate::total 0.992443 # miss rate for demand accesses +system.l2cache.overall_miss_rate::cpu.inst 0.992278 # miss rate for overall accesses +system.l2cache.overall_miss_rate::cpu.data 0.992754 # miss rate for overall accesses +system.l2cache.overall_miss_rate::total 0.992443 # miss rate for overall accesses +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 97841.463415 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 97841.463415 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 96731.517510 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 95109.090909 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 96445.512821 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 96736.040609 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 96731.517510 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 96744.525547 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 96736.040609 # average overall miss latency +system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2cache.fast_writes 0 # number of fast writes performed +system.l2cache.cache_copies 0 # number of cache copies performed +system.l2cache.ReadExReq_mshr_misses::cpu.data 82 # number of ReadExReq MSHR misses +system.l2cache.ReadExReq_mshr_misses::total 82 # number of ReadExReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 257 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.data 55 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::total 312 # number of ReadSharedReq MSHR misses +system.l2cache.demand_mshr_misses::cpu.inst 257 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses +system.l2cache.overall_mshr_misses::cpu.inst 257 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6383000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6383000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 19720000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4131000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 23851000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 19720000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10514000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 30234000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 19720000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10514000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 30234000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.982143 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.990476 # mshr miss rate for ReadSharedReq accesses +system.l2cache.demand_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::total 0.992443 # mshr miss rate for demand accesses +system.l2cache.overall_mshr_miss_rate::cpu.inst 0.992278 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::cpu.data 0.992754 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::total 0.992443 # mshr miss rate for overall accesses +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 77841.463415 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 77841.463415 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 76731.517510 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 75109.090909 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76445.512821 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 76731.517510 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 76744.525547 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 76736.040609 # average overall mshr miss latency +system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadResp 312 # Transaction distribution +system.membus.trans_dist::ReadExReq 82 # Transaction distribution +system.membus.trans_dist::ReadExResp 82 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 312 # Transaction distribution +system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 788 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 788 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 25216 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25216 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 394 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 394 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 394 # Request fanout histogram +system.membus.reqLayer0.occupancy 394000 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 0.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 2102250 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.9 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini new file mode 100644 index 000000000..1f9751232 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/config.ini @@ -0,0 +1,262 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[3] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=apic_clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.membus.slave[1] +icache_port=system.membus.slave[0] + +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.clk_domain +eventq_index=0 + +[system.cpu.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +clk_domain=system.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system + +[system.cpu.interrupts] +type=X86LocalApic +clk_domain=system.cpu.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.membus.slave[2] +int_slave=system.membus.master[1] +pio=system.membus.master[0] + +[system.cpu.isa] +type=X86ISA +eventq_index=0 + +[system.cpu.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +clk_domain=system.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/x86/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[2] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port +slave=system.cpu.icache_port system.cpu.dcache_port system.cpu.interrupts.int_master system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout new file mode 100755 index 000000000..bafc0ae61 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/simout @@ -0,0 +1,13 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 6 2015 10:35:34 +gem5 started Jul 6 2015 10:39:43 +gem5 executing on mustardseed.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-simple + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 445082000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt new file mode 100644 index 000000000..bddcc556f --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-simple/stats.txt @@ -0,0 +1,370 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000445 # Number of seconds simulated +sim_ticks 445082000 # Number of ticks simulated +final_tick 445082000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 82045 # Simulator instruction rate (inst/s) +host_op_rate 148084 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6387011035 # Simulator tick rate (ticks/s) +host_mem_usage 689252 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host +sim_insts 5712 # Number of instructions simulated +sim_ops 10314 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 58264 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 7167 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 65431 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 58264 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 58264 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_written::cpu.data 7160 # Number of bytes written to this memory +system.mem_ctrl.bytes_written::total 7160 # Number of bytes written to this memory +system.mem_ctrl.num_reads::cpu.inst 7283 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 1084 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 8367 # Number of read requests responded to by this memory +system.mem_ctrl.num_writes::cpu.data 941 # Number of write requests responded to by this memory +system.mem_ctrl.num_writes::total 941 # Number of write requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 130906215 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 16102651 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 147008866 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 130906215 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 130906215 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::cpu.data 16086923 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_write::total 16086923 # Write bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 130906215 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 32189574 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 163095789 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 8367 # Number of read requests accepted +system.mem_ctrl.writeReqs 941 # Number of write requests accepted +system.mem_ctrl.readBursts 8367 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 941 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 525184 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 10304 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 7168 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 65431 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 7160 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 161 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 810 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 277 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 4 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 227 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 102 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 1619 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 965 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 1103 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 906 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 703 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 490 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 1059 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 59 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 11 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 489 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 78 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 114 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 12 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 3 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 55 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 29 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 7 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 6 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 444958000 # Total gap between requests +system.mem_ctrl.readPktSize::0 135 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 14 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 119 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 8099 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 0 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 14 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 3 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 63 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 861 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 8206 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 1 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 8 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 8 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 7 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 849 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 625.677267 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 430.153995 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 392.580114 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 141 16.61% 16.61% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 68 8.01% 24.62% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 71 8.36% 32.98% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 65 7.66% 40.64% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 53 6.24% 46.88% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 45 5.30% 52.18% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 35 4.12% 56.30% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 15 1.77% 58.07% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 356 41.93% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 849 # Bytes accessed per row activation +system.mem_ctrl.rdPerTurnAround::samples 7 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::mean 1165.285714 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::gmean 941.793638 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::stdev 714.559471 # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::256-383 1 14.29% 14.29% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::384-511 1 14.29% 28.57% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::640-767 1 14.29% 42.86% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1280-1407 1 14.29% 57.14% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1408-1535 1 14.29% 71.43% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::1920-2047 1 14.29% 85.71% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::2048-2175 1 14.29% 100.00% # Reads before turning the bus around for writes +system.mem_ctrl.rdPerTurnAround::total 7 # Reads before turning the bus around for writes +system.mem_ctrl.wrPerTurnAround::samples 7 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::mean 16 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::gmean 16.000000 # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::16 7 100.00% 100.00% # Writes before turning the bus around for reads +system.mem_ctrl.wrPerTurnAround::total 7 # Writes before turning the bus around for reads +system.mem_ctrl.totQLat 29060250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 182922750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 41030000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 3541.34 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 22291.34 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 1179.97 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 16.10 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 147.01 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 16.09 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 9.34 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 9.22 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.13 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 23.76 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 7369 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 98 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 89.80 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate 74.81 # Row buffer hit rate for writes +system.mem_ctrl.avgGap 47803.82 # Average gap between requests +system.mem_ctrl.pageHitRate 89.56 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 3265920 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 1782000 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 40552200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 77760 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 28987920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 242604540 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 53634750 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 370905090 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 835.228387 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 86580500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 14820000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 342689500 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 3152520 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 1720125 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 23314200 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 648000 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 28987920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 267116535 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 32133000 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 357072300 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 804.078804 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 51572750 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 14820000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 377923250 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 445082 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5712 # Number of instructions committed +system.cpu.committedOps 10314 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 221 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls +system.cpu.num_int_insts 10205 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 19296 # number of times the integer registers were read +system.cpu.num_int_register_writes 7977 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written +system.cpu.num_mem_refs 2025 # number of memory refs +system.cpu.num_load_insts 1084 # Number of load instructions +system.cpu.num_store_insts 941 # Number of store instructions +system.cpu.num_idle_cycles 0.001000 # Number of idle cycles +system.cpu.num_busy_cycles 445081.999000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 1306 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction +system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction +system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 10314 # Class of executed instruction +system.membus.trans_dist::ReadReq 8367 # Transaction distribution +system.membus.trans_dist::ReadResp 8367 # Transaction distribution +system.membus.trans_dist::WriteReq 941 # Transaction distribution +system.membus.trans_dist::WriteResp 941 # Transaction distribution +system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 14566 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::total 14566 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 4050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.dcache_port::total 4050 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 18616 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 58264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::total 58264 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 14327 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.dcache_port::total 14327 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 72591 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 9308 # Request fanout histogram +system.membus.snoop_fanout::mean 0.782445 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.412605 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 2025 21.76% 21.76% # Request fanout histogram +system.membus.snoop_fanout::1 7283 78.24% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 1 # Request fanout histogram +system.membus.snoop_fanout::total 9308 # Request fanout histogram +system.membus.reqLayer2.occupancy 10249000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 2.3 # Layer utilization (%) +system.membus.respLayer0.occupancy 16547500 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.7 # Layer utilization (%) +system.membus.respLayer1.occupancy 3433750 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 0.8 # Layer utilization (%) + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini new file mode 100644 index 000000000..24aab210d --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/config.ini @@ -0,0 +1,382 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu dvfs_handler l2bus l2cache mem_ctrl membus +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrl +mmap_using_noreserve=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[2] + +[system.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.clk_domain.voltage_domain + +[system.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu] +type=TimingSimpleCPU +children=apic_clk_domain dcache dtb icache interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.clk_domain +cpu_id=-1 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu.interrupts +isa=system.cpu.isa +itb=system.cpu.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu.tracer +workload=system.cpu.workload +dcache_port=system.cpu.dcache.cpu_side +icache_port=system.cpu.icache.cpu_side + +[system.cpu.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.clk_domain +eventq_index=0 + +[system.cpu.dcache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=65536 +system=system +tags=system.cpu.dcache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.dcache_port +mem_side=system.l2bus.slave[1] + +[system.cpu.dcache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=65536 + +[system.cpu.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.dtb.walker + +[system.cpu.dtb.walker] +type=X86PagetableWalker +clk_domain=system.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system + +[system.cpu.icache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=2 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=2 +is_read_only=false +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +response_latency=2 +sequential_access=false +size=16384 +system=system +tags=system.cpu.icache.tags +tgts_per_mshr=20 +write_buffers=8 +cpu_side=system.cpu.icache_port +mem_side=system.l2bus.slave[0] + +[system.cpu.icache.tags] +type=LRU +assoc=2 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=2 +sequential_access=false +size=16384 + +[system.cpu.interrupts] +type=X86LocalApic +clk_domain=system.cpu.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.membus.slave[1] +int_slave=system.membus.master[1] +pio=system.membus.master[0] + +[system.cpu.isa] +type=X86ISA +eventq_index=0 + +[system.cpu.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu.itb.walker + +[system.cpu.itb.walker] +type=X86PagetableWalker +clk_domain=system.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system + +[system.cpu.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu.workload] +type=LiveProcess +cmd=tests/test-progs/hello/bin/x86/linux/hello +cwd= +drivers= +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable= +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l2bus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=1 +response_latency=1 +snoop_filter=Null +snoop_response_latency=1 +system=system +use_default_range=false +width=32 +master=system.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side + +[system.l2cache] +type=Cache +children=tags +addr_ranges=0:18446744073709551615 +assoc=8 +clk_domain=system.clk_domain +demand_mshr_reserve=1 +eventq_index=0 +forward_snoops=true +hit_latency=20 +is_read_only=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +sequential_access=false +size=262144 +system=system +tags=system.l2cache.tags +tgts_per_mshr=12 +write_buffers=8 +cpu_side=system.l2bus.master[0] +mem_side=system.membus.slave[0] + +[system.l2cache.tags] +type=LRU +assoc=8 +block_size=64 +clk_domain=system.clk_domain +eventq_index=0 +hit_latency=20 +sequential_access=false +size=262144 + +[system.mem_ctrl] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.membus.master[2] + +[system.membus] +type=CoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=4 +frontend_latency=3 +response_latency=2 +snoop_filter=Null +snoop_response_latency=4 +system=system +use_default_range=false +width=16 +master=system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.mem_ctrl.port +slave=system.l2cache.mem_side system.cpu.interrupts.int_master system.system_port + diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr new file mode 100755 index 000000000..8e03cc523 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simerr @@ -0,0 +1,2 @@ +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout new file mode 100755 index 000000000..f552f3ed5 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/simout @@ -0,0 +1,13 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jul 6 2015 10:35:34 +gem5 started Jul 6 2015 14:40:25 +gem5 executing on mustardseed.cs.wisc.edu +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level -re /afs/cs.wisc.edu/p/multifacet/users/powerjg/gem5-tutorial/gem5/tests/run.py build/X86/tests/opt/quick/se/03.learning-gem5/x86/linux/learning-gem5-p1-two-level + +Global frequency set at 1000000000000 ticks per second +Beginning simulation! +info: Entering event queue @ 0. Starting simulation... +Hello world! +Exiting @ tick 55844000 because target called exit() diff --git a/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt new file mode 100644 index 000000000..eeac393c4 --- /dev/null +++ b/tests/quick/se/03.learning-gem5/ref/x86/linux/learning-gem5-p1-two-level/stats.txt @@ -0,0 +1,689 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000056 # Number of seconds simulated +sim_ticks 55844000 # Number of ticks simulated +final_tick 55844000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 212931 # Simulator instruction rate (inst/s) +host_op_rate 384017 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2076955895 # Simulator tick rate (ticks/s) +host_mem_usage 693340 # Number of bytes of host memory used +host_seconds 0.03 # Real time elapsed on the host +sim_insts 5712 # Number of instructions simulated +sim_ops 10314 # Number of ops (including micro ops) simulated +system.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrl.bytes_read::cpu.inst 14656 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::cpu.data 8640 # Number of bytes read from this memory +system.mem_ctrl.bytes_read::total 23296 # Number of bytes read from this memory +system.mem_ctrl.bytes_inst_read::cpu.inst 14656 # Number of instructions bytes read from this memory +system.mem_ctrl.bytes_inst_read::total 14656 # Number of instructions bytes read from this memory +system.mem_ctrl.num_reads::cpu.inst 229 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::cpu.data 135 # Number of read requests responded to by this memory +system.mem_ctrl.num_reads::total 364 # Number of read requests responded to by this memory +system.mem_ctrl.bw_read::cpu.inst 262445384 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::cpu.data 154716711 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_read::total 417162094 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::cpu.inst 262445384 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_inst_read::total 262445384 # Instruction read bandwidth from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.inst 262445384 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::cpu.data 154716711 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.bw_total::total 417162094 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrl.readReqs 364 # Number of read requests accepted +system.mem_ctrl.writeReqs 0 # Number of write requests accepted +system.mem_ctrl.readBursts 364 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrl.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrl.bytesReadDRAM 23296 # Total number of bytes read from DRAM +system.mem_ctrl.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrl.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrl.bytesReadSys 23296 # Total read bytes from the system interface side +system.mem_ctrl.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrl.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrl.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrl.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrl.perBankRdBursts::0 30 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::1 1 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::2 5 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::3 8 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::4 43 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::5 40 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::6 13 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::7 24 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::8 17 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::9 71 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::10 62 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::11 14 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::12 2 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::13 14 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::14 4 # Per bank write bursts +system.mem_ctrl.perBankRdBursts::15 16 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrl.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrl.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrl.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrl.totGap 55714000 # Total gap between requests +system.mem_ctrl.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrl.readPktSize::6 364 # Read request sizes (log2) +system.mem_ctrl.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrl.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrl.rdQLenPdf::0 364 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::1 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::2 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::3 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrl.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrl.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrl.bytesPerActivate::samples 115 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::mean 199.234783 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::gmean 135.588464 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::stdev 217.243914 # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::0-127 49 42.61% 42.61% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::128-255 34 29.57% 72.17% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::256-383 16 13.91% 86.09% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::384-511 6 5.22% 91.30% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::512-639 2 1.74% 93.04% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::640-767 2 1.74% 94.78% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::768-895 2 1.74% 96.52% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::896-1023 1 0.87% 97.39% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::1024-1151 3 2.61% 100.00% # Bytes accessed per row activation +system.mem_ctrl.bytesPerActivate::total 115 # Bytes accessed per row activation +system.mem_ctrl.totQLat 3554250 # Total ticks spent queuing +system.mem_ctrl.totMemAccLat 10379250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrl.totBusLat 1820000 # Total ticks spent in databus transfers +system.mem_ctrl.avgQLat 9764.42 # Average queueing delay per DRAM burst +system.mem_ctrl.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrl.avgMemAccLat 28514.42 # Average memory access latency per DRAM burst +system.mem_ctrl.avgRdBW 417.16 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrl.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrl.avgRdBWSys 417.16 # Average system read bandwidth in MiByte/s +system.mem_ctrl.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrl.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrl.busUtil 3.26 # Data bus utilization in percentage +system.mem_ctrl.busUtilRead 3.26 # Data bus utilization in percentage for reads +system.mem_ctrl.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrl.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrl.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrl.readRowHits 244 # Number of row buffer hits during reads +system.mem_ctrl.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrl.readRowHitRate 67.03 # Row buffer hit rate for reads +system.mem_ctrl.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrl.avgGap 153060.44 # Average gap between requests +system.mem_ctrl.pageHitRate 67.03 # Row buffer hit rate, read and write combined +system.mem_ctrl_0.actEnergy 302400 # Energy for activate commands per rank (pJ) +system.mem_ctrl_0.preEnergy 165000 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_0.readEnergy 1240200 # Energy for read commands per rank (pJ) +system.mem_ctrl_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_0.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_0.actBackEnergy 32401080 # Energy for active background per rank (pJ) +system.mem_ctrl_0.preBackEnergy 4436250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_0.totalEnergy 42104850 # Total energy per rank (pJ) +system.mem_ctrl_0.averagePower 768.845267 # Core power per rank (mW) +system.mem_ctrl_0.memoryStateTime::IDLE 7212250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT 45745250 # Time in different power states +system.mem_ctrl_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrl_1.actEnergy 567000 # Energy for activate commands per rank (pJ) +system.mem_ctrl_1.preEnergy 309375 # Energy for precharge commands per rank (pJ) +system.mem_ctrl_1.readEnergy 1552200 # Energy for read commands per rank (pJ) +system.mem_ctrl_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrl_1.refreshEnergy 3559920 # Energy for refresh commands per rank (pJ) +system.mem_ctrl_1.actBackEnergy 36016020 # Energy for active background per rank (pJ) +system.mem_ctrl_1.preBackEnergy 1265250 # Energy for precharge background per rank (pJ) +system.mem_ctrl_1.totalEnergy 43269765 # Total energy per rank (pJ) +system.mem_ctrl_1.averagePower 790.116911 # Core power per rank (mW) +system.mem_ctrl_1.memoryStateTime::IDLE 2847000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::REF 1820000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT 51070000 # Time in different power states +system.mem_ctrl_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.cpu.apic_clk_domain.clock 16000 # Clock period in ticks +system.cpu.workload.num_syscalls 11 # Number of system calls +system.cpu.numCycles 55844 # number of cpu cycles simulated +system.cpu.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu.committedInsts 5712 # Number of instructions committed +system.cpu.committedOps 10314 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 10205 # Number of integer alu accesses +system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu.num_func_calls 221 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 986 # number of instructions that are conditional controls +system.cpu.num_int_insts 10205 # number of integer instructions +system.cpu.num_fp_insts 0 # number of float instructions +system.cpu.num_int_register_reads 19296 # number of times the integer registers were read +system.cpu.num_int_register_writes 7977 # number of times the integer registers were written +system.cpu.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu.num_cc_register_reads 7020 # number of times the CC registers were read +system.cpu.num_cc_register_writes 3825 # number of times the CC registers were written +system.cpu.num_mem_refs 2025 # number of memory refs +system.cpu.num_load_insts 1084 # Number of load instructions +system.cpu.num_store_insts 941 # Number of store instructions +system.cpu.num_idle_cycles 0.001000 # Number of idle cycles +system.cpu.num_busy_cycles 55843.999000 # Number of busy cycles +system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.000000 # Percentage of idle cycles +system.cpu.Branches 1306 # Number of branches fetched +system.cpu.op_class::No_OpClass 1 0.01% 0.01% # Class of executed instruction +system.cpu.op_class::IntAlu 8275 80.23% 80.24% # Class of executed instruction +system.cpu.op_class::IntMult 6 0.06% 80.30% # Class of executed instruction +system.cpu.op_class::IntDiv 7 0.07% 80.37% # Class of executed instruction +system.cpu.op_class::FloatAdd 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatCmp 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatCvt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatDiv 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::FloatSqrt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdAdd 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdAddAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdAlu 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdCmp 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdCvt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdMisc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdMultAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdShift 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdShiftAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdSqrt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAdd 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatAlu 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCmp 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatCvt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatDiv 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 80.37% # Class of executed instruction +system.cpu.op_class::MemRead 1084 10.51% 90.88% # Class of executed instruction +system.cpu.op_class::MemWrite 941 9.12% 100.00% # Class of executed instruction +system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu.op_class::total 10314 # Class of executed instruction +system.cpu.dcache.tags.replacements 0 # number of replacements +system.cpu.dcache.tags.tagsinuse 81.671962 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1890 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 135 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14 # Average number of references to valid blocks. +system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 81.671962 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.079758 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.079758 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 135 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 12 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 123 # Occupied blocks per task id +system.cpu.dcache.tags.occ_task_id_percent::1024 0.131836 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 4185 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4185 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1028 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1028 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 862 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 862 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1890 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1890 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1890 # number of overall hits +system.cpu.dcache.overall_hits::total 1890 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 56 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 56 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 79 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 79 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 135 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 135 # number of overall misses +system.cpu.dcache.overall_misses::total 135 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6006000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6006000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 8260000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 8260000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 14266000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 14266000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 14266000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 14266000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1084 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 941 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 941 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2025 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2025 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2025 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2025 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.051661 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.051661 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.083953 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.083953 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.066667 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.066667 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.066667 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.066667 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 107250 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 107250 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 104556.962025 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 104556.962025 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 105674.074074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 105674.074074 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 105674.074074 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 56 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 56 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 79 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5894000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8102000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8102000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 13996000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13996000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 13996000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051661 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051661 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083953 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083953 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.066667 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066667 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.066667 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 105250 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 105250 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 102556.962025 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 102556.962025 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 103674.074074 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 103674.074074 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.icache.tags.replacements 58 # number of replacements +system.cpu.icache.tags.tagsinuse 91.240171 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 7048 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 235 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 29.991489 # Average number of references to valid blocks. +system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.icache.tags.occ_blocks::cpu.inst 91.240171 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.356407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.356407 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 177 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 44 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id +system.cpu.icache.tags.occ_task_id_percent::1024 0.691406 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 14801 # Number of tag accesses +system.cpu.icache.tags.data_accesses 14801 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 7048 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 7048 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 7048 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 7048 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 7048 # number of overall hits +system.cpu.icache.overall_hits::total 7048 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 235 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 235 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 235 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 235 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 235 # number of overall misses +system.cpu.icache.overall_misses::total 235 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23702000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23702000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23702000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23702000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23702000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23702000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 7283 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 7283 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 7283 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 7283 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 7283 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 7283 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.032267 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.032267 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.032267 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.032267 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.032267 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.032267 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 100859.574468 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 100859.574468 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 100859.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 100859.574468 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 100859.574468 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.icache.fast_writes 0 # number of fast writes performed +system.cpu.icache.cache_copies 0 # number of cache copies performed +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 235 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 235 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 235 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 235 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 235 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 235 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23232000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23232000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23232000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23232000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23232000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23232000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.032267 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.032267 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.032267 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.032267 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 98859.574468 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 98859.574468 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 98859.574468 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 98859.574468 # average overall mshr miss latency +system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.l2bus.trans_dist::ReadResp 291 # Transaction distribution +system.l2bus.trans_dist::CleanEvict 58 # Transaction distribution +system.l2bus.trans_dist::ReadExReq 79 # Transaction distribution +system.l2bus.trans_dist::ReadExResp 79 # Transaction distribution +system.l2bus.trans_dist::ReadSharedReq 291 # Transaction distribution +system.l2bus.pkt_count_system.cpu.icache.mem_side::system.l2cache.cpu_side 528 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count_system.cpu.dcache.mem_side::system.l2cache.cpu_side 270 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_count::total 798 # Packet count per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.icache.mem_side::system.l2cache.cpu_side 15040 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size_system.cpu.dcache.mem_side::system.l2cache.cpu_side 8640 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.pkt_size::total 23680 # Cumulative packet size per connected master and slave (bytes) +system.l2bus.snoops 0 # Total snoops (count) +system.l2bus.snoop_fanout::samples 428 # Request fanout histogram +system.l2bus.snoop_fanout::mean 1 # Request fanout histogram +system.l2bus.snoop_fanout::stdev 0 # Request fanout histogram +system.l2bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram +system.l2bus.snoop_fanout::1 428 100.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.l2bus.snoop_fanout::min_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::max_value 1 # Request fanout histogram +system.l2bus.snoop_fanout::total 428 # Request fanout histogram +system.l2bus.reqLayer0.occupancy 428000 # Layer occupancy (ticks) +system.l2bus.reqLayer0.utilization 0.8 # Layer utilization (%) +system.l2bus.respLayer0.occupancy 705000 # Layer occupancy (ticks) +system.l2bus.respLayer0.utilization 1.3 # Layer utilization (%) +system.l2bus.respLayer1.occupancy 405000 # Layer occupancy (ticks) +system.l2bus.respLayer1.utilization 0.7 # Layer utilization (%) +system.l2cache.tags.replacements 0 # number of replacements +system.l2cache.tags.tagsinuse 135.849297 # Cycle average of tags in use +system.l2cache.tags.total_refs 64 # Total number of references to valid blocks. +system.l2cache.tags.sampled_refs 285 # Sample count of references to valid blocks. +system.l2cache.tags.avg_refs 0.224561 # Average number of references to valid blocks. +system.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.l2cache.tags.occ_blocks::cpu.inst 106.899114 # Average occupied blocks per requestor +system.l2cache.tags.occ_blocks::cpu.data 28.950183 # Average occupied blocks per requestor +system.l2cache.tags.occ_percent::cpu.inst 0.026098 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::cpu.data 0.007068 # Average percentage of cache occupancy +system.l2cache.tags.occ_percent::total 0.033166 # Average percentage of cache occupancy +system.l2cache.tags.occ_task_id_blocks::1024 285 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::0 54 # Occupied blocks per task id +system.l2cache.tags.age_task_id_blocks_1024::1 231 # Occupied blocks per task id +system.l2cache.tags.occ_task_id_percent::1024 0.069580 # Percentage of cache occupancy per task id +system.l2cache.tags.tag_accesses 3788 # Number of tag accesses +system.l2cache.tags.data_accesses 3788 # Number of data accesses +system.l2cache.ReadSharedReq_hits::cpu.inst 6 # number of ReadSharedReq hits +system.l2cache.ReadSharedReq_hits::total 6 # number of ReadSharedReq hits +system.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits +system.l2cache.demand_hits::total 6 # number of demand (read+write) hits +system.l2cache.overall_hits::cpu.inst 6 # number of overall hits +system.l2cache.overall_hits::total 6 # number of overall hits +system.l2cache.ReadExReq_misses::cpu.data 79 # number of ReadExReq misses +system.l2cache.ReadExReq_misses::total 79 # number of ReadExReq misses +system.l2cache.ReadSharedReq_misses::cpu.inst 229 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::cpu.data 56 # number of ReadSharedReq misses +system.l2cache.ReadSharedReq_misses::total 285 # number of ReadSharedReq misses +system.l2cache.demand_misses::cpu.inst 229 # number of demand (read+write) misses +system.l2cache.demand_misses::cpu.data 135 # number of demand (read+write) misses +system.l2cache.demand_misses::total 364 # number of demand (read+write) misses +system.l2cache.overall_misses::cpu.inst 229 # number of overall misses +system.l2cache.overall_misses::cpu.data 135 # number of overall misses +system.l2cache.overall_misses::total 364 # number of overall misses +system.l2cache.ReadExReq_miss_latency::cpu.data 7865000 # number of ReadExReq miss cycles +system.l2cache.ReadExReq_miss_latency::total 7865000 # number of ReadExReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.inst 22401000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::cpu.data 5726000 # number of ReadSharedReq miss cycles +system.l2cache.ReadSharedReq_miss_latency::total 28127000 # number of ReadSharedReq miss cycles +system.l2cache.demand_miss_latency::cpu.inst 22401000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::cpu.data 13591000 # number of demand (read+write) miss cycles +system.l2cache.demand_miss_latency::total 35992000 # number of demand (read+write) miss cycles +system.l2cache.overall_miss_latency::cpu.inst 22401000 # number of overall miss cycles +system.l2cache.overall_miss_latency::cpu.data 13591000 # number of overall miss cycles +system.l2cache.overall_miss_latency::total 35992000 # number of overall miss cycles +system.l2cache.ReadExReq_accesses::cpu.data 79 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadExReq_accesses::total 79 # number of ReadExReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.inst 235 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::cpu.data 56 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.ReadSharedReq_accesses::total 291 # number of ReadSharedReq accesses(hits+misses) +system.l2cache.demand_accesses::cpu.inst 235 # number of demand (read+write) accesses +system.l2cache.demand_accesses::cpu.data 135 # number of demand (read+write) accesses +system.l2cache.demand_accesses::total 370 # number of demand (read+write) accesses +system.l2cache.overall_accesses::cpu.inst 235 # number of overall (read+write) accesses +system.l2cache.overall_accesses::cpu.data 135 # number of overall (read+write) accesses +system.l2cache.overall_accesses::total 370 # number of overall (read+write) accesses +system.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses +system.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.inst 0.974468 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_miss_rate::total 0.979381 # miss rate for ReadSharedReq accesses +system.l2cache.demand_miss_rate::cpu.inst 0.974468 # miss rate for demand accesses +system.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses +system.l2cache.demand_miss_rate::total 0.983784 # miss rate for demand accesses +system.l2cache.overall_miss_rate::cpu.inst 0.974468 # miss rate for overall accesses +system.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses +system.l2cache.overall_miss_rate::total 0.983784 # miss rate for overall accesses +system.l2cache.ReadExReq_avg_miss_latency::cpu.data 99556.962025 # average ReadExReq miss latency +system.l2cache.ReadExReq_avg_miss_latency::total 99556.962025 # average ReadExReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.inst 97820.960699 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 102250 # average ReadSharedReq miss latency +system.l2cache.ReadSharedReq_avg_miss_latency::total 98691.228070 # average ReadSharedReq miss latency +system.l2cache.demand_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.demand_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency +system.l2cache.demand_avg_miss_latency::total 98879.120879 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.inst 97820.960699 # average overall miss latency +system.l2cache.overall_avg_miss_latency::cpu.data 100674.074074 # average overall miss latency +system.l2cache.overall_avg_miss_latency::total 98879.120879 # average overall miss latency +system.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2cache.blocked::no_targets 0 # number of cycles access was blocked +system.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.l2cache.fast_writes 0 # number of fast writes performed +system.l2cache.cache_copies 0 # number of cache copies performed +system.l2cache.ReadExReq_mshr_misses::cpu.data 79 # number of ReadExReq MSHR misses +system.l2cache.ReadExReq_mshr_misses::total 79 # number of ReadExReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.inst 229 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::cpu.data 56 # number of ReadSharedReq MSHR misses +system.l2cache.ReadSharedReq_mshr_misses::total 285 # number of ReadSharedReq MSHR misses +system.l2cache.demand_mshr_misses::cpu.inst 229 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::cpu.data 135 # number of demand (read+write) MSHR misses +system.l2cache.demand_mshr_misses::total 364 # number of demand (read+write) MSHR misses +system.l2cache.overall_mshr_misses::cpu.inst 229 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses +system.l2cache.overall_mshr_misses::total 364 # number of overall MSHR misses +system.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6285000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_latency::total 6285000 # number of ReadExReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.inst 17821000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4606000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.ReadSharedReq_mshr_miss_latency::total 22427000 # number of ReadSharedReq MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.inst 17821000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::cpu.data 10891000 # number of demand (read+write) MSHR miss cycles +system.l2cache.demand_mshr_miss_latency::total 28712000 # number of demand (read+write) MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.inst 17821000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::cpu.data 10891000 # number of overall MSHR miss cycles +system.l2cache.overall_mshr_miss_latency::total 28712000 # number of overall MSHR miss cycles +system.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses +system.l2cache.ReadSharedReq_mshr_miss_rate::total 0.979381 # mshr miss rate for ReadSharedReq accesses +system.l2cache.demand_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses +system.l2cache.demand_mshr_miss_rate::total 0.983784 # mshr miss rate for demand accesses +system.l2cache.overall_mshr_miss_rate::cpu.inst 0.974468 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses +system.l2cache.overall_mshr_miss_rate::total 0.983784 # mshr miss rate for overall accesses +system.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 79556.962025 # average ReadExReq mshr miss latency +system.l2cache.ReadExReq_avg_mshr_miss_latency::total 79556.962025 # average ReadExReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.inst 77820.960699 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 82250 # average ReadSharedReq mshr miss latency +system.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78691.228070 # average ReadSharedReq mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency +system.l2cache.demand_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.inst 77820.960699 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::cpu.data 80674.074074 # average overall mshr miss latency +system.l2cache.overall_avg_mshr_miss_latency::total 78879.120879 # average overall mshr miss latency +system.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.membus.trans_dist::ReadResp 285 # Transaction distribution +system.membus.trans_dist::ReadExReq 79 # Transaction distribution +system.membus.trans_dist::ReadExResp 79 # Transaction distribution +system.membus.trans_dist::ReadSharedReq 285 # Transaction distribution +system.membus.pkt_count_system.l2cache.mem_side::system.mem_ctrl.port 728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.l2cache.mem_side::total 728 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 728 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.l2cache.mem_side::system.mem_ctrl.port 23296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size_system.l2cache.mem_side::total 23296 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 23296 # Cumulative packet size per connected master and slave (bytes) +system.membus.snoops 0 # Total snoops (count) +system.membus.snoop_fanout::samples 364 # Request fanout histogram +system.membus.snoop_fanout::mean 0 # Request fanout histogram +system.membus.snoop_fanout::stdev 0 # Request fanout histogram +system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram +system.membus.snoop_fanout::0 364 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::min_value 0 # Request fanout histogram +system.membus.snoop_fanout::max_value 0 # Request fanout histogram +system.membus.snoop_fanout::total 364 # Request fanout histogram +system.membus.reqLayer2.occupancy 364000 # Layer occupancy (ticks) +system.membus.reqLayer2.utilization 0.7 # Layer utilization (%) +system.membus.respLayer0.occupancy 1952750 # Layer occupancy (ticks) +system.membus.respLayer0.utilization 3.5 # Layer utilization (%) + +---------- End Simulation Statistics ---------- |