diff options
Diffstat (limited to 'tests/quick')
36 files changed, 4771 insertions, 4677 deletions
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini index c876dab9d..9cf4fe14a 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini @@ -10,20 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=atomic -memories=system.physmem system.realview.nvmem -midr_regval=890224640 +mem_ranges=0:134217727 +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +40,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -64,16 +65,15 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -82,6 +82,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -92,6 +93,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu0.tracer width=1 @@ -104,23 +106,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -134,7 +131,7 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -144,23 +141,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -169,6 +161,23 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=ArmInterrupts +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu0.itb] type=ArmTLB children=walker @@ -177,7 +186,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -187,11 +196,10 @@ type=ExeTracer [system.cpu1] type=AtomicSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer checker=Null clock=500 cpu_id=1 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -200,6 +208,7 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -210,6 +219,7 @@ profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=system tracer=system.cpu1.tracer width=1 @@ -222,23 +232,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -252,7 +257,7 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -262,23 +267,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -287,6 +287,23 @@ mem_side=system.toL2Bus.slave[4] [system.cpu1.interrupts] type=ArmInterrupts +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu1.itb] type=ArmTLB children=walker @@ -295,7 +312,7 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -319,57 +336,47 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache -addr_ranges=0:268435455 +addr_ranges=0:134217727 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false -hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=50000 +response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c] type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 +response_latency=20 size=4194304 -subblock_size=0 system=system -tgts_per_mshr=16 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[1] [system.membus] type=CoherentBus @@ -381,11 +388,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -401,15 +408,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -424,7 +444,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -433,7 +453,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -480,7 +500,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -498,11 +518,12 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=41667 +clock=1000 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 +pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -511,7 +532,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -520,7 +541,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -537,7 +558,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -551,7 +572,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -561,7 +582,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -571,7 +592,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -581,7 +602,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -595,7 +616,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -608,7 +629,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -637,7 +658,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -647,7 +668,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -659,7 +680,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -671,7 +692,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -684,7 +705,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -694,7 +715,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -704,7 +725,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -714,7 +735,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -724,7 +745,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -738,7 +759,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -751,7 +772,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -766,7 +787,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -776,7 +797,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -786,7 +807,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -796,7 +817,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -813,7 +834,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr index 04178bb32..e8e271d58 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr @@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout index 0ce4b8c1f..4bb186944 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:07 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:29:32 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... Exiting @ tick 912096763500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt index 3841577ac..362d16758 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt @@ -4,22 +4,40 @@ sim_seconds 0.912097 # Nu sim_ticks 912096763500 # Number of ticks simulated final_tick 912096763500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1752000 # Simulator instruction rate (inst/s) -host_op_rate 2255696 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 25930494646 # Simulator tick rate (ticks/s) -host_mem_usage 382232 # Number of bytes of host memory used -host_seconds 35.17 # Real time elapsed on the host +host_inst_rate 599236 # Simulator instruction rate (inst/s) +host_op_rate 771515 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 8869004975 # Simulator tick rate (ticks/s) +host_mem_usage 384344 # Number of bytes of host memory used +host_seconds 102.84 # Real time elapsed on the host sim_insts 61625970 # Number of instructions simulated sim_ops 79343340 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 39321600 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.inst 502180 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 6234996 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 6235188 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 192 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 214556 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.data 3364528 # Number of bytes read from this memory -system.physmem.bytes_read::total 49638308 # Number of bytes read from this memory +system.physmem.bytes_read::total 49638500 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu0.inst 502180 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 214556 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory @@ -31,11 +49,11 @@ system.physmem.num_reads::realview.clcd 4915200 # Nu system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.inst 14065 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 97494 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 97497 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 3 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 3434 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.data 52597 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5082797 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5082800 # Number of read requests responded to by this memory system.physmem.num_writes::writebacks 65559 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752522 # Number of write requests responded to by this memory @@ -44,11 +62,11 @@ system.physmem.bw_read::realview.clcd 43111215 # To system.physmem.bw_read::cpu0.dtb.walker 70 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 211 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.inst 550578 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 6835893 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 6836104 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 211 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.inst 235234 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.data 3688784 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 54422195 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 54422406 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu0.inst 550578 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu1.inst 235234 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 785811 # Instruction read bandwidth from this memory (bytes/s) @@ -61,11 +79,11 @@ system.physmem.bw_total::realview.clcd 43111215 # To system.physmem.bw_total::cpu0.dtb.walker 70 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 211 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.inst 550578 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 6854532 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 6854742 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 211 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.inst 235234 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.data 6988969 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 62341162 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 62341372 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 0 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -224,47 +242,29 @@ system.physmem.writeRowHits 0 # Nu system.physmem.readRowHitRate nan # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes system.physmem.avgGap nan # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 22 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 53 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 75 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 22 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 53 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 75 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 22 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 53 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 75 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 70662 # number of replacements -system.l2c.tagsinuse 51560.217790 # Cycle average of tags in use -system.l2c.total_refs 1623342 # Total number of references to valid blocks. -system.l2c.sampled_refs 135814 # Sample count of references to valid blocks. -system.l2c.avg_refs 11.952685 # Average number of references to valid blocks. +system.l2c.replacements 70658 # number of replacements +system.l2c.tagsinuse 51560.149653 # Cycle average of tags in use +system.l2c.total_refs 1623339 # Total number of references to valid blocks. +system.l2c.sampled_refs 135810 # Sample count of references to valid blocks. +system.l2c.avg_refs 11.953015 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 39276.104351 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 39278.694978 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000049 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.001108 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 4360.752038 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 2483.307369 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 4358.955639 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 2482.445004 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.dtb.walker 2.678940 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.inst 2126.451282 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu1.data 3310.922653 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.599306 # Average percentage of cache occupancy +system.l2c.occ_percent::writebacks 0.599345 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.066540 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.037892 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.066512 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.037879 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.dtb.walker 0.000041 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.inst 0.032447 # Average percentage of cache occupancy system.l2c.occ_percent::cpu1.data 0.050521 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.786746 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.786745 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.dtb.walker 3874 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.itb.walker 1919 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.inst 421038 # number of ReadReq hits @@ -282,27 +282,27 @@ system.l2c.UpgradeReq_hits::total 1274 # nu system.l2c.SCUpgradeReq_hits::cpu0.data 137 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::cpu1.data 31 # number of SCUpgradeReq hits system.l2c.SCUpgradeReq_hits::total 168 # number of SCUpgradeReq hits -system.l2c.ReadExReq_hits::cpu0.data 58151 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu0.data 58148 # number of ReadExReq hits system.l2c.ReadExReq_hits::cpu1.data 50212 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 108363 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 108360 # number of ReadExReq hits system.l2c.demand_hits::cpu0.dtb.walker 3874 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.itb.walker 1919 # number of demand (read+write) hits system.l2c.demand_hits::cpu0.inst 421038 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 233339 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 233336 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.dtb.walker 5331 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.itb.walker 1734 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.inst 430511 # number of demand (read+write) hits system.l2c.demand_hits::cpu1.data 219723 # number of demand (read+write) hits -system.l2c.demand_hits::total 1317469 # number of demand (read+write) hits +system.l2c.demand_hits::total 1317466 # number of demand (read+write) hits system.l2c.overall_hits::cpu0.dtb.walker 3874 # number of overall hits system.l2c.overall_hits::cpu0.itb.walker 1919 # number of overall hits system.l2c.overall_hits::cpu0.inst 421038 # number of overall hits -system.l2c.overall_hits::cpu0.data 233339 # number of overall hits +system.l2c.overall_hits::cpu0.data 233336 # number of overall hits system.l2c.overall_hits::cpu1.dtb.walker 5331 # number of overall hits system.l2c.overall_hits::cpu1.itb.walker 1734 # number of overall hits system.l2c.overall_hits::cpu1.inst 430511 # number of overall hits system.l2c.overall_hits::cpu1.data 219723 # number of overall hits -system.l2c.overall_hits::total 1317469 # number of overall hits +system.l2c.overall_hits::total 1317466 # number of overall hits system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.itb.walker 3 # number of ReadReq misses system.l2c.ReadReq_misses::cpu0.inst 7432 # number of ReadReq misses @@ -317,25 +317,25 @@ system.l2c.UpgradeReq_misses::total 9236 # nu system.l2c.SCUpgradeReq_misses::cpu0.data 741 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::cpu1.data 490 # number of SCUpgradeReq misses system.l2c.SCUpgradeReq_misses::total 1231 # number of SCUpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 92461 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu0.data 92464 # number of ReadExReq misses system.l2c.ReadExReq_misses::cpu1.data 48372 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 140833 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 140836 # number of ReadExReq misses system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.itb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu0.inst 7432 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 98853 # number of demand (read+write) misses +system.l2c.demand_misses::cpu0.data 98856 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.dtb.walker 3 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.inst 3347 # number of demand (read+write) misses system.l2c.demand_misses::cpu1.data 53648 # number of demand (read+write) misses -system.l2c.demand_misses::total 163287 # number of demand (read+write) misses +system.l2c.demand_misses::total 163290 # number of demand (read+write) misses system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses system.l2c.overall_misses::cpu0.itb.walker 3 # number of overall misses system.l2c.overall_misses::cpu0.inst 7432 # number of overall misses -system.l2c.overall_misses::cpu0.data 98853 # number of overall misses +system.l2c.overall_misses::cpu0.data 98856 # number of overall misses system.l2c.overall_misses::cpu1.dtb.walker 3 # number of overall misses system.l2c.overall_misses::cpu1.inst 3347 # number of overall misses system.l2c.overall_misses::cpu1.data 53648 # number of overall misses -system.l2c.overall_misses::total 163287 # number of overall misses +system.l2c.overall_misses::total 163290 # number of overall misses system.l2c.ReadReq_accesses::cpu0.dtb.walker 3875 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.itb.walker 1922 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.inst 428470 # number of ReadReq accesses(hits+misses) @@ -388,25 +388,25 @@ system.l2c.UpgradeReq_miss_rate::total 0.878782 # mi system.l2c.SCUpgradeReq_miss_rate::cpu0.data 0.843964 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::cpu1.data 0.940499 # miss rate for SCUpgradeReq accesses system.l2c.SCUpgradeReq_miss_rate::total 0.879914 # miss rate for SCUpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 0.613902 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 0.613922 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::cpu1.data 0.490668 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.565150 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.565162 # miss rate for ReadExReq accesses system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.itb.walker 0.001561 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu0.inst 0.017345 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.297578 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.297587 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.inst 0.007715 # miss rate for demand accesses system.l2c.demand_miss_rate::cpu1.data 0.196246 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.110273 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.110275 # miss rate for demand accesses system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000258 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.itb.walker 0.001561 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu0.inst 0.017345 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.297578 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.297587 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000562 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.inst 0.007715 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu1.data 0.196246 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.110273 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.110275 # miss rate for overall accesses system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -490,15 +490,15 @@ system.cpu0.not_idle_fraction 0.021750 # Pe system.cpu0.idle_fraction 0.978250 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed system.cpu0.kern.inst.quiesce 49966 # number of quiesce instructions executed -system.cpu0.icache.replacements 428547 # number of replacements -system.cpu0.icache.tagsinuse 511.020000 # Cycle average of tags in use +system.cpu0.icache.replacements 428546 # number of replacements +system.cpu0.icache.tagsinuse 511.015216 # Cycle average of tags in use system.cpu0.icache.total_refs 29811115 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 429059 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 69.480223 # Average number of references to valid blocks. +system.cpu0.icache.sampled_refs 429058 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 69.480385 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 64537139000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 511.020000 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.998086 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.998086 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 511.015216 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.998077 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.998077 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 29811115 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 29811115 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 29811115 # number of demand (read+write) hits diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini index edcbc8719..8e8c112af 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini @@ -10,20 +10,21 @@ time_sync_spin_threshold=100000000 type=LinuxArmSystem children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem -midr_regval=890224640 +mem_ranges=0:134217727 +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +40,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -64,16 +65,15 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu0] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -81,6 +81,7 @@ dtb=system.cpu0.dtb function_trace=false function_trace_start=0 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa itb=system.cpu0.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -89,6 +90,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu0.tracer workload= @@ -100,23 +102,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -130,7 +127,7 @@ walker=system.cpu0.dtb.walker [system.cpu0.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[3] @@ -140,23 +137,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -165,6 +157,23 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=ArmInterrupts +[system.cpu0.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu0.itb] type=ArmTLB children=walker @@ -173,7 +182,7 @@ walker=system.cpu0.itb.walker [system.cpu0.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[2] @@ -183,11 +192,10 @@ type=ExeTracer [system.cpu1] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb tracer checker=Null clock=500 cpu_id=1 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -195,6 +203,7 @@ dtb=system.cpu1.dtb function_trace=false function_trace_start=0 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa itb=system.cpu1.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -203,6 +212,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu1.tracer workload= @@ -214,23 +224,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -244,7 +249,7 @@ walker=system.cpu1.dtb.walker [system.cpu1.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[7] @@ -254,23 +259,18 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -279,6 +279,23 @@ mem_side=system.toL2Bus.slave[4] [system.cpu1.interrupts] type=ArmInterrupts +[system.cpu1.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu1.itb] type=ArmTLB children=walker @@ -287,7 +304,7 @@ walker=system.cpu1.itb.walker [system.cpu1.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system port=system.toL2Bus.slave[6] @@ -311,57 +328,47 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache -addr_ranges=0:268435455 +addr_ranges=0:134217727 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false -hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=50000 +response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[1] +mem_side=system.membus.slave[2] [system.l2c] type=BaseCache addr_ranges=0:18446744073709551615 assoc=8 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=10000 +hit_latency=20 is_top_level=false max_miss_count=0 -mshrs=92 +mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 +response_latency=20 size=4194304 -subblock_size=0 system=system -tgts_per_mshr=16 -trace_addr=0 +tgts_per_mshr=12 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] -mem_side=system.membus.slave[2] +mem_side=system.membus.slave[1] [system.membus] type=CoherentBus @@ -373,11 +380,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.l2c.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -393,15 +400,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -416,7 +436,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -425,7 +445,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -472,7 +492,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -490,11 +510,12 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=41667 +clock=1000 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 +pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -503,7 +524,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -512,7 +533,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -529,7 +550,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -543,7 +564,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -553,7 +574,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -563,7 +584,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -573,7 +594,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -587,7 +608,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -600,7 +621,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -629,7 +650,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -639,7 +660,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -651,7 +672,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -663,7 +684,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -676,7 +697,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -686,7 +707,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -696,7 +717,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -706,7 +727,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -716,7 +737,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -730,7 +751,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -743,7 +764,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -758,7 +779,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -768,7 +789,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -778,7 +799,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -788,7 +809,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -805,7 +826,7 @@ port=3456 [system.toL2Bus] type=CoherentBus block_size=64 -clock=1000 +clock=500 header_cycles=1 use_default_range=false width=8 diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr index 04178bb32..e8e271d58 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simerr @@ -12,7 +12,6 @@ warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: instruction 'mcr bpiallis' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr icialluis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout index 155c18cca..cecfd8ad7 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:18 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:31:36 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 1207290627000 because m5_exit instruction encountered +Exiting @ tick 1182882156500 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt index af19e8e2a..b637311d9 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/stats.txt @@ -1,122 +1,140 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 1.182883 # Number of seconds simulated -sim_ticks 1182883275000 # Number of ticks simulated -final_tick 1182883275000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 1.182882 # Number of seconds simulated +sim_ticks 1182882156500 # Number of ticks simulated +final_tick 1182882156500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 656929 # Simulator instruction rate (inst/s) -host_op_rate 837075 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 12645375755 # Simulator tick rate (ticks/s) -host_mem_usage 400812 # Number of bytes of host memory used -host_seconds 93.54 # Real time elapsed on the host -sim_insts 61450949 # Number of instructions simulated -sim_ops 78302298 # Number of ops (including micro ops) simulated +host_inst_rate 184229 # Simulator instruction rate (inst/s) +host_op_rate 234741 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 3546252898 # Simulator tick rate (ticks/s) +host_mem_usage 402168 # Number of bytes of host memory used +host_seconds 333.56 # Real time elapsed on the host +sim_insts 61450993 # Number of instructions simulated +sim_ops 78299715 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 51904512 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.inst 393380 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 4708212 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.inst 393572 # Number of bytes read from this memory +system.physmem.bytes_read::cpu0.data 4715764 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.dtb.walker 256 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 323164 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 4780336 # Number of bytes read from this memory -system.physmem.bytes_read::total 62110052 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 393380 # Number of instructions bytes read from this memory +system.physmem.bytes_read::cpu1.data 4806320 # Number of bytes read from this memory +system.physmem.bytes_read::total 62143780 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu0.inst 393572 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::cpu1.inst 323164 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 716544 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 4085888 # Number of bytes written to this memory +system.physmem.bytes_inst_read::total 716736 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 4114688 # Number of bytes written to this memory system.physmem.bytes_written::cpu0.data 17000 # Number of bytes written to this memory system.physmem.bytes_written::cpu1.data 3010344 # Number of bytes written to this memory -system.physmem.bytes_written::total 7113232 # Number of bytes written to this memory +system.physmem.bytes_written::total 7142032 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 6488064 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.inst 12365 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 73638 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.inst 12368 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu0.data 73756 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.dtb.walker 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu1.inst 5131 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 74719 # Number of read requests responded to by this memory -system.physmem.num_reads::total 6653924 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 63842 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu1.data 75125 # Number of read requests responded to by this memory +system.physmem.num_reads::total 6654451 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 64292 # Number of write requests responded to by this memory system.physmem.num_writes::cpu0.data 4250 # Number of write requests responded to by this memory system.physmem.num_writes::cpu1.data 752586 # Number of write requests responded to by this memory -system.physmem.num_writes::total 820678 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 43879657 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 821128 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 43879698 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.dtb.walker 54 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu0.itb.walker 108 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.inst 332560 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 3980285 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 332723 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 3986673 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu1.dtb.walker 216 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 273200 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 4041258 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 52507338 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 332560 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 273200 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 605761 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 3454177 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 273201 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 4063228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 52535901 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 332723 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 273201 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 605923 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 3478527 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu0.data 14372 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1.data 2544921 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 6013469 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 3454177 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 43879657 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::cpu1.data 2544923 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 6037822 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 3478527 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 43879698 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.dtb.walker 54 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu0.itb.walker 108 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 332560 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 3994656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 332723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 4001044 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu1.dtb.walker 216 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 273200 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 6586178 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 58520807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 6653924 # Total number of read requests seen -system.physmem.writeReqs 820678 # Total number of write requests seen -system.physmem.cpureqs 271841 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 425851136 # Total number of bytes read from memory -system.physmem.bytesWritten 52523392 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62110052 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 7113232 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu1.inst 273201 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 6608151 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 58573723 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 6654451 # Total number of read requests seen +system.physmem.writeReqs 821128 # Total number of write requests seen +system.physmem.cpureqs 272784 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 425884864 # Total number of bytes read from memory +system.physmem.bytesWritten 52552192 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 62143780 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 7142032 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 132 # Number of read reqs serviced by write Q -system.physmem.neitherReadNorWrite 11752 # Reqs where no action is needed -system.physmem.perBankRdReqs::0 415519 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 415704 # Track reads on a per bank basis +system.physmem.neitherReadNorWrite 11751 # Reqs where no action is needed +system.physmem.perBankRdReqs::0 415571 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 415750 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 415458 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 415464 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 415493 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 415211 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 415304 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 415265 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 422311 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 415383 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 415455 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 415586 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 415355 # Track reads on a per bank basis -system.physmem.perBankRdReqs::13 415574 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 415386 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 415468 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 415552 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 415207 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 415303 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 415263 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 422360 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 415431 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 415464 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 415652 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 415419 # Track reads on a per bank basis +system.physmem.perBankRdReqs::13 415645 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 415452 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 415324 # Track reads on a per bank basis -system.physmem.perBankWrReqs::0 50680 # Track writes on a per bank basis -system.physmem.perBankWrReqs::1 50792 # Track writes on a per bank basis +system.physmem.perBankWrReqs::0 50727 # Track writes on a per bank basis +system.physmem.perBankWrReqs::1 50837 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 50611 # Track writes on a per bank basis -system.physmem.perBankWrReqs::3 50650 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 51629 # Track writes on a per bank basis +system.physmem.perBankWrReqs::3 50656 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 51686 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 51413 # Track writes on a per bank basis -system.physmem.perBankWrReqs::6 51506 # Track writes on a per bank basis -system.physmem.perBankWrReqs::7 51453 # Track writes on a per bank basis -system.physmem.perBankWrReqs::8 51654 # Track writes on a per bank basis -system.physmem.perBankWrReqs::9 51491 # Track writes on a per bank basis -system.physmem.perBankWrReqs::10 51429 # Track writes on a per bank basis -system.physmem.perBankWrReqs::11 51462 # Track writes on a per bank basis -system.physmem.perBankWrReqs::12 51424 # Track writes on a per bank basis -system.physmem.perBankWrReqs::13 51618 # Track writes on a per bank basis -system.physmem.perBankWrReqs::14 51455 # Track writes on a per bank basis +system.physmem.perBankWrReqs::6 51505 # Track writes on a per bank basis +system.physmem.perBankWrReqs::7 51451 # Track writes on a per bank basis +system.physmem.perBankWrReqs::8 51696 # Track writes on a per bank basis +system.physmem.perBankWrReqs::9 51531 # Track writes on a per bank basis +system.physmem.perBankWrReqs::10 51439 # Track writes on a per bank basis +system.physmem.perBankWrReqs::11 51528 # Track writes on a per bank basis +system.physmem.perBankWrReqs::12 51471 # Track writes on a per bank basis +system.physmem.perBankWrReqs::13 51659 # Track writes on a per bank basis +system.physmem.perBankWrReqs::14 51507 # Track writes on a per bank basis system.physmem.perBankWrReqs::15 51411 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 1182878800500 # Total gap between requests +system.physmem.totGap 1182877668000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6825 # Categorize read packet sizes system.physmem.readPktSize::3 6488064 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 159035 # Categorize read packet sizes +system.physmem.readPktSize::6 159562 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -125,7 +143,7 @@ system.physmem.writePktSize::2 756836 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 63842 # categorize write packet sizes +system.physmem.writePktSize::6 64292 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -134,26 +152,26 @@ system.physmem.neitherpktsize::2 0 # ca system.physmem.neitherpktsize::3 0 # categorize neither packet sizes system.physmem.neitherpktsize::4 0 # categorize neither packet sizes system.physmem.neitherpktsize::5 0 # categorize neither packet sizes -system.physmem.neitherpktsize::6 11752 # categorize neither packet sizes +system.physmem.neitherpktsize::6 11751 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 6596894 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 41002 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 1803 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 662 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 504 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 410 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 308 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 169 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 141 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 127 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 108 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 67 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 40 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 574129 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 411417 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 411845 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 427327 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1182593 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 1193140 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 2312606 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 25343 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 15031 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 14611 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 14622 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 26114 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 14563 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 25574 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 2767 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 2575 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 62 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -170,309 +188,291 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35674 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35680 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::4 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::5 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::6 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::7 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::8 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::9 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::10 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::11 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::12 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::13 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::14 35682 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::15 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::18 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::19 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::20 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::21 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::22 35681 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 8 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::27 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35697 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::4 35702 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::5 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::6 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::7 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::8 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::9 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::10 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::11 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::12 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::13 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::14 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::15 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::18 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::19 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::20 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::21 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::22 35701 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 5 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3569461684 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 123099843684 # Sum of mem lat for all requests -system.physmem.totBusLat 26615168000 # Total cycles spent in databus access -system.physmem.totBankLat 92915214000 # Total cycles spent in bank access -system.physmem.avgQLat 536.46 # Average queueing delay per request -system.physmem.avgBankLat 13964.25 # Average bank access latency per request +system.physmem.totQLat 123719908904 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 159121708904 # Sum of mem lat for all requests +system.physmem.totBusLat 26617276000 # Total cycles spent in databus access +system.physmem.totBankLat 8784524000 # Total cycles spent in bank access +system.physmem.avgQLat 18592.42 # Average queueing delay per request +system.physmem.avgBankLat 1320.12 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18500.71 # Average memory access latency -system.physmem.avgRdBW 360.01 # Average achieved read bandwidth in MB/s -system.physmem.avgWrBW 44.40 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 52.51 # Average consumed read bandwidth in MB/s -system.physmem.avgConsumedWrBW 6.01 # Average consumed write bandwidth in MB/s +system.physmem.avgMemAccLat 23912.55 # Average memory access latency +system.physmem.avgRdBW 360.04 # Average achieved read bandwidth in MB/s +system.physmem.avgWrBW 44.43 # Average achieved write bandwidth in MB/s +system.physmem.avgConsumedRdBW 52.54 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedWrBW 6.04 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.53 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.10 # Average read queue length over time -system.physmem.avgWrQLen 15.10 # Average write queue length over time -system.physmem.readRowHits 6624970 # Number of row buffer hits during reads -system.physmem.writeRowHits 788587 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.57 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.09 # Row buffer hit rate for writes -system.physmem.avgGap 158253.08 # Average gap between requests -system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::cpu1.inst 48 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 68 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu1.inst 48 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 68 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::cpu1.inst 12 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 17 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu0.inst 17 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::cpu1.inst 41 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 57 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu0.inst 17 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu1.inst 41 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 57 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu0.inst 17 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu1.inst 41 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 57 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 68922 # number of replacements -system.l2c.tagsinuse 53038.398444 # Cycle average of tags in use -system.l2c.total_refs 1676342 # Total number of references to valid blocks. -system.l2c.sampled_refs 134082 # Sample count of references to valid blocks. -system.l2c.avg_refs 12.502364 # Average number of references to valid blocks. +system.physmem.avgRdQLen 0.13 # Average read queue length over time +system.physmem.avgWrQLen 15.12 # Average write queue length over time +system.physmem.readRowHits 6628163 # Number of row buffer hits during reads +system.physmem.writeRowHits 789308 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.61 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.12 # Row buffer hit rate for writes +system.physmem.avgGap 158232.25 # Average gap between requests +system.l2c.replacements 69442 # number of replacements +system.l2c.tagsinuse 53039.972087 # Cycle average of tags in use +system.l2c.total_refs 1672967 # Total number of references to valid blocks. +system.l2c.sampled_refs 134589 # Sample count of references to valid blocks. +system.l2c.avg_refs 12.430191 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 40183.482743 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 40188.045356 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.dtb.walker 0.000405 # Average occupied blocks per requestor system.l2c.occ_blocks::cpu0.itb.walker 0.001414 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 3728.899373 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 4237.689144 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.dtb.walker 2.742166 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 2823.942801 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 2061.640399 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.613151 # Average percentage of cache occupancy +system.l2c.occ_blocks::cpu0.inst 3727.182104 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 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average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency @@ -656,26 +656,26 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu0.dtb.inst_hits 0 # ITB inst hits system.cpu0.dtb.inst_misses 0 # ITB inst misses -system.cpu0.dtb.read_hits 7072907 # DTB read hits -system.cpu0.dtb.read_misses 3765 # DTB read misses -system.cpu0.dtb.write_hits 5658426 # DTB write hits -system.cpu0.dtb.write_misses 809 # DTB write misses +system.cpu0.dtb.read_hits 7070111 # DTB read hits +system.cpu0.dtb.read_misses 3764 # DTB read misses +system.cpu0.dtb.write_hits 5656042 # DTB write hits +system.cpu0.dtb.write_misses 804 # DTB write misses system.cpu0.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu0.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu0.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu0.dtb.flush_entries 1807 # Number of entries that have been flushed from TLB system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu0.dtb.prefetch_faults 141 # Number of TLB faults due to prefetch +system.cpu0.dtb.prefetch_faults 143 # Number of TLB faults due to prefetch system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu0.dtb.perms_faults 204 # Number of TLB faults due to permissions restrictions -system.cpu0.dtb.read_accesses 7076672 # DTB read accesses -system.cpu0.dtb.write_accesses 5659235 # DTB write accesses +system.cpu0.dtb.read_accesses 7073875 # DTB read accesses +system.cpu0.dtb.write_accesses 5656846 # DTB write accesses system.cpu0.dtb.inst_accesses 0 # ITB inst accesses -system.cpu0.dtb.hits 12731333 # DTB hits -system.cpu0.dtb.misses 4574 # DTB misses -system.cpu0.dtb.accesses 12735907 # DTB accesses -system.cpu0.itb.inst_hits 29570611 # ITB inst hits +system.cpu0.dtb.hits 12726153 # DTB hits +system.cpu0.dtb.misses 4568 # DTB misses +system.cpu0.dtb.accesses 12730721 # DTB accesses +system.cpu0.itb.inst_hits 29570310 # ITB inst hits system.cpu0.itb.inst_misses 2205 # ITB inst misses system.cpu0.itb.read_hits 0 # DTB read hits system.cpu0.itb.read_misses 0 # DTB read misses @@ -692,79 +692,79 @@ system.cpu0.itb.domain_faults 0 # Nu system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu0.itb.read_accesses 0 # DTB read accesses system.cpu0.itb.write_accesses 0 # DTB write accesses -system.cpu0.itb.inst_accesses 29572816 # ITB inst accesses -system.cpu0.itb.hits 29570611 # DTB hits +system.cpu0.itb.inst_accesses 29572515 # ITB inst accesses +system.cpu0.itb.hits 29570310 # DTB hits system.cpu0.itb.misses 2205 # DTB misses -system.cpu0.itb.accesses 29572816 # DTB accesses -system.cpu0.numCycles 2365766550 # number of cpu cycles simulated +system.cpu0.itb.accesses 29572515 # DTB accesses +system.cpu0.numCycles 2365764313 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 28872677 # Number of instructions committed -system.cpu0.committedOps 37219640 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 33106294 # Number of integer alu accesses +system.cpu0.committedInsts 28872367 # Number of instructions committed +system.cpu0.committedOps 37211047 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 33098187 # Number of integer alu accesses system.cpu0.num_fp_alu_accesses 3860 # Number of float alu accesses -system.cpu0.num_func_calls 1241693 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 4373343 # number of instructions that are conditional controls -system.cpu0.num_int_insts 33106294 # number of integer instructions +system.cpu0.num_func_calls 1241715 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 4373222 # number of instructions that are conditional controls +system.cpu0.num_int_insts 33098187 # number of integer instructions system.cpu0.num_fp_insts 3860 # number of float instructions -system.cpu0.num_int_register_reads 190095681 # number of times the integer registers were read -system.cpu0.num_int_register_writes 36231150 # number of times the integer registers were written +system.cpu0.num_int_register_reads 190047206 # number of times the integer registers were read +system.cpu0.num_int_register_writes 36225366 # number of times the integer registers were written system.cpu0.num_fp_register_reads 3022 # number of times the floating registers were read system.cpu0.num_fp_register_writes 840 # number of times the floating registers were written -system.cpu0.num_mem_refs 13399479 # number of memory refs -system.cpu0.num_load_insts 7410420 # Number of load instructions -system.cpu0.num_store_insts 5989059 # Number of store instructions -system.cpu0.num_idle_cycles 2224930438.354119 # Number of idle cycles -system.cpu0.num_busy_cycles 140836111.645881 # Number of busy cycles -system.cpu0.not_idle_fraction 0.059531 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0.940469 # Percentage of idle cycles +system.cpu0.num_mem_refs 13394441 # number of memory refs +system.cpu0.num_load_insts 7407672 # Number of load instructions +system.cpu0.num_store_insts 5986769 # Number of store instructions +system.cpu0.num_idle_cycles 2224997657.358119 # Number of idle cycles +system.cpu0.num_busy_cycles 140766655.641881 # Number of busy cycles +system.cpu0.not_idle_fraction 0.059502 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.940498 # Percentage of idle cycles system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.quiesce 46695 # number of quiesce instructions executed -system.cpu0.icache.replacements 425420 # number of replacements -system.cpu0.icache.tagsinuse 509.627794 # Cycle average of tags in use -system.cpu0.icache.total_refs 29144662 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 425932 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 68.425622 # Average number of references to valid blocks. +system.cpu0.kern.inst.quiesce 46700 # number of quiesce instructions executed +system.cpu0.icache.replacements 425445 # number of replacements +system.cpu0.icache.tagsinuse 509.616014 # Cycle average of tags in use +system.cpu0.icache.total_refs 29144335 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 425957 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 68.420838 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 74931906000 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 509.627794 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.995367 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.995367 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 29144662 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 29144662 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 29144662 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 29144662 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 29144662 # number of overall hits -system.cpu0.icache.overall_hits::total 29144662 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 425932 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 425932 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 425932 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 425932 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 425932 # number of overall misses -system.cpu0.icache.overall_misses::total 425932 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5794628000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 5794628000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 5794628000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 5794628000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 5794628000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 5794628000 # number of overall miss cycles -system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570594 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 29570594 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 29570594 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 29570594 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 29570594 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 29570594 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014404 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.014404 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014404 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.014404 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014404 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.014404 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13604.584769 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 13604.584769 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 13604.584769 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13604.584769 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 13604.584769 # average overall miss latency +system.cpu0.icache.occ_blocks::cpu0.inst 509.616014 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.995344 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.995344 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 29144335 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 29144335 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 29144335 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 29144335 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 29144335 # number of overall hits +system.cpu0.icache.overall_hits::total 29144335 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 425958 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 425958 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 425958 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 425958 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 425958 # number of overall misses +system.cpu0.icache.overall_misses::total 425958 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 5792188000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 5792188000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 5792188000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 5792188000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 5792188000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 5792188000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 29570293 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 29570293 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 29570293 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 29570293 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 29570293 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 29570293 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_miss_rate::total 0.014405 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014405 # miss rate for demand accesses +system.cpu0.icache.demand_miss_rate::total 0.014405 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014405 # miss rate for overall accesses +system.cpu0.icache.overall_miss_rate::total 0.014405 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 13598.026096 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 13598.026096 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 13598.026096 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 13598.026096 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 13598.026096 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -773,120 +773,120 @@ system.cpu0.icache.avg_blocked_cycles::no_mshrs nan system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.icache.fast_writes 0 # number of fast writes performed system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425932 # number of ReadReq MSHR misses -system.cpu0.icache.ReadReq_mshr_misses::total 425932 # number of ReadReq MSHR misses -system.cpu0.icache.demand_mshr_misses::cpu0.inst 425932 # number of demand (read+write) MSHR misses -system.cpu0.icache.demand_mshr_misses::total 425932 # number of demand (read+write) MSHR misses -system.cpu0.icache.overall_mshr_misses::cpu0.inst 425932 # number of overall MSHR misses -system.cpu0.icache.overall_mshr_misses::total 425932 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4942764000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 4942764000 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4942764000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 4942764000 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4942764000 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 4942764000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 425958 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 425958 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 425958 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 425958 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 425958 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 425958 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 4940272000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 4940272000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 4940272000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 4940272000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 4940272000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 4940272000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::cpu0.inst 288882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.ReadReq_mshr_uncacheable_latency::total 288882000 # number of ReadReq MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::cpu0.inst 288882000 # number of overall MSHR uncacheable cycles system.cpu0.icache.overall_mshr_uncacheable_latency::total 288882000 # number of overall MSHR uncacheable cycles -system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014404 # mshr miss rate for ReadReq accesses -system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for demand accesses -system.cpu0.icache.demand_mshr_miss_rate::total 0.014404 # mshr miss rate for demand accesses -system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014404 # mshr miss rate for overall accesses -system.cpu0.icache.overall_mshr_miss_rate::total 0.014404 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11604.584769 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11604.584769 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 11604.584769 # average overall mshr miss latency +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.014405 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.demand_mshr_miss_rate::total 0.014405 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.overall_mshr_miss_rate::total 0.014405 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11598.026096 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 11598.026096 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 11598.026096 # average overall mshr miss latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::cpu0.inst inf # average ReadReq mshr uncacheable latency system.cpu0.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::cpu0.inst inf # average overall mshr uncacheable latency system.cpu0.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 330832 # number of replacements -system.cpu0.dcache.tagsinuse 453.835370 # Cycle average of tags in use -system.cpu0.dcache.total_refs 12275735 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 331344 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 37.048309 # Average number of references to valid blocks. +system.cpu0.dcache.replacements 330355 # number of replacements +system.cpu0.dcache.tagsinuse 453.331528 # Cycle average of tags in use +system.cpu0.dcache.total_refs 12270860 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 330867 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 37.086987 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 462692000 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 453.835370 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.886397 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.886397 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 6602660 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 6602660 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 5353299 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 5353299 # number of WriteReq hits -system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 147927 # number of LoadLockedReq hits -system.cpu0.dcache.LoadLockedReq_hits::total 147927 # number of LoadLockedReq hits -system.cpu0.dcache.StoreCondReq_hits::cpu0.data 149680 # number of StoreCondReq hits -system.cpu0.dcache.StoreCondReq_hits::total 149680 # number of StoreCondReq hits -system.cpu0.dcache.demand_hits::cpu0.data 11955959 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 11955959 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 11955959 # number of overall hits -system.cpu0.dcache.overall_hits::total 11955959 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 227931 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 227931 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 141702 # number of WriteReq misses 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for overall accesses -system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13745.938464 # average ReadReq miss latency -system.cpu0.dcache.ReadReq_avg_miss_latency::total 13745.938464 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 29122.595306 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 29122.595306 # average WriteReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9464.622642 # average LoadLockedReq miss latency -system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9464.622642 # average LoadLockedReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5928.523759 # average StoreCondReq miss latency -system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5928.523759 # average StoreCondReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 19640.712545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 19640.712545 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 19640.712545 # average overall miss latency +system.cpu0.dcache.demand_misses::cpu0.data 369378 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 369378 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 369378 # number of overall misses +system.cpu0.dcache.overall_misses::total 369378 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 3130112000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 3130112000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4103795500 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4103795500 # number of WriteReq miss cycles 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accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.033373 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.033373 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.025764 # miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_miss_rate::total 0.025764 # miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.059151 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.059151 # miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.047673 # miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_miss_rate::total 0.047673 # miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.029981 # miss rate for demand accesses +system.cpu0.dcache.demand_miss_rate::total 0.029981 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.029981 # miss rate for overall accesses +system.cpu0.dcache.overall_miss_rate::total 0.029981 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 13736.815543 # average ReadReq miss latency +system.cpu0.dcache.ReadReq_avg_miss_latency::total 13736.815543 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 28999.014239 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 28999.014239 # average WriteReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu0.data 9459.627997 # average LoadLockedReq miss latency +system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 9459.627997 # average LoadLockedReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu0.data 5940.803524 # average StoreCondReq miss latency +system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 5940.803524 # average StoreCondReq miss latency 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306514 # number of writebacks -system.cpu0.dcache.writebacks::total 306514 # number of writebacks -system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227931 # number of ReadReq MSHR misses -system.cpu0.dcache.ReadReq_mshr_misses::total 227931 # number of ReadReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 141702 # number of WriteReq MSHR misses -system.cpu0.dcache.WriteReq_mshr_misses::total 141702 # number of WriteReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 9328 # number of LoadLockedReq MSHR misses -system.cpu0.dcache.LoadLockedReq_mshr_misses::total 9328 # number of LoadLockedReq MSHR misses +system.cpu0.dcache.writebacks::writebacks 306206 # number of writebacks +system.cpu0.dcache.writebacks::total 306206 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 227863 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 227863 # number of ReadReq MSHR misses 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of StoreCondFailReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 6520589500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 6520589500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 6520589500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 6520589500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 13560077000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 13560077000 # number of ReadReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 1128521500 # number of WriteReq MSHR uncacheable cycles -system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 1128521500 # number of WriteReq MSHR uncacheable cycles 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overall MSHR uncacheable cycles +system.cpu0.dcache.overall_mshr_uncacheable_latency::total 14689842500 # number of overall MSHR uncacheable cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.033373 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.033373 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.025764 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.059151 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.059151 # mshr miss rate for LoadLockedReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.047654 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.047654 # mshr miss rate for StoreCondReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for demand accesses +system.cpu0.dcache.demand_mshr_miss_rate::total 0.029981 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.029981 # mshr miss rate for overall accesses +system.cpu0.dcache.overall_mshr_miss_rate::total 0.029981 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 11736.815543 # average ReadReq mshr miss latency +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 11736.815543 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 26999.014239 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 26999.014239 # average WriteReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 7459.627997 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7459.627997 # average LoadLockedReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 3943.450394 # average StoreCondReq mshr miss latency +system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 3943.450394 # average StoreCondReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu0.data inf # average StoreCondFailReq mshr miss latency system.cpu0.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17640.712545 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17640.712545 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 17584.023683 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 17584.023683 # average overall mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency @@ -964,26 +964,26 @@ system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dtb.inst_hits 0 # ITB inst hits system.cpu1.dtb.inst_misses 0 # ITB inst misses -system.cpu1.dtb.read_hits 8308581 # DTB read hits +system.cpu1.dtb.read_hits 8310545 # DTB read hits system.cpu1.dtb.read_misses 3643 # DTB read misses -system.cpu1.dtb.write_hits 5825594 # DTB write hits -system.cpu1.dtb.write_misses 1436 # DTB write misses +system.cpu1.dtb.write_hits 5827351 # DTB write hits +system.cpu1.dtb.write_misses 1434 # DTB write misses system.cpu1.dtb.flush_tlb 4 # Number of times complete TLB was flushed system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA system.cpu1.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID system.cpu1.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID system.cpu1.dtb.flush_entries 1965 # Number of entries that have been flushed from TLB system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions -system.cpu1.dtb.prefetch_faults 138 # Number of TLB faults due to prefetch +system.cpu1.dtb.prefetch_faults 140 # Number of TLB faults due to prefetch system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu1.dtb.perms_faults 248 # Number of TLB faults due to permissions restrictions -system.cpu1.dtb.read_accesses 8312224 # DTB read accesses -system.cpu1.dtb.write_accesses 5827030 # DTB write accesses +system.cpu1.dtb.read_accesses 8314188 # DTB read accesses +system.cpu1.dtb.write_accesses 5828785 # DTB write accesses system.cpu1.dtb.inst_accesses 0 # ITB inst accesses -system.cpu1.dtb.hits 14134175 # DTB hits -system.cpu1.dtb.misses 5079 # DTB misses -system.cpu1.dtb.accesses 14139254 # DTB accesses -system.cpu1.itb.inst_hits 33188757 # ITB inst hits +system.cpu1.dtb.hits 14137896 # DTB hits +system.cpu1.dtb.misses 5077 # DTB misses +system.cpu1.dtb.accesses 14142973 # DTB accesses +system.cpu1.itb.inst_hits 33189113 # ITB inst hits system.cpu1.itb.inst_misses 2171 # ITB inst misses system.cpu1.itb.read_hits 0 # DTB read hits system.cpu1.itb.read_misses 0 # DTB read misses @@ -1000,79 +1000,79 @@ system.cpu1.itb.domain_faults 0 # Nu system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu1.itb.read_accesses 0 # DTB read accesses system.cpu1.itb.write_accesses 0 # DTB write accesses -system.cpu1.itb.inst_accesses 33190928 # ITB inst accesses -system.cpu1.itb.hits 33188757 # DTB hits +system.cpu1.itb.inst_accesses 33191284 # ITB inst accesses +system.cpu1.itb.hits 33189113 # DTB hits system.cpu1.itb.misses 2171 # DTB misses -system.cpu1.itb.accesses 33190928 # DTB accesses -system.cpu1.numCycles 2364324282 # number of cpu cycles simulated +system.cpu1.itb.accesses 33191284 # DTB accesses +system.cpu1.numCycles 2364318212 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 32578272 # Number of instructions committed -system.cpu1.committedOps 41082658 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 37307259 # Number of integer alu accesses +system.cpu1.committedInsts 32578626 # Number of instructions committed +system.cpu1.committedOps 41088668 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 37313171 # Number of integer alu accesses system.cpu1.num_fp_alu_accesses 6793 # Number of float alu accesses -system.cpu1.num_func_calls 961975 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 3732574 # number of instructions that are conditional controls -system.cpu1.num_int_insts 37307259 # number of integer instructions +system.cpu1.num_func_calls 962009 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 3732639 # number of instructions that are conditional controls +system.cpu1.num_int_insts 37313171 # number of integer instructions system.cpu1.num_fp_insts 6793 # number of float instructions -system.cpu1.num_int_register_reads 213628675 # number of times the integer registers were read -system.cpu1.num_int_register_writes 39450611 # number of times the integer registers were written +system.cpu1.num_int_register_reads 213663418 # number of times the integer registers were read +system.cpu1.num_int_register_writes 39454743 # number of times the integer registers were written system.cpu1.num_fp_register_reads 4535 # number of times the floating registers were read system.cpu1.num_fp_register_writes 2260 # number of times the floating registers were written -system.cpu1.num_mem_refs 14671912 # number of memory refs -system.cpu1.num_load_insts 8630468 # Number of load instructions -system.cpu1.num_store_insts 6041444 # Number of store instructions -system.cpu1.num_idle_cycles 1868307269.461274 # Number of idle cycles -system.cpu1.num_busy_cycles 496017012.538726 # Number of busy cycles -system.cpu1.not_idle_fraction 0.209792 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.790208 # Percentage of idle cycles +system.cpu1.num_mem_refs 14675641 # number of memory refs +system.cpu1.num_load_insts 8632449 # Number of load instructions +system.cpu1.num_store_insts 6043192 # Number of store instructions +system.cpu1.num_idle_cycles 1868258895.232782 # Number of idle cycles +system.cpu1.num_busy_cycles 496059316.767218 # Number of busy cycles +system.cpu1.not_idle_fraction 0.209811 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.790189 # Percentage of idle cycles system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.quiesce 43897 # number of quiesce instructions executed -system.cpu1.icache.replacements 469210 # number of replacements -system.cpu1.icache.tagsinuse 478.783126 # Cycle average of tags in use -system.cpu1.icache.total_refs 32719031 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 469722 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 69.656160 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 92024110500 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 478.783126 # Average occupied blocks per requestor +system.cpu1.kern.inst.quiesce 43883 # number of quiesce instructions executed +system.cpu1.icache.replacements 469194 # number of replacements +system.cpu1.icache.tagsinuse 478.783096 # Cycle average of tags in use +system.cpu1.icache.total_refs 32719403 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 469706 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 69.659325 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 92023963500 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 478.783096 # Average occupied blocks per requestor system.cpu1.icache.occ_percent::cpu1.inst 0.935123 # Average percentage of cache occupancy system.cpu1.icache.occ_percent::total 0.935123 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 32719031 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 32719031 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 32719031 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 32719031 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 32719031 # number of overall hits -system.cpu1.icache.overall_hits::total 32719031 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 469722 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 469722 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 469722 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 469722 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 469722 # number of overall misses -system.cpu1.icache.overall_misses::total 469722 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6346616500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 6346616500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 6346616500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 6346616500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 6346616500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 6346616500 # number of overall miss cycles -system.cpu1.icache.ReadReq_accesses::cpu1.inst 33188753 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 33188753 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 33188753 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 33188753 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 33188753 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 33188753 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014153 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.014153 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014153 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.014153 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014153 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.014153 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13511.431230 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 13511.431230 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 13511.431230 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13511.431230 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 13511.431230 # average overall miss latency +system.cpu1.icache.ReadReq_hits::cpu1.inst 32719403 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 32719403 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 32719403 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 32719403 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 32719403 # number of overall hits +system.cpu1.icache.overall_hits::total 32719403 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 469706 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 469706 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 469706 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 469706 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 469706 # number of overall misses +system.cpu1.icache.overall_misses::total 469706 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 6343605000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 6343605000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 6343605000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 6343605000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 6343605000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 6343605000 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 33189109 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 33189109 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 33189109 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 33189109 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 33189109 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 33189109 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.014152 # miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_miss_rate::total 0.014152 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.014152 # miss rate for demand accesses +system.cpu1.icache.demand_miss_rate::total 0.014152 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.014152 # miss rate for overall accesses +system.cpu1.icache.overall_miss_rate::total 0.014152 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13505.480024 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 13505.480024 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 13505.480024 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13505.480024 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 13505.480024 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1081,120 +1081,120 @@ system.cpu1.icache.avg_blocked_cycles::no_mshrs nan system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.icache.fast_writes 0 # number of fast writes performed system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469722 # number of ReadReq MSHR misses -system.cpu1.icache.ReadReq_mshr_misses::total 469722 # number of ReadReq MSHR misses -system.cpu1.icache.demand_mshr_misses::cpu1.inst 469722 # number of demand (read+write) MSHR misses -system.cpu1.icache.demand_mshr_misses::total 469722 # number of demand (read+write) MSHR misses -system.cpu1.icache.overall_mshr_misses::cpu1.inst 469722 # number of overall MSHR misses -system.cpu1.icache.overall_mshr_misses::total 469722 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5407172500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 5407172500 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5407172500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 5407172500 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5407172500 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 5407172500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 469706 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 469706 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 469706 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 469706 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 469706 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 469706 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5404193000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5404193000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5404193000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5404193000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5404193000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5404193000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::cpu1.inst 4406000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.ReadReq_mshr_uncacheable_latency::total 4406000 # number of ReadReq MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::cpu1.inst 4406000 # number of overall MSHR uncacheable cycles system.cpu1.icache.overall_mshr_uncacheable_latency::total 4406000 # number of overall MSHR uncacheable cycles -system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014153 # mshr miss rate for ReadReq accesses -system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for demand accesses -system.cpu1.icache.demand_mshr_miss_rate::total 0.014153 # mshr miss rate for demand accesses -system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014153 # mshr miss rate for overall accesses -system.cpu1.icache.overall_mshr_miss_rate::total 0.014153 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11511.431230 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11511.431230 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 11511.431230 # average overall mshr miss latency +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for ReadReq accesses +system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.014152 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for demand accesses +system.cpu1.icache.demand_mshr_miss_rate::total 0.014152 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.014152 # mshr miss rate for overall accesses +system.cpu1.icache.overall_mshr_miss_rate::total 0.014152 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11505.480024 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11505.480024 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 11505.480024 # average overall mshr miss latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::cpu1.inst inf # average ReadReq mshr uncacheable latency system.cpu1.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.icache.overall_avg_mshr_uncacheable_latency::cpu1.inst inf # average overall mshr uncacheable latency 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# number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 6944335 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 4825513 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 4825513 # number of WriteReq hits -system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81763 # number of LoadLockedReq hits -system.cpu1.dcache.LoadLockedReq_hits::total 81763 # number of LoadLockedReq hits -system.cpu1.dcache.StoreCondReq_hits::cpu1.data 82710 # number of StoreCondReq hits -system.cpu1.dcache.StoreCondReq_hits::total 82710 # number of StoreCondReq hits -system.cpu1.dcache.demand_hits::cpu1.data 11769848 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 11769848 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 11769848 # number of overall hits -system.cpu1.dcache.overall_hits::total 11769848 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 170295 # number of ReadReq misses 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ReadReq miss cycles -system.cpu1.dcache.ReadReq_miss_latency::total 2151167000 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 4518557500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 4518557500 # number of WriteReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::cpu1.data 92001000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.LoadLockedReq_miss_latency::total 92001000 # number of LoadLockedReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::cpu1.data 51654000 # number of StoreCondReq miss cycles -system.cpu1.dcache.StoreCondReq_miss_latency::total 51654000 # number of StoreCondReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 6669724500 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 6669724500 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 6669724500 # number of overall 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accesses -system.cpu1.dcache.demand_accesses::total 12089932 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 12089932 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 12089932 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.023936 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.023936 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.030107 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.030107 # miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::cpu1.data 0.119237 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.119237 # miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::cpu1.data 0.108190 # miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_miss_rate::total 0.108190 # miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.026475 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.026475 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.026475 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.026475 # miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 12632.003288 # average ReadReq miss latency -system.cpu1.dcache.ReadReq_avg_miss_latency::total 12632.003288 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30166.150385 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 30166.150385 # average WriteReq miss latency -system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8311.590930 # average LoadLockedReq miss latency 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references to valid blocks. +system.cpu1.dcache.avg_refs 40.903456 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 83625409000 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 471.972808 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.921822 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.921822 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 6946091 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 6946091 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 4827134 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 4827134 # number of WriteReq hits +system.cpu1.dcache.LoadLockedReq_hits::cpu1.data 81752 # number of LoadLockedReq hits +system.cpu1.dcache.LoadLockedReq_hits::total 81752 # number of LoadLockedReq hits +system.cpu1.dcache.StoreCondReq_hits::cpu1.data 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12604.357388 # average ReadReq miss latency +system.cpu1.dcache.ReadReq_avg_miss_latency::total 12604.357388 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 30195.842560 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 30195.842560 # average WriteReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 8334.432598 # average LoadLockedReq miss latency +system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 8334.432598 # average LoadLockedReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::cpu1.data 5152.327784 # average StoreCondReq miss latency +system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 5152.327784 # average StoreCondReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20834.896813 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 20834.896813 # average overall miss latency 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# number of overall MSHR misses -system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1810577000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1810577000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4218979500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4218979500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 69863000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 69863000 # number of LoadLockedReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31600000 # number of StoreCondReq MSHR miss cycles -system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31600000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.writebacks::writebacks 265102 # number of writebacks +system.cpu1.dcache.writebacks::total 265102 # number of writebacks +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 170515 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 170515 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 149924 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 149924 # number of WriteReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 11068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.LoadLockedReq_mshr_misses::total 11068 # number of LoadLockedReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 10026 # number of StoreCondReq MSHR misses +system.cpu1.dcache.StoreCondReq_mshr_misses::total 10026 # number of StoreCondReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 320439 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 320439 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 320439 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 320439 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1808202000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1808202000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 4227233500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 4227233500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 70109500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 70109500 # number of LoadLockedReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 31633000 # number of StoreCondReq MSHR miss cycles +system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 31633000 # number of StoreCondReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::cpu1.data 1000 # number of StoreCondFailReq MSHR miss cycles system.cpu1.dcache.StoreCondFailReq_mshr_miss_latency::total 1000 # number of StoreCondFailReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6029556500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 6029556500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6029556500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 6029556500 # number of overall MSHR miss cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168626695000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168626695000 # number of ReadReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17666887000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17666887000 # number of WriteReq MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186293582000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186293582000 # number of overall MSHR uncacheable cycles -system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023936 # mshr miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030107 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030107 # mshr miss rate for WriteReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119237 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119237 # mshr miss rate for LoadLockedReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108126 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108126 # mshr miss rate for StoreCondReq accesses -system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for demand accesses -system.cpu1.dcache.demand_mshr_miss_rate::total 0.026475 # mshr miss rate for demand accesses -system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026475 # mshr miss rate for overall accesses -system.cpu1.dcache.overall_mshr_miss_rate::total 0.026475 # mshr miss rate for overall accesses -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10632.003288 # average ReadReq mshr miss latency -system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10632.003288 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28166.150385 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28166.150385 # average WriteReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6311.590930 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6311.590930 # average LoadLockedReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3151.176705 # average StoreCondReq mshr miss latency -system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3151.176705 # average StoreCondReq mshr miss latency +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 6035435500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 6035435500 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 6035435500 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 6035435500 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 168635770000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 168635770000 # number of ReadReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 17673871500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 17673871500 # number of WriteReq MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 186309641500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.overall_mshr_uncacheable_latency::total 186309641500 # number of overall MSHR uncacheable cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.023960 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.023960 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.030123 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.030123 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.119242 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.119242 # mshr miss rate for LoadLockedReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.108103 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.108103 # mshr miss rate for StoreCondReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for demand accesses +system.cpu1.dcache.demand_mshr_miss_rate::total 0.026496 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.026496 # mshr miss rate for overall accesses +system.cpu1.dcache.overall_mshr_miss_rate::total 0.026496 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 10604.357388 # average ReadReq mshr miss latency +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 10604.357388 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28195.842560 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 28195.842560 # average WriteReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 6334.432598 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 6334.432598 # average LoadLockedReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 3155.096748 # average StoreCondReq mshr miss latency +system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 3155.096748 # average StoreCondReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::cpu1.data inf # average StoreCondFailReq mshr miss latency system.cpu1.dcache.StoreCondFailReq_avg_mshr_miss_latency::total inf # average StoreCondFailReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18837.419240 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18837.419240 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 18834.896813 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 18834.896813 # average overall mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency @@ -1284,10 +1284,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 446757532781 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 446757532781 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 446757532781 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 446757532781 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 479634051298 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 479634051298 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 479634051298 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 479634051298 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini index 663527e71..eecdc36d4 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini @@ -8,22 +8,23 @@ time_sync_spin_threshold=100000000 [system] type=LinuxArmSystem -children=bridge cf0 cpu intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver +children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver atags_addr=256 -boot_loader=/projects/pd/randd/dist/binaries/boot.arm +boot_loader=/gem5/dist/binaries/boot.arm boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1 -clock=1 +clock=1000 dtb_filename= early_kernel_symbols=false +enable_context_switch_stats_dump=false flags_addr=268435504 gic_cpu_addr=520093952 init_param=0 -kernel=/projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +kernel=/gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 load_addr_mask=268435455 machine_type=RealView_PBX mem_mode=timing -memories=system.physmem system.realview.nvmem -midr_regval=890224640 +mem_ranges=0:134217727 +memories=system.realview.nvmem system.physmem multi_proc=true num_work_ids=16 readfile=tests/halt.sh @@ -39,7 +40,7 @@ system_port=system.membus.slave[0] [system.bridge] type=Bridge -clock=1 +clock=1000 delay=50000 ranges=268435456:520093695 1073741824:1610612735 req_size=16 @@ -64,16 +65,15 @@ table_size=65536 [system.cf0.image.child] type=RawDiskImage -image_file=/projects/pd/randd/dist/disks/linux-arm-ael.img +image_file=/gem5/dist/disks/linux-arm-ael.img read_only=true [system.cpu] type=TimingSimpleCPU -children=dcache dtb icache interrupts itb tracer +children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -81,6 +81,7 @@ dtb=system.cpu.dtb function_trace=false function_trace_start=0 interrupts=system.cpu.interrupts +isa=system.cpu.isa itb=system.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -89,6 +90,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.tracer workload= @@ -100,27 +102,22 @@ type=BaseCache addr_ranges=0:18446744073709551615 assoc=4 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port -mem_side=system.toL2Bus.slave[1] +mem_side=system.cpu.toL2Bus.slave[1] [system.cpu.dtb] type=ArmTLB @@ -130,41 +127,53 @@ walker=system.cpu.dtb.walker [system.cpu.dtb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[3] +port=system.cpu.toL2Bus.slave[3] [system.cpu.icache] type=BaseCache addr_ranges=0:18446744073709551615 assoc=1 block_size=64 -clock=1 +clock=500 forward_snoops=true -hash_delay=1 -hit_latency=1000 +hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=1000 +response_latency=2 size=32768 -subblock_size=0 system=system -tgts_per_mshr=8 -trace_addr=0 +tgts_per_mshr=20 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port -mem_side=system.toL2Bus.slave[0] +mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -173,10 +182,42 @@ walker=system.cpu.itb.walker [system.cpu.itb.walker] type=ArmTableWalker -clock=1 +clock=500 num_squash_per_cycle=2 sys=system -port=system.toL2Bus.slave[2] +port=system.cpu.toL2Bus.slave[2] + +[system.cpu.l2cache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +clock=500 +forward_snoops=true +hit_latency=20 +is_top_level=false +max_miss_count=0 +mshrs=20 +prefetch_on_access=false +prefetcher=Null +response_latency=20 +size=4194304 +system=system +tgts_per_mshr=12 +two_queue=false +write_buffers=8 +cpu_side=system.cpu.toL2Bus.master[0] +mem_side=system.membus.slave[1] + +[system.cpu.toL2Bus] +type=CoherentBus +block_size=64 +clock=500 +header_cycles=1 +use_default_range=false +width=32 +master=system.cpu.l2cache.cpu_side +slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port [system.cpu.tracer] type=ExeTracer @@ -197,56 +238,24 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma [system.iocache] type=BaseCache -addr_ranges=0:268435455 +addr_ranges=0:134217727 assoc=8 block_size=64 -clock=1 +clock=1000 forward_snoops=false -hash_delay=1 -hit_latency=50000 -is_top_level=false +hit_latency=50 +is_top_level=true max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=50000 +response_latency=50 size=1024 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.iobus.master[25] -mem_side=system.membus.slave[1] - -[system.l2c] -type=BaseCache -addr_ranges=0:18446744073709551615 -assoc=8 -block_size=64 -clock=1 -forward_snoops=true -hash_delay=1 -hit_latency=10000 -is_top_level=false -max_miss_count=0 -mshrs=92 -prefetch_on_access=false -prefetcher=Null -prioritizeRequests=false -repl=Null -response_latency=10000 -size=4194304 -subblock_size=0 -system=system -tgts_per_mshr=16 -trace_addr=0 -two_queue=false -write_buffers=8 -cpu_side=system.toL2Bus.master[0] mem_side=system.membus.slave[2] [system.membus] @@ -259,11 +268,11 @@ use_default_range=false width=8 default=system.membus.badaddr_responder.pio master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio -slave=system.system_port system.iocache.mem_side system.l2c.mem_side +slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side [system.membus.badaddr_responder] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=0 pio_latency=100000 @@ -279,15 +288,28 @@ warn_access=warn pio=system.membus.default [system.physmem] -type=SimpleMemory -bandwidth=73.000000 -clock=1 +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=true in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=system.membus.master[2] @@ -302,7 +324,7 @@ system=system [system.realview.a9scu] type=A9SCU -clock=1 +clock=1000 pio_addr=520093696 pio_latency=100000 system=system @@ -311,7 +333,7 @@ pio=system.membus.master[5] [system.realview.aaci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268451840 pio_latency=100000 @@ -358,7 +380,7 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 -clock=1 +clock=1000 config_latency=20000 ctrl_offset=2 disks=system.cf0 @@ -376,11 +398,12 @@ pio=system.iobus.master[7] [system.realview.clcd] type=Pl111 amba_id=1315089 -clock=41667 +clock=1000 gic=system.realview.gic int_num=55 pio_addr=268566528 pio_latency=10000 +pixel_clock=41667 system=system vnc=system.vncserver dma=system.iobus.slave[1] @@ -389,7 +412,7 @@ pio=system.iobus.master[4] [system.realview.dmac_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268632064 pio_latency=100000 @@ -398,7 +421,7 @@ pio=system.iobus.master[9] [system.realview.flash_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=true pio_addr=1073741824 pio_latency=100000 @@ -415,7 +438,7 @@ pio=system.iobus.master[24] [system.realview.gic] type=Gic -clock=1 +clock=1000 cpu_addr=520093952 cpu_pio_delay=10000 dist_addr=520097792 @@ -429,7 +452,7 @@ pio=system.membus.master[3] [system.realview.gpio0_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268513280 pio_latency=100000 @@ -439,7 +462,7 @@ pio=system.iobus.master[16] [system.realview.gpio1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268517376 pio_latency=100000 @@ -449,7 +472,7 @@ pio=system.iobus.master[17] [system.realview.gpio2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268521472 pio_latency=100000 @@ -459,7 +482,7 @@ pio=system.iobus.master[18] [system.realview.kmi0] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=52 @@ -473,7 +496,7 @@ pio=system.iobus.master[5] [system.realview.kmi1] type=Pl050 amba_id=1314896 -clock=1 +clock=1000 gic=system.realview.gic int_delay=1000000 int_num=53 @@ -486,7 +509,7 @@ pio=system.iobus.master[6] [system.realview.l2x0_fake] type=IsaFake -clock=1 +clock=1000 fake_mem=false pio_addr=520101888 pio_latency=100000 @@ -515,7 +538,7 @@ pio=system.membus.master[6] [system.realview.mmc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268455936 pio_latency=100000 @@ -525,7 +548,7 @@ pio=system.iobus.master[22] [system.realview.nvmem] type=SimpleMemory bandwidth=73.000000 -clock=1 +clock=1000 conf_table_reported=false in_addr_map=true latency=30000 @@ -537,7 +560,7 @@ port=system.membus.master[1] [system.realview.realview_io] type=RealViewCtrl -clock=1 +clock=1000 idreg=0 pio_addr=268435456 pio_latency=100000 @@ -549,7 +572,7 @@ pio=system.iobus.master[1] [system.realview.rtc] type=PL031 amba_id=3412017 -clock=1 +clock=1000 gic=system.realview.gic int_delay=100000 int_num=42 @@ -562,7 +585,7 @@ pio=system.iobus.master[23] [system.realview.sci_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268492800 pio_latency=100000 @@ -572,7 +595,7 @@ pio=system.iobus.master[20] [system.realview.smc_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=269357056 pio_latency=100000 @@ -582,7 +605,7 @@ pio=system.iobus.master[13] [system.realview.sp810_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=true pio_addr=268439552 pio_latency=100000 @@ -592,7 +615,7 @@ pio=system.iobus.master[14] [system.realview.ssp_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268488704 pio_latency=100000 @@ -602,7 +625,7 @@ pio=system.iobus.master[19] [system.realview.timer0] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -616,7 +639,7 @@ pio=system.iobus.master[2] [system.realview.timer1] type=Sp804 amba_id=1316868 -clock=1 +clock=1000 clock0=1000000 clock1=1000000 gic=system.realview.gic @@ -629,7 +652,7 @@ pio=system.iobus.master[3] [system.realview.uart] type=Pl011 -clock=1 +clock=1000 end_on_eot=false gic=system.realview.gic int_delay=100000 @@ -644,7 +667,7 @@ pio=system.iobus.master[0] [system.realview.uart1_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268476416 pio_latency=100000 @@ -654,7 +677,7 @@ pio=system.iobus.master[10] [system.realview.uart2_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268480512 pio_latency=100000 @@ -664,7 +687,7 @@ pio=system.iobus.master[11] [system.realview.uart3_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268484608 pio_latency=100000 @@ -674,7 +697,7 @@ pio=system.iobus.master[12] [system.realview.watchdog_fake] type=AmbaFake amba_id=0 -clock=1 +clock=1000 ignore_access=false pio_addr=268500992 pio_latency=100000 @@ -688,16 +711,6 @@ number=0 output=true port=3456 -[system.toL2Bus] -type=CoherentBus -block_size=64 -clock=1000 -header_cycles=1 -use_default_range=false -width=8 -master=system.l2c.cpu_side -slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port - [system.vncserver] type=VncServer frame_capture=false diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr index 9a28ceb37..3ee89fc27 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr @@ -11,7 +11,6 @@ warn: instruction 'mcr dccimvac' unimplemented warn: instruction 'mcr dccmvau' unimplemented warn: instruction 'mcr icimvau' unimplemented warn: LCD dual screen mode not supported -warn: Returning thumbEE disabled for now since we don't support CP14config registers and jumping to ThumbEE vectors warn: instruction 'mcr icialluis' unimplemented warn: instruction 'mcr bpiallis' unimplemented hack: be nice to actually delete the event here diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout index 956979587..fedaf9185 100755 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout @@ -1,12 +1,12 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Sep 21 2012 11:19:00 -gem5 started Sep 21 2012 11:19:18 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:31:27 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing Global frequency set at 1000000000000 ticks per second -info: kernel located at: /projects/pd/randd/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 +info: kernel located at: /gem5/dist/binaries/vmlinux.arm.smp.fb.2.6.38.8 info: Using bootloader at address 0x80000000 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 2629149747000 because m5_exit instruction encountered +Exiting @ tick 2603634694000 because m5_exit instruction encountered diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt index 50e9a8afa..fcb402e49 100644 --- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt +++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt @@ -1,68 +1,80 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 2.603636 # Number of seconds simulated -sim_ticks 2603636076000 # Number of ticks simulated -final_tick 2603636076000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 2.603635 # Number of seconds simulated +sim_ticks 2603634694000 # Number of ticks simulated +final_tick 2603634694000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 264193 # Simulator instruction rate (inst/s) -host_op_rate 336182 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11426847777 # Simulator tick rate (ticks/s) -host_mem_usage 395692 # Number of bytes of host memory used -host_seconds 227.85 # Real time elapsed on the host -sim_insts 60197128 # Number of instructions simulated -sim_ops 76599899 # Number of ops (including micro ops) simulated +host_inst_rate 156094 # Simulator instruction rate (inst/s) +host_op_rate 198627 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 6751306864 # Simulator tick rate (ticks/s) +host_mem_usage 397752 # Number of bytes of host memory used +host_seconds 385.65 # Real time elapsed on the host +sim_insts 60197457 # Number of instructions simulated +sim_ops 76600355 # Number of ops (including micro ops) simulated +system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory +system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory +system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory +system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory +system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory +system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) +system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) +system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory system.physmem.bytes_read::cpu.itb.walker 192 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 9050128 # Number of bytes read from this memory -system.physmem.bytes_read::total 132438832 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory -system.physmem.bytes_written::writebacks 3677504 # Number of bytes written to this memory +system.physmem.bytes_read::cpu.inst 705120 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 9050192 # Number of bytes read from this memory +system.physmem.bytes_read::total 132439216 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 705120 # Number of instructions bytes read from this memory +system.physmem.bytes_written::writebacks 3677632 # Number of bytes written to this memory system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory -system.physmem.bytes_written::total 6693576 # Number of bytes written to this memory +system.physmem.bytes_written::total 6693704 # Number of bytes written to this memory system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.itb.walker 3 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 141442 # Number of read requests responded to by this memory -system.physmem.num_reads::total 15494089 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 57461 # Number of write requests responded to by this memory +system.physmem.num_reads::cpu.inst 17220 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 141443 # Number of read requests responded to by this memory +system.physmem.num_reads::total 15494095 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 57463 # Number of write requests responded to by this memory system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory -system.physmem.num_writes::total 811479 # Number of write requests responded to by this memory -system.physmem.bw_read::realview.clcd 47120023 # Total read bandwidth from this memory (bytes/s) +system.physmem.num_writes::total 811481 # Number of write requests responded to by this memory +system.physmem.bw_read::realview.clcd 47120048 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.dtb.walker 123 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::cpu.itb.walker 74 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.inst 270698 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 3475957 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 50866875 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 270698 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 270698 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 1412449 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 270821 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 3475984 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 50867050 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 270821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 270821 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 1412499 # Write bandwidth from this memory (bytes/s) system.physmem.bw_write::cpu.data 1158408 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 2570857 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 1412449 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::realview.clcd 47120023 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::total 2570908 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 1412499 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::realview.clcd 47120048 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.dtb.walker 123 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.itb.walker 74 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 270698 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 4634365 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 53437732 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 15494089 # Total number of read requests seen -system.physmem.writeReqs 811479 # Total number of write requests seen -system.physmem.cpureqs 213984 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 991621696 # Total number of bytes read from memory -system.physmem.bytesWritten 51934656 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 132438832 # bytesRead derated as per pkt->getSize() -system.physmem.bytesConsumedWr 6693576 # bytesWritten derated as per pkt->getSize() +system.physmem.bw_total::cpu.inst 270821 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 4634392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 53437957 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 15494095 # Total number of read requests seen +system.physmem.writeReqs 811481 # Total number of write requests seen +system.physmem.cpureqs 213992 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 991622080 # Total number of bytes read from memory +system.physmem.bytesWritten 51934784 # Total number of bytes written to memory +system.physmem.bytesConsumedRd 132439216 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedWr 6693704 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 336 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 4510 # Reqs where no action is needed system.physmem.perBankRdReqs::0 968203 # Track reads on a per bank basis system.physmem.perBankRdReqs::1 968434 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 967969 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 967930 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 967593 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 967596 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 967540 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 967550 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 967729 # Track reads on a per bank basis @@ -73,12 +85,12 @@ system.physmem.perBankRdReqs::11 968056 # Tr system.physmem.perBankRdReqs::12 968172 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 968177 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 968121 # Track reads on a per bank basis -system.physmem.perBankRdReqs::15 967789 # Track reads on a per bank basis +system.physmem.perBankRdReqs::15 967792 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 50184 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 50353 # Track writes on a per bank basis system.physmem.perBankWrReqs::2 49939 # Track writes on a per bank basis system.physmem.perBankWrReqs::3 49917 # Track writes on a per bank basis -system.physmem.perBankWrReqs::4 50620 # Track writes on a per bank basis +system.physmem.perBankWrReqs::4 50621 # Track writes on a per bank basis system.physmem.perBankWrReqs::5 50586 # Track writes on a per bank basis system.physmem.perBankWrReqs::6 50545 # Track writes on a per bank basis system.physmem.perBankWrReqs::7 50763 # Track writes on a per bank basis @@ -89,17 +101,17 @@ system.physmem.perBankWrReqs::11 51005 # Tr system.physmem.perBankWrReqs::12 51208 # Track writes on a per bank basis system.physmem.perBankWrReqs::13 51196 # Track writes on a per bank basis system.physmem.perBankWrReqs::14 51260 # Track writes on a per bank basis -system.physmem.perBankWrReqs::15 51037 # Track writes on a per bank basis +system.physmem.perBankWrReqs::15 51038 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 2603631716000 # Total gap between requests +system.physmem.totGap 2603630334000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 6652 # Categorize read packet sizes system.physmem.readPktSize::3 15335424 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 152013 # Categorize read packet sizes +system.physmem.readPktSize::6 152019 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -108,7 +120,7 @@ system.physmem.writePktSize::2 754018 # ca system.physmem.writePktSize::3 0 # categorize write packet sizes system.physmem.writePktSize::4 0 # categorize write packet sizes system.physmem.writePktSize::5 0 # categorize write packet sizes -system.physmem.writePktSize::6 57461 # categorize write packet sizes +system.physmem.writePktSize::6 57463 # categorize write packet sizes system.physmem.writePktSize::7 0 # categorize write packet sizes system.physmem.writePktSize::8 0 # categorize write packet sizes system.physmem.neitherpktsize::0 0 # categorize neither packet sizes @@ -120,23 +132,23 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 4510 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 15419657 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 56436 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 11795 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2249 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1058 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 797 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 575 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 386 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 213 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 132 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::10 117 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::11 105 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::12 85 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::13 73 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::14 46 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::15 23 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::16 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 1119077 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 964362 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 964947 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 1001106 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2807161 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 2816119 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 5525790 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 40935 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 32313 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 31944 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::10 31968 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::11 59731 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::12 31858 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::13 59202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::14 3664 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::15 3479 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::16 103 # What read queue length does an incoming req see system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see @@ -153,10 +165,10 @@ system.physmem.rdQLenPdf::29 0 # Wh system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see -system.physmem.wrQLenPdf::0 35279 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::1 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::2 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::3 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::0 35270 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::1 35278 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::2 35279 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::3 35279 # What write queue length does an incoming req see system.physmem.wrQLenPdf::4 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::5 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::6 35282 # What write queue length does an incoming req see @@ -169,56 +181,44 @@ system.physmem.wrQLenPdf::12 35282 # Wh system.physmem.wrQLenPdf::13 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::14 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::15 35282 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::16 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::17 35281 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::16 35282 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::17 35282 # What write queue length does an incoming req see system.physmem.wrQLenPdf::18 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::19 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::20 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::21 35281 # What write queue length does an incoming req see system.physmem.wrQLenPdf::22 35281 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::23 3 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::24 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see -system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::23 12 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::24 4 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::25 3 # What write queue length does an incoming req see +system.physmem.wrQLenPdf::26 3 # What write queue length does an incoming req see system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3750171610 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 281910621610 # Sum of mem lat for all requests -system.physmem.totBusLat 61975012000 # Total cycles spent in databus access -system.physmem.totBankLat 216185438000 # Total cycles spent in bank access -system.physmem.avgQLat 242.04 # Average queueing delay per request -system.physmem.avgBankLat 13953.07 # Average bank access latency per request +system.physmem.totQLat 288491080973 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 367329340973 # Sum of mem lat for all requests +system.physmem.totBusLat 61975036000 # Total cycles spent in databus access +system.physmem.totBankLat 16863224000 # Total cycles spent in bank access +system.physmem.avgQLat 18619.82 # Average queueing delay per request +system.physmem.avgBankLat 1088.39 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 18195.12 # Average memory access latency +system.physmem.avgMemAccLat 23708.21 # Average memory access latency system.physmem.avgRdBW 380.86 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 19.95 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 50.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.51 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.11 # Average read queue length over time -system.physmem.avgWrQLen 12.38 # Average write queue length over time -system.physmem.readRowHits 15449450 # Number of row buffer hits during reads -system.physmem.writeRowHits 784611 # Number of row buffer hits during writes -system.physmem.readRowHitRate 99.71 # Row buffer hit rate for reads -system.physmem.writeRowHitRate 96.69 # Row buffer hit rate for writes -system.physmem.avgGap 159677.46 # Average gap between requests -system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory -system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory -system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory -system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory -system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory -system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s) -system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s) -system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s) +system.physmem.avgRdQLen 0.14 # Average read queue length over time +system.physmem.avgWrQLen 12.40 # Average write queue length over time +system.physmem.readRowHits 15451886 # Number of row buffer hits during reads +system.physmem.writeRowHits 785061 # Number of row buffer hits during writes +system.physmem.readRowHitRate 99.73 # Row buffer hit rate for reads +system.physmem.writeRowHitRate 96.74 # Row buffer hit rate for writes +system.physmem.avgGap 159677.30 # Average gap between requests system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD). system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD). @@ -227,9 +227,9 @@ system.cf0.dma_write_bytes 0 # Nu system.cf0.dma_write_txs 0 # Number of DMA write transactions. system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses -system.cpu.dtb.read_hits 14995523 # DTB read hits -system.cpu.dtb.read_misses 7332 # DTB read misses -system.cpu.dtb.write_hits 11230789 # DTB write hits +system.cpu.dtb.read_hits 14995645 # DTB read hits +system.cpu.dtb.read_misses 7331 # DTB read misses +system.cpu.dtb.write_hits 11230857 # DTB write hits system.cpu.dtb.write_misses 2203 # DTB write misses system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA @@ -240,13 +240,13 @@ system.cpu.dtb.align_faults 0 # Nu system.cpu.dtb.prefetch_faults 184 # Number of TLB faults due to prefetch system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions -system.cpu.dtb.read_accesses 15002855 # DTB read accesses -system.cpu.dtb.write_accesses 11232992 # DTB write accesses +system.cpu.dtb.read_accesses 15002976 # DTB read accesses +system.cpu.dtb.write_accesses 11233060 # DTB write accesses system.cpu.dtb.inst_accesses 0 # ITB inst accesses -system.cpu.dtb.hits 26226312 # DTB hits -system.cpu.dtb.misses 9535 # DTB misses -system.cpu.dtb.accesses 26235847 # DTB accesses -system.cpu.itb.inst_hits 61491068 # ITB inst hits +system.cpu.dtb.hits 26226502 # DTB hits +system.cpu.dtb.misses 9534 # DTB misses +system.cpu.dtb.accesses 26236036 # DTB accesses +system.cpu.itb.inst_hits 61491397 # ITB inst hits system.cpu.itb.inst_misses 4471 # ITB inst misses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses @@ -263,79 +263,79 @@ system.cpu.itb.domain_faults 0 # Nu system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions system.cpu.itb.read_accesses 0 # DTB read accesses system.cpu.itb.write_accesses 0 # DTB write accesses -system.cpu.itb.inst_accesses 61495539 # ITB inst accesses -system.cpu.itb.hits 61491068 # DTB hits +system.cpu.itb.inst_accesses 61495868 # ITB inst accesses +system.cpu.itb.hits 61491397 # DTB hits system.cpu.itb.misses 4471 # DTB misses -system.cpu.itb.accesses 61495539 # DTB accesses -system.cpu.numCycles 5207272152 # number of cpu cycles simulated +system.cpu.itb.accesses 61495868 # DTB accesses +system.cpu.numCycles 5207269388 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 60197128 # Number of instructions committed -system.cpu.committedOps 76599899 # Number of ops (including micro ops) committed -system.cpu.num_int_alu_accesses 68867725 # Number of integer alu accesses +system.cpu.committedInsts 60197457 # Number of instructions committed +system.cpu.committedOps 76600355 # Number of ops (including micro ops) committed +system.cpu.num_int_alu_accesses 68868122 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses -system.cpu.num_func_calls 2139710 # number of times a function call or return occured -system.cpu.num_conditional_control_insts 7947746 # number of instructions that are conditional controls -system.cpu.num_int_insts 68867725 # number of integer instructions +system.cpu.num_func_calls 2139722 # number of times a function call or return occured +system.cpu.num_conditional_control_insts 7947784 # number of instructions that are conditional controls +system.cpu.num_int_insts 68868122 # number of integer instructions system.cpu.num_fp_insts 10269 # number of float instructions -system.cpu.num_int_register_reads 394752708 # number of times the integer registers were read -system.cpu.num_int_register_writes 74175592 # number of times the integer registers were written +system.cpu.num_int_register_reads 394755172 # number of times the integer registers were read +system.cpu.num_int_register_writes 74176009 # number of times the integer registers were written system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written -system.cpu.num_mem_refs 27393681 # number of memory refs -system.cpu.num_load_insts 15659530 # Number of load instructions -system.cpu.num_store_insts 11734151 # Number of store instructions -system.cpu.num_idle_cycles 4579080256.576241 # Number of idle cycles -system.cpu.num_busy_cycles 628191895.423759 # Number of busy cycles -system.cpu.not_idle_fraction 0.120637 # Percentage of non-idle cycles -system.cpu.idle_fraction 0.879363 # Percentage of idle cycles +system.cpu.num_mem_refs 27393871 # number of memory refs +system.cpu.num_load_insts 15659652 # Number of load instructions +system.cpu.num_store_insts 11734219 # Number of store instructions +system.cpu.num_idle_cycles 4579130410.576241 # Number of idle cycles +system.cpu.num_busy_cycles 628138977.423759 # Number of busy cycles +system.cpu.not_idle_fraction 0.120627 # Percentage of non-idle cycles +system.cpu.idle_fraction 0.879373 # Percentage of idle cycles system.cpu.kern.inst.arm 0 # number of arm instructions executed system.cpu.kern.inst.quiesce 83000 # number of quiesce instructions executed -system.cpu.icache.replacements 855500 # number of replacements -system.cpu.icache.tagsinuse 510.984783 # Cycle average of tags in use -system.cpu.icache.total_refs 60635056 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 856012 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 70.834353 # Average number of references to valid blocks. +system.cpu.icache.replacements 855485 # number of replacements +system.cpu.icache.tagsinuse 510.984782 # Cycle average of tags in use +system.cpu.icache.total_refs 60635400 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 855997 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 70.835996 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 18657050000 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 510.984783 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 510.984782 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.998017 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.998017 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 60635056 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 60635056 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 60635056 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 60635056 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 60635056 # number of overall hits -system.cpu.icache.overall_hits::total 60635056 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 856012 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 856012 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 856012 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 856012 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 856012 # number of overall misses -system.cpu.icache.overall_misses::total 856012 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11543876000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11543876000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11543876000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11543876000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11543876000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11543876000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 61491068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 61491068 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 61491068 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 61491068 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 61491068 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 61491068 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_hits::cpu.inst 60635400 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 60635400 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 60635400 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 60635400 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 60635400 # number of overall hits +system.cpu.icache.overall_hits::total 60635400 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 855997 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 855997 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 855997 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 855997 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 855997 # number of overall misses +system.cpu.icache.overall_misses::total 855997 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11539684000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11539684000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11539684000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11539684000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11539684000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11539684000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 61491397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 61491397 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 61491397 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 61491397 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 61491397 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 61491397 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013921 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.013921 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.013921 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.013921 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.013921 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.013921 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13485.647397 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 13485.647397 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 13485.647397 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 13485.647397 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 13485.647397 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13480.986499 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 13480.986499 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 13480.986499 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 13480.986499 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 13480.986499 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -344,18 +344,18 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856012 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 856012 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 856012 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 856012 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 856012 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 856012 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9831852000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9831852000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9831852000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9831852000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9831852000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9831852000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 855997 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 855997 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 855997 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 855997 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 855997 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 855997 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9827690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9827690000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9827690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9827690000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9827690000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9827690000 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 288141500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 288141500 # number of ReadReq MSHR uncacheable cycles system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 288141500 # number of overall MSHR uncacheable cycles @@ -366,288 +366,152 @@ system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013921 system.cpu.icache.demand_mshr_miss_rate::total 0.013921 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013921 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.013921 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11485.647397 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11485.647397 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11485.647397 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 11485.647397 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11480.986499 # average ReadReq mshr miss latency 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overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37229.212939 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33142.491338 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33424.895128 # average overall mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency @@ -751,6 +615,142 @@ system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency 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WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 32117.582132 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13575.425364 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13575.425364 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 21391.364480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 21391.364480 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 21391.364480 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 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MSHR misses +system.cpu.dcache.LoadLockedReq_mshr_misses::total 11402 # number of LoadLockedReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 619291 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 619291 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 619291 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 619291 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4464142000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4464142000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7544755500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 7544755500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 131983000 # number of LoadLockedReq MSHR miss cycles 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uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 200793158500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.overall_mshr_uncacheable_latency::total 200793158500 # number of overall MSHR uncacheable cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027188 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027188 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024503 # mshr miss rate for WriteReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046035 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046035 # mshr miss rate for LoadLockedReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026034 # mshr miss rate for demand accesses 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+system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.iocache.replacements 0 # number of replacements system.iocache.tagsinuse 0 # Cycle average of tags in use system.iocache.total_refs 0 # Total number of references to valid blocks. @@ -765,10 +765,10 @@ system.iocache.avg_blocked_cycles::no_mshrs nan # system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.iocache.fast_writes 0 # number of fast writes performed system.iocache.cache_copies 0 # number of cache copies performed -system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of ReadReq MSHR uncacheable cycles -system.iocache.ReadReq_mshr_uncacheable_latency::total 1052665426345 # number of ReadReq MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1052665426345 # number of overall MSHR uncacheable cycles -system.iocache.overall_mshr_uncacheable_latency::total 1052665426345 # number of overall MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of ReadReq MSHR uncacheable cycles +system.iocache.ReadReq_mshr_uncacheable_latency::total 1130504893187 # number of ReadReq MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1130504893187 # number of overall MSHR uncacheable cycles +system.iocache.overall_mshr_uncacheable_latency::total 1130504893187 # number of overall MSHR uncacheable cycles system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini index ab2a707ae..e13d309d9 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini @@ -1,17 +1,19 @@ [drivesys] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami -boot_cpu_frequency=1 +boot_cpu_frequency=250 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/gem5/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/gem5/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges=0:134217727 memories=drivesys.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal -readfile=/tmp/gem5.ali/configs/boot/netperf-server.rcS +pal=/gem5/dist/binaries/ts_osfpal +readfile=/gem5/configs/boot/netperf-server.rcS symbolfile= system_rev=1024 system_type=34 @@ -26,22 +28,20 @@ system_port=drivesys.membus.slave[0] [drivesys.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=drivesys.iobus.slave[0] slave=drivesys.membus.master[0] [drivesys.cpu] type=AtomicSimpleCPU -children=dtb interrupts itb tracer +children=dtb interrupts isa itb tracer checker=Null -clock=1 +clock=250 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -50,17 +50,18 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=drivesys.cpu.interrupts +isa=drivesys.cpu.isa itb=drivesys.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=drivesys tracer=drivesys.cpu.tracer width=1 @@ -75,6 +76,9 @@ size=64 [drivesys.cpu.interrupts] type=AlphaInterrupts +[drivesys.cpu.isa] +type=AlphaISA + [drivesys.cpu.itb] type=AlphaTLB size=48 @@ -99,7 +103,7 @@ table_size=65536 [drivesys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/gem5/dist/disks/linux-latest.img read_only=true [drivesys.disk2] @@ -119,7 +123,7 @@ table_size=65536 [drivesys.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/gem5/dist/disks/linux-bigswap2.img read_only=true [drivesys.intrctrl] @@ -128,12 +132,11 @@ sys=drivesys [drivesys.iobridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 -ranges=0:8589934592 +ranges=0:134217727 req_size=16 resp_size=16 -write_ack=false master=drivesys.membus.slave[3] slave=drivesys.iobus.master[29] @@ -143,7 +146,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=drivesys.tsunami.pciconfig.pio master=drivesys.tsunami.cchip.pio drivesys.tsunami.pchip.pio drivesys.tsunami.fake_sm_chip.pio drivesys.tsunami.fake_uart1.pio drivesys.tsunami.fake_uart2.pio drivesys.tsunami.fake_uart3.pio drivesys.tsunami.fake_uart4.pio drivesys.tsunami.fake_ppc.pio drivesys.tsunami.fake_OROM.pio drivesys.tsunami.fake_pnp_addr.pio drivesys.tsunami.fake_pnp_write.pio drivesys.tsunami.fake_pnp_read0.pio drivesys.tsunami.fake_pnp_read1.pio drivesys.tsunami.fake_pnp_read2.pio drivesys.tsunami.fake_pnp_read3.pio drivesys.tsunami.fake_pnp_read4.pio drivesys.tsunami.fake_pnp_read5.pio drivesys.tsunami.fake_pnp_read6.pio drivesys.tsunami.fake_pnp_read7.pio drivesys.tsunami.fake_ata0.pio drivesys.tsunami.fake_ata1.pio drivesys.tsunami.fb.pio drivesys.tsunami.io.pio drivesys.tsunami.uart.pio drivesys.tsunami.backdoor.pio drivesys.tsunami.ide.pio drivesys.tsunami.ide.config drivesys.tsunami.ethernet.pio drivesys.tsunami.ethernet.config drivesys.iobridge.slave slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.dma @@ -155,16 +158,17 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=drivesys.membus.badaddr_responder.pio -master=drivesys.bridge.slave drivesys.physmem.port[0] +master=drivesys.bridge.slave drivesys.physmem.port slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port drivesys.iobridge.master [drivesys.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -177,14 +181,28 @@ warn_access= pio=drivesys.membus.default [drivesys.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=drivesys.membus.master[1] @@ -196,7 +214,7 @@ system=drivesys [drivesys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/gem5/dist/disks/linux-latest.img read_only=true [drivesys.terminal] @@ -214,10 +232,11 @@ system=drivesys [drivesys.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=drivesys.cpu disk=drivesys.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=drivesys.tsunami system=drivesys terminal=drivesys.terminal @@ -225,8 +244,9 @@ pio=drivesys.iobus.master[24] [drivesys.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=drivesys tsunami=drivesys.tsunami pio=drivesys.iobus.master[0] @@ -271,7 +291,7 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 -clock=0 +clock=2000 config_latency=20000 dma_data_free=false dma_desc_free=false @@ -282,12 +302,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:02 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=drivesys.tsunami rss=false rx_delay=1000000 @@ -305,9 +323,10 @@ pio=drivesys.iobus.master[27] [drivesys.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -321,9 +340,10 @@ pio=drivesys.iobus.master[8] [drivesys.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -337,9 +357,10 @@ pio=drivesys.iobus.master[19] [drivesys.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -353,9 +374,10 @@ pio=drivesys.iobus.master[20] [drivesys.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -369,9 +391,10 @@ pio=drivesys.iobus.master[9] [drivesys.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -385,9 +408,10 @@ pio=drivesys.iobus.master[11] [drivesys.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -401,9 +425,10 @@ pio=drivesys.iobus.master[12] [drivesys.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -417,9 +442,10 @@ pio=drivesys.iobus.master[13] [drivesys.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -433,9 +459,10 @@ pio=drivesys.iobus.master[14] [drivesys.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -449,9 +476,10 @@ pio=drivesys.iobus.master[15] [drivesys.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -465,9 +493,10 @@ pio=drivesys.iobus.master[16] [drivesys.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -481,9 +510,10 @@ pio=drivesys.iobus.master[17] [drivesys.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -497,9 +527,10 @@ pio=drivesys.iobus.master[18] [drivesys.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -513,9 +544,10 @@ pio=drivesys.iobus.master[10] [drivesys.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -529,9 +561,10 @@ pio=drivesys.iobus.master[7] [drivesys.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -545,9 +578,10 @@ pio=drivesys.iobus.master[2] [drivesys.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -561,9 +595,10 @@ pio=drivesys.iobus.master[3] [drivesys.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -577,9 +612,10 @@ pio=drivesys.iobus.master[4] [drivesys.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -593,9 +629,10 @@ pio=drivesys.iobus.master[5] [drivesys.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -609,9 +646,10 @@ pio=drivesys.iobus.master[6] [drivesys.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=drivesys pio=drivesys.iobus.master[21] @@ -655,16 +693,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=drivesys.disk0 drivesys.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=drivesys.tsunami system=drivesys config=drivesys.iobus.master[26] @@ -673,9 +710,10 @@ pio=drivesys.iobus.master[25] [drivesys.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=drivesys time=Thu Jan 1 00:00:00 2009 tsunami=drivesys.tsunami @@ -684,8 +722,9 @@ pio=drivesys.iobus.master[22] [drivesys.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=drivesys tsunami=drivesys.tsunami pio=drivesys.iobus.master[1] @@ -693,7 +732,8 @@ pio=drivesys.iobus.master[1] [drivesys.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=drivesys.tsunami size=16777216 system=drivesys @@ -701,8 +741,9 @@ pio=drivesys.iobus.default [drivesys.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=drivesys.tsunami system=drivesys terminal=drivesys.terminal @@ -733,17 +774,19 @@ time_sync_spin_threshold=100000000 [testsys] type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami -boot_cpu_frequency=1 +boot_cpu_frequency=500 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +clock=1000 +console=/gem5/dist/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/gem5/dist/binaries/vmlinux load_addr_mask=1099511627775 mem_mode=atomic +mem_ranges=0:134217727 memories=testsys.physmem num_work_ids=16 -pal=/dist/m5/system/binaries/ts_osfpal -readfile=/tmp/gem5.ali/configs/boot/netperf-stream-client.rcS +pal=/gem5/dist/binaries/ts_osfpal +readfile=/gem5/configs/boot/netperf-stream-client.rcS symbolfile= system_rev=1024 system_type=34 @@ -758,22 +801,20 @@ system_port=testsys.membus.slave[0] [testsys.bridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 ranges=8796093022208:18446744073709551615 req_size=16 resp_size=16 -write_ack=false master=testsys.iobus.slave[0] slave=testsys.membus.master[0] [testsys.cpu] type=AtomicSimpleCPU -children=dtb interrupts itb tracer +children=dtb interrupts isa itb tracer checker=Null -clock=1 +clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -782,17 +823,18 @@ fastmem=false function_trace=false function_trace_start=0 interrupts=testsys.cpu.interrupts +isa=testsys.cpu.isa itb=testsys.cpu.itb max_insts_all_threads=0 max_insts_any_thread=0 max_loads_all_threads=0 max_loads_any_thread=0 numThreads=1 -phase=0 profile=0 progress_interval=0 simulate_data_stalls=false simulate_inst_stalls=false +switched_out=false system=testsys tracer=testsys.cpu.tracer width=1 @@ -807,6 +849,9 @@ size=64 [testsys.cpu.interrupts] type=AlphaInterrupts +[testsys.cpu.isa] +type=AlphaISA + [testsys.cpu.itb] type=AlphaTLB size=48 @@ -831,7 +876,7 @@ table_size=65536 [testsys.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/gem5/dist/disks/linux-latest.img read_only=true [testsys.disk2] @@ -851,7 +896,7 @@ table_size=65536 [testsys.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/gem5/dist/disks/linux-bigswap2.img read_only=true [testsys.intrctrl] @@ -860,12 +905,11 @@ sys=testsys [testsys.iobridge] type=Bridge +clock=1000 delay=50000 -nack_delay=4000 -ranges=0:8589934592 +ranges=0:134217727 req_size=16 resp_size=16 -write_ack=false master=testsys.membus.slave[3] slave=testsys.iobus.master[29] @@ -875,7 +919,7 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=true -width=64 +width=8 default=testsys.tsunami.pciconfig.pio master=testsys.tsunami.cchip.pio testsys.tsunami.pchip.pio testsys.tsunami.fake_sm_chip.pio testsys.tsunami.fake_uart1.pio testsys.tsunami.fake_uart2.pio testsys.tsunami.fake_uart3.pio testsys.tsunami.fake_uart4.pio testsys.tsunami.fake_ppc.pio testsys.tsunami.fake_OROM.pio testsys.tsunami.fake_pnp_addr.pio testsys.tsunami.fake_pnp_write.pio testsys.tsunami.fake_pnp_read0.pio testsys.tsunami.fake_pnp_read1.pio testsys.tsunami.fake_pnp_read2.pio testsys.tsunami.fake_pnp_read3.pio testsys.tsunami.fake_pnp_read4.pio testsys.tsunami.fake_pnp_read5.pio testsys.tsunami.fake_pnp_read6.pio testsys.tsunami.fake_pnp_read7.pio testsys.tsunami.fake_ata0.pio testsys.tsunami.fake_ata1.pio testsys.tsunami.fb.pio testsys.tsunami.io.pio testsys.tsunami.uart.pio testsys.tsunami.backdoor.pio testsys.tsunami.ide.pio testsys.tsunami.ide.config testsys.tsunami.ethernet.pio testsys.tsunami.ethernet.config testsys.iobridge.slave slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma @@ -887,16 +931,17 @@ block_size=64 clock=1000 header_cycles=1 use_default_range=false -width=64 +width=8 default=testsys.membus.badaddr_responder.pio -master=testsys.bridge.slave testsys.physmem.port[0] +master=testsys.bridge.slave testsys.physmem.port slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsys.iobridge.master [testsys.membus.badaddr_responder] type=IsaFake +clock=1000 fake_mem=false pio_addr=0 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=true ret_data16=65535 @@ -909,14 +954,28 @@ warn_access= pio=testsys.membus.default [testsys.physmem] -type=SimpleMemory +type=SimpleDRAM +addr_mapping=openmap +banks_per_rank=8 +clock=1000 conf_table_reported=false -file= in_addr_map=true -latency=30000 -latency_var=0 +lines_per_rowbuffer=64 +mem_sched_policy=fcfs null=false +page_policy=open range=0:134217727 +ranks_per_channel=2 +read_buffer_size=32 +tBURST=4000 +tCL=14000 +tRCD=14000 +tREFI=7800000 +tRFC=300000 +tRP=14000 +tWTR=1000 +write_buffer_size=32 +write_thresh_perc=70 zero=false port=testsys.membus.master[1] @@ -928,7 +987,7 @@ system=testsys [testsys.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/gem5/dist/disks/linux-latest.img read_only=true [testsys.terminal] @@ -946,10 +1005,11 @@ system=testsys [testsys.tsunami.backdoor] type=AlphaBackdoor +clock=1000 cpu=testsys.cpu disk=testsys.simple_disk pio_addr=8804682956800 -pio_latency=1000 +pio_latency=100000 platform=testsys.tsunami system=testsys terminal=testsys.terminal @@ -957,8 +1017,9 @@ pio=testsys.iobus.master[24] [testsys.tsunami.cchip] type=TsunamiCChip +clock=1000 pio_addr=8803072344064 -pio_latency=1000 +pio_latency=100000 system=testsys tsunami=testsys.tsunami pio=testsys.iobus.master[0] @@ -1003,7 +1064,7 @@ SubClassCode=0 SubsystemID=0 SubsystemVendorID=0 VendorID=4107 -clock=0 +clock=2000 config_latency=20000 dma_data_free=false dma_desc_free=false @@ -1014,12 +1075,10 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=10000000 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=1 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=testsys.tsunami rss=false rx_delay=1000000 @@ -1037,9 +1096,10 @@ pio=testsys.iobus.master[27] [testsys.tsunami.fake_OROM] type=IsaFake +clock=1000 fake_mem=false pio_addr=8796093677568 -pio_latency=1000 +pio_latency=100000 pio_size=393216 ret_bad_addr=false ret_data16=65535 @@ -1053,9 +1113,10 @@ pio=testsys.iobus.master[8] [testsys.tsunami.fake_ata0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848432 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1069,9 +1130,10 @@ pio=testsys.iobus.master[19] [testsys.tsunami.fake_ata1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848304 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1085,9 +1147,10 @@ pio=testsys.iobus.master[20] [testsys.tsunami.fake_pnp_addr] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848569 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1101,9 +1164,10 @@ pio=testsys.iobus.master[9] [testsys.tsunami.fake_pnp_read0] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848451 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1117,9 +1181,10 @@ pio=testsys.iobus.master[11] [testsys.tsunami.fake_pnp_read1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848515 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1133,9 +1198,10 @@ pio=testsys.iobus.master[12] [testsys.tsunami.fake_pnp_read2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848579 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1149,9 +1215,10 @@ pio=testsys.iobus.master[13] [testsys.tsunami.fake_pnp_read3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848643 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1165,9 +1232,10 @@ pio=testsys.iobus.master[14] [testsys.tsunami.fake_pnp_read4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848707 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1181,9 +1249,10 @@ pio=testsys.iobus.master[15] [testsys.tsunami.fake_pnp_read5] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848771 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1197,9 +1266,10 @@ pio=testsys.iobus.master[16] [testsys.tsunami.fake_pnp_read6] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848835 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1213,9 +1283,10 @@ pio=testsys.iobus.master[17] [testsys.tsunami.fake_pnp_read7] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848899 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1229,9 +1300,10 @@ pio=testsys.iobus.master[18] [testsys.tsunami.fake_pnp_write] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615850617 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1245,9 +1317,10 @@ pio=testsys.iobus.master[10] [testsys.tsunami.fake_ppc] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848891 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1261,9 +1334,10 @@ pio=testsys.iobus.master[7] [testsys.tsunami.fake_sm_chip] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848816 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1277,9 +1351,10 @@ pio=testsys.iobus.master[2] [testsys.tsunami.fake_uart1] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848696 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1293,9 +1368,10 @@ pio=testsys.iobus.master[3] [testsys.tsunami.fake_uart2] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848936 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1309,9 +1385,10 @@ pio=testsys.iobus.master[4] [testsys.tsunami.fake_uart3] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848680 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1325,9 +1402,10 @@ pio=testsys.iobus.master[5] [testsys.tsunami.fake_uart4] type=IsaFake +clock=1000 fake_mem=false pio_addr=8804615848944 -pio_latency=1000 +pio_latency=100000 pio_size=8 ret_bad_addr=false ret_data16=65535 @@ -1341,9 +1419,10 @@ pio=testsys.iobus.master[6] [testsys.tsunami.fb] type=BadDevice +clock=1000 devicename=FrameBuffer pio_addr=8804615848912 -pio_latency=1000 +pio_latency=100000 system=testsys pio=testsys.iobus.master[21] @@ -1387,16 +1466,15 @@ SubClassCode=1 SubsystemID=0 SubsystemVendorID=0 VendorID=32902 +clock=1000 config_latency=20000 ctrl_offset=0 disks=testsys.disk0 testsys.disk2 io_shift=0 -max_backoff_delay=10000000 -min_backoff_delay=4000 pci_bus=0 pci_dev=0 pci_func=0 -pio_latency=1000 +pio_latency=30000 platform=testsys.tsunami system=testsys config=testsys.iobus.master[26] @@ -1405,9 +1483,10 @@ pio=testsys.iobus.master[25] [testsys.tsunami.io] type=TsunamiIO +clock=1000 frequency=976562500 pio_addr=8804615847936 -pio_latency=1000 +pio_latency=100000 system=testsys time=Thu Jan 1 00:00:00 2009 tsunami=testsys.tsunami @@ -1416,8 +1495,9 @@ pio=testsys.iobus.master[22] [testsys.tsunami.pchip] type=TsunamiPChip +clock=1000 pio_addr=8802535473152 -pio_latency=1000 +pio_latency=100000 system=testsys tsunami=testsys.tsunami pio=testsys.iobus.master[1] @@ -1425,7 +1505,8 @@ pio=testsys.iobus.master[1] [testsys.tsunami.pciconfig] type=PciConfigAll bus=0 -pio_latency=1 +clock=1000 +pio_latency=30000 platform=testsys.tsunami size=16777216 system=testsys @@ -1433,8 +1514,9 @@ pio=testsys.iobus.default [testsys.tsunami.uart] type=Uart8250 +clock=1000 pio_addr=8804615848952 -pio_latency=1000 +pio_latency=100000 platform=testsys.tsunami system=testsys terminal=testsys.terminal diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout index b25f011d8..6ea7e55c1 100755 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout @@ -1,14 +1,14 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Jun 4 2012 11:50:11 -gem5 started Jun 4 2012 14:20:01 -gem5 executing on zizzer +gem5 compiled Jan 4 2013 21:09:21 +gem5 started Jan 4 2013 21:17:35 +gem5 executing on u200540 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic Global frequency set at 1000000000000 ticks per second -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /gem5/dist/binaries/vmlinux 0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 -info: kernel located at: /dist/m5/system/binaries/vmlinux +info: kernel located at: /gem5/dist/binaries/vmlinux 0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009 info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 4300236804024 because checkpoint +Exiting @ tick 4321612280500 because checkpoint diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt index 812930542..ae987c639 100644 --- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt +++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt @@ -1,45 +1,45 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.200392 # Number of seconds simulated -sim_ticks 200392337000 # Number of ticks simulated -final_tick 4320161528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.200409 # Number of seconds simulated +sim_ticks 200409284500 # Number of ticks simulated +final_tick 4321205328500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90899186 # Simulator instruction rate (inst/s) -host_op_rate 90898450 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 67078334403 # Simulator tick rate (ticks/s) -host_mem_usage 463260 # Number of bytes of host memory used -host_seconds 2.99 # Real time elapsed on the host -sim_insts 271551386 # Number of instructions simulated -sim_ops 271551386 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 13230208 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 4514888 # Number of bytes read from this memory -testsys.physmem.bytes_read::tsunami.ethernet 1464 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 17746560 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 13230208 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 13230208 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 3697656 # Number of bytes written to this memory +host_inst_rate 7091560 # Simulator instruction rate (inst/s) +host_op_rate 7091556 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2715554324 # Simulator tick rate (ticks/s) +host_mem_usage 465632 # Number of bytes of host memory used +host_seconds 73.80 # Real time elapsed on the host +sim_insts 523360203 # Number of instructions simulated +sim_ops 523360203 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 80888044 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 27771396 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 50103096 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 158762536 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 80888044 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 80888044 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 16575224 # Number of bytes written to this memory testsys.physmem.bytes_written::tsunami.ethernet 902 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 3698558 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 3307552 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 615769 # Number of read requests responded to by this memory -testsys.physmem.num_reads::tsunami.ethernet 43 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 3923364 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 478513 # Number of write requests responded to by this memory +testsys.physmem.bytes_written::total 16576126 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 20222011 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 3834989 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 2087611 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 26144611 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 2254078 # Number of write requests responded to by this memory testsys.physmem.num_writes::tsunami.ethernet 31 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 478544 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 66021527 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 22530243 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::tsunami.ethernet 7306 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 88559075 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 66021527 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 66021527 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 18452083 # Write bandwidth from this memory (bytes/s) +testsys.physmem.num_writes::total 2254109 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 403614255 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 138573400 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 250003866 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 792191521 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 403614255 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 403614255 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 82706867 # Write bandwidth from this memory (bytes/s) testsys.physmem.bw_write::tsunami.ethernet 4501 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 18456584 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 66021527 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 40982326 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::tsunami.ethernet 11807 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 107015659 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_write::total 82711368 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 403614255 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 221280267 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 250008367 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 874902889 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.readReqs 0 # Total number of read requests seen testsys.physmem.writeReqs 0 # Total number of write requests seen testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -214,22 +214,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 611887 # DTB read hits +testsys.cpu.dtb.read_hits 3909164 # DTB read hits testsys.cpu.dtb.read_misses 3287 # DTB read misses testsys.cpu.dtb.read_acv 80 # DTB read access violations testsys.cpu.dtb.read_accesses 225414 # DTB read accesses -testsys.cpu.dtb.write_hits 478329 # DTB write hits +testsys.cpu.dtb.write_hits 2312434 # DTB write hits testsys.cpu.dtb.write_misses 528 # DTB write misses testsys.cpu.dtb.write_acv 81 # DTB write access violations testsys.cpu.dtb.write_accesses 109988 # DTB write accesses -testsys.cpu.dtb.data_hits 1090216 # DTB hits +testsys.cpu.dtb.data_hits 6221598 # DTB hits testsys.cpu.dtb.data_misses 3815 # DTB misses testsys.cpu.dtb.data_acv 161 # DTB access violations testsys.cpu.dtb.data_accesses 335402 # DTB accesses -testsys.cpu.itb.fetch_hits 1215659 # ITB hits +testsys.cpu.itb.fetch_hits 4045775 # ITB hits testsys.cpu.itb.fetch_misses 1497 # ITB misses testsys.cpu.itb.fetch_acv 69 # ITB acv -testsys.cpu.itb.fetch_accesses 1217156 # ITB accesses +testsys.cpu.itb.fetch_accesses 4047272 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -242,51 +242,51 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 399134959 # number of cpu cycles simulated +testsys.cpu.numCycles 400807419 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 3303576 # Number of instructions committed -testsys.cpu.committedOps 3303576 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 3114478 # Number of integer alu accesses +testsys.cpu.committedInsts 20218035 # Number of instructions committed +testsys.cpu.committedOps 20218035 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 18800192 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 17380 # Number of float alu accesses -testsys.cpu.num_func_calls 87508 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 347037 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 3114478 # number of integer instructions +testsys.cpu.num_func_calls 1218514 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 1439639 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 18800192 # number of integer instructions testsys.cpu.num_fp_insts 17380 # number of float instructions -testsys.cpu.num_int_register_reads 4292532 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 2256656 # number of times the integer registers were written +testsys.cpu.num_int_register_reads 24739164 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 14664877 # number of times the integer registers were written testsys.cpu.num_fp_register_reads 11166 # number of times the floating registers were read testsys.cpu.num_fp_register_writes 10823 # number of times the floating registers were written -testsys.cpu.num_mem_refs 1099900 # number of memory refs -testsys.cpu.num_load_insts 619443 # Number of load instructions -testsys.cpu.num_store_insts 480457 # Number of store instructions -testsys.cpu.num_idle_cycles 395839458.060266 # Number of idle cycles -testsys.cpu.num_busy_cycles 3295500.939734 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.008257 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.991743 # Percentage of idle cycles +testsys.cpu.num_mem_refs 6250795 # number of memory refs +testsys.cpu.num_load_insts 3936233 # Number of load instructions +testsys.cpu.num_store_insts 2314562 # Number of store instructions +testsys.cpu.num_idle_cycles 380584404.581032 # Number of idle cycles +testsys.cpu.num_busy_cycles 20223014.418968 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.050456 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.949544 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 213 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 16711 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 4122 40.56% 40.56% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::21 54 0.53% 41.09% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::22 205 2.02% 43.11% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 5781 56.89% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 10162 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 4116 48.47% 48.47% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::21 54 0.64% 49.11% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::22 205 2.41% 51.53% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 4116 48.47% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 8491 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 199321108000 99.88% 99.88% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::21 4521000 0.00% 99.88% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 99.88% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 233256500 0.12% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 199567700500 # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_used::0 0.998544 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.inst.quiesce 19525 # number of quiesce instructions executed +testsys.cpu.kern.inst.hwrei 153371 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 62656 42.67% 42.67% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 19578 13.33% 56.01% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::22 205 0.14% 56.15% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::31 64383 43.85% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 146822 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 62650 43.18% 43.18% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 19578 13.49% 56.67% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::22 205 0.14% 56.81% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::31 62661 43.19% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 145094 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 194361437500 96.98% 96.98% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 1585244500 0.79% 97.78% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::22 8815000 0.00% 97.78% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 4448431000 2.22% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 200403928000 # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_used::0 0.999904 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.711988 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.835564 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::31 0.973254 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.988231 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.syscall::2 3 3.61% 3.61% # number of syscalls executed testsys.cpu.kern.syscall::3 7 8.43% 12.05% # number of syscalls executed testsys.cpu.kern.syscall::4 1 1.20% 13.25% # number of syscalls executed @@ -309,29 +309,29 @@ testsys.cpu.kern.syscall::104 1 1.20% 93.98% # nu testsys.cpu.kern.syscall::105 3 3.61% 97.59% # number of syscalls executed testsys.cpu.kern.syscall::118 2 2.41% 100.00% # number of syscalls executed testsys.cpu.kern.syscall::total 83 # number of syscalls executed -testsys.cpu.kern.callpal::swpctx 438 4.01% 4.01% # number of callpals executed -testsys.cpu.kern.callpal::tbi 20 0.18% 4.20% # number of callpals executed -testsys.cpu.kern.callpal::swpipl 8992 82.42% 86.62% # number of callpals executed -testsys.cpu.kern.callpal::rdps 359 3.29% 89.91% # number of callpals executed -testsys.cpu.kern.callpal::wrusp 3 0.03% 89.94% # number of callpals executed -testsys.cpu.kern.callpal::rdusp 3 0.03% 89.96% # number of callpals executed -testsys.cpu.kern.callpal::rti 911 8.35% 98.31% # number of callpals executed -testsys.cpu.kern.callpal::callsys 140 1.28% 99.60% # number of callpals executed -testsys.cpu.kern.callpal::imb 44 0.40% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 10910 # number of callpals executed -testsys.cpu.kern.mode_switch::kernel 1133 # number of protection mode switches -testsys.cpu.kern.mode_switch::user 647 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 217 # number of protection mode switches -testsys.cpu.kern.mode_good::kernel 652 -testsys.cpu.kern.mode_good::user 647 +testsys.cpu.kern.callpal::swpctx 438 0.34% 0.34% # number of callpals executed +testsys.cpu.kern.callpal::tbi 20 0.02% 0.36% # number of callpals executed +testsys.cpu.kern.callpal::swpipl 106626 83.26% 83.62% # number of callpals executed +testsys.cpu.kern.callpal::rdps 359 0.28% 83.90% # number of callpals executed +testsys.cpu.kern.callpal::wrusp 3 0.00% 83.90% # number of callpals executed +testsys.cpu.kern.callpal::rdusp 3 0.00% 83.91% # number of callpals executed +testsys.cpu.kern.callpal::rti 20424 15.95% 99.86% # number of callpals executed +testsys.cpu.kern.callpal::callsys 140 0.11% 99.97% # number of callpals executed +testsys.cpu.kern.callpal::imb 44 0.03% 100.00% # number of callpals executed +testsys.cpu.kern.callpal::total 128057 # number of callpals executed +testsys.cpu.kern.mode_switch::kernel 1279 # number of protection mode switches +testsys.cpu.kern.mode_switch::user 702 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 19584 # number of protection mode switches +testsys.cpu.kern.mode_good::kernel 707 +testsys.cpu.kern.mode_good::user 702 testsys.cpu.kern.mode_good::idle 5 -testsys.cpu.kern.mode_switch_good::kernel 0.575463 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::kernel 0.552776 # fraction of useful protection mode switches testsys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::idle 0.023041 # fraction of useful protection mode switches -testsys.cpu.kern.mode_switch_good::total 0.652979 # fraction of useful protection mode switches -testsys.cpu.kern.mode_ticks::kernel 931596000 57.08% 57.08% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::user 532793000 32.64% 89.72% # number of ticks spent at the given mode -testsys.cpu.kern.mode_ticks::idle 167721000 10.28% 100.00% # number of ticks spent at the given mode +testsys.cpu.kern.mode_switch_good::idle 0.000255 # fraction of useful protection mode switches +testsys.cpu.kern.mode_switch_good::total 0.065569 # fraction of useful protection mode switches +testsys.cpu.kern.mode_ticks::kernel 993857000 59.77% 59.77% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::user 533068000 32.06% 91.82% # number of ticks spent at the given mode +testsys.cpu.kern.mode_ticks::idle 135946500 8.18% 100.00% # number of ticks spent at the given mode testsys.cpu.kern.swap_context 438 # number of times the context was actually changed testsys.tsunami.ethernet.txBytes 960 # Bytes Transmitted testsys.tsunami.ethernet.rxBytes 798 # Bytes Received @@ -343,16 +343,16 @@ testsys.tsunami.ethernet.txTcpChecksums 2 # Nu testsys.tsunami.ethernet.rxTcpChecksums 5 # Number of rx TCP Checksums done by device testsys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device testsys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -testsys.tsunami.ethernet.descDMAReads 8 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 2087576 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 192 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 50101824 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA -testsys.tsunami.ethernet.totBandwidth 70182 # Total Bandwidth (bits/s) +testsys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) testsys.tsunami.ethernet.totPackets 13 # Total Packets testsys.tsunami.ethernet.totBytes 1758 # Total Bytes testsys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s) -testsys.tsunami.ethernet.txBandwidth 38325 # Transmit Bandwidth (bits/s) -testsys.tsunami.ethernet.rxBandwidth 31858 # Receive Bandwidth (bits/s) +testsys.tsunami.ethernet.txBandwidth 38322 # Transmit Bandwidth (bits/s) +testsys.tsunami.ethernet.rxBandwidth 31855 # Receive Bandwidth (bits/s) testsys.tsunami.ethernet.txPPS 40 # Packet Tranmission Rate (packets/s) testsys.tsunami.ethernet.rxPPS 25 # Packet Reception Rate (packets/s) testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU @@ -370,9 +370,9 @@ testsys.tsunami.ethernet.totalRxDesc 5 # to testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 7 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.postedTxIdle 19525 # number of TxIdle interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 8 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.totalTxIdle 2087576 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -380,37 +380,37 @@ testsys.tsunami.ethernet.postedRxOrn 0 # nu testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 14 # number of posts to CPU +testsys.tsunami.ethernet.postedInterrupts 2087594 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read::cpu.inst 7829376 # Number of bytes read from this memory -drivesys.physmem.bytes_read::cpu.data 2782760 # Number of bytes read from this memory -drivesys.physmem.bytes_read::tsunami.ethernet 1230 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 10613366 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read::cpu.inst 7829376 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_inst_read::total 7829376 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written::cpu.data 1606716 # Number of bytes written to this memory +drivesys.physmem.bytes_read::cpu.inst 76121948 # Number of bytes read from this memory +drivesys.physmem.bytes_read::cpu.data 26255588 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 50103126 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 152480662 # Number of bytes read from this memory +drivesys.physmem.bytes_inst_read::cpu.inst 76121948 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_inst_read::total 76121948 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_written::cpu.data 14603776 # Number of bytes written to this memory drivesys.physmem.bytes_written::tsunami.ethernet 1064 # Number of bytes written to this memory -drivesys.physmem.bytes_written::total 1607780 # Number of bytes written to this memory -drivesys.physmem.num_reads::cpu.inst 1957344 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::cpu.data 393865 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::tsunami.ethernet 34 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 2351243 # Number of read requests responded to by this memory -drivesys.physmem.num_writes::cpu.data 230560 # Number of write requests responded to by this memory +drivesys.physmem.bytes_written::total 14604840 # Number of bytes written to this memory +drivesys.physmem.num_reads::cpu.inst 19030487 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::cpu.data 3643074 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 2087613 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 24761174 # Number of read requests responded to by this memory +drivesys.physmem.num_writes::cpu.data 2022588 # Number of write requests responded to by this memory drivesys.physmem.num_writes::tsunami.ethernet 37 # Number of write requests responded to by this memory -drivesys.physmem.num_writes::total 230597 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 39070237 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 13886559 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::tsunami.ethernet 6138 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 52962933 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 39070237 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 39070237 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 8017852 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::tsunami.ethernet 5310 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 8023161 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 39070237 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 21904410 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::tsunami.ethernet 11448 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 60986094 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.num_writes::total 2022625 # Number of write requests responded to by this memory +drivesys.physmem.bw_read::cpu.inst 379832442 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 131009839 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 250004016 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 760846297 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 379832442 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 379832442 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 72869758 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::tsunami.ethernet 5309 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::total 72875067 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 379832442 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 203879596 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 250009325 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 833721364 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.readReqs 0 # Total number of read requests seen drivesys.physmem.writeReqs 0 # Total number of write requests seen drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -585,22 +585,22 @@ drivesys.cpu.dtb.fetch_hits 0 # IT drivesys.cpu.dtb.fetch_misses 0 # ITB misses drivesys.cpu.dtb.fetch_acv 0 # ITB acv drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses -drivesys.cpu.dtb.read_hits 393226 # DTB read hits +drivesys.cpu.dtb.read_hits 3721202 # DTB read hits drivesys.cpu.dtb.read_misses 487 # DTB read misses drivesys.cpu.dtb.read_acv 30 # DTB read access violations drivesys.cpu.dtb.read_accesses 267991 # DTB read accesses -drivesys.cpu.dtb.write_hits 230718 # DTB write hits +drivesys.cpu.dtb.write_hits 2081819 # DTB write hits drivesys.cpu.dtb.write_misses 82 # DTB write misses drivesys.cpu.dtb.write_acv 10 # DTB write access violations drivesys.cpu.dtb.write_accesses 133239 # DTB write accesses -drivesys.cpu.dtb.data_hits 623944 # DTB hits +drivesys.cpu.dtb.data_hits 5803021 # DTB hits drivesys.cpu.dtb.data_misses 569 # DTB misses drivesys.cpu.dtb.data_acv 40 # DTB access violations drivesys.cpu.dtb.data_accesses 401230 # DTB accesses -drivesys.cpu.itb.fetch_hits 1338285 # ITB hits +drivesys.cpu.itb.fetch_hits 4194101 # ITB hits drivesys.cpu.itb.fetch_misses 194 # ITB misses drivesys.cpu.itb.fetch_acv 22 # ITB acv -drivesys.cpu.itb.fetch_accesses 1338479 # ITB accesses +drivesys.cpu.itb.fetch_accesses 4194295 # ITB accesses drivesys.cpu.itb.read_hits 0 # DTB read hits drivesys.cpu.itb.read_misses 0 # DTB read misses drivesys.cpu.itb.read_acv 0 # DTB read access violations @@ -613,51 +613,51 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 800780792 # number of cpu cycles simulated +drivesys.cpu.numCycles 801639056 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.committedInsts 1956735 # Number of instructions committed -drivesys.cpu.committedOps 1956735 # Number of ops (including micro ops) committed -drivesys.cpu.num_int_alu_accesses 1888716 # Number of integer alu accesses +drivesys.cpu.committedInsts 19029878 # Number of instructions committed +drivesys.cpu.committedOps 19029878 # Number of ops (including micro ops) committed +drivesys.cpu.num_int_alu_accesses 17721251 # Number of integer alu accesses drivesys.cpu.num_fp_alu_accesses 1412 # Number of float alu accesses -drivesys.cpu.num_func_calls 121668 # number of times a function call or return occured -drivesys.cpu.num_conditional_control_insts 160826 # number of instructions that are conditional controls -drivesys.cpu.num_int_insts 1888716 # number of integer instructions +drivesys.cpu.num_func_calls 1263632 # number of times a function call or return occured +drivesys.cpu.num_conditional_control_insts 1263629 # number of instructions that are conditional controls +drivesys.cpu.num_int_insts 17721251 # number of integer instructions drivesys.cpu.num_fp_insts 1412 # number of float instructions -drivesys.cpu.num_int_register_reads 2409464 # number of times the integer registers were read -drivesys.cpu.num_int_register_writes 1441433 # number of times the integer registers were written +drivesys.cpu.num_int_register_reads 23047059 # number of times the integer registers were read +drivesys.cpu.num_int_register_writes 13965767 # number of times the integer registers were written drivesys.cpu.num_fp_register_reads 760 # number of times the floating registers were read drivesys.cpu.num_fp_register_writes 766 # number of times the floating registers were written -drivesys.cpu.num_mem_refs 625666 # number of memory refs -drivesys.cpu.num_load_insts 394435 # Number of load instructions -drivesys.cpu.num_store_insts 231231 # Number of store instructions -drivesys.cpu.num_idle_cycles 798825150.814200 # Number of idle cycles -drivesys.cpu.num_busy_cycles 1955641.185800 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.002442 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.997558 # Percentage of idle cycles +drivesys.cpu.num_mem_refs 5824433 # number of memory refs +drivesys.cpu.num_load_insts 3742101 # Number of load instructions +drivesys.cpu.num_store_insts 2082332 # Number of store instructions +drivesys.cpu.num_idle_cycles 782608307.467164 # Number of idle cycles +drivesys.cpu.num_busy_cycles 19030748.532836 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.023740 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.976260 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.quiesce 215 # number of quiesce instructions executed -drivesys.cpu.kern.inst.hwrei 5510 # number of hwrei instructions executed -drivesys.cpu.kern.ipl_count::0 1199 28.41% 28.41% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::21 12 0.28% 28.69% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::22 205 4.86% 33.55% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::31 2805 66.45% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::total 4221 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good::0 1199 45.85% 45.85% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::21 12 0.46% 46.31% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::22 205 7.84% 54.15% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::31 1199 45.85% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::total 2615 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 200114646000 99.96% 99.96% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::21 486000 0.00% 99.96% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 99.96% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::31 75660250 0.04% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 200195199750 # number of cycles we spent at this ipl +drivesys.cpu.kern.inst.quiesce 19854 # number of quiesce instructions executed +drivesys.cpu.kern.inst.hwrei 143418 # number of hwrei instructions executed +drivesys.cpu.kern.ipl_count::0 60285 42.42% 42.42% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::21 19703 13.86% 56.28% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::22 205 0.14% 56.42% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::31 61936 43.58% 100.00% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::total 142129 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good::0 60285 42.91% 42.91% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::21 19703 14.03% 56.94% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::22 205 0.15% 57.09% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::31 60286 42.91% 100.00% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::total 140479 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks::0 197404825250 98.50% 98.50% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 797938750 0.40% 98.90% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::22 4407500 0.00% 98.90% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::31 2202592500 1.10% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 200409764000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::31 0.427451 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::total 0.619521 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::31 0.973360 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::total 0.988391 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.syscall::2 1 4.55% 4.55% # number of syscalls executed drivesys.cpu.kern.syscall::6 3 13.64% 18.18% # number of syscalls executed drivesys.cpu.kern.syscall::17 2 9.09% 27.27% # number of syscalls executed @@ -671,28 +671,28 @@ drivesys.cpu.kern.syscall::106 1 4.55% 86.36% # nu drivesys.cpu.kern.syscall::118 2 9.09% 95.45% # number of syscalls executed drivesys.cpu.kern.syscall::150 1 4.55% 100.00% # number of syscalls executed drivesys.cpu.kern.syscall::total 22 # number of syscalls executed -drivesys.cpu.kern.callpal::swpctx 72 1.61% 1.61% # number of callpals executed -drivesys.cpu.kern.callpal::tbi 5 0.11% 1.72% # number of callpals executed -drivesys.cpu.kern.callpal::swpipl 3680 82.36% 84.09% # number of callpals executed -drivesys.cpu.kern.callpal::rdps 354 7.92% 92.01% # number of callpals executed -drivesys.cpu.kern.callpal::rdusp 1 0.02% 92.03% # number of callpals executed -drivesys.cpu.kern.callpal::rti 324 7.25% 99.28% # number of callpals executed -drivesys.cpu.kern.callpal::callsys 25 0.56% 99.84% # number of callpals executed -drivesys.cpu.kern.callpal::imb 7 0.16% 100.00% # number of callpals executed -drivesys.cpu.kern.callpal::total 4468 # number of callpals executed -drivesys.cpu.kern.mode_switch::kernel 177 # number of protection mode switches -drivesys.cpu.kern.mode_switch::user 107 # number of protection mode switches -drivesys.cpu.kern.mode_switch::idle 219 # number of protection mode switches -drivesys.cpu.kern.mode_good::kernel 111 -drivesys.cpu.kern.mode_good::user 107 +drivesys.cpu.kern.callpal::swpctx 72 0.06% 0.06% # number of callpals executed +drivesys.cpu.kern.callpal::tbi 5 0.00% 0.06% # number of callpals executed +drivesys.cpu.kern.callpal::swpipl 102208 83.31% 83.37% # number of callpals executed +drivesys.cpu.kern.callpal::rdps 354 0.29% 83.66% # number of callpals executed +drivesys.cpu.kern.callpal::rdusp 1 0.00% 83.66% # number of callpals executed +drivesys.cpu.kern.callpal::rti 20014 16.31% 99.97% # number of callpals executed +drivesys.cpu.kern.callpal::callsys 25 0.02% 99.99% # number of callpals executed +drivesys.cpu.kern.callpal::imb 7 0.01% 100.00% # number of callpals executed +drivesys.cpu.kern.callpal::total 122686 # number of callpals executed +drivesys.cpu.kern.mode_switch::kernel 214 # number of protection mode switches +drivesys.cpu.kern.mode_switch::user 139 # number of protection mode switches +drivesys.cpu.kern.mode_switch::idle 19872 # number of protection mode switches +drivesys.cpu.kern.mode_good::kernel 143 +drivesys.cpu.kern.mode_good::user 139 drivesys.cpu.kern.mode_good::idle 4 -drivesys.cpu.kern.mode_switch_good::kernel 0.627119 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::kernel 0.668224 # fraction of useful protection mode switches drivesys.cpu.kern.mode_switch_good::user 1 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::idle 0.018265 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_switch_good::total 0.441352 # fraction of useful protection mode switches -drivesys.cpu.kern.mode_ticks::kernel 66889000 2.31% 2.31% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::user 319585750 11.03% 13.34% # number of ticks spent at the given mode -drivesys.cpu.kern.mode_ticks::idle 2511080250 86.66% 100.00% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_switch_good::idle 0.000201 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_switch_good::total 0.014141 # fraction of useful protection mode switches +drivesys.cpu.kern.mode_ticks::kernel 78132750 2.64% 2.64% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::user 319665750 10.81% 13.45% # number of ticks spent at the given mode +drivesys.cpu.kern.mode_ticks::idle 2560362000 86.55% 100.00% # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 72 # number of times the context was actually changed drivesys.tsunami.ethernet.txBytes 798 # Bytes Transmitted drivesys.tsunami.ethernet.rxBytes 960 # Bytes Received @@ -704,16 +704,16 @@ drivesys.tsunami.ethernet.txTcpChecksums 2 # Nu drivesys.tsunami.ethernet.rxTcpChecksums 8 # Number of rx TCP Checksums done by device drivesys.tsunami.ethernet.txUdpChecksums 0 # Number of tx UDP Checksums done by device drivesys.tsunami.ethernet.rxUdpChecksums 0 # Number of rx UDP Checksums done by device -drivesys.tsunami.ethernet.descDMAReads 5 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 2087584 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 13 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 120 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 50102016 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 104 # number of descriptor bytes write w/ DMA -drivesys.tsunami.ethernet.totBandwidth 70182 # Total Bandwidth (bits/s) +drivesys.tsunami.ethernet.totBandwidth 70176 # Total Bandwidth (bits/s) drivesys.tsunami.ethernet.totPackets 13 # Total Packets drivesys.tsunami.ethernet.totBytes 1758 # Total Bytes drivesys.tsunami.ethernet.totPPS 65 # Total Tranmission Rate (packets/s) -drivesys.tsunami.ethernet.txBandwidth 31858 # Transmit Bandwidth (bits/s) -drivesys.tsunami.ethernet.rxBandwidth 38325 # Receive Bandwidth (bits/s) +drivesys.tsunami.ethernet.txBandwidth 31855 # Transmit Bandwidth (bits/s) +drivesys.tsunami.ethernet.rxBandwidth 38322 # Receive Bandwidth (bits/s) drivesys.tsunami.ethernet.txPPS 25 # Packet Tranmission Rate (packets/s) drivesys.tsunami.ethernet.rxPPS 40 # Packet Reception Rate (packets/s) drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU @@ -725,15 +725,15 @@ drivesys.tsunami.ethernet.totalRxIdle 0 # to drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR -drivesys.tsunami.ethernet.postedRxDesc 7 # number of RxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxDesc 1 # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.postedRxDesc 8 # number of RxDesc interrupts posted to CPU +drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post drivesys.tsunami.ethernet.totalRxDesc 8 # total number of RxDesc written to ISR drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -drivesys.tsunami.ethernet.postedTxIdle 5 # number of TxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxIdle 0 # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 5 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.postedTxIdle 19702 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.totalTxIdle 2087584 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR @@ -741,45 +741,49 @@ drivesys.tsunami.ethernet.postedRxOrn 0 # nu drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 14 # number of posts to CPU +drivesys.tsunami.ethernet.postedInterrupts 2087605 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000390 # Number of seconds simulated -sim_ticks 390393500 # Number of ticks simulated -final_tick 4320551921500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000407 # Number of seconds simulated +sim_ticks 406952000 # Number of ticks simulated +final_tick 4321612280500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 123937139701 # Simulator instruction rate (inst/s) -host_op_rate 122659857960 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 174562814371 # Simulator tick rate (ticks/s) -host_mem_usage 463260 # Number of bytes of host memory used -host_seconds 0.00 # Real time elapsed on the host -sim_insts 271554329 # Number of instructions simulated -sim_ops 271554329 # Number of ops (including micro ops) simulated -testsys.physmem.bytes_read::cpu.inst 5888 # Number of bytes read from this memory -testsys.physmem.bytes_read::cpu.data 2272 # Number of bytes read from this memory -testsys.physmem.bytes_read::total 8160 # Number of bytes read from this memory -testsys.physmem.bytes_inst_read::cpu.inst 5888 # Number of instructions bytes read from this memory -testsys.physmem.bytes_inst_read::total 5888 # Number of instructions bytes read from this memory -testsys.physmem.bytes_written::cpu.data 1288 # Number of bytes written to this memory -testsys.physmem.bytes_written::total 1288 # Number of bytes written to this memory -testsys.physmem.num_reads::cpu.inst 1472 # Number of read requests responded to by this memory -testsys.physmem.num_reads::cpu.data 309 # Number of read requests responded to by this memory -testsys.physmem.num_reads::total 1781 # Number of read requests responded to by this memory -testsys.physmem.num_writes::cpu.data 172 # Number of write requests responded to by this memory -testsys.physmem.num_writes::total 172 # Number of write requests responded to by this memory -testsys.physmem.bw_read::cpu.inst 15082218 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::cpu.data 5819769 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_read::total 20901987 # Total read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::cpu.inst 15082218 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_inst_read::total 15082218 # Instruction read bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::cpu.data 3299235 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_write::total 3299235 # Write bandwidth from this memory (bytes/s) -testsys.physmem.bw_total::cpu.inst 15082218 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s) -testsys.physmem.bw_total::total 24201223 # Total bandwidth to/from this memory (bytes/s) +host_inst_rate 3682675458 # Simulator instruction rate (inst/s) +host_op_rate 3681807032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 2861829739 # Simulator tick rate (ticks/s) +host_mem_usage 465632 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +sim_insts 523432506 # Number of instructions simulated +sim_ops 523432506 # Number of ops (including micro ops) simulated +testsys.physmem.bytes_read::cpu.inst 144604 # Number of bytes read from this memory +testsys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory +testsys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory +testsys.physmem.bytes_read::total 296292 # Number of bytes read from this memory +testsys.physmem.bytes_inst_read::cpu.inst 144604 # Number of instructions bytes read from this memory +testsys.physmem.bytes_inst_read::total 144604 # Number of instructions bytes read from this memory +testsys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory +testsys.physmem.bytes_written::total 27688 # Number of bytes written to this memory +testsys.physmem.num_reads::cpu.inst 36151 # Number of read requests responded to by this memory +testsys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory +testsys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory +testsys.physmem.num_reads::total 47299 # Number of read requests responded to by this memory +testsys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory +testsys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory +testsys.physmem.bw_read::cpu.inst 355334290 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_read::total 728076038 # Total read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::cpu.inst 355334290 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_inst_read::total 355334290 # Instruction read bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s) +testsys.physmem.bw_total::cpu.inst 355334290 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s) +testsys.physmem.bw_total::total 796113547 # Total bandwidth to/from this memory (bytes/s) testsys.physmem.readReqs 0 # Total number of read requests seen testsys.physmem.writeReqs 0 # Total number of write requests seen testsys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -954,22 +958,22 @@ testsys.cpu.dtb.fetch_hits 0 # IT testsys.cpu.dtb.fetch_misses 0 # ITB misses testsys.cpu.dtb.fetch_acv 0 # ITB acv testsys.cpu.dtb.fetch_accesses 0 # ITB accesses -testsys.cpu.dtb.read_hits 309 # DTB read hits +testsys.cpu.dtb.read_hits 7069 # DTB read hits testsys.cpu.dtb.read_misses 0 # DTB read misses testsys.cpu.dtb.read_acv 0 # DTB read access violations testsys.cpu.dtb.read_accesses 0 # DTB read accesses -testsys.cpu.dtb.write_hits 173 # DTB write hits +testsys.cpu.dtb.write_hits 3933 # DTB write hits testsys.cpu.dtb.write_misses 0 # DTB write misses testsys.cpu.dtb.write_acv 0 # DTB write access violations testsys.cpu.dtb.write_accesses 0 # DTB write accesses -testsys.cpu.dtb.data_hits 482 # DTB hits +testsys.cpu.dtb.data_hits 11002 # DTB hits testsys.cpu.dtb.data_misses 0 # DTB misses testsys.cpu.dtb.data_acv 0 # DTB access violations testsys.cpu.dtb.data_accesses 0 # DTB accesses -testsys.cpu.itb.fetch_hits 192 # ITB hits +testsys.cpu.itb.fetch_hits 5992 # ITB hits testsys.cpu.itb.fetch_misses 0 # ITB misses testsys.cpu.itb.fetch_acv 0 # ITB acv -testsys.cpu.itb.fetch_accesses 192 # ITB accesses +testsys.cpu.itb.fetch_accesses 5992 # ITB accesses testsys.cpu.itb.read_hits 0 # DTB read hits testsys.cpu.itb.read_misses 0 # DTB read misses testsys.cpu.itb.read_acv 0 # DTB read access violations @@ -982,54 +986,58 @@ testsys.cpu.itb.data_hits 0 # DT testsys.cpu.itb.data_misses 0 # DTB misses testsys.cpu.itb.data_acv 0 # DTB access violations testsys.cpu.itb.data_accesses 0 # DTB accesses -testsys.cpu.numCycles 1953126 # number of cpu cycles simulated +testsys.cpu.numCycles 821760 # number of cpu cycles simulated testsys.cpu.numWorkItemsStarted 0 # number of work items this cpu started testsys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -testsys.cpu.committedInsts 1472 # Number of instructions committed -testsys.cpu.committedOps 1472 # Number of ops (including micro ops) committed -testsys.cpu.num_int_alu_accesses 1356 # Number of integer alu accesses +testsys.cpu.committedInsts 36151 # Number of instructions committed +testsys.cpu.committedOps 36151 # Number of ops (including micro ops) committed +testsys.cpu.num_int_alu_accesses 33514 # Number of integer alu accesses testsys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -testsys.cpu.num_func_calls 68 # number of times a function call or return occured -testsys.cpu.num_conditional_control_insts 107 # number of instructions that are conditional controls -testsys.cpu.num_int_insts 1356 # number of integer instructions +testsys.cpu.num_func_calls 2388 # number of times a function call or return occured +testsys.cpu.num_conditional_control_insts 2348 # number of instructions that are conditional controls +testsys.cpu.num_int_insts 33514 # number of integer instructions testsys.cpu.num_fp_insts 0 # number of float instructions -testsys.cpu.num_int_register_reads 1852 # number of times the integer registers were read -testsys.cpu.num_int_register_writes 1059 # number of times the integer registers were written +testsys.cpu.num_int_register_reads 43768 # number of times the integer registers were read +testsys.cpu.num_int_register_writes 26496 # number of times the integer registers were written testsys.cpu.num_fp_register_reads 0 # number of times the floating registers were read testsys.cpu.num_fp_register_writes 0 # number of times the floating registers were written -testsys.cpu.num_mem_refs 483 # number of memory refs -testsys.cpu.num_load_insts 309 # Number of load instructions -testsys.cpu.num_store_insts 174 # Number of store instructions -testsys.cpu.num_idle_cycles 1949443.815916 # Number of idle cycles -testsys.cpu.num_busy_cycles 3682.184084 # Number of busy cycles -testsys.cpu.not_idle_fraction 0.001885 # Percentage of non-idle cycles -testsys.cpu.idle_fraction 0.998115 # Percentage of idle cycles +testsys.cpu.num_mem_refs 11043 # number of memory refs +testsys.cpu.num_load_insts 7109 # Number of load instructions +testsys.cpu.num_store_insts 3934 # Number of store instructions +testsys.cpu.num_idle_cycles 785260.061817 # Number of idle cycles +testsys.cpu.num_busy_cycles 36499.938183 # Number of busy cycles +testsys.cpu.not_idle_fraction 0.044417 # Percentage of non-idle cycles +testsys.cpu.idle_fraction 0.955583 # Percentage of idle cycles testsys.cpu.kern.inst.arm 0 # number of arm instructions executed -testsys.cpu.kern.inst.quiesce 1 # number of quiesce instructions executed -testsys.cpu.kern.inst.hwrei 15 # number of hwrei instructions executed -testsys.cpu.kern.ipl_count::0 3 21.43% 21.43% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::22 1 7.14% 28.57% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::31 10 71.43% 100.00% # number of times we switched to this ipl -testsys.cpu.kern.ipl_count::total 14 # number of times we switched to this ipl -testsys.cpu.kern.ipl_good::0 3 42.86% 42.86% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::22 1 14.29% 57.14% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::31 3 42.86% 100.00% # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_good::total 7 # number of times we switched to this ipl from a different ipl -testsys.cpu.kern.ipl_ticks::0 975901000 99.93% 99.93% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::22 43000 0.00% 99.94% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::31 619000 0.06% 100.00% # number of cycles we spent at this ipl -testsys.cpu.kern.ipl_ticks::total 976563000 # number of cycles we spent at this ipl +testsys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed +testsys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed +testsys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl +testsys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl +testsys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl +testsys.cpu.kern.ipl_ticks::0 398338500 96.95% 96.95% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::21 3240000 0.79% 97.74% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::22 43000 0.01% 97.75% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::31 9258500 2.25% 100.00% # number of cycles we spent at this ipl +testsys.cpu.kern.ipl_ticks::total 410880000 # number of cycles we spent at this ipl testsys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl testsys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::31 0.300000 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.ipl_used::total 0.500000 # fraction of swpipl calls that actually changed the ipl -testsys.cpu.kern.callpal::swpipl 12 85.71% 85.71% # number of callpals executed -testsys.cpu.kern.callpal::rdps 1 7.14% 92.86% # number of callpals executed -testsys.cpu.kern.callpal::rti 1 7.14% 100.00% # number of callpals executed -testsys.cpu.kern.callpal::total 14 # number of callpals executed +testsys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl +testsys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed +testsys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed +testsys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed +testsys.cpu.kern.callpal::total 254 # number of callpals executed testsys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches testsys.cpu.kern.mode_switch::user 0 # number of protection mode switches -testsys.cpu.kern.mode_switch::idle 1 # number of protection mode switches +testsys.cpu.kern.mode_switch::idle 41 # number of protection mode switches testsys.cpu.kern.mode_good::kernel 0 testsys.cpu.kern.mode_good::user 0 testsys.cpu.kern.mode_good::idle 0 @@ -1041,59 +1049,63 @@ testsys.cpu.kern.mode_ticks::kernel 0 # nu testsys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode testsys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode testsys.cpu.kern.swap_context 0 # number of times the context was actually changed -testsys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +testsys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA testsys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -testsys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +testsys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA testsys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA testsys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -testsys.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +testsys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post testsys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR testsys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -testsys.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +testsys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post testsys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR testsys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -testsys.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post testsys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR testsys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -testsys.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post testsys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR testsys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -testsys.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +testsys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post testsys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -testsys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -testsys.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -testsys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +testsys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU +testsys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post +testsys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR testsys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -testsys.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +testsys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post testsys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR testsys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -testsys.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +testsys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post testsys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -testsys.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -testsys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +testsys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post +testsys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU testsys.tsunami.ethernet.droppedPackets 0 # number of packets dropped -drivesys.physmem.bytes_read::cpu.inst 5884 # Number of bytes read from this memory -drivesys.physmem.bytes_read::cpu.data 2272 # Number of bytes read from this memory -drivesys.physmem.bytes_read::total 8156 # Number of bytes read from this memory -drivesys.physmem.bytes_inst_read::cpu.inst 5884 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_inst_read::total 5884 # Number of instructions bytes read from this memory -drivesys.physmem.bytes_written::cpu.data 1288 # Number of bytes written to this memory -drivesys.physmem.bytes_written::total 1288 # Number of bytes written to this memory -drivesys.physmem.num_reads::cpu.inst 1471 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::cpu.data 309 # Number of read requests responded to by this memory -drivesys.physmem.num_reads::total 1780 # Number of read requests responded to by this memory -drivesys.physmem.num_writes::cpu.data 172 # Number of write requests responded to by this memory -drivesys.physmem.num_writes::total 172 # Number of write requests responded to by this memory -drivesys.physmem.bw_read::cpu.inst 15071972 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::cpu.data 5819769 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_read::total 20891741 # Total read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::cpu.inst 15071972 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_inst_read::total 15071972 # Instruction read bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::cpu.data 3299235 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_write::total 3299235 # Write bandwidth from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.inst 15071972 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::cpu.data 9119004 # Total bandwidth to/from this memory (bytes/s) -drivesys.physmem.bw_total::total 24190977 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bytes_read::cpu.inst 144608 # Number of bytes read from this memory +drivesys.physmem.bytes_read::cpu.data 49952 # Number of bytes read from this memory +drivesys.physmem.bytes_read::tsunami.ethernet 101736 # Number of bytes read from this memory +drivesys.physmem.bytes_read::total 296296 # Number of bytes read from this memory +drivesys.physmem.bytes_inst_read::cpu.inst 144608 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_inst_read::total 144608 # Number of instructions bytes read from this memory +drivesys.physmem.bytes_written::cpu.data 27688 # Number of bytes written to this memory +drivesys.physmem.bytes_written::total 27688 # Number of bytes written to this memory +drivesys.physmem.num_reads::cpu.inst 36152 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::cpu.data 6909 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::tsunami.ethernet 4239 # Number of read requests responded to by this memory +drivesys.physmem.num_reads::total 47300 # Number of read requests responded to by this memory +drivesys.physmem.num_writes::cpu.data 3812 # Number of write requests responded to by this memory +drivesys.physmem.num_writes::total 3812 # Number of write requests responded to by this memory +drivesys.physmem.bw_read::cpu.inst 355344119 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::cpu.data 122746663 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::tsunami.ethernet 249995085 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_read::total 728085868 # Total read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::cpu.inst 355344119 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_inst_read::total 355344119 # Instruction read bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::cpu.data 68037508 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_write::total 68037508 # Write bandwidth from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.inst 355344119 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::cpu.data 190784171 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::tsunami.ethernet 249995085 # Total bandwidth to/from this memory (bytes/s) +drivesys.physmem.bw_total::total 796123376 # Total bandwidth to/from this memory (bytes/s) drivesys.physmem.readReqs 0 # Total number of read requests seen drivesys.physmem.writeReqs 0 # Total number of write requests seen drivesys.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady @@ -1268,22 +1280,22 @@ drivesys.cpu.dtb.fetch_hits 0 # IT drivesys.cpu.dtb.fetch_misses 0 # ITB misses drivesys.cpu.dtb.fetch_acv 0 # ITB acv drivesys.cpu.dtb.fetch_accesses 0 # ITB accesses -drivesys.cpu.dtb.read_hits 309 # DTB read hits +drivesys.cpu.dtb.read_hits 7069 # DTB read hits drivesys.cpu.dtb.read_misses 0 # DTB read misses drivesys.cpu.dtb.read_acv 0 # DTB read access violations drivesys.cpu.dtb.read_accesses 0 # DTB read accesses -drivesys.cpu.dtb.write_hits 173 # DTB write hits +drivesys.cpu.dtb.write_hits 3933 # DTB write hits drivesys.cpu.dtb.write_misses 0 # DTB write misses drivesys.cpu.dtb.write_acv 0 # DTB write access violations drivesys.cpu.dtb.write_accesses 0 # DTB write accesses -drivesys.cpu.dtb.data_hits 482 # DTB hits +drivesys.cpu.dtb.data_hits 11002 # DTB hits drivesys.cpu.dtb.data_misses 0 # DTB misses drivesys.cpu.dtb.data_acv 0 # DTB access violations drivesys.cpu.dtb.data_accesses 0 # DTB accesses -drivesys.cpu.itb.fetch_hits 192 # ITB hits +drivesys.cpu.itb.fetch_hits 5992 # ITB hits drivesys.cpu.itb.fetch_misses 0 # ITB misses drivesys.cpu.itb.fetch_acv 0 # ITB acv -drivesys.cpu.itb.fetch_accesses 192 # ITB accesses +drivesys.cpu.itb.fetch_accesses 5992 # ITB accesses drivesys.cpu.itb.read_hits 0 # DTB read hits drivesys.cpu.itb.read_misses 0 # DTB read misses drivesys.cpu.itb.read_acv 0 # DTB read access violations @@ -1296,54 +1308,58 @@ drivesys.cpu.itb.data_hits 0 # DT drivesys.cpu.itb.data_misses 0 # DTB misses drivesys.cpu.itb.data_acv 0 # DTB access violations drivesys.cpu.itb.data_accesses 0 # DTB accesses -drivesys.cpu.numCycles 3906249 # number of cpu cycles simulated +drivesys.cpu.numCycles 1628160 # number of cpu cycles simulated drivesys.cpu.numWorkItemsStarted 0 # number of work items this cpu started drivesys.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -drivesys.cpu.committedInsts 1471 # Number of instructions committed -drivesys.cpu.committedOps 1471 # Number of ops (including micro ops) committed -drivesys.cpu.num_int_alu_accesses 1354 # Number of integer alu accesses +drivesys.cpu.committedInsts 36152 # Number of instructions committed +drivesys.cpu.committedOps 36152 # Number of ops (including micro ops) committed +drivesys.cpu.num_int_alu_accesses 33516 # Number of integer alu accesses drivesys.cpu.num_fp_alu_accesses 0 # Number of float alu accesses -drivesys.cpu.num_func_calls 68 # number of times a function call or return occured -drivesys.cpu.num_conditional_control_insts 108 # number of instructions that are conditional controls -drivesys.cpu.num_int_insts 1354 # number of integer instructions +drivesys.cpu.num_func_calls 2388 # number of times a function call or return occured +drivesys.cpu.num_conditional_control_insts 2347 # number of instructions that are conditional controls +drivesys.cpu.num_int_insts 33516 # number of integer instructions drivesys.cpu.num_fp_insts 0 # number of float instructions -drivesys.cpu.num_int_register_reads 1848 # number of times the integer registers were read -drivesys.cpu.num_int_register_writes 1056 # number of times the integer registers were written +drivesys.cpu.num_int_register_reads 43772 # number of times the integer registers were read +drivesys.cpu.num_int_register_writes 26499 # number of times the integer registers were written drivesys.cpu.num_fp_register_reads 0 # number of times the floating registers were read drivesys.cpu.num_fp_register_writes 0 # number of times the floating registers were written -drivesys.cpu.num_mem_refs 483 # number of memory refs -drivesys.cpu.num_load_insts 309 # Number of load instructions -drivesys.cpu.num_store_insts 174 # Number of store instructions -drivesys.cpu.num_idle_cycles 3902569.320225 # Number of idle cycles -drivesys.cpu.num_busy_cycles 3679.679775 # Number of busy cycles -drivesys.cpu.not_idle_fraction 0.000942 # Percentage of non-idle cycles -drivesys.cpu.idle_fraction 0.999058 # Percentage of idle cycles +drivesys.cpu.num_mem_refs 11043 # number of memory refs +drivesys.cpu.num_load_insts 7109 # Number of load instructions +drivesys.cpu.num_store_insts 3934 # Number of store instructions +drivesys.cpu.num_idle_cycles 1592000.182518 # Number of idle cycles +drivesys.cpu.num_busy_cycles 36159.817482 # Number of busy cycles +drivesys.cpu.not_idle_fraction 0.022209 # Percentage of non-idle cycles +drivesys.cpu.idle_fraction 0.977791 # Percentage of idle cycles drivesys.cpu.kern.inst.arm 0 # number of arm instructions executed -drivesys.cpu.kern.inst.quiesce 1 # number of quiesce instructions executed -drivesys.cpu.kern.inst.hwrei 15 # number of hwrei instructions executed -drivesys.cpu.kern.ipl_count::0 3 21.43% 21.43% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::22 1 7.14% 28.57% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::31 10 71.43% 100.00% # number of times we switched to this ipl -drivesys.cpu.kern.ipl_count::total 14 # number of times we switched to this ipl -drivesys.cpu.kern.ipl_good::0 3 42.86% 42.86% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::22 1 14.29% 57.14% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::31 3 42.86% 100.00% # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_good::total 7 # number of times we switched to this ipl from a different ipl -drivesys.cpu.kern.ipl_ticks::0 976231500 99.97% 99.97% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::22 21500 0.00% 99.97% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::31 309250 0.03% 100.00% # number of cycles we spent at this ipl -drivesys.cpu.kern.ipl_ticks::total 976562250 # number of cycles we spent at this ipl +drivesys.cpu.kern.inst.quiesce 41 # number of quiesce instructions executed +drivesys.cpu.kern.inst.hwrei 295 # number of hwrei instructions executed +drivesys.cpu.kern.ipl_count::0 123 41.84% 41.84% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::21 40 13.61% 55.44% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::22 1 0.34% 55.78% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::31 130 44.22% 100.00% # number of times we switched to this ipl +drivesys.cpu.kern.ipl_count::total 294 # number of times we switched to this ipl +drivesys.cpu.kern.ipl_good::0 123 42.86% 42.86% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::21 40 13.94% 56.79% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::22 1 0.35% 57.14% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::31 123 42.86% 100.00% # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_good::total 287 # number of times we switched to this ipl from a different ipl +drivesys.cpu.kern.ipl_ticks::0 400769000 98.46% 98.46% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::21 1620000 0.40% 98.86% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::22 21500 0.01% 98.86% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::31 4629500 1.14% 100.00% # number of cycles we spent at this ipl +drivesys.cpu.kern.ipl_ticks::total 407040000 # number of cycles we spent at this ipl drivesys.cpu.kern.ipl_used::0 1 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl drivesys.cpu.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::31 0.300000 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.ipl_used::total 0.500000 # fraction of swpipl calls that actually changed the ipl -drivesys.cpu.kern.callpal::swpipl 12 85.71% 85.71% # number of callpals executed -drivesys.cpu.kern.callpal::rdps 1 7.14% 92.86% # number of callpals executed -drivesys.cpu.kern.callpal::rti 1 7.14% 100.00% # number of callpals executed -drivesys.cpu.kern.callpal::total 14 # number of callpals executed +drivesys.cpu.kern.ipl_used::31 0.946154 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.ipl_used::total 0.976190 # fraction of swpipl calls that actually changed the ipl +drivesys.cpu.kern.callpal::swpipl 212 83.46% 83.46% # number of callpals executed +drivesys.cpu.kern.callpal::rdps 1 0.39% 83.86% # number of callpals executed +drivesys.cpu.kern.callpal::rti 41 16.14% 100.00% # number of callpals executed +drivesys.cpu.kern.callpal::total 254 # number of callpals executed drivesys.cpu.kern.mode_switch::kernel 0 # number of protection mode switches drivesys.cpu.kern.mode_switch::user 0 # number of protection mode switches -drivesys.cpu.kern.mode_switch::idle 1 # number of protection mode switches +drivesys.cpu.kern.mode_switch::idle 41 # number of protection mode switches drivesys.cpu.kern.mode_good::kernel 0 drivesys.cpu.kern.mode_good::user 0 drivesys.cpu.kern.mode_good::idle 0 @@ -1355,36 +1371,36 @@ drivesys.cpu.kern.mode_ticks::kernel 0 # nu drivesys.cpu.kern.mode_ticks::user 0 # number of ticks spent at the given mode drivesys.cpu.kern.mode_ticks::idle 0 # number of ticks spent at the given mode drivesys.cpu.kern.swap_context 0 # number of times the context was actually changed -drivesys.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA +drivesys.tsunami.ethernet.descDMAReads 4239 # Number of descriptors the device read w/ DMA drivesys.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA -drivesys.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA +drivesys.tsunami.ethernet.descDmaReadBytes 101736 # number of descriptor bytes read w/ DMA drivesys.tsunami.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA drivesys.tsunami.ethernet.postedSwi 0 # number of software interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post +drivesys.tsunami.ethernet.coalescedSwi 0 # average number of Swi's coalesced into each post drivesys.tsunami.ethernet.totalSwi 0 # total number of Swi written to ISR drivesys.tsunami.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxIdle 0 # average number of RxIdle's coalesced into each post drivesys.tsunami.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR drivesys.tsunami.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOk 0 # average number of RxOk's coalesced into each post drivesys.tsunami.ethernet.totalRxOk 0 # total number of RxOk written to ISR drivesys.tsunami.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxDesc 0 # average number of RxDesc's coalesced into each post drivesys.tsunami.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR drivesys.tsunami.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxOk 0 # average number of TxOk's coalesced into each post drivesys.tsunami.ethernet.totalTxOk 0 # total number of TxOk written to ISR -drivesys.tsunami.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post -drivesys.tsunami.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR +drivesys.tsunami.ethernet.postedTxIdle 40 # number of TxIdle interrupts posted to CPU +drivesys.tsunami.ethernet.coalescedTxIdle 1 # average number of TxIdle's coalesced into each post +drivesys.tsunami.ethernet.totalTxIdle 4239 # total number of TxIdle written to ISR drivesys.tsunami.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU -drivesys.tsunami.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post +drivesys.tsunami.ethernet.coalescedTxDesc 0 # average number of TxDesc's coalesced into each post drivesys.tsunami.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR drivesys.tsunami.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU -drivesys.tsunami.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post +drivesys.tsunami.ethernet.coalescedRxOrn 0 # average number of RxOrn's coalesced into each post drivesys.tsunami.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR -drivesys.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post -drivesys.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU +drivesys.tsunami.ethernet.coalescedTotal 1 # average number of interrupts coalesced into each post +drivesys.tsunami.ethernet.postedInterrupts 4239 # number of posts to CPU drivesys.tsunami.ethernet.droppedPackets 0 # number of packets dropped ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini index 6a6ed7d49..773d3c5ec 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=checker dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -126,11 +128,10 @@ icache_port=system.cpu.icache.cpu_side [system.cpu.checker] type=O3Checker -children=dtb itb tracer +children=dtb isa itb tracer checker=Null clock=500 cpu_id=0 -defer_registration=false do_checkpoint_insts=true do_quiesce=true do_statistics_insts=true @@ -139,6 +140,7 @@ exitOnError=false function_trace=false function_trace_start=0 interrupts=Null +isa=system.cpu.checker.isa itb=system.cpu.checker.itb max_insts_all_threads=0 max_insts_any_thread=0 @@ -147,6 +149,7 @@ max_loads_any_thread=0 numThreads=1 profile=0 progress_interval=0 +switched_out=false system=system tracer=system.cpu.checker.tracer updateOnError=true @@ -166,6 +169,23 @@ num_squash_per_cycle=2 sys=system port=system.cpu.toL2Bus.slave[5] +[system.cpu.checker.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.checker.itb] type=ArmTLB children=walker @@ -189,21 +209,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -492,21 +507,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -515,6 +525,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -535,21 +562,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -576,7 +598,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/arm/linux/hello +executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout index edb619587..dbd9474aa 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 1 2012 15:18:10 -gem5 started Nov 1 2012 22:40:56 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:26:41 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13371000 because target called exit() +Exiting @ tick 13372000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 28f275f3a..d1f8143b0 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13371000 # Number of ticks simulated -final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13372000 # Number of ticks simulated +final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 32987 # Simulator instruction rate (inst/s) -host_op_rate 41149 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 95942804 # Simulator tick rate (ticks/s) -host_mem_usage 272856 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host +host_inst_rate 16216 # Simulator instruction rate (inst/s) +host_op_rate 20228 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 47166036 # Simulator tick rate (ticks/s) +host_mem_usage 230800 # Number of bytes of host memory used +host_seconds 0.28 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13312500 # Total gap between requests +system.physmem.totGap 13314500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -172,9 +172,9 @@ system.physmem.avgQLat 6245.92 # Av system.physmem.avgBankLat 16558.38 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 11.79 # Data bus utilization in percentage @@ -184,7 +184,7 @@ system.physmem.readRowHits 319 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33788.07 # Average gap between requests +system.physmem.avgGap 33793.15 # Average gap between requests system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -273,7 +273,7 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 26743 # number of cpu cycles simulated +system.cpu.numCycles 26745 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 2505 # Number of BP lookups @@ -284,22 +284,21 @@ system.cpu.BPredUnit.BTBHits 707 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) @@ -310,11 +309,11 @@ system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2446 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing @@ -327,17 +326,17 @@ system.cpu.rename.IdleCycles 7146 # Nu system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2247 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 44 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer @@ -352,13 +351,13 @@ system.cpu.iq.iqSquashedInstsIssued 116 # Nu system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle @@ -368,7 +367,7 @@ system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -438,10 +437,10 @@ system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336088 # Inst issue rate +system.cpu.iq.rate 0.336063 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -464,7 +463,7 @@ system.cpu.iew.iewSquashCycles 963 # Nu system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions @@ -482,13 +481,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1446 # Number of branches executed system.cpu.iew.exec_stores 1164 # Number of stores executed -system.cpu.iew.exec_rate 0.320233 # Inst execution rate +system.cpu.iew.exec_rate 0.320209 # Inst execution rate system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8109 # cumulative count of insts written-back system.cpu.iew.wb_producers 3899 # num instructions producing a value system.cpu.iew.wb_consumers 7837 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle +system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit @@ -526,64 +525,64 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 22988 # The number of ROB reads system.cpu.rob.rob_writes 23599 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads +system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 39369 # number of integer regfile reads system.cpu.int_regfile_writes 8027 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2981 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use +system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits system.cpu.icache.overall_hits::total 1601 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -592,46 +591,180 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 20 # 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miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50501.838235 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54372.093023 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51431.564246 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51839.598997 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50501.838235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54704.724409 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51839.598997 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits @@ -654,16 +787,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # 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number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -686,16 +819,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 42607.329843 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42615.183246 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 42615.183246 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 48558.631922 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 48558.631922 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 46276.104418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 46276.104418 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 46276.104418 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -722,14 +855,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # 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miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini index 675d12028..38f0d4bce 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -434,21 +431,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -457,6 +449,23 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=ArmInterrupts +[system.cpu.isa] +type=ArmISA +fpsid=1090793632 +id_isar0=34607377 +id_isar1=34677009 +id_isar2=555950401 +id_isar3=17899825 +id_isar4=268501314 +id_isar5=0 +id_mmfr0=3 +id_mmfr1=0 +id_mmfr2=19070976 +id_mmfr3=4027589137 +id_pfr0=49 +id_pfr1=1 +midr=890224640 + [system.cpu.itb] type=ArmTLB children=walker @@ -477,21 +486,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -518,7 +522,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/arm/linux/hello +executable=/gem5/dist/test-progs/hello/bin/arm/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout index 116fbeb57..b1b5545bf 100755 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout @@ -1,11 +1,11 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:20:14 -gem5 started Oct 30 2012 18:52:17 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:17:24 +gem5 started Jan 4 2013 23:26:30 +gem5 executing on u200540 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... Hello world! -Exiting @ tick 13371000 because target called exit() +Exiting @ tick 13372000 because target called exit() diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 11fc8e27b..5c779e5dd 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000013 # Number of seconds simulated -sim_ticks 13371000 # Number of ticks simulated -final_tick 13371000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 13372000 # Number of ticks simulated +final_tick 13372000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36978 # Simulator instruction rate (inst/s) -host_op_rate 46127 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 107546339 # Simulator tick rate (ticks/s) -host_mem_usage 272728 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host +host_inst_rate 20879 # Simulator instruction rate (inst/s) +host_op_rate 26045 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 60729168 # Simulator tick rate (ticks/s) +host_mem_usage 230484 # Number of bytes of host memory used +host_seconds 0.22 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 17408 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 17408 # Nu system.physmem.num_reads::cpu.inst 272 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory system.physmem.num_reads::total 394 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1301922070 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 583950340 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1885872410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1301922070 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1301922070 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 583950340 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1885872410 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1301824708 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 583906671 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1885731379 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1301824708 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1301824708 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 583906671 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1885731379 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 394 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 394 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13312500 # Total gap between requests +system.physmem.totGap 13314500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -172,9 +172,9 @@ system.physmem.avgQLat 6245.92 # Av system.physmem.avgBankLat 16558.38 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request system.physmem.avgMemAccLat 26804.30 # Average memory access latency -system.physmem.avgRdBW 1885.87 # Average achieved read bandwidth in MB/s +system.physmem.avgRdBW 1885.73 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1885.87 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1885.73 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 11.79 # Data bus utilization in percentage @@ -184,7 +184,7 @@ system.physmem.readRowHits 319 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 80.96 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33788.07 # Average gap between requests +system.physmem.avgGap 33793.15 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,7 +228,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 26743 # number of cpu cycles simulated +system.cpu.numCycles 26745 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.BPredUnit.lookups 2505 # Number of BP lookups @@ -239,22 +239,21 @@ system.cpu.BPredUnit.BTBHits 707 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 294 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6899 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 6900 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12026 # Number of instructions fetch has processed system.cpu.fetch.Branches 2505 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 1001 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2655 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1629 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2242 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1960 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 284 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.180488 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.590506 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.BlockedCycles 2243 # Number of cycles fetch has spent blocked +system.cpu.fetch.CacheLines 1961 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.180396 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.590427 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10260 79.44% 79.44% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 225 1.74% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10261 79.44% 79.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 225 1.74% 81.19% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::2 205 1.59% 82.77% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::3 227 1.76% 84.53% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 222 1.72% 86.25% # Number of instructions fetched each cycle (Total) @@ -265,11 +264,11 @@ system.cpu.fetch.rateDist::8 1257 9.73% 100.00% # Nu system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12915 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.093669 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.449688 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::total 12916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093662 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.449654 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 6881 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2556 # Number of cycles decode is blocked +system.cpu.decode.BlockedCycles 2557 # Number of cycles decode is blocked system.cpu.decode.RunCycles 2446 # Number of cycles decode is running system.cpu.decode.UnblockCycles 69 # Number of cycles decode is unblocking system.cpu.decode.SquashCycles 963 # Number of cycles decode is squashing @@ -282,17 +281,17 @@ system.cpu.rename.IdleCycles 7146 # Nu system.cpu.rename.BlockCycles 329 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 2019 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 2247 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 211 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12572 # Number of instructions processed by rename +system.cpu.rename.UnblockCycles 212 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12579 # Number of instructions processed by rename system.cpu.rename.ROBFullEvents 3 # Number of times rename has blocked due to ROB full system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu.rename.LSQFullEvents 170 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12584 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 57100 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56740 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 12590 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57131 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56771 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 360 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6903 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 6909 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 44 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed system.cpu.rename.skidInsts 683 # count of insts added to the skid buffer @@ -307,13 +306,13 @@ system.cpu.iq.iqSquashedInstsIssued 116 # Nu system.cpu.iq.iqSquashedInstsExamined 5232 # Number of squashed instructions iterated over during squash; mainly for profiling system.cpu.iq.iqSquashedOperandsExamined 14387 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 15 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12915 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.695935 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.400594 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 12916 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.695881 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.400554 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9326 72.21% 72.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9327 72.21% 72.21% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::1 1316 10.19% 82.40% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 809 6.26% 88.66% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 809 6.26% 88.67% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::3 539 4.17% 92.84% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::4 464 3.59% 96.43% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 270 2.09% 98.52% # Number of insts issued each cycle @@ -323,7 +322,7 @@ system.cpu.iq.issued_per_cycle::8 15 0.12% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12915 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 12916 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 6 2.63% 2.63% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available @@ -393,10 +392,10 @@ system.cpu.iq.FU_type_0::MemWrite 1220 13.57% 100.00% # Ty system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::total 8988 # Type of FU issued -system.cpu.iq.rate 0.336088 # Inst issue rate +system.cpu.iq.rate 0.336063 # Inst issue rate system.cpu.iq.fu_busy_cnt 228 # FU busy when requested system.cpu.iq.fu_busy_rate 0.025367 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31199 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_reads 31200 # Number of integer instruction queue reads system.cpu.iq.int_inst_queue_writes 16508 # Number of integer instruction queue writes system.cpu.iq.int_inst_queue_wakeup_accesses 8093 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads @@ -419,7 +418,7 @@ system.cpu.iew.iewSquashCycles 963 # Nu system.cpu.iew.iewBlockCycles 192 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking system.cpu.iew.iewDispatchedInsts 11306 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 103 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2803 # Number of dispatched load instructions system.cpu.iew.iewDispStoreInsts 1586 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 40 # Number of dispatched non-speculative instructions @@ -437,13 +436,13 @@ system.cpu.iew.exec_nop 0 # nu system.cpu.iew.exec_refs 3300 # number of memory reference insts executed system.cpu.iew.exec_branches 1446 # Number of branches executed system.cpu.iew.exec_stores 1164 # Number of stores executed -system.cpu.iew.exec_rate 0.320233 # Inst execution rate +system.cpu.iew.exec_rate 0.320209 # Inst execution rate system.cpu.iew.wb_sent 8265 # cumulative count of insts sent to commit system.cpu.iew.wb_count 8109 # cumulative count of insts written-back system.cpu.iew.wb_producers 3899 # num instructions producing a value system.cpu.iew.wb_consumers 7837 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.303220 # insts written-back per cycle +system.cpu.iew.wb_rate 0.303197 # insts written-back per cycle system.cpu.iew.wb_fanout 0.497512 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.commit.commitSquashedInsts 5577 # The number of squashed insts skipped by commit @@ -481,64 +480,64 @@ system.cpu.commit.bw_limited 0 # nu system.cpu.rob.rob_reads 22988 # The number of ROB reads system.cpu.rob.rob_writes 23599 # The number of ROB writes system.cpu.timesIdled 223 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13828 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 13829 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 5.818755 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.818755 # CPI: Total CPI of All Threads -system.cpu.ipc 0.171858 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.171858 # IPC: Total IPC of All Threads +system.cpu.cpi 5.819191 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.819191 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171845 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171845 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 39369 # number of integer regfile reads system.cpu.int_regfile_writes 8027 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.misc_regfile_reads 2981 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 147.796211 # Cycle average of tags in use +system.cpu.icache.tagsinuse 147.790169 # Cycle average of tags in use system.cpu.icache.total_refs 1601 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 292 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 5.482877 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 147.796211 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072166 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072166 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 147.790169 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072163 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072163 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1601 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1601 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1601 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1601 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1601 # number of overall hits system.cpu.icache.overall_hits::total 1601 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 359 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 359 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 359 # number of overall misses -system.cpu.icache.overall_misses::total 359 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17228000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17228000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17228000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17228000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17228000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17228000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1960 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1960 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1960 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1960 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1960 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183163 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183163 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183163 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183163 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183163 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183163 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47988.857939 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47988.857939 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47988.857939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47988.857939 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47988.857939 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 360 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 360 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 360 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 360 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 360 # number of overall misses +system.cpu.icache.overall_misses::total 360 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17300500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17300500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17300500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17300500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17300500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17300500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1961 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1961 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1961 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1961 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1961 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183580 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.183580 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.183580 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.183580 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.183580 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.183580 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48056.944444 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48056.944444 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48056.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48056.944444 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48056.944444 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked @@ -547,46 +546,180 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 60 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 292 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 292 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 292 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 292 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 292 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 292 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14228000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14228000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14228000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14228000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14228000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14228000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148980 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.148980 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148980 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.148980 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48726.027397 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48726.027397 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48726.027397 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48726.027397 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14229500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14229500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14229500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14229500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.148904 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.148904 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.148904 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.148904 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48731.164384 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48731.164384 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48731.164384 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48731.164384 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.l2cache.replacements 0 # number of replacements +system.cpu.l2cache.tagsinuse 186.095027 # Cycle average of tags in use +system.cpu.l2cache.total_refs 40 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 353 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.113314 # Average number of references to valid blocks. +system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.l2cache.occ_blocks::cpu.inst 139.199950 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.895077 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004248 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001431 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 40 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 40 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits +system.cpu.l2cache.overall_hits::total 40 # number of overall hits +system.cpu.l2cache.ReadReq_misses::cpu.inst 272 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 86 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 358 # number of ReadReq misses +system.cpu.l2cache.ReadExReq_misses::cpu.data 41 # number of ReadExReq misses +system.cpu.l2cache.ReadExReq_misses::total 41 # number of ReadExReq misses +system.cpu.l2cache.demand_misses::cpu.inst 272 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 272 # 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number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6947500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20684000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) +system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 147 # 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average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37940.816176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42787.737705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39441.639594 # average overall mshr miss latency +system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 86.861870 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 86.859001 # Cycle average of tags in use system.cpu.dcache.total_refs 2396 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 16.410959 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 86.861870 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021207 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021207 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 86.859001 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021206 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021206 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1765 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1765 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 606 # number of WriteReq hits @@ -609,16 +742,16 @@ system.cpu.dcache.demand_misses::cpu.data 498 # n system.cpu.dcache.demand_misses::total 498 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 498 # number of overall misses system.cpu.dcache.overall_misses::total 498 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8138000 # 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number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23047000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23047000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23047000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) @@ -641,16 +774,16 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.173580 system.cpu.dcache.demand_miss_rate::total 0.173580 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.173580 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.173580 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 42607.329843 # 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average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46279.116466 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46279.116466 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 63 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked @@ -677,14 +810,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4925000 # 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number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2271500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 13735000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6946500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 20681500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 13735000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6946500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 20681500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 292 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::cpu.data 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.ReadExReq_accesses::total 41 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 292 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 439 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 292 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 439 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.931507 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.811321 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.899497 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.931507 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863946 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.908884 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.931507 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863946 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.908884 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50496.323529 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54360.465116 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51424.581006 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55402.439024 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51833.333333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50496.323529 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54696.850394 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51833.333333 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.l2cache.fast_writes 0 # number of fast writes performed -system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.data 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 5 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 272 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 353 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.ReadExReq_mshr_misses::total 41 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 272 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 394 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 394 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10319402 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3455064 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13774466 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1764540 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10319402 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5219604 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15539006 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10319402 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5219604 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15539006 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.886935 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.897494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.931507 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.829932 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.897494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37938.977941 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42655.111111 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39021.150142 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 43037.560976 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37938.977941 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42783.639344 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39439.101523 # average overall mshr miss latency -system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini index 6eeed9c1d..3748def17 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -116,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -132,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -426,21 +422,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -465,21 +456,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -506,7 +492,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello +executable=/gem5/dist/test-progs/hello/bin/mips/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout index 5f05c3882..f2fe39e9e 100755 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:08:52 -gem5 started Oct 30 2012 13:57:41 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:13:46 +gem5 started Jan 4 2013 21:58:53 +gem5 executing on u200540 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index d0a749f15..f897666a8 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000017 # Nu sim_ticks 16532500 # Number of ticks simulated final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 48770 # Simulator instruction rate (inst/s) -host_op_rate 48763 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 156337427 # Simulator tick rate (ticks/s) -host_mem_usage 215260 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 25568 # Simulator instruction rate (inst/s) +host_op_rate 25564 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 81956278 # Simulator tick rate (ticks/s) +host_mem_usage 217336 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16452500 # Total gap between requests +system.physmem.totGap 16453500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2527972 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13083972 # Sum of mem lat for all requests +system.physmem.totQLat 2530972 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 13086972 # Sum of mem lat for all requests system.physmem.totBusLat 1904000 # Total cycles spent in databus access system.physmem.totBankLat 8652000 # Total cycles spent in bank access -system.physmem.avgQLat 5310.87 # Average queueing delay per request +system.physmem.avgQLat 5317.17 # Average queueing delay per request system.physmem.avgBankLat 18176.47 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27487.34 # Average memory access latency +system.physmem.avgMemAccLat 27493.64 # Average memory access latency system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 376 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 34564.08 # Average gap between requests +system.physmem.avgGap 34566.18 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -215,17 +215,16 @@ system.cpu.BPredUnit.BTBHits 517 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8641 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 8642 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 1949 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 271 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total) @@ -471,50 +470,50 @@ system.cpu.fp_regfile_reads 3 # nu system.cpu.fp_regfile_writes 1 # number of floating regfile writes system.cpu.misc_regfile_reads 147 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 163.149412 # Cycle average of tags in use +system.cpu.icache.tagsinuse 163.159030 # Cycle average of tags in use system.cpu.icache.total_refs 1502 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 163.149412 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079663 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079663 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 163.159030 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.079667 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.079667 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits system.cpu.icache.overall_hits::total 1502 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses -system.cpu.icache.overall_misses::total 446 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 21402000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 21402000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 21402000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 21402000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 21402000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 21402000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47986.547085 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 47986.547085 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 47986.547085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 47986.547085 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 447 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 447 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 447 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 447 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 447 # number of overall misses +system.cpu.icache.overall_misses::total 447 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21475500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21475500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21475500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21475500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21475500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21475500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1949 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1949 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1949 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1949 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1949 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229348 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.229348 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.229348 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.229348 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.229348 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.229348 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48043.624161 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48043.624161 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48043.624161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48043.624161 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48043.624161 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -523,48 +522,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 6 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 108 # 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number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16954500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16954500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16954500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16954500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16954500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16954500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173511 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173511 # 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number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16956000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16956000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16956000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16956000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16956000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173422 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.173422 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173422 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.173422 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50165.680473 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50165.680473 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50165.680473 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50165.680473 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 223.784369 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 223.797313 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 425 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.007059 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 165.662974 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.121395 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 165.672562 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 58.124752 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005056 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006829 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006830 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -582,17 +581,17 @@ system.cpu.l2cache.demand_misses::total 476 # nu system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 476 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16586500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5449500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 22036000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16588000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5450000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22038000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702000 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2702000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16586500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 24738000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16586500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 24738000 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16588000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8152000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24740000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16588000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8152000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24740000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses) @@ -615,17 +614,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993737 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49511.940299 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60550 # 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number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12363045 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4340573 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16703618 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12365045 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4341573 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16706618 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12363045 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6411627 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18774672 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12363045 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6411627 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18774672 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12365045 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6412627 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18777672 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12365045 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6412627 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18777672 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses @@ -667,27 +666,27 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36904.611940 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48228.588889 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39302.630588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36910.582090 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48239.700000 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39309.689412 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36910.582090 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45479.624113 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39448.890756 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 92.011405 # Cycle average of tags in use +system.cpu.dcache.tagsinuse 92.017211 # Cycle average of tags in use system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 92.011405 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022464 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022464 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 92.017211 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022465 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022465 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits @@ -704,14 +703,14 @@ system.cpu.dcache.demand_misses::cpu.data 504 # n system.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses system.cpu.dcache.overall_misses::total 504 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8901000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8901000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8905500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8905500 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 24504499 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 24504499 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 24504499 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 24504499 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24508999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24508999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24508999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24508999 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -728,14 +727,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.172367 system.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58947.019868 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 58947.019868 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58976.821192 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 58976.821192 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48620.037698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48620.037698 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48628.966270 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48628.966270 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48628.966270 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked @@ -760,14 +759,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543500 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8296999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8296999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8296999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8296999 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8297499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8297499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8297499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8297499 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -776,14 +775,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222 system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61588.888889 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61588.888889 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61594.444444 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61594.444444 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58847.510638 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 58847.510638 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini index 71523c506..ed3b8ffac 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -57,7 +58,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -117,6 +117,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -133,21 +134,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -427,21 +423,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,21 +455,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -505,7 +491,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/hello/bin/power/linux/hello +executable=/gem5/dist/test-progs/hello/bin/power/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout index 71a23fbd5..302c5d913 100755 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Oct 30 2012 11:09:52 -gem5 started Oct 30 2012 13:58:22 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:14:12 +gem5 started Jan 4 2013 21:59:04 +gem5 executing on u200540 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index b47dafade..32c8057b9 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000014 # Nu sim_ticks 14065500 # Number of ticks simulated final_tick 14065500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 60799 # Simulator instruction rate (inst/s) -host_op_rate 60790 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 147601989 # Simulator tick rate (ticks/s) -host_mem_usage 210652 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host +host_inst_rate 28037 # Simulator instruction rate (inst/s) +host_op_rate 28032 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 68062430 # Simulator tick rate (ticks/s) +host_mem_usage 213288 # Number of bytes of host memory used +host_seconds 0.21 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 22080 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 13957000 # Total gap between requests +system.physmem.totGap 13958000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -164,14 +164,14 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1923444 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11085444 # Sum of mem lat for all requests +system.physmem.totQLat 1923944 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11085944 # Sum of mem lat for all requests system.physmem.totBusLat 1784000 # Total cycles spent in databus access system.physmem.totBankLat 7378000 # Total cycles spent in bank access -system.physmem.avgQLat 4312.65 # Average queueing delay per request +system.physmem.avgQLat 4313.78 # Average queueing delay per request system.physmem.avgBankLat 16542.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24855.26 # Average memory access latency +system.physmem.avgMemAccLat 24856.38 # Average memory access latency system.physmem.avgRdBW 2029.36 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s system.physmem.avgConsumedRdBW 2029.36 # Average consumed read bandwidth in MB/s @@ -184,7 +184,7 @@ system.physmem.readRowHits 369 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.74 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 31293.72 # Average gap between requests +system.physmem.avgGap 31295.96 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -215,16 +215,15 @@ system.cpu.BPredUnit.BTBHits 602 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 198 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7397 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 7398 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 13218 # Number of instructions fetch has processed system.cpu.fetch.Branches 2247 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 800 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 2267 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 1291 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 1136 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1812 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 306 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 1813 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 307 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 11663 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.133328 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.550093 # Number of instructions fetched each cycle (Total) @@ -469,12 +468,12 @@ system.cpu.int_regfile_writes 7068 # nu system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 168.326699 # Cycle average of tags in use +system.cpu.icache.tagsinuse 168.326770 # Cycle average of tags in use system.cpu.icache.total_refs 1375 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 3.917379 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 168.326699 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 168.326770 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.082191 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.082191 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1375 # number of ReadReq hits @@ -483,36 +482,36 @@ system.cpu.icache.demand_hits::cpu.inst 1375 # nu system.cpu.icache.demand_hits::total 1375 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1375 # number of overall hits system.cpu.icache.overall_hits::total 1375 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses -system.cpu.icache.overall_misses::total 437 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 20187000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 20187000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 20187000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 20187000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 20187000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 20187000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1812 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1812 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1812 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1812 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1812 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241170 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.241170 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.241170 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.241170 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.241170 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.241170 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46194.508009 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46194.508009 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46194.508009 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46194.508009 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46194.508009 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses +system.cpu.icache.overall_misses::total 438 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20259000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20259000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20259000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20259000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20259000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20259000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1813 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1813 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1813 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1813 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1813 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1813 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.241589 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.241589 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.241589 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.241589 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.241589 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.241589 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46253.424658 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46253.424658 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46253.424658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46253.424658 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46253.424658 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 4 # number of cycles access was blocked @@ -521,44 +520,44 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 52 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 86 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 86 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 86 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 86 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 86 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 86 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 87 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 87 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 87 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 87 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 87 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 351 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 351 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 351 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16769000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16769000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16769000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16769000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193709 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.193709 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193709 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.193709 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47774.928775 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47774.928775 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47774.928775 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47774.928775 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16770000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16770000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16770000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16770000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16770000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16770000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.193602 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.193602 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.193602 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.193602 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47777.777778 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47777.777778 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47777.777778 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47777.777778 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 198.645490 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 198.645596 # Cycle average of tags in use system.cpu.l2cache.total_refs 7 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.017544 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 167.286066 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 167.286173 # Average occupied blocks per requestor system.cpu.l2cache.occ_blocks::cpu.data 31.359424 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.005105 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy @@ -583,17 +582,17 @@ system.cpu.l2cache.demand_misses::total 446 # nu system.cpu.l2cache.overall_misses::cpu.inst 345 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses system.cpu.l2cache.overall_misses::total 446 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16357500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2980500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19338000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2765500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2765500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16357500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5746000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22103500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16357500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5746000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22103500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16358500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2981000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19339500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2766000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2766000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16358500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5747000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22105500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16358500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5747000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22105500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 351 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -616,17 +615,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.984547 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982906 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.984547 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47413.043478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55194.444444 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 48466.165414 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58840.425532 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58840.425532 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47413.043478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56891.089109 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49559.417040 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47413.043478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56891.089109 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49559.417040 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47415.942029 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 55203.703704 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48469.924812 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58851.063830 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58851.063830 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49563.901345 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47415.942029 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56900.990099 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49563.901345 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -646,17 +645,17 @@ system.cpu.l2cache.demand_mshr_misses::total 446 system.cpu.l2cache.overall_mshr_misses::cpu.inst 345 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 446 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12035015 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2314548 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14349563 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2186544 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2186544 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12035015 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4501092 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16536107 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12035015 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4501092 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16536107 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12035515 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2315048 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14350563 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2187044 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2187044 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12035515 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4502092 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16537607 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12035515 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4502092 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16537607 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982759 # mshr miss rate for ReadReq accesses @@ -668,17 +667,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.984547 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982906 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.984547 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34884.101449 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42862 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35963.817043 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46522.212766 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46522.212766 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34884.101449 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44565.267327 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37076.473094 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34885.550725 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42871.259259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35966.323308 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46532.851064 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46532.851064 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34885.550725 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44575.168317 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37079.836323 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements system.cpu.dcache.tagsinuse 63.407702 # Cycle average of tags in use @@ -705,14 +704,14 @@ system.cpu.dcache.demand_misses::cpu.data 435 # n system.cpu.dcache.demand_misses::total 435 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 435 # number of overall misses system.cpu.dcache.overall_misses::total 435 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5221500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5221500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14127997 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14127997 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19349497 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19349497 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19349497 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19349497 # number of overall miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5222000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5222000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14128997 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14128997 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 19350997 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 19350997 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 19350997 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 19350997 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1579 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1579 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) @@ -729,14 +728,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.165714 system.cpu.dcache.demand_miss_rate::total 0.165714 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.165714 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.165714 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.730769 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.730769 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42682.770393 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 42682.770393 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 44481.602299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 44481.602299 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 44481.602299 # average overall miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50211.538462 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50211.538462 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42685.791541 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42685.791541 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44485.050575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44485.050575 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44485.050575 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 414 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked @@ -761,14 +760,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2814999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2814999 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5860999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5860999 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5860999 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5860999 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3046500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3046500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2815499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2815499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5861999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5861999 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5861999 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5861999 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034832 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034832 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses @@ -777,14 +776,14 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038857 system.cpu.dcache.demand_mshr_miss_rate::total 0.038857 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038857 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.038857 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55381.818182 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55381.818182 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59893.595745 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59893.595745 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57460.774510 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 57460.774510 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55390.909091 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55390.909091 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59904.234043 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59904.234043 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57470.578431 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57470.578431 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini index 26b2b0376..2a2790447 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -433,21 +430,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -464,6 +456,9 @@ int_master=system.membus.slave[2] int_slave=system.membus.master[2] pio=system.membus.master[1] +[system.cpu.isa] +type=X86ISA + [system.cpu.itb] type=X86TLB children=walker @@ -483,21 +478,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -524,7 +514,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/hello/bin/x86/linux/hello +executable=/gem5/dist/test-progs/hello/bin/x86/linux/hello gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout index 894b4b41a..8a267af68 100755 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout @@ -1,11 +1,9 @@ -Redirecting stdout to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simout -Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/simerr gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Dec 30 2012 00:35:18 -gem5 started Dec 30 2012 01:12:54 -gem5 executing on ribera.cs.wisc.edu +gem5 compiled Jan 4 2013 21:20:54 +gem5 started Jan 4 2013 22:09:04 +gem5 executing on u200540 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index f54c83934..59d569d41 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -4,11 +4,11 @@ sim_seconds 0.000015 # Nu sim_ticks 15014000 # Number of ticks simulated final_tick 15014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27939 # Simulator instruction rate (inst/s) -host_op_rate 50607 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 77954156 # Simulator tick rate (ticks/s) -host_mem_usage 273052 # Number of bytes of host memory used -host_seconds 0.19 # Real time elapsed on the host +host_inst_rate 15963 # Simulator instruction rate (inst/s) +host_op_rate 28915 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 44538984 # Simulator tick rate (ticks/s) +host_mem_usage 232848 # Number of bytes of host memory used +host_seconds 0.34 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9746 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19392 # Number of bytes read from this memory @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 14992500 # Total gap between requests +system.physmem.totGap 14993500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -184,7 +184,7 @@ system.physmem.readRowHits 352 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 78.22 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 33316.67 # Average gap between requests +system.physmem.avgGap 33318.89 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls system.cpu.numCycles 30029 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started @@ -197,18 +197,18 @@ system.cpu.BPredUnit.BTBHits 796 # Nu system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8962 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.icacheStallCycles 8963 # Number of cycles fetch is stalled on an Icache miss system.cpu.fetch.Insts 14512 # Number of instructions fetch has processed system.cpu.fetch.Branches 3018 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 796 # Number of branches that fetch has predicted taken system.cpu.fetch.Cycles 3937 # Number of cycles fetch has run and was not squashing or blocked system.cpu.fetch.SquashCycles 2417 # Number of cycles fetch has spent squashing system.cpu.fetch.BlockedCycles 3663 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 29 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.MiscStallCycles 28 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 144 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 18 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 1880 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.CacheLines 1881 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 288 # Number of outstanding Icache misses that were squashed system.cpu.fetch.rateDist::samples 18583 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::mean 1.378787 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::stdev 2.879591 # Number of instructions fetched each cycle (Total) @@ -451,12 +451,12 @@ system.cpu.int_regfile_writes 17233 # nu system.cpu.fp_regfile_reads 4 # number of floating regfile reads system.cpu.misc_regfile_reads 7157 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 144.838361 # Cycle average of tags in use +system.cpu.icache.tagsinuse 144.838495 # Cycle average of tags in use system.cpu.icache.total_refs 1482 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 304 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 4.875000 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 144.838361 # Average occupied blocks per requestor +system.cpu.icache.occ_blocks::cpu.inst 144.838495 # Average occupied blocks per requestor system.cpu.icache.occ_percent::cpu.inst 0.070722 # Average percentage of cache occupancy system.cpu.icache.occ_percent::total 0.070722 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 1482 # number of ReadReq hits @@ -465,36 +465,36 @@ system.cpu.icache.demand_hits::cpu.inst 1482 # nu system.cpu.icache.demand_hits::total 1482 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 1482 # number of overall hits system.cpu.icache.overall_hits::total 1482 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 398 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 398 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 398 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 398 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 398 # number of overall misses -system.cpu.icache.overall_misses::total 398 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 19300000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 19300000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 19300000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 19300000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 19300000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 19300000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1880 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1880 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1880 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1880 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1880 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1880 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.211702 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.211702 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.211702 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.211702 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.211702 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.211702 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48492.462312 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 48492.462312 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 48492.462312 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 48492.462312 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 48492.462312 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 399 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 399 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 399 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 399 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 399 # number of overall misses +system.cpu.icache.overall_misses::total 399 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19371000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19371000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19371000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19371000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19371000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19371000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1881 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1881 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1881 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1881 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1881 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1881 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.212121 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.212121 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.212121 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.212121 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.212121 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.212121 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48548.872180 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48548.872180 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48548.872180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48548.872180 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48548.872180 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 308 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked @@ -503,12 +503,12 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs 44 system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 95 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 95 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 95 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 95 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 95 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 304 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 304 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 304 # number of demand (read+write) MSHR misses @@ -521,12 +521,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15461500 system.cpu.icache.demand_mshr_miss_latency::total 15461500 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15461500 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 15461500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161702 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.161702 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161702 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.161702 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161616 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.161616 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161616 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.161616 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50860.197368 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50860.197368 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency @@ -534,118 +534,14 @@ system.cpu.icache.demand_avg_mshr_miss_latency::total 50860.197368 system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50860.197368 # average overall mshr miss latency system.cpu.icache.overall_avg_mshr_miss_latency::total 50860.197368 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use -system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2284 # 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average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 52259.900990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 52259.900990 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 52259.900990 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # 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number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52605.633803 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52605.633803 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53085.034014 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 53085.034014 # average overall mshr miss latency -system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 178.021325 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 178.021458 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.985294 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.036031 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.inst 144.985394 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.036064 # Average occupied blocks per requestor system.cpu.l2cache.occ_percent::cpu.inst 0.004425 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::total 0.005433 # Average percentage of cache occupancy @@ -667,16 +563,16 @@ system.cpu.l2cache.overall_misses::cpu.inst 303 # system.cpu.l2cache.overall_misses::cpu.data 147 # number of overall misses system.cpu.l2cache.overall_misses::total 450 # number of overall misses system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15146500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 18957500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3811500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18958000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3992500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3992500 # number of ReadExReq miss cycles system.cpu.l2cache.demand_miss_latency::cpu.inst 15146500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7803500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22950000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7804000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22950500 # number of demand (read+write) miss cycles system.cpu.l2cache.overall_miss_latency::cpu.inst 15146500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7803500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22950000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7804000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22950500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 304 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 71 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 375 # number of ReadReq accesses(hits+misses) @@ -700,16 +596,16 @@ system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996711 system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997783 # miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49988.448845 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53676.056338 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 50688.502674 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53683.098592 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50689.839572 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52532.894737 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52532.894737 # average ReadExReq miss latency system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51000 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51001.111111 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49988.448845 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53085.034014 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51000 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53088.435374 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51001.111111 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -729,17 +625,17 @@ system.cpu.l2cache.demand_mshr_misses::total 450 system.cpu.l2cache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 450 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336452 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11336952 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2944072 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14280524 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14281024 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3029110 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3029110 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336452 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11336952 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5973182 # 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mshr miss rate for ReadReq accesses @@ -751,17 +647,121 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997783 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996711 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997783 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37414.033003 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37415.683168 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41465.802817 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38183.219251 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38184.556150 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39856.710526 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39856.710526 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37414.033003 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37415.683168 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40633.891156 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38465.853333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38466.964444 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu.dcache.replacements 0 # number of replacements +system.cpu.dcache.tagsinuse 83.281408 # Cycle average of tags in use +system.cpu.dcache.total_refs 2284 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 144 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.861111 # Average number of references to valid blocks. +system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu.dcache.occ_blocks::cpu.data 83.281408 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020332 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1425 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1425 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 859 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 859 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2284 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2284 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2284 # number of overall hits +system.cpu.dcache.overall_hits::total 2284 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 126 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 126 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 76 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 202 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 202 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 202 # number of overall misses +system.cpu.dcache.overall_misses::total 202 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6336500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6336500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4220500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4220500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10557000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10557000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10557000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10557000 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1551 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::cpu.data 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.WriteReq_accesses::total 935 # number of WriteReq accesses(hits+misses) +system.cpu.dcache.demand_accesses::cpu.data 2486 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2486 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2486 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2486 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081238 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.081238 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081283 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.081283 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.081255 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.081255 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.081255 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.081255 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50289.682540 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50289.682540 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55532.894737 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55532.894737 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 52262.376238 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 52262.376238 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 52262.376238 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 132 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 22 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked +system.cpu.dcache.fast_writes 0 # number of fast writes performed +system.cpu.dcache.cache_copies 0 # number of cache copies performed +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 55 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 55 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 55 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 71 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 71 # number of ReadReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 76 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 76 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3735500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3735500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4068500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4068500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7804000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7804000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7804000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045777 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081283 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081283 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.059131 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059131 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.059131 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52612.676056 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52612.676056 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53532.894737 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53532.894737 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53088.435374 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53088.435374 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini index 9a57b4e8b..37d5abdb3 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini @@ -14,7 +14,8 @@ clock=1000 init_param=0 kernel= load_addr_mask=1099511627775 -mem_mode=atomic +mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[0] [system.cpu] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload +children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu.interrupts +isa=system.cpu.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=262144 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.dcache_port @@ -425,21 +422,16 @@ assoc=2 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=131072 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.icache_port @@ -448,6 +440,9 @@ mem_side=system.cpu.toL2Bus.slave[0] [system.cpu.interrupts] type=SparcInterrupts +[system.cpu.isa] +type=SparcISA + [system.cpu.itb] type=SparcTLB size=64 @@ -459,21 +454,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=2097152 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu.toL2Bus.master[0] @@ -500,7 +490,7 @@ egid=100 env= errout=cerr euid=100 -executable=/projects/pd/randd/dist/test-progs/insttest/bin/sparc/linux/insttest +executable=/gem5/dist/test-progs/insttest/bin/sparc/linux/insttest gid=100 input=cin max_stack_size=67108864 diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout index 9433cbefd..c7e6fdca4 100755 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 2 2012 11:45:16 -gem5 started Nov 2 2012 11:45:40 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:16:54 +gem5 started Jan 4 2013 21:59:36 +gem5 executing on u200540 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -18,4 +18,4 @@ LDTX: Passed LDTW: Passed STTW: Passed Done -Exiting @ tick 23190500 because target called exit() +Exiting @ tick 23180500 because target called exit() diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index e7a1232b3..a62497bbb 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000023 # Number of seconds simulated -sim_ticks 23190500 # Number of ticks simulated -final_tick 23190500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 23180500 # Number of ticks simulated +final_tick 23180500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 24201 # Simulator instruction rate (inst/s) -host_op_rate 24200 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 38875523 # Simulator tick rate (ticks/s) -host_mem_usage 222232 # Number of bytes of host memory used -host_seconds 0.60 # Real time elapsed on the host +host_inst_rate 21899 # Simulator instruction rate (inst/s) +host_op_rate 21897 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 35159544 # Simulator tick rate (ticks/s) +host_mem_usage 223288 # Number of bytes of host memory used +host_seconds 0.66 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21504 # Nu system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 147 # Number of read requests responded to by this memory system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 927276255 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 405683362 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1332959617 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 927276255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 927276255 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 927276255 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 405683362 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1332959617 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 927676280 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 405858372 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1333534652 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 927676280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 927676280 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 927676280 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 405858372 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1333534652 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 483 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 23130500 # Total gap between requests +system.physmem.totGap 23120500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,8 +98,8 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 146 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 12 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see @@ -164,17 +164,17 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2984483 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12938483 # Sum of mem lat for all requests +system.physmem.totQLat 3040483 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12980483 # Sum of mem lat for all requests system.physmem.totBusLat 1932000 # Total cycles spent in databus access -system.physmem.totBankLat 8022000 # Total cycles spent in bank access -system.physmem.avgQLat 6179.05 # Average queueing delay per request -system.physmem.avgBankLat 16608.70 # Average bank access latency per request +system.physmem.totBankLat 8008000 # Total cycles spent in bank access +system.physmem.avgQLat 6295.00 # Average queueing delay per request +system.physmem.avgBankLat 16579.71 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26787.75 # Average memory access latency -system.physmem.avgRdBW 1332.96 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26874.71 # Average memory access latency +system.physmem.avgRdBW 1333.53 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1332.96 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1333.53 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 8.33 # Data bus utilization in percentage @@ -184,59 +184,59 @@ system.physmem.readRowHits 394 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 47889.23 # Average gap between requests +system.physmem.avgGap 47868.53 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 46382 # number of cpu cycles simulated +system.cpu.numCycles 46362 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6758 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4516 # Number of conditional branches predicted +system.cpu.BPredUnit.lookups 6759 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4517 # Number of conditional branches predicted system.cpu.BPredUnit.condIncorrect 1074 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4657 # Number of BTB lookups +system.cpu.BPredUnit.BTBLookups 4658 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 2448 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. system.cpu.fetch.icacheStallCycles 12203 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 31427 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6758 # Number of branches that fetch encountered +system.cpu.fetch.Insts 31435 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6759 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 2890 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9180 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3075 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 8320 # Number of cycles fetch has spent blocked +system.cpu.fetch.Cycles 9181 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3076 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8341 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 908 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5337 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 445 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 32520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.966390 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.158060 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 5338 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 446 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 32543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.965953 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.157796 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 23340 71.77% 71.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4525 13.91% 85.69% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 464 1.43% 87.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 371 1.14% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23362 71.79% 71.79% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4525 13.90% 85.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 464 1.43% 87.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 371 1.14% 88.26% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::4 671 2.06% 90.32% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::5 764 2.35% 92.67% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::6 234 0.72% 93.39% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::7 255 0.78% 94.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1896 5.83% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1897 5.83% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 32520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.145703 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.677569 # Number of inst fetches per cycle +system.cpu.fetch.rateDist::total 32543 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.145787 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.678034 # Number of inst fetches per cycle system.cpu.decode.IdleCycles 12825 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 9195 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8404 # Number of cycles decode is running +system.cpu.decode.BlockedCycles 9216 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8405 # Number of cycles decode is running system.cpu.decode.UnblockCycles 191 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1905 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 29366 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1905 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13469 # Number of cycles rename is idle +system.cpu.decode.SquashCycles 1906 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 29374 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1906 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13470 # Number of cycles rename is idle system.cpu.rename.BlockCycles 359 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 8329 # count of cycles rename stalled for serializing inst +system.cpu.rename.serializeStallCycles 8350 # count of cycles rename stalled for serializing inst system.cpu.rename.RunCycles 8008 # Number of cycles rename is running system.cpu.rename.UnblockCycles 450 # Number of cycles rename is unblocking system.cpu.rename.RenamedInsts 26929 # Number of instructions processed by rename @@ -249,27 +249,27 @@ system.cpu.rename.CommittedMaps 13819 # Nu system.cpu.rename.UndoneMaps 10347 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 691 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 693 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2732 # count of insts added to the skid buffer +system.cpu.rename.skidInsts 2734 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 3540 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2330 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2331 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 22740 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 22748 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 650 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21250 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 137 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8195 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 5897 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 21285 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 105 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 8188 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 5672 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 175 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 32520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.653444 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.275128 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 32543 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.654058 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.275967 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 23284 71.60% 71.60% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3476 10.69% 82.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.50% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 913 2.81% 97.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23299 71.59% 71.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3475 10.68% 82.27% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2346 7.21% 89.48% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1731 5.32% 94.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 922 2.83% 97.63% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 467 1.44% 99.07% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 238 0.73% 99.80% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 46 0.14% 99.94% # Number of insts issued each cycle @@ -277,7 +277,7 @@ system.cpu.iq.issued_per_cycle::8 19 0.06% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 32520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 32543 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu.iq.fu_full::IntAlu 45 29.41% 29.41% # attempts to use FU when none available system.cpu.iq.fu_full::IntMult 0 0.00% 29.41% # attempts to use FU when none available @@ -313,69 +313,69 @@ system.cpu.iq.fu_full::MemWrite 81 52.94% 100.00% # at system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 15763 74.18% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3339 15.71% 89.89% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2148 10.11% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 15766 74.07% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 74.07% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3371 15.84% 89.91% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2148 10.09% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21250 # Type of FU issued -system.cpu.iq.rate 0.458152 # Inst issue rate +system.cpu.iq.FU_type_0::total 21285 # Type of FU issued +system.cpu.iq.rate 0.459104 # Inst issue rate system.cpu.iq.fu_busy_cnt 153 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.007200 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75310 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 31611 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19572 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.007188 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 75371 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 31612 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19647 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21403 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21438 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 31 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1315 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 26 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 882 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 883 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 28 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1905 # Number of cycles IEW is squashing +system.cpu.iew.iewSquashCycles 1906 # Number of cycles IEW is squashing system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 24529 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 387 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispatchedInsts 24537 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 379 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 3540 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2330 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 2331 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 650 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -383,33 +383,33 @@ system.cpu.iew.memOrderViolationEvents 26 # Nu system.cpu.iew.predictedTakenIncorrect 254 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 945 # Number of branches that were predicted not taken incorrectly system.cpu.iew.branchMispredicts 1199 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20156 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3213 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1094 # Number of squashed instructions skipped in execute +system.cpu.iew.iewExecutedInsts 20207 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3221 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1078 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 1139 # number of nop insts executed -system.cpu.iew.exec_refs 5233 # number of memory reference insts executed +system.cpu.iew.exec_refs 5276 # number of memory reference insts executed system.cpu.iew.exec_branches 4247 # Number of branches executed -system.cpu.iew.exec_stores 2020 # Number of stores executed -system.cpu.iew.exec_rate 0.434565 # Inst execution rate -system.cpu.iew.wb_sent 19807 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19572 # cumulative count of insts written-back +system.cpu.iew.exec_stores 2055 # Number of stores executed +system.cpu.iew.exec_rate 0.435853 # Inst execution rate +system.cpu.iew.wb_sent 19873 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19647 # cumulative count of insts written-back system.cpu.iew.wb_producers 9210 # num instructions producing a value system.cpu.iew.wb_consumers 11373 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.421974 # insts written-back per cycle +system.cpu.iew.wb_rate 0.423774 # insts written-back per cycle system.cpu.iew.wb_fanout 0.809813 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9292 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9300 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 1074 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 30632 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.494973 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.191764 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 30637 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.494892 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.191683 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 23334 76.18% 76.18% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23339 76.18% 76.18% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::1 4026 13.14% 89.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1377 4.50% 93.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1377 4.49% 93.81% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::3 766 2.50% 96.31% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::4 357 1.17% 97.48% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::5 269 0.88% 98.36% # Number of insts commited each cycle @@ -419,7 +419,7 @@ system.cpu.commit.committed_per_cycle::8 114 0.37% 100.00% # Nu system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 30632 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 30637 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -432,66 +432,66 @@ system.cpu.commit.int_insts 12174 # Nu system.cpu.commit.function_calls 187 # Number of function calls committed. system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 54149 # The number of ROB reads -system.cpu.rob.rob_writes 50819 # The number of ROB writes +system.cpu.rob.rob_reads 54162 # The number of ROB reads +system.cpu.rob.rob_writes 50836 # The number of ROB writes system.cpu.timesIdled 206 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 13862 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.idleCycles 13819 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 3.212940 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.212940 # CPI: Total CPI of All Threads -system.cpu.ipc 0.311241 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.311241 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32188 # number of integer regfile reads -system.cpu.int_regfile_writes 17920 # number of integer regfile writes -system.cpu.misc_regfile_reads 6865 # number of misc regfile reads +system.cpu.cpi 3.211554 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.211554 # CPI: Total CPI of All Threads +system.cpu.ipc 0.311376 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.311376 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32290 # number of integer regfile reads +system.cpu.int_regfile_writes 17967 # number of integer regfile writes +system.cpu.misc_regfile_reads 6967 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 191.561206 # Cycle average of tags in use +system.cpu.icache.tagsinuse 191.466325 # Cycle average of tags in use system.cpu.icache.total_refs 4845 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 14.334320 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 191.561206 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.093536 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.093536 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 191.466325 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.093489 # Average percentage of cache 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-system.cpu.icache.ReadReq_miss_latency::cpu.inst 23061000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23061000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23061000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23061000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23061000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23061000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5337 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5337 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5337 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5337 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5337 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5337 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.092187 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.092187 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.092187 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.092187 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.092187 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.092187 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46871.951220 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 46871.951220 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 46871.951220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 46871.951220 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 46871.951220 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 493 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 493 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 493 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 493 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 493 # number of overall misses +system.cpu.icache.overall_misses::total 493 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23383000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23383000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23383000 # number of demand (read+write) miss cycles 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blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,158 +500,48 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 154 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 154 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 154 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 154 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 154 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 154 # number of overall MSHR hits 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overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17056000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 17056000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17056000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 17056000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17056000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 17056000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063331 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063331 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063331 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.063331 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063331 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.063331 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50461.538462 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50461.538462 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50461.538462 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 50461.538462 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50461.538462 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 50461.538462 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17113500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17113500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17113500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17113500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17113500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17113500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.063320 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.063320 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.063320 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.063320 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50631.656805 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50631.656805 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50631.656805 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50631.656805 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 99.978765 # Cycle average of tags in use -system.cpu.dcache.total_refs 4011 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.285714 # Average number of references to valid blocks. -system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 99.978765 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.024409 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.024409 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 2972 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 2972 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits -system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits -system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4005 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4005 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4005 # number of overall hits -system.cpu.dcache.overall_hits::total 4005 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 539 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 539 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 539 # number of overall misses -system.cpu.dcache.overall_misses::total 539 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6945000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6945000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 19513974 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 19513974 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 26458974 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 26458974 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 26458974 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 26458974 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3102 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3102 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4544 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4544 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4544 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4544 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041908 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.041908 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.118618 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.118618 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.118618 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.118618 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 53423.076923 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 53423.076923 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47711.427873 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47711.427873 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 49089.005566 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 49089.005566 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 49089.005566 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 49089.005566 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 378 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 13.500000 # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu.dcache.fast_writes 0 # number of fast writes performed -system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 64 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 64 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 83 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3837000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3837000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4507500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4507500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8344500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8344500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8344500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8344500 # number of overall MSHR miss cycles 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blocks. system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 190.966695 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 34.909617 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005828 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 190.872097 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 34.895277 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005825 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001065 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006893 # Average percentage of cache occupancy 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latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51654.244306 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49867.559524 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55738.095238 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51654.244306 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -732,17 +622,17 @@ system.cpu.l2cache.demand_mshr_misses::total 483 system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses 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# Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024400 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 2980 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 2980 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits +system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits +system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits +system.cpu.dcache.demand_hits::cpu.data 4013 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4013 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4013 # number of overall hits +system.cpu.dcache.overall_hits::total 4013 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 130 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 130 # number of ReadReq misses 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miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8342000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8342000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8342000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8342000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020579 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.032293 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.032293 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.032293 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59945.312500 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59945.312500 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54283.132530 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54283.132530 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56748.299320 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56748.299320 # average overall mshr miss latency +system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini index 92d6d9a2f..74f1370ce 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini @@ -15,6 +15,7 @@ init_param=0 kernel= load_addr_mask=1099511627775 mem_mode=timing +mem_ranges= memories=system.physmem num_work_ids=16 readfile= @@ -30,7 +31,7 @@ system_port=system.membus.slave[1] [system.cpu0] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer workload +children=dcache dtb fuPool icache interrupts isa itb tracer workload BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -56,7 +57,6 @@ cpu_id=0 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -78,6 +78,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu0.interrupts +isa=system.cpu0.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu0.itb @@ -115,6 +116,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu0.tracer trapLatency=13 @@ -131,21 +133,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.dcache_port @@ -425,21 +422,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu0.icache_port @@ -448,6 +440,9 @@ mem_side=system.toL2Bus.slave[0] [system.cpu0.interrupts] type=SparcInterrupts +[system.cpu0.isa] +type=SparcISA + [system.cpu0.itb] type=SparcTLB size=64 @@ -463,7 +458,7 @@ egid=100 env= errout=cerr euid=100 -executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic +executable=/gem5/dist/test-progs/m5threads/bin/sparc/linux/test_atomic gid=100 input=cin max_stack_size=67108864 @@ -476,7 +471,7 @@ uid=100 [system.cpu1] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -502,7 +497,6 @@ cpu_id=1 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -524,6 +518,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu1.interrupts +isa=system.cpu1.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu1.itb @@ -561,6 +556,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu1.tracer trapLatency=13 @@ -577,21 +573,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.dcache_port @@ -871,21 +862,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu1.icache_port @@ -894,6 +880,9 @@ mem_side=system.toL2Bus.slave[2] [system.cpu1.interrupts] type=SparcInterrupts +[system.cpu1.isa] +type=SparcISA + [system.cpu1.itb] type=SparcTLB size=64 @@ -903,7 +892,7 @@ type=ExeTracer [system.cpu2] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -929,7 +918,6 @@ cpu_id=2 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -951,6 +939,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu2.interrupts +isa=system.cpu2.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu2.itb @@ -988,6 +977,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu2.tracer trapLatency=13 @@ -1004,21 +994,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.dcache_port @@ -1298,21 +1283,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu2.icache_port @@ -1321,6 +1301,9 @@ mem_side=system.toL2Bus.slave[4] [system.cpu2.interrupts] type=SparcInterrupts +[system.cpu2.isa] +type=SparcISA + [system.cpu2.itb] type=SparcTLB size=64 @@ -1330,7 +1313,7 @@ type=ExeTracer [system.cpu3] type=DerivO3CPU -children=dcache dtb fuPool icache interrupts itb tracer +children=dcache dtb fuPool icache interrupts isa itb tracer BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -1356,7 +1339,6 @@ cpu_id=3 decodeToFetchDelay=1 decodeToRenameDelay=1 decodeWidth=8 -defer_registration=false dispatchWidth=8 do_checkpoint_insts=true do_quiesce=true @@ -1378,6 +1360,7 @@ iewToFetchDelay=1 iewToRenameDelay=1 instShiftAmt=2 interrupts=system.cpu3.interrupts +isa=system.cpu3.isa issueToExecuteDelay=1 issueWidth=8 itb=system.cpu3.itb @@ -1415,6 +1398,7 @@ smtROBPolicy=Partitioned smtROBThreshold=100 squashWidth=8 store_set_clear_period=250000 +switched_out=false system=system tracer=system.cpu3.tracer trapLatency=13 @@ -1431,21 +1415,16 @@ assoc=4 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.dcache_port @@ -1725,21 +1704,16 @@ assoc=1 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=2 is_top_level=true max_miss_count=0 mshrs=4 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=2 size=32768 -subblock_size=0 system=system tgts_per_mshr=20 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.cpu3.icache_port @@ -1748,6 +1722,9 @@ mem_side=system.toL2Bus.slave[6] [system.cpu3.interrupts] type=SparcInterrupts +[system.cpu3.isa] +type=SparcISA + [system.cpu3.itb] type=SparcTLB size=64 @@ -1762,21 +1739,16 @@ assoc=8 block_size=64 clock=500 forward_snoops=true -hash_delay=1 hit_latency=20 is_top_level=false max_miss_count=0 mshrs=20 prefetch_on_access=false prefetcher=Null -prioritizeRequests=false -repl=Null response_latency=20 size=4194304 -subblock_size=0 system=system tgts_per_mshr=12 -trace_addr=0 two_queue=false write_buffers=8 cpu_side=system.toL2Bus.master[0] diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout index b5c2c149d..4d35b5bd4 100755 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout @@ -1,9 +1,9 @@ gem5 Simulator System. http://gem5.org gem5 is copyrighted software; use the --copyright option for details. -gem5 compiled Nov 2 2012 11:45:16 -gem5 started Nov 2 2012 11:45:40 -gem5 executing on u200540-lin +gem5 compiled Jan 4 2013 21:16:54 +gem5 started Jan 4 2013 21:59:48 +gem5 executing on u200540 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... @@ -79,4 +79,4 @@ Iteration 9 completed [Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 Iteration 10 completed PASSED :-) -Exiting @ tick 104830500 because target called exit() +Exiting @ tick 104832500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt index bb0098d76..a08676b4f 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000105 # Number of seconds simulated -sim_ticks 104830500 # Number of ticks simulated -final_tick 104830500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 104832500 # Number of ticks simulated +final_tick 104832500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 112424 # Simulator instruction rate (inst/s) -host_op_rate 112424 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 11388036 # Simulator tick rate (ticks/s) -host_mem_usage 275264 # Number of bytes of host memory used -host_seconds 9.21 # Real time elapsed on the host -sim_insts 1034897 # Number of instructions simulated -sim_ops 1034897 # Number of ops (including micro ops) simulated +host_inst_rate 49068 # Simulator instruction rate (inst/s) +host_op_rate 49068 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 4970400 # Simulator tick rate (ticks/s) +host_mem_usage 237836 # Number of bytes of host memory used +host_seconds 21.09 # Real time elapsed on the host +sim_insts 1034907 # Number of instructions simulated +sim_ops 1034907 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu0.inst 22784 # Number of bytes read from this memory system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory system.physmem.bytes_read::cpu1.inst 5184 # Number of bytes read from this memory @@ -34,29 +34,29 @@ system.physmem.num_reads::cpu2.data 13 # Nu system.physmem.num_reads::cpu3.inst 4 # Number of read requests responded to by this memory system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory system.physmem.num_reads::total 658 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 217341327 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 102565570 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 49451257 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 12210187 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1831528 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 7936621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 2442037 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 7936621 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 401715150 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 217341327 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 49451257 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1831528 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 2442037 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 271066150 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 217341327 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 102565570 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 49451257 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 12210187 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1831528 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 7936621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 2442037 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 7936621 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 401715150 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu0.inst 217337181 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu0.data 102563613 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.inst 49450314 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1.data 12209954 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.inst 1831493 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2.data 7936470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.inst 2441991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3.data 7936470 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 401707486 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu0.inst 217337181 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu1.inst 49450314 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu2.inst 1831493 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu3.inst 2441991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 271060978 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu0.inst 217337181 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0.data 102563613 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.inst 49450314 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1.data 12209954 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.inst 1831493 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2.data 7936470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.inst 2441991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3.data 7936470 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 401707486 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 659 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 980 # Reqs generatd by CPU via cache - shady @@ -100,7 +100,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 104802500 # Total gap between requests +system.physmem.totGap 104804500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -194,17 +194,17 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2987155 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 17761155 # Sum of mem lat for all requests +system.physmem.totQLat 2976655 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 17750655 # Sum of mem lat for all requests system.physmem.totBusLat 2636000 # Total cycles spent in databus access system.physmem.totBankLat 12138000 # Total cycles spent in bank access -system.physmem.avgQLat 4532.86 # Average queueing delay per request +system.physmem.avgQLat 4516.93 # Average queueing delay per request system.physmem.avgBankLat 18418.82 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26951.68 # Average memory access latency -system.physmem.avgRdBW 401.72 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26935.74 # Average memory access latency +system.physmem.avgRdBW 401.71 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 401.72 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 401.71 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s system.physmem.busUtil 2.51 # Data bus utilization in percentage @@ -214,9 +214,9 @@ system.physmem.readRowHits 506 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 76.78 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 159032.63 # Average gap between requests +system.physmem.avgGap 159035.66 # Average gap between requests system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 209662 # number of cpu cycles simulated +system.cpu0.numCycles 209666 # number of cpu cycles simulated system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu0.BPredUnit.lookups 82004 # Number of BP lookups @@ -227,38 +227,38 @@ system.cpu0.BPredUnit.BTBHits 77227 # Nu system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu0.BPredUnit.usedRAS 516 # Number of times the RAS was used to get a target. system.cpu0.BPredUnit.RASInCorrect 132 # Number of incorrect RAS predictions. -system.cpu0.fetch.icacheStallCycles 16907 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.icacheStallCycles 16910 # Number of cycles fetch is stalled on an Icache miss system.cpu0.fetch.Insts 486703 # Number of instructions fetch has processed system.cpu0.fetch.Branches 82004 # Number of branches that fetch encountered system.cpu0.fetch.predictedBranches 77743 # Number of branches that fetch has predicted taken system.cpu0.fetch.Cycles 159637 # Number of cycles fetch has run and was not squashing or blocked system.cpu0.fetch.SquashCycles 3804 # Number of cycles fetch has spent squashing -system.cpu0.fetch.BlockedCycles 12545 # Number of cycles fetch has spent blocked +system.cpu0.fetch.BlockedCycles 12561 # Number of cycles fetch has spent blocked system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu0.fetch.PendingTrapStallCycles 1361 # Number of stall cycles due to pending traps system.cpu0.fetch.CacheLines 5871 # Number of cache lines fetched -system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed -system.cpu0.fetch.rateDist::samples 192893 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::mean 2.523176 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::stdev 2.215866 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.IcacheSquashes 483 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 192912 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 2.522928 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.215898 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::0 33256 17.24% 17.24% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::1 79042 40.98% 58.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 33275 17.25% 17.25% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 79042 40.97% 58.22% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::2 584 0.30% 58.52% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::3 987 0.51% 59.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 987 0.51% 59.04% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::4 454 0.24% 59.27% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::5 75108 38.94% 98.21% # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::6 578 0.30% 98.50% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 75108 38.93% 98.21% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 578 0.30% 98.51% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::7 364 0.19% 98.69% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::8 2520 1.31% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.rateDist::total 192893 # Number of instructions fetched each cycle (Total) -system.cpu0.fetch.branchRate 0.391125 # Number of branch fetches per cycle -system.cpu0.fetch.rate 2.321370 # Number of inst fetches per cycle +system.cpu0.fetch.rateDist::total 192912 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.391117 # Number of branch fetches per cycle +system.cpu0.fetch.rate 2.321325 # Number of inst fetches per cycle system.cpu0.decode.IdleCycles 17503 # Number of cycles decode is idle -system.cpu0.decode.BlockedCycles 14000 # Number of cycles decode is blocked +system.cpu0.decode.BlockedCycles 14019 # Number of cycles decode is blocked system.cpu0.decode.RunCycles 158668 # Number of cycles decode is running system.cpu0.decode.UnblockCycles 284 # Number of cycles decode is unblocking system.cpu0.decode.SquashCycles 2438 # Number of cycles decode is squashing @@ -266,7 +266,7 @@ system.cpu0.decode.DecodedInsts 483730 # Nu system.cpu0.rename.SquashCycles 2438 # Number of cycles rename is squashing system.cpu0.rename.IdleCycles 18159 # Number of cycles rename is idle system.cpu0.rename.BlockCycles 648 # Number of cycles rename is blocking -system.cpu0.rename.serializeStallCycles 12765 # count of cycles rename stalled for serializing inst +system.cpu0.rename.serializeStallCycles 12784 # count of cycles rename stalled for serializing inst system.cpu0.rename.RunCycles 158332 # Number of cycles rename is running system.cpu0.rename.UnblockCycles 551 # Number of cycles rename is unblocking system.cpu0.rename.RenamedInsts 480873 # Number of instructions processed by rename @@ -279,35 +279,35 @@ system.cpu0.rename.CommittedMaps 315995 # Nu system.cpu0.rename.UndoneMaps 13032 # Number of HB maps that are undone due to squashing system.cpu0.rename.serializingInsts 877 # count of serializing insts renamed system.cpu0.rename.tempSerializingInsts 903 # count of temporary serializing insts renamed -system.cpu0.rename.skidInsts 3587 # count of insts added to the skid buffer +system.cpu0.rename.skidInsts 3595 # count of insts added to the skid buffer system.cpu0.memDep0.insertedLoads 153720 # Number of loads inserted to the mem dependence unit. system.cpu0.memDep0.insertedStores 77689 # Number of stores inserted to the mem dependence unit. system.cpu0.memDep0.conflictingLoads 74928 # Number of conflicting loads. system.cpu0.memDep0.conflictingStores 74758 # Number of conflicting stores. system.cpu0.iq.iqInstsAdded 402151 # Number of instructions added to the IQ (excludes non-spec) system.cpu0.iq.iqNonSpecInstsAdded 922 # Number of non-speculative instructions added to the IQ -system.cpu0.iq.iqInstsIssued 399521 # Number of instructions issued -system.cpu0.iq.iqSquashedInstsIssued 164 # Number of squashed instructions issued -system.cpu0.iq.iqSquashedInstsExamined 10786 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu0.iq.iqSquashedOperandsExamined 9496 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqInstsIssued 399553 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 132 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 10756 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 9264 # Number of squashed operands that are examined and possibly removed from graph system.cpu0.iq.iqSquashedNonSpecRemoved 363 # Number of squashed non-spec instructions that were removed -system.cpu0.iq.issued_per_cycle::samples 192893 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::mean 2.071205 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::stdev 1.088777 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::samples 192912 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 2.071167 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.088883 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::0 32269 16.73% 16.73% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::1 4844 2.51% 19.24% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::2 76822 39.83% 59.07% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::3 76327 39.57% 98.64% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::4 1582 0.82% 99.46% # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::5 687 0.36% 99.81% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 32280 16.73% 16.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 4842 2.51% 19.24% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 76824 39.82% 59.07% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 76328 39.57% 98.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 1590 0.82% 99.46% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 686 0.36% 99.81% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::6 263 0.14% 99.95% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::7 81 0.04% 99.99% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu0.iq.issued_per_cycle::total 192893 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 192912 # Number of insts issued each cycle system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu0.iq.fu_full::IntAlu 57 25.45% 25.45% # attempts to use FU when none available system.cpu0.iq.fu_full::IntMult 0 0.00% 25.45% # attempts to use FU when none available @@ -343,50 +343,50 @@ system.cpu0.iq.fu_full::MemWrite 114 50.89% 100.00% # at system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu0.iq.FU_type_0::IntAlu 169105 42.33% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.33% # Type of FU issued -system.cpu0.iq.FU_type_0::MemRead 153283 38.37% 80.69% # Type of FU issued -system.cpu0.iq.FU_type_0::MemWrite 77133 19.31% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 169105 42.32% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.32% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 153315 38.37% 80.70% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 77133 19.30% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu0.iq.FU_type_0::total 399521 # Type of FU issued -system.cpu0.iq.rate 1.905548 # Inst issue rate +system.cpu0.iq.FU_type_0::total 399553 # Type of FU issued +system.cpu0.iq.rate 1.905664 # Inst issue rate system.cpu0.iq.fu_busy_cnt 224 # FU busy when requested system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst) -system.cpu0.iq.int_inst_queue_reads 992323 # Number of integer instruction queue reads -system.cpu0.iq.int_inst_queue_writes 413903 # Number of integer instruction queue writes -system.cpu0.iq.int_inst_queue_wakeup_accesses 397700 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.int_inst_queue_reads 992374 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 413873 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 397773 # Number of integer instruction queue wakeup accesses system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu0.iq.int_alu_accesses 399745 # Number of integer alu accesses +system.cpu0.iq.int_alu_accesses 399777 # Number of integer alu accesses system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu0.iew.lsq.thread0.forwLoads 74515 # Number of loads that had data forwarded from stores system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address @@ -413,43 +413,43 @@ system.cpu0.iew.memOrderViolationEvents 44 # Nu system.cpu0.iew.predictedTakenIncorrect 327 # Number of branches that were predicted taken incorrectly system.cpu0.iew.predictedNotTakenIncorrect 1115 # Number of branches that were predicted not taken incorrectly system.cpu0.iew.branchMispredicts 1442 # Number of branch mispredicts detected at execute -system.cpu0.iew.iewExecutedInsts 398429 # Number of executed instructions -system.cpu0.iew.iewExecLoadInsts 152970 # Number of load instructions executed -system.cpu0.iew.iewExecSquashedInsts 1092 # Number of squashed instructions skipped in execute +system.cpu0.iew.iewExecutedInsts 398478 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 152978 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1075 # Number of squashed instructions skipped in execute system.cpu0.iew.exec_swp 0 # number of swp insts executed system.cpu0.iew.exec_nop 75469 # number of nop insts executed -system.cpu0.iew.exec_refs 229968 # number of memory reference insts executed +system.cpu0.iew.exec_refs 230010 # number of memory reference insts executed system.cpu0.iew.exec_branches 79152 # Number of branches executed -system.cpu0.iew.exec_stores 76998 # Number of stores executed -system.cpu0.iew.exec_rate 1.900340 # Inst execution rate -system.cpu0.iew.wb_sent 398024 # cumulative count of insts sent to commit -system.cpu0.iew.wb_count 397700 # cumulative count of insts written-back -system.cpu0.iew.wb_producers 235727 # num instructions producing a value -system.cpu0.iew.wb_consumers 238246 # num instructions consuming a value +system.cpu0.iew.exec_stores 77032 # Number of stores executed +system.cpu0.iew.exec_rate 1.900537 # Inst execution rate +system.cpu0.iew.wb_sent 398087 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 397773 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 235728 # num instructions producing a value +system.cpu0.iew.wb_consumers 238247 # num instructions consuming a value system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu0.iew.wb_rate 1.896863 # insts written-back per cycle +system.cpu0.iew.wb_rate 1.897175 # insts written-back per cycle system.cpu0.iew.wb_fanout 0.989427 # average fanout of values written-back system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu0.commit.commitSquashedInsts 12164 # The number of squashed insts skipped by commit system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards system.cpu0.commit.branchMispredicts 1218 # The number of times a branch was mispredicted -system.cpu0.commit.committed_per_cycle::samples 190472 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::mean 2.448360 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::stdev 2.135276 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::samples 190474 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 2.448334 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 2.135304 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::0 32802 17.22% 17.22% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 32805 17.22% 17.22% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::1 78740 41.34% 58.56% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::2 2340 1.23% 59.79% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 2339 1.23% 59.79% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::3 693 0.36% 60.15% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::4 545 0.29% 60.44% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::5 74330 39.02% 99.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 74329 39.02% 99.46% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::6 456 0.24% 99.70% # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::7 249 0.13% 99.83% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 250 0.13% 99.83% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::8 317 0.17% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu0.commit.committed_per_cycle::total 190472 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 190474 # Number of insts commited each cycle system.cpu0.commit.committedInsts 466344 # Number of instructions committed system.cpu0.commit.committedOps 466344 # Number of ops (including micro ops) committed system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed @@ -462,31 +462,31 @@ system.cpu0.commit.int_insts 314326 # Nu system.cpu0.commit.function_calls 223 # Number of function calls committed. system.cpu0.commit.bw_lim_events 317 # number cycles where commit BW limit reached system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu0.rob.rob_reads 667502 # The number of ROB reads +system.cpu0.rob.rob_reads 667504 # The number of ROB reads system.cpu0.rob.rob_writes 959472 # The number of ROB writes system.cpu0.timesIdled 316 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu0.idleCycles 16769 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.idleCycles 16754 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu0.committedInsts 391341 # Number of Instructions Simulated system.cpu0.committedOps 391341 # Number of Ops (including micro ops) Simulated system.cpu0.committedInsts_total 391341 # Number of Instructions Simulated -system.cpu0.cpi 0.535753 # CPI: Cycles Per Instruction -system.cpu0.cpi_total 0.535753 # CPI: Total CPI of All Threads -system.cpu0.ipc 1.866533 # IPC: Instructions Per Cycle -system.cpu0.ipc_total 1.866533 # IPC: Total IPC of All Threads -system.cpu0.int_regfile_reads 712669 # number of integer regfile reads -system.cpu0.int_regfile_writes 321346 # number of integer regfile writes +system.cpu0.cpi 0.535763 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.535763 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.866497 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.866497 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 712766 # number of integer regfile reads +system.cpu0.int_regfile_writes 321389 # number of integer regfile writes system.cpu0.fp_regfile_reads 192 # number of floating regfile reads -system.cpu0.misc_regfile_reads 231752 # number of misc regfile reads +system.cpu0.misc_regfile_reads 231850 # number of misc regfile reads system.cpu0.misc_regfile_writes 564 # number of misc regfile writes system.cpu0.icache.replacements 297 # number of replacements -system.cpu0.icache.tagsinuse 245.466325 # Cycle average of tags in use +system.cpu0.icache.tagsinuse 245.463196 # Cycle average of tags in use system.cpu0.icache.total_refs 5129 # Total number of references to valid blocks. system.cpu0.icache.sampled_refs 587 # Sample count of references to valid blocks. system.cpu0.icache.avg_refs 8.737649 # Average number of references to valid blocks. system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 245.466325 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.479426 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.479426 # Average percentage of cache occupancy +system.cpu0.icache.occ_blocks::cpu0.inst 245.463196 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.479420 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.479420 # Average percentage of cache occupancy system.cpu0.icache.ReadReq_hits::cpu0.inst 5129 # number of ReadReq hits system.cpu0.icache.ReadReq_hits::total 5129 # number of ReadReq hits system.cpu0.icache.demand_hits::cpu0.inst 5129 # number of demand (read+write) hits @@ -499,12 +499,12 @@ system.cpu0.icache.demand_misses::cpu0.inst 742 # system.cpu0.icache.demand_misses::total 742 # number of demand (read+write) misses system.cpu0.icache.overall_misses::cpu0.inst 742 # number of overall misses system.cpu0.icache.overall_misses::total 742 # number of overall misses -system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25612000 # number of ReadReq miss cycles -system.cpu0.icache.ReadReq_miss_latency::total 25612000 # number of ReadReq miss cycles -system.cpu0.icache.demand_miss_latency::cpu0.inst 25612000 # number of demand (read+write) miss cycles -system.cpu0.icache.demand_miss_latency::total 25612000 # number of demand (read+write) miss cycles -system.cpu0.icache.overall_miss_latency::cpu0.inst 25612000 # number of overall miss cycles -system.cpu0.icache.overall_miss_latency::total 25612000 # number of overall miss cycles +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 25596000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 25596000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 25596000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 25596000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 25596000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 25596000 # number of overall miss cycles system.cpu0.icache.ReadReq_accesses::cpu0.inst 5871 # number of ReadReq accesses(hits+misses) system.cpu0.icache.ReadReq_accesses::total 5871 # number of ReadReq accesses(hits+misses) system.cpu0.icache.demand_accesses::cpu0.inst 5871 # number of demand (read+write) accesses @@ -517,12 +517,12 @@ system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126384 system.cpu0.icache.demand_miss_rate::total 0.126384 # miss rate for demand accesses system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126384 # miss rate for overall accesses system.cpu0.icache.overall_miss_rate::total 0.126384 # miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34517.520216 # average ReadReq miss latency -system.cpu0.icache.ReadReq_avg_miss_latency::total 34517.520216 # average ReadReq miss latency -system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency -system.cpu0.icache.demand_avg_miss_latency::total 34517.520216 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34517.520216 # average overall miss latency -system.cpu0.icache.overall_avg_miss_latency::total 34517.520216 # average overall miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 34495.956873 # average ReadReq miss latency +system.cpu0.icache.ReadReq_avg_miss_latency::total 34495.956873 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency +system.cpu0.icache.demand_avg_miss_latency::total 34495.956873 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 34495.956873 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::total 34495.956873 # average overall miss latency system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -543,44 +543,44 @@ system.cpu0.icache.demand_mshr_misses::cpu0.inst 588 system.cpu0.icache.demand_mshr_misses::total 588 # number of demand (read+write) MSHR misses system.cpu0.icache.overall_mshr_misses::cpu0.inst 588 # number of overall MSHR misses system.cpu0.icache.overall_mshr_misses::total 588 # number of overall MSHR misses -system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20478500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.ReadReq_mshr_miss_latency::total 20478500 # number of ReadReq MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20478500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.demand_mshr_miss_latency::total 20478500 # number of demand (read+write) MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20478500 # number of overall MSHR miss cycles -system.cpu0.icache.overall_mshr_miss_latency::total 20478500 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 20466000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 20466000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 20466000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 20466000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 20466000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 20466000 # number of overall MSHR miss cycles system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for ReadReq accesses system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.100153 # mshr miss rate for ReadReq accesses system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for demand accesses system.cpu0.icache.demand_mshr_miss_rate::total 0.100153 # mshr miss rate for demand accesses system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.100153 # mshr miss rate for overall accesses system.cpu0.icache.overall_mshr_miss_rate::total 0.100153 # mshr miss rate for overall accesses -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average ReadReq mshr miss latency -system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34827.380952 # average ReadReq mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency -system.cpu0.icache.demand_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34827.380952 # average overall mshr miss latency -system.cpu0.icache.overall_avg_mshr_miss_latency::total 34827.380952 # average overall mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average ReadReq mshr miss latency +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 34806.122449 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 34806.122449 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::total 34806.122449 # average overall mshr miss latency system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 143.868426 # Cycle average of tags in use -system.cpu0.dcache.total_refs 153554 # Total number of references to valid blocks. +system.cpu0.dcache.tagsinuse 143.865824 # Cycle average of tags in use +system.cpu0.dcache.total_refs 153562 # Total number of references to valid blocks. system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 903.258824 # Average number of references to valid blocks. +system.cpu0.dcache.avg_refs 903.305882 # Average number of references to valid blocks. system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 143.868426 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.280993 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.280993 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 77923 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 77923 # number of ReadReq hits +system.cpu0.dcache.occ_blocks::cpu0.data 143.865824 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.280988 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.280988 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 77931 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 77931 # number of ReadReq hits system.cpu0.dcache.WriteReq_hits::cpu0.data 75708 # number of WriteReq hits system.cpu0.dcache.WriteReq_hits::total 75708 # number of WriteReq hits system.cpu0.dcache.SwapReq_hits::cpu0.data 22 # number of SwapReq hits system.cpu0.dcache.SwapReq_hits::total 22 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 153631 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 153631 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 153631 # number of overall hits -system.cpu0.dcache.overall_hits::total 153631 # number of overall hits +system.cpu0.dcache.demand_hits::cpu0.data 153639 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 153639 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 153639 # number of overall hits +system.cpu0.dcache.overall_hits::total 153639 # number of overall hits system.cpu0.dcache.ReadReq_misses::cpu0.data 471 # number of ReadReq misses system.cpu0.dcache.ReadReq_misses::total 471 # number of ReadReq misses system.cpu0.dcache.WriteReq_misses::cpu0.data 550 # number of WriteReq misses @@ -593,26 +593,26 @@ system.cpu0.dcache.overall_misses::cpu0.data 1021 system.cpu0.dcache.overall_misses::total 1021 # number of overall misses system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11085500 # number of ReadReq miss cycles system.cpu0.dcache.ReadReq_miss_latency::total 11085500 # number of ReadReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22991498 # number of WriteReq miss cycles -system.cpu0.dcache.WriteReq_miss_latency::total 22991498 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 23032998 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 23032998 # number of WriteReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 390000 # number of SwapReq miss cycles system.cpu0.dcache.SwapReq_miss_latency::total 390000 # number of SwapReq miss cycles -system.cpu0.dcache.demand_miss_latency::cpu0.data 34076998 # number of demand (read+write) miss cycles -system.cpu0.dcache.demand_miss_latency::total 34076998 # number of demand (read+write) miss cycles -system.cpu0.dcache.overall_miss_latency::cpu0.data 34076998 # number of overall miss cycles -system.cpu0.dcache.overall_miss_latency::total 34076998 # number of overall miss cycles -system.cpu0.dcache.ReadReq_accesses::cpu0.data 78394 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 78394 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.demand_miss_latency::cpu0.data 34118498 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 34118498 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 34118498 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 34118498 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 78402 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 78402 # number of ReadReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::cpu0.data 76258 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.WriteReq_accesses::total 76258 # number of WriteReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 154652 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 154652 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 154652 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 154652 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006008 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.006008 # miss rate for ReadReq accesses +system.cpu0.dcache.demand_accesses::cpu0.data 154660 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 154660 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 154660 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 154660 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006007 # miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_miss_rate::total 0.006007 # miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007212 # miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_miss_rate::total 0.007212 # miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.476190 # miss rate for SwapReq accesses @@ -623,14 +623,14 @@ system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006602 system.cpu0.dcache.overall_miss_rate::total 0.006602 # miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 23536.093418 # average ReadReq miss latency system.cpu0.dcache.ReadReq_avg_miss_latency::total 23536.093418 # average ReadReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41802.723636 # average WriteReq miss latency -system.cpu0.dcache.WriteReq_avg_miss_latency::total 41802.723636 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 41878.178182 # average WriteReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::total 41878.178182 # average WriteReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 19500 # average SwapReq miss latency system.cpu0.dcache.SwapReq_avg_miss_latency::total 19500 # average SwapReq miss latency -system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency -system.cpu0.dcache.demand_avg_miss_latency::total 33376.099902 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33376.099902 # average overall miss latency -system.cpu0.dcache.overall_avg_miss_latency::total 33376.099902 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency +system.cpu0.dcache.demand_avg_miss_latency::total 33416.746327 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 33416.746327 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::total 33416.746327 # average overall miss latency system.cpu0.dcache.blocked_cycles::no_mshrs 196 # number of cycles access was blocked system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked @@ -661,16 +661,16 @@ system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4894000 # number of ReadReq MSHR miss cycles system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4894000 # number of ReadReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5605500 # number of WriteReq MSHR miss cycles -system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5605500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5613000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5613000 # number of WriteReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 350000 # number of SwapReq MSHR miss cycles system.cpu0.dcache.SwapReq_mshr_miss_latency::total 350000 # number of SwapReq MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10499500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.demand_mshr_miss_latency::total 10499500 # number of demand (read+write) MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10499500 # number of overall MSHR miss cycles -system.cpu0.dcache.overall_mshr_miss_latency::total 10499500 # number of overall MSHR miss cycles -system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002475 # mshr miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002475 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 10507000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 10507000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 10507000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 10507000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002474 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002474 # mshr miss rate for ReadReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002177 # mshr miss rate for WriteReq accesses system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002177 # mshr miss rate for WriteReq accesses system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.476190 # mshr miss rate for SwapReq accesses @@ -681,98 +681,98 @@ system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002328 system.cpu0.dcache.overall_mshr_miss_rate::total 0.002328 # mshr miss rate for overall accesses system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 25226.804124 # average ReadReq mshr miss latency system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 25226.804124 # average ReadReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33768.072289 # average WriteReq mshr miss latency -system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33768.072289 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33813.253012 # average WriteReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33813.253012 # average WriteReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 17500 # average SwapReq mshr miss latency system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 17500 # average SwapReq mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency -system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29165.277778 # average overall mshr miss latency -system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29165.277778 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 29186.111111 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::total 29186.111111 # average overall mshr miss latency system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 174084 # number of cpu cycles simulated +system.cpu1.numCycles 174086 # number of cpu cycles simulated system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.BPredUnit.lookups 52904 # Number of BP lookups -system.cpu1.BPredUnit.condPredicted 50238 # Number of conditional branches predicted +system.cpu1.BPredUnit.lookups 52905 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 50239 # Number of conditional branches predicted system.cpu1.BPredUnit.condIncorrect 1268 # Number of conditional branches incorrect -system.cpu1.BPredUnit.BTBLookups 46828 # Number of BTB lookups -system.cpu1.BPredUnit.BTBHits 46138 # Number of BTB hits +system.cpu1.BPredUnit.BTBLookups 46829 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 46139 # Number of BTB hits system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu1.BPredUnit.usedRAS 659 # Number of times the RAS was used to get a target. system.cpu1.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu1.fetch.icacheStallCycles 27344 # Number of cycles fetch is stalled on an Icache miss -system.cpu1.fetch.Insts 297398 # Number of instructions fetch has processed -system.cpu1.fetch.Branches 52904 # Number of branches that fetch encountered -system.cpu1.fetch.predictedBranches 46797 # Number of branches that fetch has predicted taken -system.cpu1.fetch.Cycles 103835 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.Insts 297404 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 52905 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 46798 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 103837 # Number of cycles fetch has run and was not squashing or blocked system.cpu1.fetch.SquashCycles 3694 # Number of cycles fetch has spent squashing -system.cpu1.fetch.BlockedCycles 29305 # Number of cycles fetch has spent blocked +system.cpu1.fetch.BlockedCycles 29303 # Number of cycles fetch has spent blocked system.cpu1.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu1.fetch.NoActiveThreadStallCycles 6116 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.NoActiveThreadStallCycles 6120 # Number of stall cycles due to no active thread to fetch from system.cpu1.fetch.PendingTrapStallCycles 727 # Number of stall cycles due to pending traps system.cpu1.fetch.CacheLines 18660 # Number of cache lines fetched system.cpu1.fetch.IcacheSquashes 267 # Number of outstanding Icache misses that were squashed -system.cpu1.fetch.rateDist::samples 169680 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::mean 1.752699 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::stdev 2.165176 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::samples 169684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.752693 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.165174 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::0 65845 38.81% 38.81% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::1 52566 30.98% 69.78% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 65847 38.81% 38.81% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 52567 30.98% 69.79% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::2 5632 3.32% 73.10% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::3 3204 1.89% 74.99% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::4 655 0.39% 75.38% # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::5 36566 21.55% 96.93% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 36567 21.55% 96.93% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::6 1212 0.71% 97.64% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::7 766 0.45% 98.09% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::8 3234 1.91% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.rateDist::total 169680 # Number of instructions fetched each cycle (Total) -system.cpu1.fetch.branchRate 0.303899 # Number of branch fetches per cycle -system.cpu1.fetch.rate 1.708359 # Number of inst fetches per cycle +system.cpu1.fetch.rateDist::total 169684 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.303902 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.708374 # Number of inst fetches per cycle system.cpu1.decode.IdleCycles 31981 # Number of cycles decode is idle -system.cpu1.decode.BlockedCycles 26240 # Number of cycles decode is blocked -system.cpu1.decode.RunCycles 98388 # Number of cycles decode is running +system.cpu1.decode.BlockedCycles 26238 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 98390 # Number of cycles decode is running system.cpu1.decode.UnblockCycles 4607 # Number of cycles decode is unblocking system.cpu1.decode.SquashCycles 2348 # Number of cycles decode is squashing -system.cpu1.decode.DecodedInsts 293925 # Number of instructions handled by decode +system.cpu1.decode.DecodedInsts 293931 # Number of instructions handled by decode system.cpu1.rename.SquashCycles 2348 # Number of cycles rename is squashing system.cpu1.rename.IdleCycles 32683 # Number of cycles rename is idle system.cpu1.rename.BlockCycles 13600 # Number of cycles rename is blocking -system.cpu1.rename.serializeStallCycles 11858 # count of cycles rename stalled for serializing inst -system.cpu1.rename.RunCycles 94082 # Number of cycles rename is running +system.cpu1.rename.serializeStallCycles 11856 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 94084 # Number of cycles rename is running system.cpu1.rename.UnblockCycles 8993 # Number of cycles rename is unblocking -system.cpu1.rename.RenamedInsts 291891 # Number of instructions processed by rename +system.cpu1.rename.RenamedInsts 291897 # Number of instructions processed by rename system.cpu1.rename.LSQFullEvents 40 # Number of times rename has blocked due to LSQ full -system.cpu1.rename.RenamedOperands 205019 # Number of destination operands rename has renamed -system.cpu1.rename.RenameLookups 562522 # Number of register rename lookups that rename has made -system.cpu1.rename.int_rename_lookups 562522 # Number of integer rename lookups -system.cpu1.rename.CommittedMaps 192184 # Number of HB maps that are committed +system.cpu1.rename.RenamedOperands 205023 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 562534 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 562534 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 192188 # Number of HB maps that are committed system.cpu1.rename.UndoneMaps 12835 # Number of HB maps that are undone due to squashing system.cpu1.rename.serializingInsts 1091 # count of serializing insts renamed system.cpu1.rename.tempSerializingInsts 1214 # count of temporary serializing insts renamed system.cpu1.rename.skidInsts 11554 # count of insts added to the skid buffer -system.cpu1.memDep0.insertedLoads 83196 # Number of loads inserted to the mem dependence unit. -system.cpu1.memDep0.insertedStores 39822 # Number of stores inserted to the mem dependence unit. -system.cpu1.memDep0.conflictingLoads 39557 # Number of conflicting loads. -system.cpu1.memDep0.conflictingStores 34785 # Number of conflicting stores. -system.cpu1.iq.iqInstsAdded 242788 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.memDep0.insertedLoads 83198 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 39823 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 39558 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 34786 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 242793 # Number of instructions added to the IQ (excludes non-spec) system.cpu1.iq.iqNonSpecInstsAdded 5818 # Number of non-speculative instructions added to the IQ -system.cpu1.iq.iqInstsIssued 244431 # Number of instructions issued +system.cpu1.iq.iqInstsIssued 244436 # Number of instructions issued system.cpu1.iq.iqSquashedInstsIssued 88 # Number of squashed instructions issued -system.cpu1.iq.iqSquashedInstsExamined 10770 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu1.iq.iqSquashedOperandsExamined 10393 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedInstsExamined 10755 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 10381 # Number of squashed operands that are examined and possibly removed from graph system.cpu1.iq.iqSquashedNonSpecRemoved 573 # Number of squashed non-spec instructions that were removed -system.cpu1.iq.issued_per_cycle::samples 169680 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::mean 1.440541 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::samples 169684 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.440537 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::stdev 1.314007 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::0 63213 37.25% 37.25% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 63215 37.25% 37.25% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::1 21011 12.38% 49.64% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::2 39930 23.53% 73.17% # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::3 40650 23.96% 97.13% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 39931 23.53% 73.17% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 40651 23.96% 97.13% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::4 3306 1.95% 99.07% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::5 1205 0.71% 99.78% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::6 253 0.15% 99.93% # Number of insts issued each cycle @@ -781,7 +781,7 @@ system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Nu system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu1.iq.issued_per_cycle::total 169680 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 169684 # Number of insts issued each cycle system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu1.iq.fu_full::IntAlu 17 5.76% 5.76% # attempts to use FU when none available system.cpu1.iq.fu_full::IntMult 0 0.00% 5.76% # attempts to use FU when none available @@ -817,7 +817,7 @@ system.cpu1.iq.fu_full::MemWrite 210 71.19% 100.00% # at system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu1.iq.FU_type_0::IntAlu 118248 48.38% 48.38% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 118250 48.38% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::IntMult 0 0.00% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 48.38% # Type of FU issued @@ -846,23 +846,23 @@ system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.38% # Ty system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.38% # Type of FU issued system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.38% # Type of FU issued -system.cpu1.iq.FU_type_0::MemRead 87044 35.61% 83.99% # Type of FU issued -system.cpu1.iq.FU_type_0::MemWrite 39139 16.01% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 87046 35.61% 83.99% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 39140 16.01% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu1.iq.FU_type_0::total 244431 # Type of FU issued -system.cpu1.iq.rate 1.404098 # Inst issue rate +system.cpu1.iq.FU_type_0::total 244436 # Type of FU issued +system.cpu1.iq.rate 1.404111 # Inst issue rate system.cpu1.iq.fu_busy_cnt 295 # FU busy when requested system.cpu1.iq.fu_busy_rate 0.001207 # FU busy rate (busy events/executed inst) -system.cpu1.iq.int_inst_queue_reads 658925 # Number of integer instruction queue reads -system.cpu1.iq.int_inst_queue_writes 259421 # Number of integer instruction queue writes -system.cpu1.iq.int_inst_queue_wakeup_accesses 242675 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.int_inst_queue_reads 658939 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 259411 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 242683 # Number of integer instruction queue wakeup accesses system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu1.iq.int_alu_accesses 244726 # Number of integer alu accesses +system.cpu1.iq.int_alu_accesses 244731 # Number of integer alu accesses system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu1.iew.lsq.thread0.forwLoads 34549 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.forwLoads 34550 # Number of loads that had data forwarded from stores system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu1.iew.lsq.thread0.squashedLoads 2395 # Number of loads squashed system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed @@ -876,10 +876,10 @@ system.cpu1.iew.iewIdleCycles 0 # Nu system.cpu1.iew.iewSquashCycles 2348 # Number of cycles IEW is squashing system.cpu1.iew.iewBlockCycles 954 # Number of cycles IEW is blocking system.cpu1.iew.iewUnblockCycles 69 # Number of cycles IEW is unblocking -system.cpu1.iew.iewDispatchedInsts 289058 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispatchedInsts 289064 # Number of instructions dispatched to IQ system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch -system.cpu1.iew.iewDispLoadInsts 83196 # Number of dispatched load instructions -system.cpu1.iew.iewDispStoreInsts 39822 # Number of dispatched store instructions +system.cpu1.iew.iewDispLoadInsts 83198 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 39823 # Number of dispatched store instructions system.cpu1.iew.iewDispNonSpecInsts 1054 # Number of dispatched non-speculative instructions system.cpu1.iew.iewIQFullEvents 70 # Number of times the IQ has become full, causing a stall system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -887,81 +887,81 @@ system.cpu1.iew.memOrderViolationEvents 45 # Nu system.cpu1.iew.predictedTakenIncorrect 455 # Number of branches that were predicted taken incorrectly system.cpu1.iew.predictedNotTakenIncorrect 930 # Number of branches that were predicted not taken incorrectly system.cpu1.iew.branchMispredicts 1385 # Number of branch mispredicts detected at execute -system.cpu1.iew.iewExecutedInsts 243269 # Number of executed instructions -system.cpu1.iew.iewExecLoadInsts 82226 # Number of load instructions executed -system.cpu1.iew.iewExecSquashedInsts 1162 # Number of squashed instructions skipped in execute +system.cpu1.iew.iewExecutedInsts 243277 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 82228 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 1159 # Number of squashed instructions skipped in execute system.cpu1.iew.exec_swp 0 # number of swp insts executed -system.cpu1.iew.exec_nop 40452 # number of nop insts executed -system.cpu1.iew.exec_refs 121286 # number of memory reference insts executed -system.cpu1.iew.exec_branches 49717 # Number of branches executed -system.cpu1.iew.exec_stores 39060 # Number of stores executed -system.cpu1.iew.exec_rate 1.397423 # Inst execution rate -system.cpu1.iew.wb_sent 242942 # cumulative count of insts sent to commit -system.cpu1.iew.wb_count 242675 # cumulative count of insts written-back -system.cpu1.iew.wb_producers 138073 # num instructions producing a value -system.cpu1.iew.wb_consumers 142763 # num instructions consuming a value +system.cpu1.iew.exec_nop 40453 # number of nop insts executed +system.cpu1.iew.exec_refs 121292 # number of memory reference insts executed +system.cpu1.iew.exec_branches 49718 # Number of branches executed +system.cpu1.iew.exec_stores 39064 # Number of stores executed +system.cpu1.iew.exec_rate 1.397453 # Inst execution rate +system.cpu1.iew.wb_sent 242950 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 242683 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 138076 # num instructions producing a value +system.cpu1.iew.wb_consumers 142766 # num instructions consuming a value system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu1.iew.wb_rate 1.394011 # insts written-back per cycle -system.cpu1.iew.wb_fanout 0.967148 # average fanout of values written-back +system.cpu1.iew.wb_rate 1.394041 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.967149 # average fanout of values written-back system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu1.commit.commitSquashedInsts 12362 # The number of squashed insts skipped by commit system.cpu1.commit.commitNonSpecStalls 5245 # The number of times commit has been forced to stall to communicate backwards system.cpu1.commit.branchMispredicts 1268 # The number of times a branch was mispredicted -system.cpu1.commit.committed_per_cycle::samples 161217 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::mean 1.716302 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::stdev 2.045846 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::samples 161216 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.716349 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 2.045856 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::0 62248 38.61% 38.61% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::1 47764 29.63% 68.24% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 62245 38.61% 38.61% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 47765 29.63% 68.24% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::2 6052 3.75% 71.99% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.83% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 6179 3.83% 75.82% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::4 1571 0.97% 76.80% # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::5 35062 21.75% 98.55% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 35063 21.75% 98.55% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::6 510 0.32% 98.86% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::7 1010 0.63% 99.49% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::8 821 0.51% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu1.commit.committed_per_cycle::total 161217 # Number of insts commited each cycle -system.cpu1.commit.committedInsts 276697 # Number of instructions committed -system.cpu1.commit.committedOps 276697 # Number of ops (including micro ops) committed +system.cpu1.commit.committed_per_cycle::total 161216 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 276703 # Number of instructions committed +system.cpu1.commit.committedOps 276703 # Number of ops (including micro ops) committed system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu1.commit.refs 119191 # Number of memory references committed -system.cpu1.commit.loads 80801 # Number of loads committed +system.cpu1.commit.refs 119194 # Number of memory references committed +system.cpu1.commit.loads 80803 # Number of loads committed system.cpu1.commit.membars 4532 # Number of memory barriers committed -system.cpu1.commit.branches 48885 # Number of branches committed +system.cpu1.commit.branches 48886 # Number of branches committed system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu1.commit.int_insts 190199 # Number of committed integer instructions. +system.cpu1.commit.int_insts 190203 # Number of committed integer instructions. system.cpu1.commit.function_calls 322 # Number of function calls committed. system.cpu1.commit.bw_lim_events 821 # number cycles where commit BW limit reached system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu1.rob.rob_reads 448868 # The number of ROB reads -system.cpu1.rob.rob_writes 580470 # The number of ROB writes +system.cpu1.rob.rob_reads 448873 # The number of ROB reads +system.cpu1.rob.rob_writes 580482 # The number of ROB writes system.cpu1.timesIdled 225 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu1.idleCycles 4404 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu1.quiesceCycles 35576 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu1.committedInsts 232489 # Number of Instructions Simulated -system.cpu1.committedOps 232489 # Number of Ops (including micro ops) Simulated -system.cpu1.committedInsts_total 232489 # Number of Instructions Simulated -system.cpu1.cpi 0.748784 # CPI: Cycles Per Instruction -system.cpu1.cpi_total 0.748784 # CPI: Total CPI of All Threads -system.cpu1.ipc 1.335499 # IPC: Instructions Per Cycle -system.cpu1.ipc_total 1.335499 # IPC: Total IPC of All Threads -system.cpu1.int_regfile_reads 422509 # number of integer regfile reads -system.cpu1.int_regfile_writes 197149 # number of integer regfile writes +system.cpu1.idleCycles 4402 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 35578 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 232494 # Number of Instructions Simulated +system.cpu1.committedOps 232494 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 232494 # Number of Instructions Simulated +system.cpu1.cpi 0.748776 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.748776 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.335512 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.335512 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 422524 # number of integer regfile reads +system.cpu1.int_regfile_writes 197153 # number of integer regfile writes system.cpu1.fp_regfile_writes 64 # number of floating regfile writes -system.cpu1.misc_regfile_reads 122869 # number of misc regfile reads +system.cpu1.misc_regfile_reads 122878 # number of misc regfile reads system.cpu1.misc_regfile_writes 648 # number of misc regfile writes system.cpu1.icache.replacements 317 # number of replacements -system.cpu1.icache.tagsinuse 85.783317 # Cycle average of tags in use +system.cpu1.icache.tagsinuse 85.782711 # Cycle average of tags in use system.cpu1.icache.total_refs 18178 # Total number of references to valid blocks. system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks. system.cpu1.icache.avg_refs 42.771765 # Average number of references to valid blocks. system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 85.783317 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.167546 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.167546 # Average percentage of cache occupancy +system.cpu1.icache.occ_blocks::cpu1.inst 85.782711 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.167544 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.167544 # Average percentage of cache occupancy system.cpu1.icache.ReadReq_hits::cpu1.inst 18178 # number of ReadReq hits system.cpu1.icache.ReadReq_hits::total 18178 # number of ReadReq hits system.cpu1.icache.demand_hits::cpu1.inst 18178 # number of demand (read+write) hits @@ -974,12 +974,12 @@ system.cpu1.icache.demand_misses::cpu1.inst 482 # system.cpu1.icache.demand_misses::total 482 # number of demand (read+write) misses system.cpu1.icache.overall_misses::cpu1.inst 482 # number of overall misses system.cpu1.icache.overall_misses::total 482 # number of overall misses -system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9898500 # number of ReadReq miss cycles -system.cpu1.icache.ReadReq_miss_latency::total 9898500 # number of ReadReq miss cycles -system.cpu1.icache.demand_miss_latency::cpu1.inst 9898500 # number of demand (read+write) miss cycles -system.cpu1.icache.demand_miss_latency::total 9898500 # number of demand (read+write) miss cycles -system.cpu1.icache.overall_miss_latency::cpu1.inst 9898500 # number of overall miss cycles -system.cpu1.icache.overall_miss_latency::total 9898500 # number of overall miss cycles +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 9897000 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 9897000 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 9897000 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 9897000 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 9897000 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 9897000 # number of overall miss cycles system.cpu1.icache.ReadReq_accesses::cpu1.inst 18660 # number of ReadReq accesses(hits+misses) system.cpu1.icache.ReadReq_accesses::total 18660 # number of ReadReq accesses(hits+misses) system.cpu1.icache.demand_accesses::cpu1.inst 18660 # number of demand (read+write) accesses @@ -992,12 +992,12 @@ system.cpu1.icache.demand_miss_rate::cpu1.inst 0.025831 system.cpu1.icache.demand_miss_rate::total 0.025831 # miss rate for demand accesses system.cpu1.icache.overall_miss_rate::cpu1.inst 0.025831 # miss rate for overall accesses system.cpu1.icache.overall_miss_rate::total 0.025831 # miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20536.307054 # average ReadReq miss latency -system.cpu1.icache.ReadReq_avg_miss_latency::total 20536.307054 # average ReadReq miss latency -system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency -system.cpu1.icache.demand_avg_miss_latency::total 20536.307054 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20536.307054 # average overall miss latency -system.cpu1.icache.overall_avg_miss_latency::total 20536.307054 # average overall miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 20533.195021 # average ReadReq miss latency +system.cpu1.icache.ReadReq_avg_miss_latency::total 20533.195021 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency +system.cpu1.icache.demand_avg_miss_latency::total 20533.195021 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 20533.195021 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::total 20533.195021 # average overall miss latency system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked @@ -1018,44 +1018,44 @@ system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses -system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8055000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.ReadReq_mshr_miss_latency::total 8055000 # number of ReadReq MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8055000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.demand_mshr_miss_latency::total 8055000 # number of demand (read+write) MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8055000 # number of overall MSHR miss cycles -system.cpu1.icache.overall_mshr_miss_latency::total 8055000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8054000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 8054000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8054000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 8054000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8054000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 8054000 # number of overall MSHR miss cycles system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for ReadReq accesses system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.022776 # mshr miss rate for ReadReq accesses system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for demand accesses system.cpu1.icache.demand_mshr_miss_rate::total 0.022776 # mshr miss rate for demand accesses system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.022776 # mshr miss rate for overall accesses system.cpu1.icache.overall_mshr_miss_rate::total 0.022776 # mshr miss rate for overall accesses -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average ReadReq mshr miss latency -system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18952.941176 # average ReadReq mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency -system.cpu1.icache.demand_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18952.941176 # average overall mshr miss latency -system.cpu1.icache.overall_avg_mshr_miss_latency::total 18952.941176 # average overall mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average ReadReq mshr miss latency +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 18950.588235 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 18950.588235 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::total 18950.588235 # average overall mshr miss latency system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 27.224773 # Cycle average of tags in use -system.cpu1.dcache.total_refs 44406 # Total number of references to valid blocks. +system.cpu1.dcache.tagsinuse 27.224520 # Cycle average of tags in use +system.cpu1.dcache.total_refs 44407 # Total number of references to valid blocks. system.cpu1.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1585.928571 # Average number of references to valid blocks. +system.cpu1.dcache.avg_refs 1585.964286 # Average number of references to valid blocks. system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 27.224773 # Average occupied blocks per requestor +system.cpu1.dcache.occ_blocks::cpu1.data 27.224520 # Average occupied blocks per requestor system.cpu1.dcache.occ_percent::cpu1.data 0.053173 # Average percentage of cache occupancy system.cpu1.dcache.occ_percent::total 0.053173 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 47254 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 47254 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 38186 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 38186 # number of WriteReq hits +system.cpu1.dcache.ReadReq_hits::cpu1.data 47255 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 47255 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 38187 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 38187 # number of WriteReq hits system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 85440 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 85440 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 85440 # number of overall hits -system.cpu1.dcache.overall_hits::total 85440 # number of overall hits +system.cpu1.dcache.demand_hits::cpu1.data 85442 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 85442 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 85442 # number of overall hits +system.cpu1.dcache.overall_hits::total 85442 # number of overall hits system.cpu1.dcache.ReadReq_misses::cpu1.data 407 # number of ReadReq misses system.cpu1.dcache.ReadReq_misses::total 407 # number of ReadReq misses system.cpu1.dcache.WriteReq_misses::cpu1.data 137 # number of WriteReq misses @@ -1068,24 +1068,24 @@ system.cpu1.dcache.overall_misses::cpu1.data 544 system.cpu1.dcache.overall_misses::total 544 # number of overall misses system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 6159500 # number of ReadReq miss cycles system.cpu1.dcache.ReadReq_miss_latency::total 6159500 # number of ReadReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2649500 # number of WriteReq miss cycles -system.cpu1.dcache.WriteReq_miss_latency::total 2649500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 2641000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 2641000 # number of WriteReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 528500 # number of SwapReq miss cycles system.cpu1.dcache.SwapReq_miss_latency::total 528500 # number of SwapReq miss cycles -system.cpu1.dcache.demand_miss_latency::cpu1.data 8809000 # number of demand (read+write) miss cycles -system.cpu1.dcache.demand_miss_latency::total 8809000 # number of demand (read+write) miss cycles -system.cpu1.dcache.overall_miss_latency::cpu1.data 8809000 # number of overall miss cycles -system.cpu1.dcache.overall_miss_latency::total 8809000 # number of overall miss cycles -system.cpu1.dcache.ReadReq_accesses::cpu1.data 47661 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 47661 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 38323 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 38323 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.demand_miss_latency::cpu1.data 8800500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 8800500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 8800500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 8800500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 47662 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 47662 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 38324 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 38324 # number of WriteReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::cpu1.data 67 # number of SwapReq accesses(hits+misses) system.cpu1.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 85984 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 85984 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 85984 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 85984 # number of overall (read+write) accesses +system.cpu1.dcache.demand_accesses::cpu1.data 85986 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 85986 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 85986 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 85986 # number of overall (read+write) accesses system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008539 # miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_miss_rate::total 0.008539 # miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003575 # miss rate for WriteReq accesses @@ -1098,14 +1098,14 @@ system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006327 system.cpu1.dcache.overall_miss_rate::total 0.006327 # miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 15133.906634 # average ReadReq miss latency system.cpu1.dcache.ReadReq_avg_miss_latency::total 15133.906634 # average ReadReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19339.416058 # average WriteReq miss latency -system.cpu1.dcache.WriteReq_avg_miss_latency::total 19339.416058 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 19277.372263 # average WriteReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::total 19277.372263 # average WriteReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 9971.698113 # average SwapReq miss latency system.cpu1.dcache.SwapReq_avg_miss_latency::total 9971.698113 # average SwapReq miss latency -system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency -system.cpu1.dcache.demand_avg_miss_latency::total 16193.014706 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16193.014706 # average overall miss latency -system.cpu1.dcache.overall_avg_miss_latency::total 16193.014706 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency +system.cpu1.dcache.demand_avg_miss_latency::total 16177.389706 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 16177.389706 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::total 16177.389706 # average overall miss latency system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1134,14 +1134,14 @@ system.cpu1.dcache.overall_mshr_misses::cpu1.data 260 system.cpu1.dcache.overall_mshr_misses::total 260 # number of overall MSHR misses system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1530000 # number of ReadReq MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1530000 # number of ReadReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1383500 # number of WriteReq MSHR miss cycles -system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1383500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1381000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1381000 # number of WriteReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 422500 # number of SwapReq MSHR miss cycles system.cpu1.dcache.SwapReq_mshr_miss_latency::total 422500 # number of SwapReq MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2913500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.demand_mshr_miss_latency::total 2913500 # number of demand (read+write) MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2913500 # number of overall MSHR miss cycles -system.cpu1.dcache.overall_mshr_miss_latency::total 2913500 # number of overall MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2911000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2911000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2911000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2911000 # number of overall MSHR miss cycles system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003252 # mshr miss rate for ReadReq accesses system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003252 # mshr miss rate for ReadReq accesses system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002740 # mshr miss rate for WriteReq accesses @@ -1154,16 +1154,16 @@ system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003024 system.cpu1.dcache.overall_mshr_miss_rate::total 0.003024 # mshr miss rate for overall accesses system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9870.967742 # average ReadReq mshr miss latency system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9870.967742 # average ReadReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13176.190476 # average WriteReq mshr miss latency -system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13176.190476 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 13152.380952 # average WriteReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 13152.380952 # average WriteReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 7971.698113 # average SwapReq mshr miss latency system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 7971.698113 # average SwapReq mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency -system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11205.769231 # average overall mshr miss latency -system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11205.769231 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11196.153846 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11196.153846 # average overall mshr miss latency system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 173759 # number of cpu cycles simulated +system.cpu2.numCycles 173761 # number of cpu cycles simulated system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu2.BPredUnit.lookups 43658 # Number of BP lookups @@ -1180,17 +1180,17 @@ system.cpu2.fetch.Branches 43658 # Nu system.cpu2.fetch.predictedBranches 37372 # Number of branches that fetch has predicted taken system.cpu2.fetch.Cycles 88227 # Number of cycles fetch has run and was not squashing or blocked system.cpu2.fetch.SquashCycles 3786 # Number of cycles fetch has spent squashing -system.cpu2.fetch.BlockedCycles 41179 # Number of cycles fetch has spent blocked +system.cpu2.fetch.BlockedCycles 41181 # Number of cycles fetch has spent blocked system.cpu2.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu2.fetch.NoActiveThreadStallCycles 6107 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.NoActiveThreadStallCycles 6111 # Number of stall cycles due to no active thread to fetch from system.cpu2.fetch.PendingTrapStallCycles 690 # Number of stall cycles due to pending traps system.cpu2.fetch.CacheLines 25041 # Number of cache lines fetched system.cpu2.fetch.IcacheSquashes 268 # Number of outstanding Icache misses that were squashed -system.cpu2.fetch.rateDist::samples 172022 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::mean 1.367924 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::stdev 2.005612 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::samples 172028 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.367876 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.005593 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::0 83795 48.71% 48.71% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 83801 48.71% 48.71% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::1 46271 26.90% 75.61% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::2 8744 5.08% 80.69% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::3 3171 1.84% 82.54% # Number of instructions fetched each cycle (Total) @@ -1202,11 +1202,11 @@ system.cpu2.fetch.rateDist::8 3307 1.92% 100.00% # Nu system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.rateDist::total 172022 # Number of instructions fetched each cycle (Total) -system.cpu2.fetch.branchRate 0.251256 # Number of branch fetches per cycle -system.cpu2.fetch.rate 1.354249 # Number of inst fetches per cycle +system.cpu2.fetch.rateDist::total 172028 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.251253 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.354234 # Number of inst fetches per cycle system.cpu2.decode.IdleCycles 40935 # Number of cycles decode is idle -system.cpu2.decode.BlockedCycles 35177 # Number of cycles decode is blocked +system.cpu2.decode.BlockedCycles 35179 # Number of cycles decode is blocked system.cpu2.decode.RunCycles 79843 # Number of cycles decode is running system.cpu2.decode.UnblockCycles 7534 # Number of cycles decode is unblocking system.cpu2.decode.SquashCycles 2426 # Number of cycles decode is squashing @@ -1214,7 +1214,7 @@ system.cpu2.decode.DecodedInsts 231751 # Nu system.cpu2.rename.SquashCycles 2426 # Number of cycles rename is squashing system.cpu2.rename.IdleCycles 41648 # Number of cycles rename is idle system.cpu2.rename.BlockCycles 22387 # Number of cycles rename is blocking -system.cpu2.rename.serializeStallCycles 11999 # count of cycles rename stalled for serializing inst +system.cpu2.rename.serializeStallCycles 12001 # count of cycles rename stalled for serializing inst system.cpu2.rename.RunCycles 72579 # Number of cycles rename is running system.cpu2.rename.UnblockCycles 14876 # Number of cycles rename is unblocking system.cpu2.rename.RenamedInsts 229374 # Number of instructions processed by rename @@ -1236,14 +1236,14 @@ system.cpu2.iq.iqInstsAdded 186544 # Nu system.cpu2.iq.iqNonSpecInstsAdded 8963 # Number of non-speculative instructions added to the IQ system.cpu2.iq.iqInstsIssued 190992 # Number of instructions issued system.cpu2.iq.iqSquashedInstsIssued 109 # Number of squashed instructions issued -system.cpu2.iq.iqSquashedInstsExamined 11074 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu2.iq.iqSquashedOperandsExamined 10969 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedInstsExamined 11059 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 10957 # Number of squashed operands that are examined and possibly removed from graph system.cpu2.iq.iqSquashedNonSpecRemoved 650 # Number of squashed non-spec instructions that were removed -system.cpu2.iq.issued_per_cycle::samples 172022 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::mean 1.110277 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::stdev 1.273783 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::samples 172028 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.110238 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.273778 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::0 81441 47.34% 47.34% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 81447 47.35% 47.35% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::1 30126 17.51% 64.86% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::2 27409 15.93% 80.79% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::3 28202 16.39% 97.18% # Number of insts issued each cycle @@ -1255,7 +1255,7 @@ system.cpu2.iq.issued_per_cycle::8 55 0.03% 100.00% # Nu system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu2.iq.issued_per_cycle::total 172022 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 172028 # Number of insts issued each cycle system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu2.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available system.cpu2.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available @@ -1325,12 +1325,12 @@ system.cpu2.iq.FU_type_0::MemWrite 26665 13.96% 100.00% # Ty system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued system.cpu2.iq.FU_type_0::total 190992 # Type of FU issued -system.cpu2.iq.rate 1.099178 # Inst issue rate +system.cpu2.iq.rate 1.099165 # Inst issue rate system.cpu2.iq.fu_busy_cnt 287 # FU busy when requested system.cpu2.iq.fu_busy_rate 0.001503 # FU busy rate (busy events/executed inst) -system.cpu2.iq.int_inst_queue_reads 554402 # Number of integer instruction queue reads -system.cpu2.iq.int_inst_queue_writes 206628 # Number of integer instruction queue writes -system.cpu2.iq.int_inst_queue_wakeup_accesses 189208 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.int_inst_queue_reads 554408 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 206613 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 189211 # Number of integer instruction queue wakeup accesses system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses @@ -1361,31 +1361,31 @@ system.cpu2.iew.memOrderViolationEvents 47 # Nu system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly system.cpu2.iew.predictedNotTakenIncorrect 929 # Number of branches that were predicted not taken incorrectly system.cpu2.iew.branchMispredicts 1394 # Number of branch mispredicts detected at execute -system.cpu2.iew.iewExecutedInsts 189816 # Number of executed instructions +system.cpu2.iew.iewExecutedInsts 189819 # Number of executed instructions system.cpu2.iew.iewExecLoadInsts 60231 # Number of load instructions executed -system.cpu2.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute +system.cpu2.iew.iewExecSquashedInsts 1173 # Number of squashed instructions skipped in execute system.cpu2.iew.exec_swp 0 # number of swp insts executed system.cpu2.iew.exec_nop 31084 # number of nop insts executed -system.cpu2.iew.exec_refs 86812 # number of memory reference insts executed +system.cpu2.iew.exec_refs 86815 # number of memory reference insts executed system.cpu2.iew.exec_branches 40244 # Number of branches executed -system.cpu2.iew.exec_stores 26581 # Number of stores executed -system.cpu2.iew.exec_rate 1.092410 # Inst execution rate -system.cpu2.iew.wb_sent 189478 # cumulative count of insts sent to commit -system.cpu2.iew.wb_count 189208 # cumulative count of insts written-back +system.cpu2.iew.exec_stores 26584 # Number of stores executed +system.cpu2.iew.exec_rate 1.092414 # Inst execution rate +system.cpu2.iew.wb_sent 189481 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 189211 # cumulative count of insts written-back system.cpu2.iew.wb_producers 103581 # num instructions producing a value system.cpu2.iew.wb_consumers 108246 # num instructions consuming a value system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu2.iew.wb_rate 1.088911 # insts written-back per cycle +system.cpu2.iew.wb_rate 1.088915 # insts written-back per cycle system.cpu2.iew.wb_fanout 0.956904 # average fanout of values written-back system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu2.commit.commitSquashedInsts 12701 # The number of squashed insts skipped by commit system.cpu2.commit.commitNonSpecStalls 8313 # The number of times commit has been forced to stall to communicate backwards system.cpu2.commit.branchMispredicts 1282 # The number of times a branch was mispredicted -system.cpu2.commit.committed_per_cycle::samples 163490 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::mean 1.308153 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::stdev 1.875243 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::samples 163491 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 1.308145 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.875240 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::0 83402 51.01% 51.01% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 83403 51.01% 51.01% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::1 38322 23.44% 74.45% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::2 6091 3.73% 78.18% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::3 9201 5.63% 83.81% # Number of insts commited each cycle @@ -1397,7 +1397,7 @@ system.cpu2.commit.committed_per_cycle::8 815 0.50% 100.00% # N system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu2.commit.committed_per_cycle::total 163490 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 163491 # Number of insts commited each cycle system.cpu2.commit.committedInsts 213870 # Number of instructions committed system.cpu2.commit.committedOps 213870 # Number of ops (including micro ops) committed system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed @@ -1410,30 +1410,30 @@ system.cpu2.commit.int_insts 146274 # Nu system.cpu2.commit.function_calls 322 # Number of function calls committed. system.cpu2.commit.bw_lim_events 815 # number cycles where commit BW limit reached system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu2.rob.rob_reads 388659 # The number of ROB reads +system.cpu2.rob.rob_reads 388660 # The number of ROB reads system.cpu2.rob.rob_writes 455572 # The number of ROB writes system.cpu2.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu2.idleCycles 1737 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu2.quiesceCycles 35901 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.idleCycles 1733 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 35903 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt system.cpu2.committedInsts 176057 # Number of Instructions Simulated system.cpu2.committedOps 176057 # Number of Ops (including micro ops) Simulated system.cpu2.committedInsts_total 176057 # Number of Instructions Simulated -system.cpu2.cpi 0.986947 # CPI: Cycles Per Instruction -system.cpu2.cpi_total 0.986947 # CPI: Total CPI of All Threads -system.cpu2.ipc 1.013225 # IPC: Instructions Per Cycle -system.cpu2.ipc_total 1.013225 # IPC: Total IPC of All Threads -system.cpu2.int_regfile_reads 319017 # number of integer regfile reads +system.cpu2.cpi 0.986959 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.986959 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.013214 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.013214 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 319023 # number of integer regfile reads system.cpu2.int_regfile_writes 150022 # number of integer regfile writes system.cpu2.fp_regfile_writes 64 # number of floating regfile writes -system.cpu2.misc_regfile_reads 88362 # number of misc regfile reads +system.cpu2.misc_regfile_reads 88368 # number of misc regfile reads system.cpu2.misc_regfile_writes 648 # number of misc regfile writes system.cpu2.icache.replacements 319 # number of replacements -system.cpu2.icache.tagsinuse 80.119670 # Cycle average of tags in use +system.cpu2.icache.tagsinuse 80.119801 # Cycle average of tags in use system.cpu2.icache.total_refs 24566 # Total number of references to valid blocks. system.cpu2.icache.sampled_refs 429 # Sample count of references to valid blocks. system.cpu2.icache.avg_refs 57.263403 # Average number of references to valid blocks. system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 80.119670 # Average occupied blocks per requestor +system.cpu2.icache.occ_blocks::cpu2.inst 80.119801 # Average occupied blocks per requestor system.cpu2.icache.occ_percent::cpu2.inst 0.156484 # Average percentage of cache occupancy system.cpu2.icache.occ_percent::total 0.156484 # Average percentage of cache occupancy system.cpu2.icache.ReadReq_hits::cpu2.inst 24566 # number of ReadReq hits @@ -1448,12 +1448,12 @@ system.cpu2.icache.demand_misses::cpu2.inst 475 # system.cpu2.icache.demand_misses::total 475 # number of demand (read+write) misses system.cpu2.icache.overall_misses::cpu2.inst 475 # number of overall misses system.cpu2.icache.overall_misses::total 475 # number of overall misses -system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6356500 # number of ReadReq miss cycles -system.cpu2.icache.ReadReq_miss_latency::total 6356500 # number of ReadReq miss cycles -system.cpu2.icache.demand_miss_latency::cpu2.inst 6356500 # number of demand (read+write) miss cycles -system.cpu2.icache.demand_miss_latency::total 6356500 # number of demand (read+write) miss cycles -system.cpu2.icache.overall_miss_latency::cpu2.inst 6356500 # number of overall miss cycles -system.cpu2.icache.overall_miss_latency::total 6356500 # number of overall miss cycles +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6355000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 6355000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 6355000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 6355000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 6355000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 6355000 # number of overall miss cycles system.cpu2.icache.ReadReq_accesses::cpu2.inst 25041 # number of ReadReq accesses(hits+misses) system.cpu2.icache.ReadReq_accesses::total 25041 # number of ReadReq accesses(hits+misses) system.cpu2.icache.demand_accesses::cpu2.inst 25041 # number of demand (read+write) accesses @@ -1466,12 +1466,12 @@ system.cpu2.icache.demand_miss_rate::cpu2.inst 0.018969 system.cpu2.icache.demand_miss_rate::total 0.018969 # miss rate for demand accesses system.cpu2.icache.overall_miss_rate::cpu2.inst 0.018969 # miss rate for overall accesses system.cpu2.icache.overall_miss_rate::total 0.018969 # miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13382.105263 # average ReadReq miss latency -system.cpu2.icache.ReadReq_avg_miss_latency::total 13382.105263 # average ReadReq miss latency -system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency -system.cpu2.icache.demand_avg_miss_latency::total 13382.105263 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13382.105263 # average overall miss latency -system.cpu2.icache.overall_avg_miss_latency::total 13382.105263 # average overall miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 13378.947368 # average ReadReq miss latency +system.cpu2.icache.ReadReq_avg_miss_latency::total 13378.947368 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency +system.cpu2.icache.demand_avg_miss_latency::total 13378.947368 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 13378.947368 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::total 13378.947368 # average overall miss latency system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1492,32 +1492,32 @@ system.cpu2.icache.demand_mshr_misses::cpu2.inst 429 system.cpu2.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses system.cpu2.icache.overall_mshr_misses::cpu2.inst 429 # number of overall MSHR misses system.cpu2.icache.overall_mshr_misses::total 429 # number of overall MSHR misses -system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5130000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.ReadReq_mshr_miss_latency::total 5130000 # number of ReadReq MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5130000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.demand_mshr_miss_latency::total 5130000 # number of demand (read+write) MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5130000 # number of overall MSHR miss cycles -system.cpu2.icache.overall_mshr_miss_latency::total 5130000 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5129000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 5129000 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5129000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 5129000 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5129000 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 5129000 # number of overall MSHR miss cycles system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for ReadReq accesses system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.017132 # mshr miss rate for ReadReq accesses system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for demand accesses system.cpu2.icache.demand_mshr_miss_rate::total 0.017132 # mshr miss rate for demand accesses system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.017132 # mshr miss rate for overall accesses system.cpu2.icache.overall_mshr_miss_rate::total 0.017132 # mshr miss rate for overall accesses -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average ReadReq mshr miss latency -system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11958.041958 # average ReadReq mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency -system.cpu2.icache.demand_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11958.041958 # average overall mshr miss latency -system.cpu2.icache.overall_avg_mshr_miss_latency::total 11958.041958 # average overall mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average ReadReq mshr miss latency +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 11955.710956 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11955.710956 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::total 11955.710956 # average overall mshr miss latency system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 24.750979 # Cycle average of tags in use +system.cpu2.dcache.tagsinuse 24.751060 # Cycle average of tags in use system.cpu2.dcache.total_refs 32016 # Total number of references to valid blocks. system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. system.cpu2.dcache.avg_refs 1104 # Average number of references to valid blocks. system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 24.750979 # Average occupied blocks per requestor +system.cpu2.dcache.occ_blocks::cpu2.data 24.751060 # Average occupied blocks per requestor system.cpu2.dcache.occ_percent::cpu2.data 0.048342 # Average percentage of cache occupancy system.cpu2.dcache.occ_percent::total 0.048342 # Average percentage of cache occupancy system.cpu2.dcache.ReadReq_hits::cpu2.data 37788 # number of ReadReq hits @@ -1540,16 +1540,16 @@ system.cpu2.dcache.demand_misses::cpu2.data 530 # system.cpu2.dcache.demand_misses::total 530 # number of demand (read+write) misses system.cpu2.dcache.overall_misses::cpu2.data 530 # number of overall misses system.cpu2.dcache.overall_misses::total 530 # number of overall misses -system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5135500 # number of ReadReq miss cycles -system.cpu2.dcache.ReadReq_miss_latency::total 5135500 # number of ReadReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2343500 # number of WriteReq miss cycles -system.cpu2.dcache.WriteReq_miss_latency::total 2343500 # number of WriteReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5134500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 5134500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2352000 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 2352000 # number of WriteReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 565000 # number of SwapReq miss cycles system.cpu2.dcache.SwapReq_miss_latency::total 565000 # number of SwapReq miss cycles -system.cpu2.dcache.demand_miss_latency::cpu2.data 7479000 # number of demand (read+write) miss cycles -system.cpu2.dcache.demand_miss_latency::total 7479000 # number of demand (read+write) miss cycles -system.cpu2.dcache.overall_miss_latency::cpu2.data 7479000 # number of overall miss cycles -system.cpu2.dcache.overall_miss_latency::total 7479000 # number of overall miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 7486500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 7486500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 7486500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 7486500 # number of overall miss cycles system.cpu2.dcache.ReadReq_accesses::cpu2.data 38185 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.ReadReq_accesses::total 38185 # number of ReadReq accesses(hits+misses) system.cpu2.dcache.WriteReq_accesses::cpu2.data 25814 # number of WriteReq accesses(hits+misses) @@ -1570,16 +1570,16 @@ system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008281 system.cpu2.dcache.demand_miss_rate::total 0.008281 # miss rate for demand accesses system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008281 # miss rate for overall accesses system.cpu2.dcache.overall_miss_rate::total 0.008281 # miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12935.768262 # average ReadReq miss latency -system.cpu2.dcache.ReadReq_avg_miss_latency::total 12935.768262 # average ReadReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17620.300752 # average WriteReq miss latency -system.cpu2.dcache.WriteReq_avg_miss_latency::total 17620.300752 # average WriteReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12933.249370 # average ReadReq miss latency +system.cpu2.dcache.ReadReq_avg_miss_latency::total 12933.249370 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 17684.210526 # average WriteReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::total 17684.210526 # average WriteReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9576.271186 # average SwapReq miss latency system.cpu2.dcache.SwapReq_avg_miss_latency::total 9576.271186 # average SwapReq miss latency -system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency -system.cpu2.dcache.demand_avg_miss_latency::total 14111.320755 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14111.320755 # average overall miss latency -system.cpu2.dcache.overall_avg_miss_latency::total 14111.320755 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency +system.cpu2.dcache.demand_avg_miss_latency::total 14125.471698 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 14125.471698 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::total 14125.471698 # average overall miss latency system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1606,16 +1606,16 @@ system.cpu2.dcache.demand_mshr_misses::cpu2.data 271 system.cpu2.dcache.demand_mshr_misses::total 271 # number of demand (read+write) MSHR misses system.cpu2.dcache.overall_mshr_misses::cpu2.data 271 # number of overall MSHR misses system.cpu2.dcache.overall_mshr_misses::total 271 # number of overall MSHR misses -system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1409000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1409000 # number of ReadReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1142500 # number of WriteReq MSHR miss cycles -system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1142500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1408000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1408000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1144000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1144000 # number of WriteReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 447000 # number of SwapReq MSHR miss cycles system.cpu2.dcache.SwapReq_mshr_miss_latency::total 447000 # number of SwapReq MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2551500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.demand_mshr_miss_latency::total 2551500 # number of demand (read+write) MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2551500 # number of overall MSHR miss cycles -system.cpu2.dcache.overall_mshr_miss_latency::total 2551500 # number of overall MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2552000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2552000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2552000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2552000 # number of overall MSHR miss cycles system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.004452 # mshr miss rate for ReadReq accesses system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.004452 # mshr miss rate for ReadReq accesses system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003913 # mshr miss rate for WriteReq accesses @@ -1626,101 +1626,101 @@ system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.004234 system.cpu2.dcache.demand_mshr_miss_rate::total 0.004234 # mshr miss rate for demand accesses system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.004234 # mshr miss rate for overall accesses system.cpu2.dcache.overall_mshr_miss_rate::total 0.004234 # mshr miss rate for overall accesses -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8288.235294 # average ReadReq mshr miss latency -system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8288.235294 # average ReadReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11311.881188 # average WriteReq mshr miss latency -system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11311.881188 # average WriteReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8282.352941 # average ReadReq mshr miss latency +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8282.352941 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 11326.732673 # average WriteReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 11326.732673 # average WriteReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7576.271186 # average SwapReq mshr miss latency system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7576.271186 # average SwapReq mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency -system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9415.129151 # average overall mshr miss latency -system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9415.129151 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 9416.974170 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::total 9416.974170 # average overall mshr miss latency system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 173449 # number of cpu cycles simulated +system.cpu3.numCycles 173451 # number of cpu cycles simulated system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.BPredUnit.lookups 53688 # Number of BP lookups -system.cpu3.BPredUnit.condPredicted 50962 # Number of conditional branches predicted +system.cpu3.BPredUnit.lookups 53689 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 50963 # Number of conditional branches predicted system.cpu3.BPredUnit.condIncorrect 1276 # Number of conditional branches incorrect -system.cpu3.BPredUnit.BTBLookups 47521 # Number of BTB lookups -system.cpu3.BPredUnit.BTBHits 46771 # Number of BTB hits +system.cpu3.BPredUnit.BTBLookups 47522 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 46772 # Number of BTB hits system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu3.BPredUnit.usedRAS 661 # Number of times the RAS was used to get a target. system.cpu3.BPredUnit.RASInCorrect 232 # Number of incorrect RAS predictions. system.cpu3.fetch.icacheStallCycles 27478 # Number of cycles fetch is stalled on an Icache miss -system.cpu3.fetch.Insts 301358 # Number of instructions fetch has processed -system.cpu3.fetch.Branches 53688 # Number of branches that fetch encountered -system.cpu3.fetch.predictedBranches 47432 # Number of branches that fetch has predicted taken -system.cpu3.fetch.Cycles 105431 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.Insts 301364 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 53689 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 47433 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 105433 # Number of cycles fetch has run and was not squashing or blocked system.cpu3.fetch.SquashCycles 3739 # Number of cycles fetch has spent squashing system.cpu3.fetch.BlockedCycles 29902 # Number of cycles fetch has spent blocked system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu3.fetch.NoActiveThreadStallCycles 6125 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.NoActiveThreadStallCycles 6129 # Number of stall cycles due to no active thread to fetch from system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps system.cpu3.fetch.CacheLines 19205 # Number of cache lines fetched system.cpu3.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed -system.cpu3.fetch.rateDist::samples 172027 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::mean 1.751806 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::stdev 2.162661 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::samples 172033 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.751780 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.162655 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::0 66596 38.71% 38.71% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::1 53420 31.05% 69.77% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 66600 38.71% 38.71% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 53421 31.05% 69.77% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::2 5840 3.39% 73.16% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::3 3208 1.86% 75.03% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::4 724 0.42% 75.45% # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::5 37059 21.54% 96.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 37060 21.54% 96.99% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::6 1114 0.65% 97.64% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::7 769 0.45% 98.08% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::8 3297 1.92% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.rateDist::total 172027 # Number of instructions fetched each cycle (Total) -system.cpu3.fetch.branchRate 0.309532 # Number of branch fetches per cycle -system.cpu3.fetch.rate 1.737444 # Number of inst fetches per cycle +system.cpu3.fetch.rateDist::total 172033 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.309534 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.737459 # Number of inst fetches per cycle system.cpu3.decode.IdleCycles 32330 # Number of cycles decode is idle system.cpu3.decode.BlockedCycles 26595 # Number of cycles decode is blocked -system.cpu3.decode.RunCycles 99738 # Number of cycles decode is running +system.cpu3.decode.RunCycles 99740 # Number of cycles decode is running system.cpu3.decode.UnblockCycles 4852 # Number of cycles decode is unblocking system.cpu3.decode.SquashCycles 2387 # Number of cycles decode is squashing -system.cpu3.decode.DecodedInsts 297869 # Number of instructions handled by decode +system.cpu3.decode.DecodedInsts 297875 # Number of instructions handled by decode system.cpu3.rename.SquashCycles 2387 # Number of cycles rename is squashing system.cpu3.rename.IdleCycles 33042 # Number of cycles rename is idle system.cpu3.rename.BlockCycles 14161 # Number of cycles rename is blocking system.cpu3.rename.serializeStallCycles 11648 # count of cycles rename stalled for serializing inst -system.cpu3.rename.RunCycles 95158 # Number of cycles rename is running +system.cpu3.rename.RunCycles 95160 # Number of cycles rename is running system.cpu3.rename.UnblockCycles 9506 # Number of cycles rename is unblocking -system.cpu3.rename.RenamedInsts 295495 # Number of instructions processed by rename +system.cpu3.rename.RenamedInsts 295501 # Number of instructions processed by rename system.cpu3.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full system.cpu3.rename.LSQFullEvents 42 # Number of times rename has blocked due to LSQ full -system.cpu3.rename.RenamedOperands 206972 # Number of destination operands rename has renamed -system.cpu3.rename.RenameLookups 568769 # Number of register rename lookups that rename has made -system.cpu3.rename.int_rename_lookups 568769 # Number of integer rename lookups -system.cpu3.rename.CommittedMaps 194051 # Number of HB maps that are committed +system.cpu3.rename.RenamedOperands 206976 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 568781 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 568781 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 194055 # Number of HB maps that are committed system.cpu3.rename.UndoneMaps 12921 # Number of HB maps that are undone due to squashing system.cpu3.rename.serializingInsts 1094 # count of serializing insts renamed system.cpu3.rename.tempSerializingInsts 1213 # count of temporary serializing insts renamed system.cpu3.rename.skidInsts 12164 # count of insts added to the skid buffer -system.cpu3.memDep0.insertedLoads 84321 # Number of loads inserted to the mem dependence unit. -system.cpu3.memDep0.insertedStores 40263 # Number of stores inserted to the mem dependence unit. -system.cpu3.memDep0.conflictingLoads 40233 # Number of conflicting loads. -system.cpu3.memDep0.conflictingStores 35230 # Number of conflicting stores. -system.cpu3.iq.iqInstsAdded 245462 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.memDep0.insertedLoads 84323 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 40264 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 40234 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 35231 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 245467 # Number of instructions added to the IQ (excludes non-spec) system.cpu3.iq.iqNonSpecInstsAdded 6061 # Number of non-speculative instructions added to the IQ -system.cpu3.iq.iqInstsIssued 247263 # Number of instructions issued +system.cpu3.iq.iqInstsIssued 247268 # Number of instructions issued system.cpu3.iq.iqSquashedInstsIssued 84 # Number of squashed instructions issued -system.cpu3.iq.iqSquashedInstsExamined 10948 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu3.iq.iqSquashedOperandsExamined 10583 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedInstsExamined 10933 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 10571 # Number of squashed operands that are examined and possibly removed from graph system.cpu3.iq.iqSquashedNonSpecRemoved 569 # Number of squashed non-spec instructions that were removed -system.cpu3.iq.issued_per_cycle::samples 172027 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::mean 1.437350 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::stdev 1.311410 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::samples 172033 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.437329 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.311411 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::0 63993 37.20% 37.20% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 63997 37.20% 37.20% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::1 21775 12.66% 49.86% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::2 40281 23.42% 73.27% # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::3 41063 23.87% 97.14% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 40282 23.42% 73.27% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 41064 23.87% 97.14% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::4 3352 1.95% 99.09% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::5 1207 0.70% 99.79% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::6 253 0.15% 99.94% # Number of insts issued each cycle @@ -1729,7 +1729,7 @@ system.cpu3.iq.issued_per_cycle::8 55 0.03% 100.00% # Nu system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu3.iq.issued_per_cycle::total 172027 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 172033 # Number of insts issued each cycle system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available system.cpu3.iq.fu_full::IntAlu 11 3.83% 3.83% # attempts to use FU when none available system.cpu3.iq.fu_full::IntMult 0 0.00% 3.83% # attempts to use FU when none available @@ -1765,7 +1765,7 @@ system.cpu3.iq.fu_full::MemWrite 210 73.17% 100.00% # at system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu3.iq.FU_type_0::IntAlu 119304 48.25% 48.25% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 119306 48.25% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::IntMult 0 0.00% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 48.25% # Type of FU issued @@ -1794,23 +1794,23 @@ system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 48.25% # Ty system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 48.25% # Type of FU issued system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 48.25% # Type of FU issued -system.cpu3.iq.FU_type_0::MemRead 88373 35.74% 83.99% # Type of FU issued -system.cpu3.iq.FU_type_0::MemWrite 39586 16.01% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 88375 35.74% 83.99% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 39587 16.01% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu3.iq.FU_type_0::total 247263 # Type of FU issued -system.cpu3.iq.rate 1.425566 # Inst issue rate +system.cpu3.iq.FU_type_0::total 247268 # Type of FU issued +system.cpu3.iq.rate 1.425578 # Inst issue rate system.cpu3.iq.fu_busy_cnt 287 # FU busy when requested system.cpu3.iq.fu_busy_rate 0.001161 # FU busy rate (busy events/executed inst) -system.cpu3.iq.int_inst_queue_reads 666924 # Number of integer instruction queue reads -system.cpu3.iq.int_inst_queue_writes 262516 # Number of integer instruction queue writes -system.cpu3.iq.int_inst_queue_wakeup_accesses 245480 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.int_inst_queue_reads 666940 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 262506 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 245488 # Number of integer instruction queue wakeup accesses system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu3.iq.int_alu_accesses 247550 # Number of integer alu accesses +system.cpu3.iq.int_alu_accesses 247555 # Number of integer alu accesses system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses -system.cpu3.iew.lsq.thread0.forwLoads 34961 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.forwLoads 34962 # Number of loads that had data forwarded from stores system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu3.iew.lsq.thread0.squashedLoads 2463 # Number of loads squashed system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed @@ -1824,10 +1824,10 @@ system.cpu3.iew.iewIdleCycles 0 # Nu system.cpu3.iew.iewSquashCycles 2387 # Number of cycles IEW is squashing system.cpu3.iew.iewBlockCycles 786 # Number of cycles IEW is blocking system.cpu3.iew.iewUnblockCycles 47 # Number of cycles IEW is unblocking -system.cpu3.iew.iewDispatchedInsts 292666 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispatchedInsts 292672 # Number of instructions dispatched to IQ system.cpu3.iew.iewDispSquashedInsts 339 # Number of squashed instructions skipped by dispatch -system.cpu3.iew.iewDispLoadInsts 84321 # Number of dispatched load instructions -system.cpu3.iew.iewDispStoreInsts 40263 # Number of dispatched store instructions +system.cpu3.iew.iewDispLoadInsts 84323 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 40264 # Number of dispatched store instructions system.cpu3.iew.iewDispNonSpecInsts 1055 # Number of dispatched non-speculative instructions system.cpu3.iew.iewIQFullEvents 46 # Number of times the IQ has become full, causing a stall system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall @@ -1835,79 +1835,79 @@ system.cpu3.iew.memOrderViolationEvents 45 # Nu system.cpu3.iew.predictedTakenIncorrect 463 # Number of branches that were predicted taken incorrectly system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly system.cpu3.iew.branchMispredicts 1395 # Number of branch mispredicts detected at execute -system.cpu3.iew.iewExecutedInsts 246084 # Number of executed instructions -system.cpu3.iew.iewExecLoadInsts 83306 # Number of load instructions executed -system.cpu3.iew.iewExecSquashedInsts 1179 # Number of squashed instructions skipped in execute +system.cpu3.iew.iewExecutedInsts 246092 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 83308 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 1176 # Number of squashed instructions skipped in execute system.cpu3.iew.exec_swp 0 # number of swp insts executed -system.cpu3.iew.exec_nop 41143 # number of nop insts executed -system.cpu3.iew.exec_refs 122808 # number of memory reference insts executed -system.cpu3.iew.exec_branches 50377 # Number of branches executed -system.cpu3.iew.exec_stores 39502 # Number of stores executed -system.cpu3.iew.exec_rate 1.418769 # Inst execution rate -system.cpu3.iew.wb_sent 245746 # cumulative count of insts sent to commit -system.cpu3.iew.wb_count 245480 # cumulative count of insts written-back -system.cpu3.iew.wb_producers 139608 # num instructions producing a value -system.cpu3.iew.wb_consumers 144273 # num instructions consuming a value +system.cpu3.iew.exec_nop 41144 # number of nop insts executed +system.cpu3.iew.exec_refs 122814 # number of memory reference insts executed +system.cpu3.iew.exec_branches 50378 # Number of branches executed +system.cpu3.iew.exec_stores 39506 # Number of stores executed +system.cpu3.iew.exec_rate 1.418798 # Inst execution rate +system.cpu3.iew.wb_sent 245754 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 245488 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 139611 # num instructions producing a value +system.cpu3.iew.wb_consumers 144276 # num instructions consuming a value system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu3.iew.wb_rate 1.415286 # insts written-back per cycle -system.cpu3.iew.wb_fanout 0.967665 # average fanout of values written-back +system.cpu3.iew.wb_rate 1.415316 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.967666 # average fanout of values written-back system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu3.commit.commitSquashedInsts 12526 # The number of squashed insts skipped by commit system.cpu3.commit.commitNonSpecStalls 5492 # The number of times commit has been forced to stall to communicate backwards system.cpu3.commit.branchMispredicts 1276 # The number of times a branch was mispredicted -system.cpu3.commit.committed_per_cycle::samples 163516 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::mean 1.713105 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::stdev 2.043722 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::samples 163517 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.713131 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 2.043728 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::0 63247 38.68% 38.68% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::1 48404 29.60% 68.28% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 63246 38.68% 38.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 48405 29.60% 68.28% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::2 6092 3.73% 72.01% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::3 6399 3.91% 75.92% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::4 1556 0.95% 76.87% # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::5 35437 21.67% 98.54% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 35438 21.67% 98.54% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::6 553 0.34% 98.88% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::7 1016 0.62% 99.50% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::8 812 0.50% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu3.commit.committed_per_cycle::total 163516 # Number of insts commited each cycle -system.cpu3.commit.committedInsts 280120 # Number of instructions committed -system.cpu3.commit.committedOps 280120 # Number of ops (including micro ops) committed +system.cpu3.commit.committed_per_cycle::total 163517 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 280126 # Number of instructions committed +system.cpu3.commit.committedOps 280126 # Number of ops (including micro ops) committed system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed -system.cpu3.commit.refs 120652 # Number of memory references committed -system.cpu3.commit.loads 81858 # Number of loads committed +system.cpu3.commit.refs 120655 # Number of memory references committed +system.cpu3.commit.loads 81860 # Number of loads committed system.cpu3.commit.membars 4779 # Number of memory barriers committed -system.cpu3.commit.branches 49540 # Number of branches committed +system.cpu3.commit.branches 49541 # Number of branches committed system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. -system.cpu3.commit.int_insts 192312 # Number of committed integer instructions. +system.cpu3.commit.int_insts 192316 # Number of committed integer instructions. system.cpu3.commit.function_calls 322 # Number of function calls committed. system.cpu3.commit.bw_lim_events 812 # number cycles where commit BW limit reached system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu3.rob.rob_reads 454763 # The number of ROB reads -system.cpu3.rob.rob_writes 587684 # The number of ROB writes +system.cpu3.rob.rob_reads 454770 # The number of ROB reads +system.cpu3.rob.rob_writes 587696 # The number of ROB writes system.cpu3.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu3.idleCycles 1422 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu3.quiesceCycles 36211 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt -system.cpu3.committedInsts 235010 # Number of Instructions Simulated -system.cpu3.committedOps 235010 # Number of Ops (including micro ops) Simulated -system.cpu3.committedInsts_total 235010 # Number of Instructions Simulated -system.cpu3.cpi 0.738049 # CPI: Cycles Per Instruction -system.cpu3.cpi_total 0.738049 # CPI: Total CPI of All Threads -system.cpu3.ipc 1.354923 # IPC: Instructions Per Cycle -system.cpu3.ipc_total 1.354923 # IPC: Total IPC of All Threads -system.cpu3.int_regfile_reads 427031 # number of integer regfile reads -system.cpu3.int_regfile_writes 198982 # number of integer regfile writes +system.cpu3.idleCycles 1418 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 36213 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 235015 # Number of Instructions Simulated +system.cpu3.committedOps 235015 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 235015 # Number of Instructions Simulated +system.cpu3.cpi 0.738042 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.738042 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.354936 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.354936 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 427046 # number of integer regfile reads +system.cpu3.int_regfile_writes 198986 # number of integer regfile writes system.cpu3.fp_regfile_writes 64 # number of floating regfile writes -system.cpu3.misc_regfile_reads 124365 # number of misc regfile reads +system.cpu3.misc_regfile_reads 124374 # number of misc regfile reads system.cpu3.misc_regfile_writes 648 # number of misc regfile writes system.cpu3.icache.replacements 318 # number of replacements -system.cpu3.icache.tagsinuse 83.493816 # Cycle average of tags in use +system.cpu3.icache.tagsinuse 83.494084 # Cycle average of tags in use system.cpu3.icache.total_refs 18731 # Total number of references to valid blocks. system.cpu3.icache.sampled_refs 428 # Sample count of references to valid blocks. system.cpu3.icache.avg_refs 43.764019 # Average number of references to valid blocks. system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 83.493816 # Average occupied blocks per requestor +system.cpu3.icache.occ_blocks::cpu3.inst 83.494084 # Average occupied blocks per requestor system.cpu3.icache.occ_percent::cpu3.inst 0.163074 # Average percentage of cache occupancy system.cpu3.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy system.cpu3.icache.ReadReq_hits::cpu3.inst 18731 # number of ReadReq hits @@ -1922,12 +1922,12 @@ system.cpu3.icache.demand_misses::cpu3.inst 474 # system.cpu3.icache.demand_misses::total 474 # number of demand (read+write) misses system.cpu3.icache.overall_misses::cpu3.inst 474 # number of overall misses system.cpu3.icache.overall_misses::total 474 # number of overall misses -system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6191000 # number of ReadReq miss cycles -system.cpu3.icache.ReadReq_miss_latency::total 6191000 # number of ReadReq miss cycles -system.cpu3.icache.demand_miss_latency::cpu3.inst 6191000 # number of demand (read+write) miss cycles -system.cpu3.icache.demand_miss_latency::total 6191000 # number of demand (read+write) miss cycles -system.cpu3.icache.overall_miss_latency::cpu3.inst 6191000 # number of overall miss cycles -system.cpu3.icache.overall_miss_latency::total 6191000 # number of overall miss cycles +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6189500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 6189500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 6189500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 6189500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 6189500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 6189500 # number of overall miss cycles system.cpu3.icache.ReadReq_accesses::cpu3.inst 19205 # number of ReadReq accesses(hits+misses) system.cpu3.icache.ReadReq_accesses::total 19205 # number of ReadReq accesses(hits+misses) system.cpu3.icache.demand_accesses::cpu3.inst 19205 # number of demand (read+write) accesses @@ -1940,12 +1940,12 @@ system.cpu3.icache.demand_miss_rate::cpu3.inst 0.024681 system.cpu3.icache.demand_miss_rate::total 0.024681 # miss rate for demand accesses system.cpu3.icache.overall_miss_rate::cpu3.inst 0.024681 # miss rate for overall accesses system.cpu3.icache.overall_miss_rate::total 0.024681 # miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13061.181435 # average ReadReq miss latency -system.cpu3.icache.ReadReq_avg_miss_latency::total 13061.181435 # average ReadReq miss latency -system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency -system.cpu3.icache.demand_avg_miss_latency::total 13061.181435 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13061.181435 # average overall miss latency -system.cpu3.icache.overall_avg_miss_latency::total 13061.181435 # average overall miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13058.016878 # average ReadReq miss latency +system.cpu3.icache.ReadReq_avg_miss_latency::total 13058.016878 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency +system.cpu3.icache.demand_avg_miss_latency::total 13058.016878 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13058.016878 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::total 13058.016878 # average overall miss latency system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1966,44 +1966,44 @@ system.cpu3.icache.demand_mshr_misses::cpu3.inst 428 system.cpu3.icache.demand_mshr_misses::total 428 # number of demand (read+write) MSHR misses system.cpu3.icache.overall_mshr_misses::cpu3.inst 428 # number of overall MSHR misses system.cpu3.icache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4970500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.ReadReq_mshr_miss_latency::total 4970500 # number of ReadReq MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4970500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.demand_mshr_miss_latency::total 4970500 # number of demand (read+write) MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4970500 # number of overall MSHR miss cycles -system.cpu3.icache.overall_mshr_miss_latency::total 4970500 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4969500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 4969500 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4969500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 4969500 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4969500 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 4969500 # number of overall MSHR miss cycles system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for ReadReq accesses system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.022286 # mshr miss rate for ReadReq accesses system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for demand accesses system.cpu3.icache.demand_mshr_miss_rate::total 0.022286 # mshr miss rate for demand accesses system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.022286 # mshr miss rate for overall accesses system.cpu3.icache.overall_mshr_miss_rate::total 0.022286 # mshr miss rate for overall accesses -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average ReadReq mshr miss latency -system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11613.317757 # average ReadReq mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency -system.cpu3.icache.demand_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11613.317757 # average overall mshr miss latency -system.cpu3.icache.overall_avg_mshr_miss_latency::total 11613.317757 # average overall mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average ReadReq mshr miss latency +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11610.981308 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11610.981308 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::total 11610.981308 # average overall mshr miss latency system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 25.854093 # Cycle average of tags in use -system.cpu3.dcache.total_refs 44811 # Total number of references to valid blocks. +system.cpu3.dcache.tagsinuse 25.854191 # Cycle average of tags in use +system.cpu3.dcache.total_refs 44812 # Total number of references to valid blocks. system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1600.392857 # Average number of references to valid blocks. +system.cpu3.dcache.avg_refs 1600.428571 # Average number of references to valid blocks. system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 25.854093 # Average occupied blocks per requestor +system.cpu3.dcache.occ_blocks::cpu3.data 25.854191 # Average occupied blocks per requestor system.cpu3.dcache.occ_percent::cpu3.data 0.050496 # Average percentage of cache occupancy system.cpu3.dcache.occ_percent::total 0.050496 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 47901 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 47901 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 38585 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 38585 # number of WriteReq hits +system.cpu3.dcache.ReadReq_hits::cpu3.data 47902 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 47902 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 38586 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 38586 # number of WriteReq hits system.cpu3.dcache.SwapReq_hits::cpu3.data 11 # number of SwapReq hits system.cpu3.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 86486 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 86486 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 86486 # number of overall hits -system.cpu3.dcache.overall_hits::total 86486 # number of overall hits +system.cpu3.dcache.demand_hits::cpu3.data 86488 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 86488 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 86488 # number of overall hits +system.cpu3.dcache.overall_hits::total 86488 # number of overall hits system.cpu3.dcache.ReadReq_misses::cpu3.data 426 # number of ReadReq misses system.cpu3.dcache.ReadReq_misses::total 426 # number of ReadReq misses system.cpu3.dcache.WriteReq_misses::cpu3.data 142 # number of WriteReq misses @@ -2014,26 +2014,26 @@ system.cpu3.dcache.demand_misses::cpu3.data 568 # system.cpu3.dcache.demand_misses::total 568 # number of demand (read+write) misses system.cpu3.dcache.overall_misses::cpu3.data 568 # number of overall misses system.cpu3.dcache.overall_misses::total 568 # number of overall misses -system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5342000 # number of ReadReq miss cycles -system.cpu3.dcache.ReadReq_miss_latency::total 5342000 # number of ReadReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2332500 # number of WriteReq miss cycles -system.cpu3.dcache.WriteReq_miss_latency::total 2332500 # number of WriteReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5341000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 5341000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2325000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 2325000 # number of WriteReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 555000 # number of SwapReq miss cycles system.cpu3.dcache.SwapReq_miss_latency::total 555000 # number of SwapReq miss cycles -system.cpu3.dcache.demand_miss_latency::cpu3.data 7674500 # number of demand (read+write) miss cycles -system.cpu3.dcache.demand_miss_latency::total 7674500 # number of demand (read+write) miss cycles -system.cpu3.dcache.overall_miss_latency::cpu3.data 7674500 # number of overall miss cycles -system.cpu3.dcache.overall_miss_latency::total 7674500 # number of overall miss cycles -system.cpu3.dcache.ReadReq_accesses::cpu3.data 48327 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 48327 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 38727 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 38727 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.demand_miss_latency::cpu3.data 7666000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 7666000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 7666000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 7666000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 48328 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 48328 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 38728 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 38728 # number of WriteReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::cpu3.data 67 # number of SwapReq accesses(hits+misses) system.cpu3.dcache.SwapReq_accesses::total 67 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 87054 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 87054 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 87054 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 87054 # number of overall (read+write) accesses +system.cpu3.dcache.demand_accesses::cpu3.data 87056 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 87056 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 87056 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 87056 # number of overall (read+write) accesses system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008815 # miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_miss_rate::total 0.008815 # miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003667 # miss rate for WriteReq accesses @@ -2044,16 +2044,16 @@ system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006525 system.cpu3.dcache.demand_miss_rate::total 0.006525 # miss rate for demand accesses system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006525 # miss rate for overall accesses system.cpu3.dcache.overall_miss_rate::total 0.006525 # miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12539.906103 # average ReadReq miss latency -system.cpu3.dcache.ReadReq_avg_miss_latency::total 12539.906103 # average ReadReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16426.056338 # average WriteReq miss latency -system.cpu3.dcache.WriteReq_avg_miss_latency::total 16426.056338 # average WriteReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 12537.558685 # average ReadReq miss latency +system.cpu3.dcache.ReadReq_avg_miss_latency::total 12537.558685 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 16373.239437 # average WriteReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::total 16373.239437 # average WriteReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 9910.714286 # average SwapReq miss latency system.cpu3.dcache.SwapReq_avg_miss_latency::total 9910.714286 # average SwapReq miss latency -system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency -system.cpu3.dcache.demand_avg_miss_latency::total 13511.443662 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13511.443662 # average overall miss latency -system.cpu3.dcache.overall_avg_miss_latency::total 13511.443662 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency +system.cpu3.dcache.demand_avg_miss_latency::total 13496.478873 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 13496.478873 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::total 13496.478873 # average overall miss latency system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2080,16 +2080,16 @@ system.cpu3.dcache.demand_mshr_misses::cpu3.data 262 system.cpu3.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses system.cpu3.dcache.overall_mshr_misses::cpu3.data 262 # number of overall MSHR misses system.cpu3.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses -system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1265000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1265000 # number of ReadReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1159500 # number of WriteReq MSHR miss cycles -system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1159500 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1264000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1264000 # number of ReadReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1158000 # number of WriteReq MSHR miss cycles +system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1158000 # number of WriteReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 443000 # number of SwapReq MSHR miss cycles system.cpu3.dcache.SwapReq_mshr_miss_latency::total 443000 # number of SwapReq MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2424500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.demand_mshr_miss_latency::total 2424500 # number of demand (read+write) MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2424500 # number of overall MSHR miss cycles -system.cpu3.dcache.overall_mshr_miss_latency::total 2424500 # number of overall MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2422000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.demand_mshr_miss_latency::total 2422000 # number of demand (read+write) MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2422000 # number of overall MSHR miss cycles +system.cpu3.dcache.overall_mshr_miss_latency::total 2422000 # number of overall MSHR miss cycles system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.003166 # mshr miss rate for ReadReq accesses system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.003166 # mshr miss rate for ReadReq accesses system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002815 # mshr miss rate for WriteReq accesses @@ -2100,32 +2100,32 @@ system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003010 system.cpu3.dcache.demand_mshr_miss_rate::total 0.003010 # mshr miss rate for demand accesses system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003010 # mshr miss rate for overall accesses system.cpu3.dcache.overall_mshr_miss_rate::total 0.003010 # mshr miss rate for overall accesses -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8267.973856 # average ReadReq mshr miss latency -system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8267.973856 # average ReadReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10637.614679 # average WriteReq mshr miss latency -system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10637.614679 # average WriteReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8261.437908 # average ReadReq mshr miss latency +system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8261.437908 # average ReadReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 10623.853211 # average WriteReq mshr miss latency +system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 10623.853211 # average WriteReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 7910.714286 # average SwapReq mshr miss latency system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 7910.714286 # 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Cycle average of tags in use +system.l2c.tagsinuse 425.291959 # Cycle average of tags in use system.l2c.total_refs 1448 # Total number of references to valid blocks. system.l2c.sampled_refs 525 # Sample count of references to valid blocks. system.l2c.avg_refs 2.758095 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.828895 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 289.891501 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 59.268437 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 63.508816 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 5.639642 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 2.310248 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.728233 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 2.354110 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.766714 # Average occupied blocks per requestor +system.l2c.occ_blocks::writebacks 0.828889 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 289.887816 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 59.267955 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 63.508377 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 5.639601 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 2.310233 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.728238 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.inst 2.354132 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.766718 # Average occupied blocks per requestor system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy system.l2c.occ_percent::cpu0.data 0.000904 # Average percentage of cache occupancy @@ -2135,7 +2135,7 @@ system.l2c.occ_percent::cpu2.inst 0.000035 # Av system.l2c.occ_percent::cpu2.data 0.000011 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.inst 0.000036 # Average percentage of cache occupancy system.l2c.occ_percent::cpu3.data 0.000012 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.006490 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.006489 # Average percentage of cache occupancy system.l2c.ReadReq_hits::cpu0.inst 229 # number of ReadReq hits system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits system.l2c.ReadReq_hits::cpu1.inst 342 # number of ReadReq hits @@ -2204,38 +2204,38 @@ system.l2c.overall_misses::cpu2.data 13 # nu system.l2c.overall_misses::cpu3.inst 4 # number of overall misses system.l2c.overall_misses::cpu3.data 13 # number of overall misses system.l2c.overall_misses::total 668 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0.inst 17565000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu0.inst 17552500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu0.data 4069000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1.inst 4146500 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1.inst 4145500 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu1.data 381000 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2.inst 396000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2.inst 395000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3.inst 233000 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3.inst 232000 # number of ReadReq miss cycles system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 26927500 # 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number of ReadReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0.data 5008000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1.data 878500 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2.data 701000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3.data 660000 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 7247500 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0.inst 17552500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu0.data 9077000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.inst 4145500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1.data 1259500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.inst 395000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2.data 769500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.inst 232000 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3.data 728500 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 34159500 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0.inst 17552500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu0.data 9077000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.inst 4145500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1.data 1259500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.inst 395000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2.data 769500 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.inst 232000 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3.data 728500 # number of overall miss cycles +system.l2c.overall_miss_latency::total 34159500 # number of overall miss cycles system.l2c.ReadReq_accesses::cpu0.inst 588 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses) system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses) @@ -2312,38 +2312,38 @@ system.l2c.overall_miss_rate::cpu2.data 0.541667 # mi system.l2c.overall_miss_rate::cpu3.inst 0.009346 # miss rate for overall accesses system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses system.l2c.overall_miss_rate::total 0.315690 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48927.576602 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu0.inst 48892.757660 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu0.data 54986.486486 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49957.831325 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1.inst 49945.783133 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu1.data 54428.571429 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49500 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2.inst 49375 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu2.data 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3.inst 58250 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3.inst 58000 # average ReadReq miss latency system.l2c.ReadReq_avg_miss_latency::cpu3.data 68500 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 50144.320298 # average ReadReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0.data 53196.808511 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1.data 67769.230769 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2.data 58291.666667 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3.data 55125 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 55286.259542 # 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average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1.data 62975 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.inst 49375 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2.data 59192.307692 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.inst 58000 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3.data 56038.461538 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 51136.976048 # average overall miss latency system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked @@ -2401,43 +2401,43 @@ system.l2c.overall_mshr_misses::cpu2.data 13 # n system.l2c.overall_mshr_misses::cpu3.inst 4 # number of overall MSHR misses system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses system.l2c.overall_mshr_misses::total 659 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13017059 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13005059 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3150576 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3026126 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu1.data 293010 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 103002 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 181507 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 180507 # number of ReadReq MSHR miss cycles system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56002 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 19883284 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 19870284 # number of ReadReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 193013 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 181515 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 153009 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200519 # number of UpgradeReq MSHR miss cycles system.l2c.UpgradeReq_mshr_miss_latency::total 728056 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 3829610 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 719513 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 549018 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 511018 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 5609159 # 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number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 25492443 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 606020 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 180507 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 566020 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 25482443 # number of overall MSHR miss cycles system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.607143 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.190588 # mshr miss rate for ReadReq accesses @@ -2475,43 +2475,43 @@ system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 system.l2c.overall_mshr_miss_rate::cpu3.inst 0.009346 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses system.l2c.overall_mshr_miss_rate::total 0.311437 # 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average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 37633.113636 # average ReadReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10158.578947 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10084.166667 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10200.600000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10025.950000 # average UpgradeReq mshr miss latency system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10111.888889 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40740.531915 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 55347.153846 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 45751.500000 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 42584.833333 # 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average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43616.923077 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 38683.525038 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 46616.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 45126.750000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 43540 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 38668.350531 # average overall mshr miss latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- |