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-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini19
-rwxr-xr-xtests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr3
-rwxr-xr-xtests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout13
-rw-r--r--tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt2356
4 files changed, 1200 insertions, 1191 deletions
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
index f716f7509..5c4d73bb2 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/config.ini
@@ -65,7 +65,7 @@ SSITSize=1024
activity=0
backComSize=5
branchPred=system.cpu.branchPred
-cachePorts=200
+cacheStorePorts=200
checker=Null
clk_domain=system.cpu_clk_domain
commitToDecodeDelay=1
@@ -139,6 +139,7 @@ socket_id=0
squashWidth=8
store_set_clear_period=250000
switched_out=false
+syscallRetryLatency=10000
system=system
tracer=system.cpu.tracer
trapLatency=13
@@ -725,7 +726,7 @@ type=ExeTracer
eventq_index=0
[system.cpu.workload0]
-type=LiveProcess
+type=Process
cmd=hello
cwd=
drivers=
@@ -734,21 +735,22 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
+pgid=100
pid=100
-ppid=99
+ppid=0
simpoint=0
system=system
uid=100
useArchPT=false
[system.cpu.workload1]
-type=LiveProcess
+type=Process
cmd=hello
cwd=
drivers=
@@ -757,14 +759,15 @@ env=
errout=cerr
euid=100
eventq_index=0
-executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
+executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
kvmInSE=false
max_stack_size=67108864
output=cout
-pid=100
-ppid=99
+pgid=100
+pid=101
+ppid=100
simpoint=0
system=system
uid=100
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
index b4f78c475..b1d1f26e1 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simerr
@@ -2,3 +2,6 @@ warn: DRAM device capacity (8192 Mbytes) does not match the address range assign
warn: Sockets disabled, not accepting gdb connections
warn: ClockedObject: More than one power state change request encountered within the same simulation tick
warn: ClockedObject: Already in the requested power state, request ignored
+info: Entering event queue @ 0. Starting simulation...
+info: Increasing stack size by one page.
+info: Increasing stack size by one page.
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
index c8d7343f8..98b12d0fa 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/simout
@@ -3,15 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Nov 29 2016 18:06:09
-gem5 started Nov 29 2016 18:06:32
-gem5 executing on zizzer, pid 27586
-command line: /z/powerjg/gem5-upstream/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt -re /z/powerjg/gem5-upstream/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
+gem5 compiled Mar 29 2017 21:35:16
+gem5 started Mar 29 2017 21:35:26
+gem5 executing on gabeblack-desktop.mtv.corp.google.com, pid 87431
+command line: /usr/local/google/home/gabeblack/gem5/gem5-public/build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt --stats-file 'text://stats.txt?desc=False' -re /usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../run.py quick/se/01.hello-2T-smt/alpha/linux/o3-timing-mt
Global frequency set at 1000000000000 ticks per second
-info: Entering event queue @ 0. Starting simulation...
-info: Increasing stack size by one page.
-info: Increasing stack size by one page.
Hello world!
Hello world!
-Exiting @ tick 26661500 because target called exit()
+Exiting @ tick 27117500 because target called exit()
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
index 255fcdbff..d3b8cc574 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing-mt/stats.txt
@@ -1,1179 +1,1185 @@
---------- Begin Simulation Statistics ----------
-sim_seconds 0.000026 # Number of seconds simulated
-sim_ticks 25563000 # Number of ticks simulated
-final_tick 25563000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
-sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 149418 # Simulator instruction rate (inst/s)
-host_op_rate 149401 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 290951659 # Simulator tick rate (ticks/s)
-host_mem_usage 254508 # Number of bytes of host memory used
-host_seconds 0.09 # Real time elapsed on the host
-sim_insts 13125 # Number of instructions simulated
-sim_ops 13125 # Number of ops (including micro ops) simulated
-system.voltage_domain.voltage 1 # Voltage in Volts
-system.clk_domain.clock 1000 # Clock period in ticks
-system.physmem.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states
-system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 11200 # Number of bytes read from this memory
-system.physmem.bytes_read::total 31488 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 20288 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 20288 # Number of instructions bytes read from this memory
-system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 175 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 492 # Number of read requests responded to by this memory
-system.physmem.bw_read::cpu.inst 793647068 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 438133239 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 1231780307 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 793647068 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 793647068 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 793647068 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 438133239 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 1231780307 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 492 # Number of read requests accepted
-system.physmem.writeReqs 0 # Number of write requests accepted
-system.physmem.readBursts 492 # Number of DRAM read bursts, including those serviced by the write queue
-system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
-system.physmem.bytesReadDRAM 31488 # Total number of bytes read from DRAM
-system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
-system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
-system.physmem.bytesReadSys 31488 # Total read bytes from the system interface side
-system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
-system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
-system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
-system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
-system.physmem.perBankRdBursts::0 14 # Per bank write bursts
-system.physmem.perBankRdBursts::1 155 # Per bank write bursts
-system.physmem.perBankRdBursts::2 30 # Per bank write bursts
-system.physmem.perBankRdBursts::3 55 # Per bank write bursts
-system.physmem.perBankRdBursts::4 70 # Per bank write bursts
-system.physmem.perBankRdBursts::5 0 # Per bank write bursts
-system.physmem.perBankRdBursts::6 6 # Per bank write bursts
-system.physmem.perBankRdBursts::7 3 # Per bank write bursts
-system.physmem.perBankRdBursts::8 43 # Per bank write bursts
-system.physmem.perBankRdBursts::9 15 # Per bank write bursts
-system.physmem.perBankRdBursts::10 26 # Per bank write bursts
-system.physmem.perBankRdBursts::11 0 # Per bank write bursts
-system.physmem.perBankRdBursts::12 0 # Per bank write bursts
-system.physmem.perBankRdBursts::13 2 # Per bank write bursts
-system.physmem.perBankRdBursts::14 44 # Per bank write bursts
-system.physmem.perBankRdBursts::15 29 # Per bank write bursts
-system.physmem.perBankWrBursts::0 0 # Per bank write bursts
-system.physmem.perBankWrBursts::1 0 # Per bank write bursts
-system.physmem.perBankWrBursts::2 0 # Per bank write bursts
-system.physmem.perBankWrBursts::3 0 # Per bank write bursts
-system.physmem.perBankWrBursts::4 0 # Per bank write bursts
-system.physmem.perBankWrBursts::5 0 # Per bank write bursts
-system.physmem.perBankWrBursts::6 0 # Per bank write bursts
-system.physmem.perBankWrBursts::7 0 # Per bank write bursts
-system.physmem.perBankWrBursts::8 0 # Per bank write bursts
-system.physmem.perBankWrBursts::9 0 # Per bank write bursts
-system.physmem.perBankWrBursts::10 0 # Per bank write bursts
-system.physmem.perBankWrBursts::11 0 # Per bank write bursts
-system.physmem.perBankWrBursts::12 0 # Per bank write bursts
-system.physmem.perBankWrBursts::13 0 # Per bank write bursts
-system.physmem.perBankWrBursts::14 0 # Per bank write bursts
-system.physmem.perBankWrBursts::15 0 # Per bank write bursts
-system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
-system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
-system.physmem.totGap 25412500 # Total gap between requests
-system.physmem.readPktSize::0 0 # Read request sizes (log2)
-system.physmem.readPktSize::1 0 # Read request sizes (log2)
-system.physmem.readPktSize::2 0 # Read request sizes (log2)
-system.physmem.readPktSize::3 0 # Read request sizes (log2)
-system.physmem.readPktSize::4 0 # Read request sizes (log2)
-system.physmem.readPktSize::5 0 # Read request sizes (log2)
-system.physmem.readPktSize::6 492 # Read request sizes (log2)
-system.physmem.writePktSize::0 0 # Write request sizes (log2)
-system.physmem.writePktSize::1 0 # Write request sizes (log2)
-system.physmem.writePktSize::2 0 # Write request sizes (log2)
-system.physmem.writePktSize::3 0 # Write request sizes (log2)
-system.physmem.writePktSize::4 0 # Write request sizes (log2)
-system.physmem.writePktSize::5 0 # Write request sizes (log2)
-system.physmem.writePktSize::6 0 # Write request sizes (log2)
-system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 142 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
-system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::mean 284.647619 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::gmean 175.785516 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::stdev 296.753264 # Bytes accessed per row activation
-system.physmem.bytesPerActivate::0-127 38 36.19% 36.19% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::128-255 31 29.52% 65.71% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::256-383 6 5.71% 71.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::384-511 9 8.57% 80.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::512-639 3 2.86% 82.86% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::640-767 4 3.81% 86.67% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::768-895 5 4.76% 91.43% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::896-1023 3 2.86% 94.29% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation
-system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation
-system.physmem.totQLat 8936250 # Total ticks spent queuing
-system.physmem.totMemAccLat 18161250 # Total ticks spent from burst creation until serviced by the DRAM
-system.physmem.totBusLat 2460000 # Total ticks spent in databus transfers
-system.physmem.avgQLat 18163.11 # Average queueing delay per DRAM burst
-system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
-system.physmem.avgMemAccLat 36913.11 # Average memory access latency per DRAM burst
-system.physmem.avgRdBW 1231.78 # Average DRAM read bandwidth in MiByte/s
-system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
-system.physmem.avgRdBWSys 1231.78 # Average system read bandwidth in MiByte/s
-system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
-system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
-system.physmem.busUtil 9.62 # Data bus utilization in percentage
-system.physmem.busUtilRead 9.62 # Data bus utilization in percentage for reads
-system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
-system.physmem.avgRdQLen 1.77 # Average read queue length when enqueuing
-system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
-system.physmem.readRowHits 382 # Number of row buffer hits during reads
-system.physmem.writeRowHits 0 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 77.64 # Row buffer hit rate for reads
-system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
-system.physmem.avgGap 51651.42 # Average gap between requests
-system.physmem.pageHitRate 77.64 # Row buffer hit rate, read and write combined
-system.physmem_0.actEnergy 564060 # Energy for activate commands per rank (pJ)
-system.physmem_0.preEnergy 288420 # Energy for precharge commands per rank (pJ)
-system.physmem_0.readEnergy 2377620 # Energy for read commands per rank (pJ)
-system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_0.actBackEnergy 4052700 # Energy for active background per rank (pJ)
-system.physmem_0.preBackEnergy 52800 # Energy for precharge background per rank (pJ)
-system.physmem_0.actPowerDownEnergy 7250970 # Energy for active power-down per rank (pJ)
-system.physmem_0.prePowerDownEnergy 244800 # Energy for precharge power-down per rank (pJ)
-system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.physmem_0.totalEnergy 16675290 # Total energy per rank (pJ)
-system.physmem_0.averagePower 652.302186 # Core power per rank (mW)
-system.physmem_0.totalIdleTime 16451750 # Total Idle time Per DRAM Rank
-system.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states
-system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
-system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
-system.physmem_0.memoryStateTime::PRE_PDN 637500 # Time in different power states
-system.physmem_0.memoryStateTime::ACT 8201250 # Time in different power states
-system.physmem_0.memoryStateTime::ACT_PDN 15903750 # Time in different power states
-system.physmem_1.actEnergy 221340 # Energy for activate commands per rank (pJ)
-system.physmem_1.preEnergy 110055 # Energy for precharge commands per rank (pJ)
-system.physmem_1.readEnergy 1135260 # Energy for read commands per rank (pJ)
-system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
-system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
-system.physmem_1.actBackEnergy 2074800 # Energy for active background per rank (pJ)
-system.physmem_1.preBackEnergy 239040 # Energy for precharge background per rank (pJ)
-system.physmem_1.actPowerDownEnergy 8714160 # Energy for active power-down per rank (pJ)
-system.physmem_1.prePowerDownEnergy 492000 # Energy for precharge power-down per rank (pJ)
-system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
-system.physmem_1.totalEnergy 14830575 # Total energy per rank (pJ)
-system.physmem_1.averagePower 580.140824 # Core power per rank (mW)
-system.physmem_1.totalIdleTime 20195750 # Total Idle time Per DRAM Rank
-system.physmem_1.memoryStateTime::IDLE 443500 # Time in different power states
-system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
-system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
-system.physmem_1.memoryStateTime::PRE_PDN 1279500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT 3943500 # Time in different power states
-system.physmem_1.memoryStateTime::ACT_PDN 19116500 # Time in different power states
-system.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states
-system.cpu.branchPred.lookups 5883 # Number of BP lookups
-system.cpu.branchPred.condPredicted 3464 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1044 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 4417 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 1219 # Number of BTB hits
-system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 27.597917 # BTB Hit Percentage
-system.cpu.branchPred.usedRAS 791 # Number of times the RAS was used to get a target.
-system.cpu.branchPred.RASInCorrect 72 # Number of incorrect RAS predictions.
-system.cpu.branchPred.indirectLookups 1012 # Number of indirect predictor lookups.
-system.cpu.branchPred.indirectHits 40 # Number of indirect target hits.
-system.cpu.branchPred.indirectMisses 972 # Number of indirect misses.
-system.cpu.branchPredindirectMispredicted 246 # Number of mispredicted indirect branches.
-system.cpu_clk_domain.clock 500 # Clock period in ticks
-system.cpu.dtb.fetch_hits 0 # ITB hits
-system.cpu.dtb.fetch_misses 0 # ITB misses
-system.cpu.dtb.fetch_acv 0 # ITB acv
-system.cpu.dtb.fetch_accesses 0 # ITB accesses
-system.cpu.dtb.read_hits 4167 # DTB read hits
-system.cpu.dtb.read_misses 88 # DTB read misses
-system.cpu.dtb.read_acv 0 # DTB read access violations
-system.cpu.dtb.read_accesses 4255 # DTB read accesses
-system.cpu.dtb.write_hits 2106 # DTB write hits
-system.cpu.dtb.write_misses 58 # DTB write misses
-system.cpu.dtb.write_acv 0 # DTB write access violations
-system.cpu.dtb.write_accesses 2164 # DTB write accesses
-system.cpu.dtb.data_hits 6273 # DTB hits
-system.cpu.dtb.data_misses 146 # DTB misses
-system.cpu.dtb.data_acv 0 # DTB access violations
-system.cpu.dtb.data_accesses 6419 # DTB accesses
-system.cpu.itb.fetch_hits 4394 # ITB hits
-system.cpu.itb.fetch_misses 52 # ITB misses
-system.cpu.itb.fetch_acv 0 # ITB acv
-system.cpu.itb.fetch_accesses 4446 # ITB accesses
-system.cpu.itb.read_hits 0 # DTB read hits
-system.cpu.itb.read_misses 0 # DTB read misses
-system.cpu.itb.read_acv 0 # DTB read access violations
-system.cpu.itb.read_accesses 0 # DTB read accesses
-system.cpu.itb.write_hits 0 # DTB write hits
-system.cpu.itb.write_misses 0 # DTB write misses
-system.cpu.itb.write_acv 0 # DTB write access violations
-system.cpu.itb.write_accesses 0 # DTB write accesses
-system.cpu.itb.data_hits 0 # DTB hits
-system.cpu.itb.data_misses 0 # DTB misses
-system.cpu.itb.data_acv 0 # DTB access violations
-system.cpu.itb.data_accesses 0 # DTB accesses
-system.cpu.workload0.num_syscalls 18 # Number of system calls
-system.cpu.workload1.num_syscalls 18 # Number of system calls
-system.cpu.pwrStateResidencyTicks::ON 25563000 # Cumulative time (in ticks) in various power states
-system.cpu.numCycles 51127 # number of cpu cycles simulated
-system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
-system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 960 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 33549 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 5883 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 2050 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 9426 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 1118 # Number of cycles fetch has spent squashing
-system.cpu.fetch.MiscStallCycles 44 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.CacheLines 4394 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 660 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.rateDist::samples 17609 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 1.905219 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.084149 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 11843 67.26% 67.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 481 2.73% 69.99% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 427 2.42% 72.41% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 478 2.71% 75.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 423 2.40% 77.53% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 397 2.25% 79.78% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 518 2.94% 82.72% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 341 1.94% 84.66% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 2701 15.34% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 17609 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.115066 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.656189 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 18146 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 10408 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 5085 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 609 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 960 # Number of cycles decode is squashing
-system.cpu.decode.BranchResolved 1283 # Number of times decode resolved a branch
-system.cpu.decode.BranchMispred 162 # Number of times decode detected a branch misprediction
-system.cpu.decode.DecodedInsts 29203 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 227 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 960 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 18571 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 3611 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 1447 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 5248 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 5371 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 27754 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 18 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 466 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LQFullEvents 832 # Number of times rename has blocked due to LQ full
-system.cpu.rename.SQFullEvents 4294 # Number of times rename has blocked due to SQ full
-system.cpu.rename.RenamedOperands 20868 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 34818 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 34800 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 9408 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 11460 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 54 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 1221 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 2635 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 1335 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 7 # Number of conflicting stores.
-system.cpu.memDep1.insertedLoads 2668 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep1.insertedStores 1295 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep1.conflictingLoads 8 # Number of conflicting loads.
-system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 25217 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 49 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 21059 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 12140 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 6785 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 13 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 17609 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 1.195923 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.068924 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 11762 66.80% 66.80% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 1075 6.10% 72.90% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 1081 6.14% 79.04% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 919 5.22% 84.26% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 899 5.11% 89.36% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 701 3.98% 93.34% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 574 3.26% 96.60% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 264 1.50% 98.10% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 334 1.90% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 17609 # Number of insts issued each cycle
-system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 153 31.03% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntMult 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntDiv 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatAdd 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCmp 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatCvt 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMult 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatDiv 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMisc 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatSqrt 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAdd 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdAlu 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCmp 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdCvt 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMisc 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMult 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShift 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdSqrt 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 31.03% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 227 46.04% 77.08% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 109 22.11% 99.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.19% # attempts to use FU when none available
-system.cpu.iq.fu_full::FloatMemWrite 4 0.81% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 7042 67.16% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.18% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 2285 21.79% 88.99% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 1146 10.93% 99.92% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.93% # Type of FU issued
-system.cpu.iq.FU_type_0::FloatMemWrite 7 0.07% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 10486 # Type of FU issued
-system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued
-system.cpu.iq.FU_type_1::IntAlu 7119 67.33% 67.35% # Type of FU issued
-system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.36% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMultAcc 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMisc 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.38% # Type of FU issued
-system.cpu.iq.FU_type_1::MemRead 2310 21.85% 89.23% # Type of FU issued
-system.cpu.iq.FU_type_1::MemWrite 1131 10.70% 99.92% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMemRead 1 0.01% 99.93% # Type of FU issued
-system.cpu.iq.FU_type_1::FloatMemWrite 7 0.07% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_1::total 10573 # Type of FU issued
-system.cpu.iq.FU_type::total 21059 0.00% 0.00% # Type of FU issued
-system.cpu.iq.rate 0.411896 # Inst issue rate
-system.cpu.iq.fu_busy_cnt::0 245 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::1 248 # FU busy when requested
-system.cpu.iq.fu_busy_cnt::total 493 # FU busy when requested
-system.cpu.iq.fu_busy_rate::0 0.011634 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::1 0.011776 # FU busy rate (busy events/executed inst)
-system.cpu.iq.fu_busy_rate::total 0.023410 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 60282 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 37413 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 19074 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 21524 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 24 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 1418 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 16 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 450 # Number of stores squashed
-system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 58 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.lsq.thread1.forwLoads 83 # Number of loads that had data forwarded from stores
-system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread1.squashedLoads 1434 # Number of loads squashed
-system.cpu.iew.lsq.thread1.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread1.memOrderViolation 13 # Number of memory ordering violations
-system.cpu.iew.lsq.thread1.squashedStores 405 # Number of stores squashed
-system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
-system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread1.cacheBlocked 57 # Number of times an access to memory failed due to the cache being blocked
-system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 960 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 2021 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 347 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 25404 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 199 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 5303 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 2630 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 49 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 341 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 29 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 167 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 860 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1027 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 19999 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts::0 2117 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::1 2148 # Number of load instructions executed
-system.cpu.iew.iewExecLoadInsts::total 4265 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1060 # Number of squashed instructions skipped in execute
-system.cpu.iew.exec_swp::0 0 # number of swp insts executed
-system.cpu.iew.exec_swp::1 0 # number of swp insts executed
-system.cpu.iew.exec_swp::total 0 # number of swp insts executed
-system.cpu.iew.exec_nop::0 69 # number of nop insts executed
-system.cpu.iew.exec_nop::1 69 # number of nop insts executed
-system.cpu.iew.exec_nop::total 138 # number of nop insts executed
-system.cpu.iew.exec_refs::0 3217 # number of memory reference insts executed
-system.cpu.iew.exec_refs::1 3234 # number of memory reference insts executed
-system.cpu.iew.exec_refs::total 6451 # number of memory reference insts executed
-system.cpu.iew.exec_branches::0 1607 # Number of branches executed
-system.cpu.iew.exec_branches::1 1627 # Number of branches executed
-system.cpu.iew.exec_branches::total 3234 # Number of branches executed
-system.cpu.iew.exec_stores::0 1100 # Number of stores executed
-system.cpu.iew.exec_stores::1 1086 # Number of stores executed
-system.cpu.iew.exec_stores::total 2186 # Number of stores executed
-system.cpu.iew.exec_rate 0.391163 # Inst execution rate
-system.cpu.iew.wb_sent::0 9679 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::1 9769 # cumulative count of insts sent to commit
-system.cpu.iew.wb_sent::total 19448 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count::0 9504 # cumulative count of insts written-back
-system.cpu.iew.wb_count::1 9590 # cumulative count of insts written-back
-system.cpu.iew.wb_count::total 19094 # cumulative count of insts written-back
-system.cpu.iew.wb_producers::0 4946 # num instructions producing a value
-system.cpu.iew.wb_producers::1 5011 # num instructions producing a value
-system.cpu.iew.wb_producers::total 9957 # num instructions producing a value
-system.cpu.iew.wb_consumers::0 6500 # num instructions consuming a value
-system.cpu.iew.wb_consumers::1 6565 # num instructions consuming a value
-system.cpu.iew.wb_consumers::total 13065 # num instructions consuming a value
-system.cpu.iew.wb_rate::0 0.185890 # insts written-back per cycle
-system.cpu.iew.wb_rate::1 0.187572 # insts written-back per cycle
-system.cpu.iew.wb_rate::total 0.373462 # insts written-back per cycle
-system.cpu.iew.wb_fanout::0 0.760923 # average fanout of values written-back
-system.cpu.iew.wb_fanout::1 0.763290 # average fanout of values written-back
-system.cpu.iew.wb_fanout::total 0.762113 # average fanout of values written-back
-system.cpu.commit.commitSquashedInsts 12156 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 36 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 887 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 17042 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 0.772151 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 1.826014 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 13049 76.57% 76.57% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 1202 7.05% 83.62% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 934 5.48% 89.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 454 2.66% 91.77% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 336 1.97% 93.74% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 195 1.14% 94.88% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 209 1.23% 96.11% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 150 0.88% 96.99% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 513 3.01% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 17042 # Number of insts commited each cycle
-system.cpu.commit.committedInsts::0 6547 # Number of instructions committed
-system.cpu.commit.committedInsts::1 6612 # Number of instructions committed
-system.cpu.commit.committedInsts::total 13159 # Number of instructions committed
-system.cpu.commit.committedOps::0 6547 # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::1 6612 # Number of ops (including micro ops) committed
-system.cpu.commit.committedOps::total 13159 # Number of ops (including micro ops) committed
-system.cpu.commit.swp_count::0 0 # Number of s/w prefetches committed
-system.cpu.commit.swp_count::1 0 # Number of s/w prefetches committed
-system.cpu.commit.swp_count::total 0 # Number of s/w prefetches committed
-system.cpu.commit.refs::0 2102 # Number of memory references committed
-system.cpu.commit.refs::1 2124 # Number of memory references committed
-system.cpu.commit.refs::total 4226 # Number of memory references committed
-system.cpu.commit.loads::0 1217 # Number of loads committed
-system.cpu.commit.loads::1 1234 # Number of loads committed
-system.cpu.commit.loads::total 2451 # Number of loads committed
-system.cpu.commit.membars::0 0 # Number of memory barriers committed
-system.cpu.commit.membars::1 0 # Number of memory barriers committed
-system.cpu.commit.membars::total 0 # Number of memory barriers committed
-system.cpu.commit.branches::0 1082 # Number of branches committed
-system.cpu.commit.branches::1 1095 # Number of branches committed
-system.cpu.commit.branches::total 2177 # Number of branches committed
-system.cpu.commit.fp_insts::0 10 # Number of committed floating point instructions.
-system.cpu.commit.fp_insts::1 10 # Number of committed floating point instructions.
-system.cpu.commit.fp_insts::total 20 # Number of committed floating point instructions.
-system.cpu.commit.int_insts::0 6462 # Number of committed integer instructions.
-system.cpu.commit.int_insts::1 6526 # Number of committed integer instructions.
-system.cpu.commit.int_insts::total 12988 # Number of committed integer instructions.
-system.cpu.commit.function_calls::0 132 # Number of function calls committed.
-system.cpu.commit.function_calls::1 133 # Number of function calls committed.
-system.cpu.commit.function_calls::total 265 # Number of function calls committed.
-system.cpu.commit.op_class_0::No_OpClass 19 0.29% 0.29% # Class of committed instruction
-system.cpu.commit.op_class_0::IntAlu 4423 67.56% 67.85% # Class of committed instruction
-system.cpu.commit.op_class_0::IntMult 1 0.02% 67.86% # Class of committed instruction
-system.cpu.commit.op_class_0::IntDiv 0 0.00% 67.86% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMult 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMult 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShift 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.89% # Class of committed instruction
-system.cpu.commit.op_class_0::MemRead 1216 18.57% 86.47% # Class of committed instruction
-system.cpu.commit.op_class_0::MemWrite 878 13.41% 99.88% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
-system.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_0::total 6547 # Class of committed instruction
-system.cpu.commit.op_class_1::No_OpClass 19 0.29% 0.29% # Class of committed instruction
-system.cpu.commit.op_class_1::IntAlu 4466 67.54% 67.83% # Class of committed instruction
-system.cpu.commit.op_class_1::IntMult 1 0.02% 67.85% # Class of committed instruction
-system.cpu.commit.op_class_1::IntDiv 0 0.00% 67.85% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatAdd 2 0.03% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatCmp 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatCvt 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatMult 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatMultAcc 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatDiv 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatMisc 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatSqrt 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdAdd 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdAddAcc 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdAlu 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdCmp 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdCvt 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdMisc 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdMult 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdMultAcc 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdShift 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdShiftAcc 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdSqrt 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatAdd 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatAlu 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatCmp 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatCvt 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatDiv 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatMisc 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatMult 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatMultAcc 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::SimdFloatSqrt 0 0.00% 67.88% # Class of committed instruction
-system.cpu.commit.op_class_1::MemRead 1233 18.65% 86.52% # Class of committed instruction
-system.cpu.commit.op_class_1::MemWrite 883 13.35% 99.88% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatMemRead 1 0.02% 99.89% # Class of committed instruction
-system.cpu.commit.op_class_1::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_1::IprAccess 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_1::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
-system.cpu.commit.op_class_1::total 6612 # Class of committed instruction
-system.cpu.commit.op_class::total 13159 0.00% 0.00% # Class of committed instruction
-system.cpu.commit.bw_lim_events 513 # number cycles where commit BW limit reached
-system.cpu.rob.rob_reads 93105 # The number of ROB reads
-system.cpu.rob.rob_writes 52882 # The number of ROB writes
-system.cpu.timesIdled 260 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 33518 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.committedInsts::0 6530 # Number of Instructions Simulated
-system.cpu.committedInsts::1 6595 # Number of Instructions Simulated
-system.cpu.committedInsts::total 13125 # Number of Instructions Simulated
-system.cpu.committedOps::0 6530 # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::1 6595 # Number of Ops (including micro ops) Simulated
-system.cpu.committedOps::total 13125 # Number of Ops (including micro ops) Simulated
-system.cpu.cpi::0 7.829556 # CPI: Cycles Per Instruction
-system.cpu.cpi::1 7.752388 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 3.895390 # CPI: Total CPI of All Threads
-system.cpu.ipc::0 0.127721 # IPC: Instructions Per Cycle
-system.cpu.ipc::1 0.128993 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.256714 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 25576 # number of integer regfile reads
-system.cpu.int_regfile_writes 14448 # number of integer regfile writes
-system.cpu.fp_regfile_reads 16 # number of floating regfile reads
-system.cpu.fp_regfile_writes 4 # number of floating regfile writes
-system.cpu.misc_regfile_reads 2 # number of misc regfile reads
-system.cpu.misc_regfile_writes 2 # number of misc regfile writes
-system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.tags.replacements::0 0 # number of replacements
-system.cpu.dcache.tags.replacements::1 0 # number of replacements
-system.cpu.dcache.tags.replacements::total 0 # number of replacements
-system.cpu.dcache.tags.tagsinuse 108.945725 # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs 4625 # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs 175 # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs 26.428571 # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data 108.945725 # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data 0.026598 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total 0.026598 # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_task_id_blocks::1024 175 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id
-system.cpu.dcache.tags.age_task_id_blocks_1024::1 134 # Occupied blocks per task id
-system.cpu.dcache.tags.occ_task_id_percent::1024 0.042725 # Percentage of cache occupancy per task id
-system.cpu.dcache.tags.tag_accesses 11523 # Number of tag accesses
-system.cpu.dcache.tags.data_accesses 11523 # Number of data accesses
-system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states
-system.cpu.dcache.ReadReq_hits::cpu.data 3561 # number of ReadReq hits
-system.cpu.dcache.ReadReq_hits::total 3561 # number of ReadReq hits
-system.cpu.dcache.WriteReq_hits::cpu.data 1064 # number of WriteReq hits
-system.cpu.dcache.WriteReq_hits::total 1064 # number of WriteReq hits
-system.cpu.dcache.demand_hits::cpu.data 4625 # number of demand (read+write) hits
-system.cpu.dcache.demand_hits::total 4625 # number of demand (read+write) hits
-system.cpu.dcache.overall_hits::cpu.data 4625 # number of overall hits
-system.cpu.dcache.overall_hits::total 4625 # number of overall hits
-system.cpu.dcache.ReadReq_misses::cpu.data 338 # number of ReadReq misses
-system.cpu.dcache.ReadReq_misses::total 338 # number of ReadReq misses
-system.cpu.dcache.WriteReq_misses::cpu.data 711 # number of WriteReq misses
-system.cpu.dcache.WriteReq_misses::total 711 # number of WriteReq misses
-system.cpu.dcache.demand_misses::cpu.data 1049 # number of demand (read+write) misses
-system.cpu.dcache.demand_misses::total 1049 # number of demand (read+write) misses
-system.cpu.dcache.overall_misses::cpu.data 1049 # number of overall misses
-system.cpu.dcache.overall_misses::total 1049 # number of overall misses
-system.cpu.dcache.ReadReq_miss_latency::cpu.data 29216500 # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_latency::total 29216500 # number of ReadReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::cpu.data 54293993 # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_latency::total 54293993 # number of WriteReq miss cycles
-system.cpu.dcache.demand_miss_latency::cpu.data 83510493 # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_latency::total 83510493 # number of demand (read+write) miss cycles
-system.cpu.dcache.overall_miss_latency::cpu.data 83510493 # number of overall miss cycles
-system.cpu.dcache.overall_miss_latency::total 83510493 # number of overall miss cycles
-system.cpu.dcache.ReadReq_accesses::cpu.data 3899 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_accesses::total 3899 # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::cpu.data 1775 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_accesses::total 1775 # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.demand_accesses::cpu.data 5674 # number of demand (read+write) accesses
-system.cpu.dcache.demand_accesses::total 5674 # number of demand (read+write) accesses
-system.cpu.dcache.overall_accesses::cpu.data 5674 # number of overall (read+write) accesses
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-system.cpu.l2cache.overall_mshr_misses::cpu.data 175 # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_misses::total 492 # number of overall MSHR misses
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 5408000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 5408000 # number of ReadExReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 23927500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 23927500 # number of ReadCleanReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 9091000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 9091000 # number of ReadSharedReq MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23927500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14499000 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_latency::total 38426500 # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23927500 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14499000 # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_latency::total 38426500 # number of overall MSHR miss cycles
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 1 # mshr miss rate for ReadCleanReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 74082.191781 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 74082.191781 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 75481.072555 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 75481.072555 # average ReadCleanReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 89127.450980 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 89127.450980 # average ReadSharedReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 75481.072555 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 82851.428571 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 78102.642276 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 75481.072555 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 82851.428571 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 78102.642276 # average overall mshr miss latency
-system.cpu.toL2Bus.snoop_filter.tot_requests 493 # Total number of requests made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states
-system.cpu.toL2Bus.trans_dist::ReadResp 419 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::WritebackClean 1 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadCleanReq 317 # Transaction distribution
-system.cpu.toL2Bus.trans_dist::ReadSharedReq 102 # Transaction distribution
-system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 635 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 350 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_count::total 985 # Packet count per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 20352 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11200 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.pkt_size::total 31552 # Cumulative packet size per connected master and slave (bytes)
-system.cpu.toL2Bus.snoops 0 # Total snoops (count)
-system.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.cpu.toL2Bus.snoop_fanout::samples 492 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
-system.cpu.toL2Bus.snoop_fanout::total 492 # Request fanout histogram
-system.cpu.toL2Bus.reqLayer0.occupancy 247500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer0.occupancy 475500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer0.utilization 1.9 # Layer utilization (%)
-system.cpu.toL2Bus.respLayer1.occupancy 262500 # Layer occupancy (ticks)
-system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
-system.membus.snoop_filter.tot_requests 492 # Total number of requests made to the snoop filter.
-system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
-system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
-system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
-system.membus.pwrStateResidencyTicks::UNDEFINED 25563000 # Cumulative time (in ticks) in various power states
-system.membus.trans_dist::ReadResp 419 # Transaction distribution
-system.membus.trans_dist::ReadExReq 73 # Transaction distribution
-system.membus.trans_dist::ReadExResp 73 # Transaction distribution
-system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
-system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 984 # Packet count per connected master and slave (bytes)
-system.membus.pkt_count::total 984 # Packet count per connected master and slave (bytes)
-system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 31488 # Cumulative packet size per connected master and slave (bytes)
-system.membus.pkt_size::total 31488 # Cumulative packet size per connected master and slave (bytes)
-system.membus.snoops 0 # Total snoops (count)
-system.membus.snoopTraffic 0 # Total snoop traffic (bytes)
-system.membus.snoop_fanout::samples 492 # Request fanout histogram
-system.membus.snoop_fanout::mean 0 # Request fanout histogram
-system.membus.snoop_fanout::stdev 0 # Request fanout histogram
-system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
-system.membus.snoop_fanout::0 492 100.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
-system.membus.snoop_fanout::min_value 0 # Request fanout histogram
-system.membus.snoop_fanout::max_value 0 # Request fanout histogram
-system.membus.snoop_fanout::total 492 # Request fanout histogram
-system.membus.reqLayer0.occupancy 588500 # Layer occupancy (ticks)
-system.membus.reqLayer0.utilization 2.3 # Layer utilization (%)
-system.membus.respLayer1.occupancy 2626750 # Layer occupancy (ticks)
-system.membus.respLayer1.utilization 10.3 # Layer utilization (%)
+sim_seconds 0.000027
+sim_ticks 27117500
+final_tick 27117500
+sim_freq 1000000000000
+host_inst_rate 132500
+host_op_rate 132484
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+host_seconds 0.10
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+system.physmem.bytes_read::cpu.data 21888
+system.physmem.bytes_read::total 61568
+system.physmem.bytes_inst_read::cpu.inst 39680
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+system.physmem.readReqs 963
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+system.physmem.bytesReadDRAM 61632
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+system.physmem.bytesWritten 0
+system.physmem.bytesReadSys 61632
+system.physmem.bytesWrittenSys 0
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+system.physmem.bytesPerActivate::samples 202
+system.physmem.bytesPerActivate::mean 288.316832
+system.physmem.bytesPerActivate::gmean 177.342258
+system.physmem.bytesPerActivate::stdev 298.023303
+system.physmem.bytesPerActivate::0-127 71 35.15% 35.15%
+system.physmem.bytesPerActivate::128-255 55 27.23% 62.38%
+system.physmem.bytesPerActivate::256-383 17 8.42% 70.79%
+system.physmem.bytesPerActivate::384-511 14 6.93% 77.72%
+system.physmem.bytesPerActivate::512-639 12 5.94% 83.66%
+system.physmem.bytesPerActivate::640-767 6 2.97% 86.63%
+system.physmem.bytesPerActivate::768-895 9 4.46% 91.09%
+system.physmem.bytesPerActivate::896-1023 5 2.48% 93.56%
+system.physmem.bytesPerActivate::1024-1151 13 6.44% 100.00%
+system.physmem.bytesPerActivate::total 202
+system.physmem.totQLat 16137750
+system.physmem.totMemAccLat 34194000
+system.physmem.totBusLat 4815000
+system.physmem.avgQLat 16757.79
+system.physmem.avgBusLat 5000.00
+system.physmem.avgMemAccLat 35507.79
+system.physmem.avgRdBW 2272.78
+system.physmem.avgWrBW 0.00
+system.physmem.avgRdBWSys 2272.78
+system.physmem.avgWrBWSys 0.00
+system.physmem.peakBW 12800.00
+system.physmem.busUtil 17.76
+system.physmem.busUtilRead 17.76
+system.physmem.busUtilWrite 0.00
+system.physmem.avgRdQLen 2.46
+system.physmem.avgWrQLen 0.00
+system.physmem.readRowHits 750
+system.physmem.writeRowHits 0
+system.physmem.readRowHitRate 77.88
+system.physmem.writeRowHitRate nan
+system.physmem.avgGap 28127.21
+system.physmem.pageHitRate 77.88
+system.physmem_0.actEnergy 835380
+system.physmem_0.preEnergy 428835
+system.physmem_0.readEnergy 4162620
+system.physmem_0.writeEnergy 0
+system.physmem_0.refreshEnergy 1843920.000000
+system.physmem_0.actBackEnergy 5930850
+system.physmem_0.preBackEnergy 47520
+system.physmem_0.actPowerDownEnergy 6376590
+system.physmem_0.prePowerDownEnergy 1440
+system.physmem_0.selfRefreshEnergy 0
+system.physmem_0.totalEnergy 19627155
+system.physmem_0.averagePower 723.781875
+system.physmem_0.totalIdleTime 13833750
+system.physmem_0.memoryStateTime::IDLE 40500
+system.physmem_0.memoryStateTime::REF 780000
+system.physmem_0.memoryStateTime::SREF 0
+system.physmem_0.memoryStateTime::PRE_PDN 3750
+system.physmem_0.memoryStateTime::ACT 12310750
+system.physmem_0.memoryStateTime::ACT_PDN 13982500
+system.physmem_1.actEnergy 685440
+system.physmem_1.preEnergy 337755
+system.physmem_1.readEnergy 2713200
+system.physmem_1.writeEnergy 0
+system.physmem_1.refreshEnergy 1843920.000000
+system.physmem_1.actBackEnergy 4668300
+system.physmem_1.preBackEnergy 160320
+system.physmem_1.actPowerDownEnergy 7500060
+system.physmem_1.prePowerDownEnergy 5760
+system.physmem_1.selfRefreshEnergy 0
+system.physmem_1.totalEnergy 17914755
+system.physmem_1.averagePower 660.634461
+system.physmem_1.totalIdleTime 16457500
+system.physmem_1.memoryStateTime::IDLE 306000
+system.physmem_1.memoryStateTime::REF 780000
+system.physmem_1.memoryStateTime::SREF 0
+system.physmem_1.memoryStateTime::PRE_PDN 15250
+system.physmem_1.memoryStateTime::ACT 9574000
+system.physmem_1.memoryStateTime::ACT_PDN 16442250
+system.pwrStateResidencyTicks::UNDEFINED 27117500
+system.cpu.branchPred.lookups 5015
+system.cpu.branchPred.condPredicted 3001
+system.cpu.branchPred.condIncorrect 806
+system.cpu.branchPred.BTBLookups 3809
+system.cpu.branchPred.BTBHits 1166
+system.cpu.branchPred.BTBCorrect 0
+system.cpu.branchPred.BTBHitPct 30.611709
+system.cpu.branchPred.usedRAS 698
+system.cpu.branchPred.RASInCorrect 53
+system.cpu.branchPred.indirectLookups 824
+system.cpu.branchPred.indirectHits 156
+system.cpu.branchPred.indirectMisses 668
+system.cpu.branchPredindirectMispredicted 131
+system.cpu_clk_domain.clock 500
+system.cpu.dtb.fetch_hits 0
+system.cpu.dtb.fetch_misses 0
+system.cpu.dtb.fetch_acv 0
+system.cpu.dtb.fetch_accesses 0
+system.cpu.dtb.read_hits 4101
+system.cpu.dtb.read_misses 90
+system.cpu.dtb.read_acv 0
+system.cpu.dtb.read_accesses 4191
+system.cpu.dtb.write_hits 1999
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+system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00%
+system.cpu.toL2Bus.snoop_fanout::0 964 99.79% 99.79%
+system.cpu.toL2Bus.snoop_fanout::1 2 0.21% 100.00%
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+system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00%
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+system.membus.snoop_fanout::mean 0
+system.membus.snoop_fanout::stdev 0
+system.membus.snoop_fanout::underflows 0 0.00% 0.00%
+system.membus.snoop_fanout::0 963 100.00% 100.00%
+system.membus.snoop_fanout::1 0 0.00% 100.00%
+system.membus.snoop_fanout::overflows 0 0.00% 100.00%
+system.membus.snoop_fanout::min_value 0
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+system.membus.snoop_fanout::total 963
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+system.membus.reqLayer0.utilization 4.3
+system.membus.respLayer1.occupancy 5110750
+system.membus.respLayer1.utilization 18.8
---------- End Simulation Statistics ----------