diff options
Diffstat (limited to 'tests/quick')
15 files changed, 6963 insertions, 7694 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt index ecf052997..823f9b4c3 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19841500 # Number of ticks simulated -final_tick 19841500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000019 # Number of seconds simulated +sim_ticks 18769500 # Number of ticks simulated +final_tick 18769500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 31060 # Simulator instruction rate (inst/s) -host_op_rate 31057 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 96425663 # Simulator tick rate (ticks/s) -host_mem_usage 216044 # Number of bytes of host memory used -host_seconds 0.21 # Real time elapsed on the host +host_inst_rate 10228 # Simulator instruction rate (inst/s) +host_op_rate 10227 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 30039955 # Simulator tick rate (ticks/s) +host_mem_usage 216300 # Number of bytes of host memory used +host_seconds 0.62 # Real time elapsed on the host sim_insts 6390 # Number of instructions simulated sim_ops 6390 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19200 # Nu system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory system.physmem.num_reads::total 468 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 967668775 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 541894514 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1509563289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 967668775 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 967668775 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 967668775 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 541894514 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1509563289 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1022936146 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 572844242 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1595780388 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1022936146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1022936146 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1022936146 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 572844242 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1595780388 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 469 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 469 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19827000 # Total gap between requests +system.physmem.totGap 18755000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,8 +98,8 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 334 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 108 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 304 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 138 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 19 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1719468 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11463468 # Sum of mem lat for all requests +system.physmem.totQLat 1862969 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11662969 # Sum of mem lat for all requests system.physmem.totBusLat 1876000 # Total cycles spent in databus access -system.physmem.totBankLat 7868000 # Total cycles spent in bank access -system.physmem.avgQLat 3666.24 # Average queueing delay per request -system.physmem.avgBankLat 16776.12 # Average bank access latency per request +system.physmem.totBankLat 7924000 # Total cycles spent in bank access +system.physmem.avgQLat 3972.22 # Average queueing delay per request +system.physmem.avgBankLat 16895.52 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24442.36 # Average memory access latency -system.physmem.avgRdBW 1509.56 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24867.74 # Average memory access latency +system.physmem.avgRdBW 1595.78 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1509.56 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1595.78 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.43 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.58 # Average read queue length over time +system.physmem.busUtil 9.97 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.62 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 401 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 85.50 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42275.05 # Average gap between requests +system.physmem.avgGap 39989.34 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1184 # DTB read hits +system.cpu.dtb.read_hits 1183 # DTB read hits system.cpu.dtb.read_misses 7 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1191 # DTB read accesses -system.cpu.dtb.write_hits 900 # DTB write hits +system.cpu.dtb.read_accesses 1190 # DTB read accesses +system.cpu.dtb.write_hits 865 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 903 # DTB write accesses -system.cpu.dtb.data_hits 2084 # DTB hits +system.cpu.dtb.write_accesses 868 # DTB write accesses +system.cpu.dtb.data_hits 2048 # DTB hits system.cpu.dtb.data_misses 10 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2094 # DTB accesses -system.cpu.itb.fetch_hits 908 # ITB hits +system.cpu.dtb.data_accesses 2058 # DTB accesses +system.cpu.itb.fetch_hits 909 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 925 # ITB accesses +system.cpu.itb.fetch_accesses 926 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,42 +218,42 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 39684 # number of cpu cycles simulated +system.cpu.numCycles 37540 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1606 # Number of BP lookups +system.cpu.branch_predictor.lookups 1605 # Number of BP lookups system.cpu.branch_predictor.condPredicted 1125 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 713 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1186 # Number of BTB lookups +system.cpu.branch_predictor.BTBLookups 1185 # Number of BTB lookups system.cpu.branch_predictor.BTBHits 314 # Number of BTB hits system.cpu.branch_predictor.usedRAS 126 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 26.475548 # BTB Hit Percentage +system.cpu.branch_predictor.BTBHitPct 26.497890 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 464 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1142 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5205 # Number of Reads from Int. Register File +system.cpu.branch_predictor.predictedNotTaken 1141 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5235 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9772 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9802 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 2961 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 2929 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2181 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 284 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 368 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 652 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.predicted 399 # Number of Branches Incorrectly Predicted system.cpu.execution_unit.mispredictPct 62.036156 # Percentage of Incorrect Branches Predicts -system.cpu.execution_unit.executions 4463 # Number of Instructions Executed. +system.cpu.execution_unit.executions 4462 # Number of Instructions Executed. system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 11913 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 11564 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 522 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 32282 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 7402 # Number of cycles cpu stages are processed. -system.cpu.activity 18.652354 # Percentage of cycles cpu is active +system.cpu.timesIdled 496 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 30143 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 7397 # Number of cycles cpu stages are processed. +system.cpu.activity 19.704315 # Percentage of cycles cpu is active system.cpu.comLoads 1183 # Number of Load instructions committed system.cpu.comStores 865 # Number of Store instructions committed system.cpu.comBranches 1050 # Number of Branches instructions committed @@ -265,144 +265,144 @@ system.cpu.committedInsts 6390 # Nu system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total) -system.cpu.cpi 6.210329 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 5.874804 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.210329 # CPI: Total CPI of All Threads -system.cpu.ipc 0.161022 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 5.874804 # CPI: Total CPI of All Threads +system.cpu.ipc 0.170218 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.161022 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 34772 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4912 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.377784 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35806 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3878 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 9.772200 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 35512 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 4172 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 10.513053 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 38344 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1340 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.376676 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 35226 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 4458 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 11.233747 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.170218 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 32631 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4909 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 13.076718 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 33667 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3873 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 10.316995 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 33372 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 4168 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 11.102824 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 36235 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1305 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.476292 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 33023 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 4517 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 12.032499 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 142.150123 # Cycle average of tags in use -system.cpu.icache.total_refs 558 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 143.255742 # Cycle average of tags in use +system.cpu.icache.total_refs 556 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 301 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 1.853821 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 1.847176 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 142.150123 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.069409 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.069409 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 558 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 558 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 558 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 558 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 558 # number of overall hits -system.cpu.icache.overall_hits::total 558 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 350 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 350 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 350 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 350 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 350 # number of overall misses -system.cpu.icache.overall_misses::total 350 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 17305000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 17305000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 17305000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 17305000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 17305000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 17305000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 908 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 908 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 908 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 908 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 908 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.385463 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.385463 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.385463 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.385463 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.385463 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.385463 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49442.857143 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49442.857143 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49442.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49442.857143 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49442.857143 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 143.255742 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.069949 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.069949 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 556 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 556 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 556 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 556 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 556 # number of overall hits +system.cpu.icache.overall_hits::total 556 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 353 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 353 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 353 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 353 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 353 # number of overall misses +system.cpu.icache.overall_misses::total 353 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17380500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17380500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17380500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17380500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17380500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17380500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 909 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 909 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 909 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 909 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 909 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.388339 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.388339 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.388339 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.388339 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.388339 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.388339 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49236.543909 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 49236.543909 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 49236.543909 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 49236.543909 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 49236.543909 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 48 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 48 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 48 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 48 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 51 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 51 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 51 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 51 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 51 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 51 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14791500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14791500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14791500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14791500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14791500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14791500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332599 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.332599 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.332599 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48978.476821 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48978.476821 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48978.476821 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 48978.476821 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14765000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14765000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14765000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14765000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14765000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14765000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.332233 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.332233 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.332233 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.332233 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48890.728477 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48890.728477 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48890.728477 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48890.728477 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 104.047429 # Cycle average of tags in use -system.cpu.dcache.total_refs 1700 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 104.285094 # Cycle average of tags in use +system.cpu.dcache.total_refs 1601 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 168 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 10.119048 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.529762 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 104.047429 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025402 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025402 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 104.285094 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.025460 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.025460 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 614 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 614 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1700 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1700 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1700 # number of overall hits -system.cpu.dcache.overall_hits::total 1700 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 515 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1601 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1601 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1601 # number of overall hits +system.cpu.dcache.overall_hits::total 1601 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 251 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 251 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 348 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 348 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 348 # number of overall misses -system.cpu.dcache.overall_misses::total 348 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5354000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5354000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 11296500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 11296500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16650500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16650500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16650500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16650500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 350 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 350 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 447 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses +system.cpu.dcache.overall_misses::total 447 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5354500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5354500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14914000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14914000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20268500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20268500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20268500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20268500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) @@ -413,36 +413,36 @@ system.cpu.dcache.overall_accesses::cpu.data 2048 system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.290173 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.290173 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.169922 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.169922 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.169922 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.169922 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55195.876289 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55195.876289 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45005.976096 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 45005.976096 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47846.264368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47846.264368 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47846.264368 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2586 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 37 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 69.891892 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55201.030928 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55201.030928 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42611.428571 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42611.428571 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45343.400447 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45343.400447 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45343.400447 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 134 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 134 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 178 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 178 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 180 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 180 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 180 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 180 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses @@ -451,14 +451,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 168 system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5078500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5078500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3447000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3447000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8525500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8525500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8525500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8525500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5079000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3674000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8753000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8753000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8753000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses @@ -467,26 +467,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53457.894737 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53457.894737 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 47219.178082 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 47219.178082 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50747.023810 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50747.023810 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53463.157895 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53463.157895 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50328.767123 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50328.767123 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52101.190476 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52101.190476 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 199.193487 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 200.317780 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 395 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.002532 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 142.245680 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 56.947807 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004341 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 143.356757 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 56.961023 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004375 # Average percentage of cache occupancy system.cpu.l2cache.occ_percent::cpu.data 0.001738 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006079 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006113 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -504,17 +504,17 @@ system.cpu.l2cache.demand_misses::total 469 # nu system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses system.cpu.l2cache.overall_misses::total 469 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14473000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 19450000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3369500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3369500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14473000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8346500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 22819500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14473000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8346500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 22819500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14446500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4977500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19424000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3596500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3596500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14446500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8574000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23020500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14446500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8574000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23020500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses) @@ -537,17 +537,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997872 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48083.056478 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52389.473684 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49116.161616 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 46157.534247 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 46157.534247 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 48655.650320 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48083.056478 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 49681.547619 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 48655.650320 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47995.016611 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52394.736842 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49050.505051 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49267.123288 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49267.123288 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49084.221748 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47995.016611 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51035.714286 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49084.221748 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -567,17 +567,17 @@ system.cpu.l2cache.demand_mshr_misses::total 469 system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10688499 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3791620 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14480119 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2447596 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2447596 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10688499 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6239216 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16927715 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10688499 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6239216 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16927715 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10662000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3792120 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14454120 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2674096 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2674096 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10662000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6466216 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17128216 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10662000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6466216 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17128216 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses @@ -589,17 +589,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35509.963455 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39911.789474 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36565.957071 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 33528.712329 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 33528.712329 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35509.963455 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37138.190476 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36093.208955 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35421.926910 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 39917.052632 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36500.303030 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36631.452055 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36631.452055 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35421.926910 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38489.380952 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36520.716418 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt index d5736f11f..fb45a6f1f 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/stats.txt @@ -1,51 +1,51 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 11568000 # Number of ticks simulated -final_tick 11568000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 15653000 # Number of ticks simulated +final_tick 15653000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 27765 # Simulator instruction rate (inst/s) -host_op_rate 27764 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 50400871 # Simulator tick rate (ticks/s) -host_mem_usage 217072 # Number of bytes of host memory used -host_seconds 0.23 # Real time elapsed on the host +host_inst_rate 11804 # Simulator instruction rate (inst/s) +host_op_rate 11803 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 28994780 # Simulator tick rate (ticks/s) +host_mem_usage 217308 # Number of bytes of host memory used +host_seconds 0.54 # Real time elapsed on the host sim_insts 6372 # Number of instructions simulated sim_ops 6372 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20032 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory -system.physmem.bytes_read::total 31104 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 11136 # Number of bytes read from this memory +system.physmem.bytes_read::total 31168 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 20032 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 20032 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 313 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory -system.physmem.num_reads::total 486 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1731673582 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 957123098 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2688796680 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1731673582 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1731673582 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1731673582 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 957123098 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2688796680 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 486 # Total number of read requests seen +system.physmem.num_reads::cpu.data 174 # Number of read requests responded to by this memory +system.physmem.num_reads::total 487 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1279754680 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 711429119 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1991183799 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1279754680 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1279754680 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1279754680 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 711429119 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1991183799 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 487 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 486 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 31104 # Total number of bytes read from memory +system.physmem.cpureqs 487 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 31168 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 31104 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 31168 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 51 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 19 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 18 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 30 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 31 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 25 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 4 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 67 # Track reads on a per bank basis -system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 33 # Track reads on a per bank basis +system.physmem.perBankRdReqs::8 23 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 67 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 44 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 11441000 # Total gap between requests +system.physmem.totGap 15508000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 486 # Categorize read packet sizes +system.physmem.readPktSize::6 487 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 243 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 70 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 258 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 153 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 55 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3089486 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12593486 # Sum of mem lat for all requests -system.physmem.totBusLat 1944000 # Total cycles spent in databus access -system.physmem.totBankLat 7560000 # Total cycles spent in bank access -system.physmem.avgQLat 6356.97 # Average queueing delay per request -system.physmem.avgBankLat 15555.56 # Average bank access latency per request +system.physmem.totQLat 2668987 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12414987 # Sum of mem lat for all requests +system.physmem.totBusLat 1948000 # Total cycles spent in databus access +system.physmem.totBankLat 7798000 # Total cycles spent in bank access +system.physmem.avgQLat 5480.47 # Average queueing delay per request +system.physmem.avgBankLat 16012.32 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25912.52 # Average memory access latency -system.physmem.avgRdBW 2688.80 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25492.79 # Average memory access latency +system.physmem.avgRdBW 1991.18 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2688.80 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1991.18 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 16.80 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.09 # Average read queue length over time +system.physmem.busUtil 12.44 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 416 # Number of row buffer hits during reads +system.physmem.readRowHits 417 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 85.60 # Row buffer hit rate for reads +system.physmem.readRowHitRate 85.63 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23541.15 # Average gap between requests +system.physmem.avgGap 31843.94 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1960 # DTB read hits +system.cpu.dtb.read_hits 2048 # DTB read hits system.cpu.dtb.read_misses 58 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 2018 # DTB read accesses -system.cpu.dtb.write_hits 1076 # DTB write hits +system.cpu.dtb.read_accesses 2106 # DTB read accesses +system.cpu.dtb.write_hits 1074 # DTB write hits system.cpu.dtb.write_misses 32 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 1108 # DTB write accesses -system.cpu.dtb.data_hits 3036 # DTB hits +system.cpu.dtb.write_accesses 1106 # DTB write accesses +system.cpu.dtb.data_hits 3122 # DTB hits system.cpu.dtb.data_misses 90 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 3126 # DTB accesses -system.cpu.itb.fetch_hits 2261 # ITB hits +system.cpu.dtb.data_accesses 3212 # DTB accesses +system.cpu.itb.fetch_hits 2395 # ITB hits system.cpu.itb.fetch_misses 38 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2299 # ITB accesses +system.cpu.itb.fetch_accesses 2433 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,244 +218,243 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 23137 # number of cpu cycles simulated +system.cpu.numCycles 31307 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2774 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1638 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 514 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2124 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 769 # Number of BTB hits +system.cpu.BPredUnit.lookups 2894 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1701 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 520 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2227 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 814 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 405 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 66 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7948 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15915 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2774 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1174 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2854 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1765 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 730 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 422 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 72 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8391 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 16487 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2894 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1236 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2984 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1891 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 950 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 746 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 2261 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 327 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.177755 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.562670 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 757 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2395 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 373 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.145010 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.528367 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10659 78.88% 78.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 293 2.17% 81.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 218 1.61% 82.66% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 238 1.76% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 276 2.04% 86.46% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 191 1.41% 87.88% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 258 1.91% 89.79% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 175 1.30% 91.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1205 8.92% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 11415 79.28% 79.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 325 2.26% 81.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 232 1.61% 83.14% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 251 1.74% 84.89% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 272 1.89% 86.78% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 212 1.47% 88.25% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 276 1.92% 90.17% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 187 1.30% 91.46% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1229 8.54% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13513 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.119895 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.687859 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8886 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 751 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2667 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1129 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 236 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 88 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 14776 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 14399 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.092439 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.526623 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9352 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 969 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2779 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 88 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1211 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 252 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 87 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 15295 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 230 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 1129 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9097 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 177 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 345 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2538 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 227 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 14039 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 7 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 174 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10509 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 17564 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 17547 # Number of integer rename lookups +system.cpu.rename.SquashCycles 1211 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9558 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 276 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 373 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2656 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 325 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 14562 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 299 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10896 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 18155 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 18138 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4570 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5939 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 34 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 671 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2611 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1355 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 6326 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 25 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 714 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2751 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1359 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 12555 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 31 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 10392 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 59 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5880 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 3411 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 14 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13513 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.769037 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.410550 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 12925 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 29 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 10660 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 6224 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 3683 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 12 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14399 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.740329 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.373860 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9295 68.79% 68.79% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1391 10.29% 79.08% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1141 8.44% 87.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 752 5.57% 93.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 466 3.45% 96.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 269 1.99% 98.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 153 1.13% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 32 0.24% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9938 69.02% 69.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1614 11.21% 80.23% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1141 7.92% 88.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 759 5.27% 93.42% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 488 3.39% 96.81% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 274 1.90% 98.72% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 143 0.99% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 29 0.20% 99.91% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 13 0.09% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13513 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14399 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 11 9.57% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 9.57% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 65 56.52% 66.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 39 33.91% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 7.89% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 7.89% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 66 57.89% 65.79% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 39 34.21% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7044 67.78% 67.80% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.81% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2192 21.09% 88.92% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1151 11.08% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7159 67.16% 67.18% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 67.19% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 67.20% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2350 22.05% 89.25% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1146 10.75% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10392 # Type of FU issued -system.cpu.iq.rate 0.449151 # Inst issue rate -system.cpu.iq.fu_busy_cnt 115 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011066 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 34450 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 18472 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 9469 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 10660 # Type of FU issued +system.cpu.iq.rate 0.340499 # Inst issue rate +system.cpu.iq.fu_busy_cnt 114 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.010694 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 35869 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 19185 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 9545 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 10494 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 10761 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1568 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 490 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 494 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 92 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1129 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 30 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 12672 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 152 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2611 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1355 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 31 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1211 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 18 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 13042 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 178 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2751 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1359 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 29 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 18 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 142 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 377 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 519 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 9865 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2029 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 527 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 144 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 376 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 520 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 10013 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2117 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 647 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 86 # number of nop insts executed -system.cpu.iew.exec_refs 3139 # number of memory reference insts executed -system.cpu.iew.exec_branches 1600 # Number of branches executed -system.cpu.iew.exec_stores 1110 # Number of stores executed -system.cpu.iew.exec_rate 0.426373 # Inst execution rate -system.cpu.iew.wb_sent 9638 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 9479 # cumulative count of insts written-back -system.cpu.iew.wb_producers 5022 # num instructions producing a value -system.cpu.iew.wb_consumers 6814 # num instructions consuming a value +system.cpu.iew.exec_nop 88 # number of nop insts executed +system.cpu.iew.exec_refs 3225 # number of memory reference insts executed +system.cpu.iew.exec_branches 1609 # Number of branches executed +system.cpu.iew.exec_stores 1108 # Number of stores executed +system.cpu.iew.exec_rate 0.319833 # Inst execution rate +system.cpu.iew.wb_sent 9713 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 9555 # cumulative count of insts written-back +system.cpu.iew.wb_producers 5016 # num instructions producing a value +system.cpu.iew.wb_consumers 6802 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.409690 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.737012 # average fanout of values written-back +system.cpu.iew.wb_rate 0.305203 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.737430 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 6282 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 6652 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 432 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12384 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.515908 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.366435 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 438 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13188 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.484456 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.302208 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9732 78.59% 78.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1344 10.85% 89.44% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 509 4.11% 93.55% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 223 1.80% 95.35% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 188 1.52% 96.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 75 0.61% 97.47% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 105 0.85% 98.32% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 63 0.51% 98.83% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 145 1.17% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10412 78.95% 78.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1478 11.21% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 518 3.93% 94.09% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 238 1.80% 95.89% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 160 1.21% 97.10% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 94 0.71% 97.82% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 109 0.83% 98.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 35 0.27% 98.91% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 144 1.09% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12384 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13188 # Number of insts commited each cycle system.cpu.commit.committedInsts 6389 # Number of instructions committed system.cpu.commit.committedOps 6389 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -466,70 +465,70 @@ system.cpu.commit.branches 1050 # Nu system.cpu.commit.fp_insts 10 # Number of committed floating point instructions. system.cpu.commit.int_insts 6307 # Number of committed integer instructions. system.cpu.commit.function_calls 127 # Number of function calls committed. -system.cpu.commit.bw_lim_events 145 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 144 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 24559 # The number of ROB reads -system.cpu.rob.rob_writes 26483 # The number of ROB writes -system.cpu.timesIdled 248 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9624 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 25734 # The number of ROB reads +system.cpu.rob.rob_writes 27303 # The number of ROB writes +system.cpu.timesIdled 259 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16908 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 6372 # Number of Instructions Simulated system.cpu.committedOps 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 6372 # Number of Instructions Simulated -system.cpu.cpi 3.631042 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.631042 # CPI: Total CPI of All Threads -system.cpu.ipc 0.275403 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.275403 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 12554 # number of integer regfile reads -system.cpu.int_regfile_writes 7112 # number of integer regfile writes +system.cpu.cpi 4.913214 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.913214 # CPI: Total CPI of All Threads +system.cpu.ipc 0.203533 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.203533 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 12695 # number of integer regfile reads +system.cpu.int_regfile_writes 7186 # number of integer regfile writes system.cpu.fp_regfile_reads 8 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 160.502909 # Cycle average of tags in use -system.cpu.icache.total_refs 1827 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 160.377030 # Cycle average of tags in use +system.cpu.icache.total_refs 1916 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 314 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.818471 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 6.101911 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 160.502909 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.078371 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.078371 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1827 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1827 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1827 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1827 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1827 # number of overall hits -system.cpu.icache.overall_hits::total 1827 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 434 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 434 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 434 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 434 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 434 # number of overall misses -system.cpu.icache.overall_misses::total 434 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13420000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13420000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13420000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13420000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13420000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13420000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2261 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2261 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2261 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2261 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2261 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2261 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191950 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.191950 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.191950 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.191950 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.191950 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.191950 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30921.658986 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30921.658986 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30921.658986 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30921.658986 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30921.658986 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30921.658986 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 160.377030 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.078309 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.078309 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1916 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1916 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1916 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1916 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1916 # number of overall hits +system.cpu.icache.overall_hits::total 1916 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 479 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 479 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 479 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 479 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 479 # number of overall misses +system.cpu.icache.overall_misses::total 479 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21334000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21334000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21334000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21334000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21334000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21334000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2395 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2395 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2395 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2395 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2395 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2395 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.200000 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.200000 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.200000 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.200000 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.200000 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.200000 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44538.622129 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 44538.622129 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 44538.622129 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 44538.622129 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 44538.622129 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,154 +537,154 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 120 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 120 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 120 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 120 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 120 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 120 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 165 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 165 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 165 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 165 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 165 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 165 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 314 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 314 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 314 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 314 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 314 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 314 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10333000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10333000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10333000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10333000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10333000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10333000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138877 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138877 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138877 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138877 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32907.643312 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32907.643312 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32907.643312 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 32907.643312 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15306500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15306500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15306500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15306500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15306500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15306500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.131106 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.131106 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.131106 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.131106 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48746.815287 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48746.815287 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48746.815287 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48746.815287 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 107.685258 # Cycle average of tags in use -system.cpu.dcache.total_refs 2236 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 173 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 12.924855 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 107.831538 # Cycle average of tags in use +system.cpu.dcache.total_refs 2240 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 174 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 12.873563 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 107.685258 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.026290 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.026290 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1732 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1732 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 504 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 504 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2236 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2236 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2236 # number of overall hits -system.cpu.dcache.overall_hits::total 2236 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 158 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 158 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 361 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 361 # number of WriteReq misses +system.cpu.dcache.occ_blocks::cpu.data 107.831538 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.026326 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.026326 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1734 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1734 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 506 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 506 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2240 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2240 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2240 # number of overall hits +system.cpu.dcache.overall_hits::total 2240 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 160 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 160 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 359 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 359 # number of WriteReq misses system.cpu.dcache.demand_misses::cpu.data 519 # number of demand (read+write) misses system.cpu.dcache.demand_misses::total 519 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 519 # number of overall misses system.cpu.dcache.overall_misses::total 519 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 6015000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 6015000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9645000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9645000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15660000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15660000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15660000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15660000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1890 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1890 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8308500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8308500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15746484 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15746484 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 24054984 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 24054984 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 24054984 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 24054984 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1894 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1894 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2755 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2755 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2755 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2755 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083598 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.083598 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.417341 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.417341 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.188385 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.188385 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.188385 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.188385 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38069.620253 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38069.620253 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26717.451524 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 26717.451524 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 30173.410405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 30173.410405 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 30173.410405 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2759 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2759 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2759 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2759 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084477 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084477 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.415029 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.188112 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188112 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188112 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188112 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 51928.125000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 51928.125000 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43862.072423 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43862.072423 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46348.716763 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46348.716763 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46348.716763 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 810 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 28 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.928571 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 289 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 289 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 346 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 346 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 346 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 286 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 286 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 345 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 345 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 345 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 345 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses -system.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4270000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 4270000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2285000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2285000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6555000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6555000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6555000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6555000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053439 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053439 # mshr miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062795 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.062795 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062795 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.062795 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42277.227723 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42277.227723 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31736.111111 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31736.111111 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 37890.173410 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 37890.173410 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 37890.173410 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 37890.173410 # average overall mshr miss latency +system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses +system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses +system.cpu.dcache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 174 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 174 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6029500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6029500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3803500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 3803500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9833000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9833000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9833000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9833000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053326 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053326 # mshr miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063066 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063066 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59698.019802 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59698.019802 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 52102.739726 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 52102.739726 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56511.494253 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56511.494253 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 220.821936 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 220.955415 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 413 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002421 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 414 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002415 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 160.499801 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 60.322135 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004898 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001841 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006739 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 160.525117 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 60.430298 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004899 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001844 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006743 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -693,60 +692,60 @@ system.cpu.l2cache.demand_hits::total 1 # nu system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits system.cpu.l2cache.overall_hits::total 1 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 313 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 100 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 413 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 101 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 414 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 313 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 486 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 174 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 487 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 313 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses -system.cpu.l2cache.overall_misses::total 486 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10016000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4131000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 14147000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2238500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2238500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10016000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6369500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16385500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10016000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6369500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16385500 # number of overall miss cycles +system.cpu.l2cache.overall_misses::cpu.data 174 # number of overall misses +system.cpu.l2cache.overall_misses::total 487 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14981000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5921000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 20902000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3727500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 3727500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14981000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9648500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24629500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14981000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9648500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24629500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 314 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 100 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 414 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 101 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 415 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.demand_accesses::cpu.inst 314 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 487 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 174 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 488 # number of demand (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.inst 314 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 487 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 174 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 488 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996815 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997585 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997590 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996815 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997947 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.997951 # miss rate for demand accesses system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996815 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997947 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 32000 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41310 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34254.237288 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 30664.383562 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 30664.383562 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 32000 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 36817.919075 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 33715.020576 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 32000 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 36817.919075 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 33715.020576 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.997951 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47862.619808 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58623.762376 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50487.922705 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 51061.643836 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 51061.643836 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50573.921971 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47862.619808 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55451.149425 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50573.921971 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -756,49 +755,49 @@ system.cpu.l2cache.avg_blocked_cycles::no_targets nan system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 313 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 100 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 413 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 313 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 486 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 174 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 487 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 313 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 486 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 8904460 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3801580 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12706040 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2007032 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2007032 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 8904460 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5808612 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14713072 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 8904460 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5808612 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14713072 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::cpu.data 174 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 487 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11042494 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4678584 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15721078 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2834058 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2834058 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11042494 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7512642 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18555136 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11042494 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7512642 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18555136 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997585 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997590 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997947 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997951 # mshr miss rate for demand accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996815 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997947 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28448.753994 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38015.800000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30765.230024 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 27493.589041 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 27493.589041 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28448.753994 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 33575.791908 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 30273.810700 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997951 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35279.533546 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46322.613861 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37973.618357 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 38822.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 38822.712329 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35279.533546 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43176.103448 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38100.895277 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt index d5e0f20d7..9eea9fb92 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000006 # Number of seconds simulated -sim_ticks 6408000 # Number of ticks simulated -final_tick 6408000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000009 # Number of seconds simulated +sim_ticks 9061000 # Number of ticks simulated +final_tick 9061000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 494 # Simulator instruction rate (inst/s) -host_op_rate 494 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1327192 # Simulator tick rate (ticks/s) -host_mem_usage 215760 # Number of bytes of host memory used -host_seconds 4.83 # Real time elapsed on the host +host_inst_rate 62320 # Simulator instruction rate (inst/s) +host_op_rate 62299 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 236406021 # Simulator tick rate (ticks/s) +host_mem_usage 216020 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 2387 # Number of instructions simulated sim_ops 2387 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 12032 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 11968 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 5440 # Number of bytes read from this memory -system.physmem.bytes_read::total 17472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 12032 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 12032 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 188 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 17408 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 11968 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 11968 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 187 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 85 # Number of read requests responded to by this memory -system.physmem.num_reads::total 273 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1877652934 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 848938826 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2726591760 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1877652934 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1877652934 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1877652934 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 848938826 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2726591760 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 273 # Total number of read requests seen +system.physmem.num_reads::total 272 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1320825516 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 600375235 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1921200750 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1320825516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1320825516 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1320825516 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 600375235 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1921200750 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 272 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 273 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 17472 # Total number of bytes read from memory +system.physmem.cpureqs 272 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 17408 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 17472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 17408 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -47,7 +47,7 @@ system.physmem.perBankRdReqs::7 23 # Tr system.physmem.perBankRdReqs::8 26 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 9 # Track reads on a per bank basis system.physmem.perBankRdReqs::10 27 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 25 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 36 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 21 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 6357500 # Total gap between requests +system.physmem.totGap 8992500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 273 # Categorize read packet sizes +system.physmem.readPktSize::6 272 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 90 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 149 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 88 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 27 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 7 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1341773 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 7053773 # Sum of mem lat for all requests -system.physmem.totBusLat 1092000 # Total cycles spent in databus access +system.physmem.totQLat 1105772 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 6813772 # Sum of mem lat for all requests +system.physmem.totBusLat 1088000 # Total cycles spent in databus access system.physmem.totBankLat 4620000 # Total cycles spent in bank access -system.physmem.avgQLat 4914.92 # Average queueing delay per request -system.physmem.avgBankLat 16923.08 # Average bank access latency per request +system.physmem.avgQLat 4065.34 # Average queueing delay per request +system.physmem.avgBankLat 16985.29 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25838.00 # Average memory access latency -system.physmem.avgRdBW 2726.59 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25050.63 # Average memory access latency +system.physmem.avgRdBW 1921.20 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2726.59 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1921.20 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 17.04 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.10 # Average read queue length over time +system.physmem.busUtil 12.01 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.75 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 229 # Number of row buffer hits during reads +system.physmem.readRowHits 228 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.88 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.82 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 23287.55 # Average gap between requests +system.physmem.avgGap 33060.66 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 718 # DTB read hits -system.cpu.dtb.read_misses 36 # DTB read misses +system.cpu.dtb.read_hits 743 # DTB read hits +system.cpu.dtb.read_misses 38 # DTB read misses system.cpu.dtb.read_acv 1 # DTB read access violations -system.cpu.dtb.read_accesses 754 # DTB read accesses -system.cpu.dtb.write_hits 382 # DTB write hits +system.cpu.dtb.read_accesses 781 # DTB read accesses +system.cpu.dtb.write_hits 387 # DTB write hits system.cpu.dtb.write_misses 24 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 406 # DTB write accesses -system.cpu.dtb.data_hits 1100 # DTB hits -system.cpu.dtb.data_misses 60 # DTB misses +system.cpu.dtb.write_accesses 411 # DTB write accesses +system.cpu.dtb.data_hits 1130 # DTB hits +system.cpu.dtb.data_misses 62 # DTB misses system.cpu.dtb.data_acv 1 # DTB access violations -system.cpu.dtb.data_accesses 1160 # DTB accesses -system.cpu.itb.fetch_hits 1042 # ITB hits +system.cpu.dtb.data_accesses 1192 # DTB accesses +system.cpu.itb.fetch_hits 1097 # ITB hits system.cpu.itb.fetch_misses 30 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 1072 # ITB accesses +system.cpu.itb.fetch_accesses 1127 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -218,244 +218,245 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 4 # Number of system calls -system.cpu.numCycles 12817 # number of cpu cycles simulated +system.cpu.numCycles 18123 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 1162 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 576 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 259 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 820 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 228 # Number of BTB hits +system.cpu.BPredUnit.lookups 1200 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 612 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 260 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 849 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 266 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 224 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 229 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 39 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 4082 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 7077 # Number of instructions fetch has processed -system.cpu.fetch.Branches 1162 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 452 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 1223 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 886 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 261 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 857 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1042 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 173 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 7043 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.004827 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.418564 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 4258 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 7288 # Number of instructions fetch has processed +system.cpu.fetch.Branches 1200 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 495 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 1268 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 917 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 438 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 18 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 961 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1097 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 7579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.961604 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.365122 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 5820 82.64% 82.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 52 0.74% 83.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 133 1.89% 85.26% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 101 1.43% 86.70% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 157 2.23% 88.93% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 70 0.99% 89.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 69 0.98% 90.90% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 64 0.91% 91.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 577 8.19% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 6311 83.27% 83.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 53 0.70% 83.97% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 134 1.77% 85.74% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 102 1.35% 87.08% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 181 2.39% 89.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 82 1.08% 90.55% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 68 0.90% 91.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 65 0.86% 92.31% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 583 7.69% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 7043 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.090661 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.552157 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5035 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 297 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 1173 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 15 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 523 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 176 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 84 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 6290 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 301 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 523 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 5140 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 24 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 214 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 1083 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 59 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 6004 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 7579 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.066214 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.402141 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5340 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 471 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 1207 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 14 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 547 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 173 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 82 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 6471 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 293 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 547 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 5441 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 165 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 250 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 1119 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 57 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 6174 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 29 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 20 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 4336 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 6797 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 6785 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 19 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 4474 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 6979 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 6967 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 12 # Number of floating rename lookups system.cpu.rename.CommittedMaps 1768 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 2568 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 2706 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 8 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 6 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 172 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 984 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 506 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 162 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1006 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 508 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 0 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 5173 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 5283 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 4204 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 57 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 2615 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1486 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 4254 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 65 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 2663 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1563 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 7043 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.596905 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.307061 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 7579 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.561288 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.273203 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 5344 75.88% 75.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 621 8.82% 84.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 394 5.59% 90.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 268 3.81% 94.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 205 2.91% 97.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 132 1.87% 98.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 55 0.78% 99.66% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 11 0.16% 99.82% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.18% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 5858 77.29% 77.29% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 621 8.19% 85.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 415 5.48% 90.96% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 261 3.44% 94.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 216 2.85% 97.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 132 1.74% 99.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 51 0.67% 99.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 10 0.13% 99.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 15 0.20% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 7043 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 7579 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 2 4.26% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 46.81% 51.06% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 23 48.94% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 1 2.13% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.13% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 22 46.81% 48.94% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 24 51.06% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 2977 70.81% 70.81% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 808 19.22% 90.06% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 418 9.94% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 2999 70.50% 70.50% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.02% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 70.52% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 829 19.49% 90.01% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 425 9.99% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 4204 # Type of FU issued -system.cpu.iq.rate 0.328002 # Inst issue rate +system.cpu.iq.FU_type_0::total 4254 # Type of FU issued +system.cpu.iq.rate 0.234729 # Inst issue rate system.cpu.iq.fu_busy_cnt 47 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.011180 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 15542 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 7792 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 3821 # Number of integer instruction queue wakeup accesses +system.cpu.iq.fu_busy_rate 0.011048 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 16186 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 7949 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 3830 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 13 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 6 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 6 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 4244 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 4294 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 7 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 34 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 569 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 591 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 212 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 5 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 214 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 10 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 523 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 12 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 5532 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 63 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 984 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 506 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 547 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 5652 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 108 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 1006 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 508 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 6 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 61 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 160 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 221 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 4011 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 755 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 193 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 5 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 62 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 155 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 217 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 4043 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 782 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 211 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 353 # number of nop insts executed -system.cpu.iew.exec_refs 1161 # number of memory reference insts executed -system.cpu.iew.exec_branches 678 # Number of branches executed -system.cpu.iew.exec_stores 406 # Number of stores executed -system.cpu.iew.exec_rate 0.312944 # Inst execution rate -system.cpu.iew.wb_sent 3922 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 3827 # cumulative count of insts written-back -system.cpu.iew.wb_producers 1795 # num instructions producing a value -system.cpu.iew.wb_consumers 2353 # num instructions consuming a value +system.cpu.iew.exec_nop 363 # number of nop insts executed +system.cpu.iew.exec_refs 1193 # number of memory reference insts executed +system.cpu.iew.exec_branches 672 # Number of branches executed +system.cpu.iew.exec_stores 411 # Number of stores executed +system.cpu.iew.exec_rate 0.223087 # Inst execution rate +system.cpu.iew.wb_sent 3934 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 3836 # cumulative count of insts written-back +system.cpu.iew.wb_producers 1789 # num instructions producing a value +system.cpu.iew.wb_consumers 2358 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.298588 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.762856 # average fanout of values written-back +system.cpu.iew.wb_rate 0.211665 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.758694 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2928 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 3067 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 179 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 6520 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.395092 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.243251 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 182 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 7032 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.366325 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.202351 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 5631 86.37% 86.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 221 3.39% 89.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 313 4.80% 94.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 120 1.84% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 64 0.98% 97.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 55 0.84% 98.22% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 34 0.52% 98.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 22 0.34% 99.08% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 60 0.92% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 6145 87.39% 87.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 219 3.11% 90.50% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 312 4.44% 94.94% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 120 1.71% 96.64% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 65 0.92% 97.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 56 0.80% 98.36% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 33 0.47% 98.83% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 21 0.30% 99.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 61 0.87% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 6520 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 7032 # Number of insts commited each cycle system.cpu.commit.committedInsts 2576 # Number of instructions committed system.cpu.commit.committedOps 2576 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -466,181 +467,181 @@ system.cpu.commit.branches 396 # Nu system.cpu.commit.fp_insts 6 # Number of committed floating point instructions. system.cpu.commit.int_insts 2367 # Number of committed integer instructions. system.cpu.commit.function_calls 71 # Number of function calls committed. -system.cpu.commit.bw_lim_events 60 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 61 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 11717 # The number of ROB reads -system.cpu.rob.rob_writes 11541 # The number of ROB writes -system.cpu.timesIdled 158 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 5774 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 12367 # The number of ROB reads +system.cpu.rob.rob_writes 11843 # The number of ROB writes +system.cpu.timesIdled 164 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 10544 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 2387 # Number of Instructions Simulated system.cpu.committedOps 2387 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 2387 # Number of Instructions Simulated -system.cpu.cpi 5.369501 # CPI: Cycles Per Instruction -system.cpu.cpi_total 5.369501 # CPI: Total CPI of All Threads -system.cpu.ipc 0.186237 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.186237 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 4858 # number of integer regfile reads -system.cpu.int_regfile_writes 2964 # number of integer regfile writes +system.cpu.cpi 7.592375 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.592375 # CPI: Total CPI of All Threads +system.cpu.ipc 0.131711 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.131711 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 4904 # number of integer regfile reads +system.cpu.int_regfile_writes 2974 # number of integer regfile writes system.cpu.fp_regfile_reads 6 # number of floating regfile reads system.cpu.misc_regfile_reads 1 # number of misc regfile reads system.cpu.misc_regfile_writes 1 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 92.000483 # Cycle average of tags in use -system.cpu.icache.total_refs 799 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 188 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.250000 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 92.415859 # Cycle average of tags in use +system.cpu.icache.total_refs 849 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 187 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.540107 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 92.000483 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.044922 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.044922 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 799 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 799 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 799 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 799 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 799 # number of overall hits -system.cpu.icache.overall_hits::total 799 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 243 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 243 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 243 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 243 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 243 # number of overall misses -system.cpu.icache.overall_misses::total 243 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 7449000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 7449000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 7449000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 7449000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 7449000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 7449000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1042 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1042 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1042 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1042 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1042 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.233205 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.233205 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.233205 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.233205 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.233205 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.233205 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30654.320988 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30654.320988 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30654.320988 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30654.320988 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30654.320988 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 92.415859 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.045125 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.045125 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 849 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 849 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 849 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 849 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 849 # number of overall hits +system.cpu.icache.overall_hits::total 849 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 248 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 248 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 248 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 248 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 248 # number of overall misses +system.cpu.icache.overall_misses::total 248 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 11771499 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 11771499 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 11771499 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 11771499 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 11771499 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 11771499 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1097 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1097 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1097 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1097 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1097 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1097 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.226071 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.226071 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.226071 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.226071 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.226071 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.226071 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47465.721774 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47465.721774 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47465.721774 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47465.721774 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47465.721774 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 102 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 34 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 55 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 55 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 55 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 55 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 55 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 188 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 188 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 188 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 5938000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 5938000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 5938000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 5938000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 5938000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 5938000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.180422 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.180422 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.180422 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.180422 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 31585.106383 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 31585.106383 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 31585.106383 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 31585.106383 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 61 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 61 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 61 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 61 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 61 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 187 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 187 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 187 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9118999 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 9118999 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9118999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 9118999 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9118999 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 9118999 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170465 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.170465 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170465 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.170465 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48764.700535 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48764.700535 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48764.700535 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48764.700535 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48764.700535 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48764.700535 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 44.834744 # Cycle average of tags in use -system.cpu.dcache.total_refs 777 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 45.370052 # Cycle average of tags in use +system.cpu.dcache.total_refs 789 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 9.141176 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 9.282353 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 44.834744 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.010946 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.010946 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 564 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 564 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 45.370052 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.011077 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.011077 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 576 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 576 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 213 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 213 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 777 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 777 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 777 # number of overall hits -system.cpu.dcache.overall_hits::total 777 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 120 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 120 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 789 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 789 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 789 # number of overall hits +system.cpu.dcache.overall_hits::total 789 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 123 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 123 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 81 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 81 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 201 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 201 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 201 # number of overall misses -system.cpu.dcache.overall_misses::total 201 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3706500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3706500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 2874500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 2874500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 6581000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 6581000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 6581000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 6581000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 684 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 684 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 204 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 204 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 204 # number of overall misses +system.cpu.dcache.overall_misses::total 204 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5446500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5446500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4115000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4115000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 9561500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 9561500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 9561500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 9561500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 699 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 699 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 294 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 294 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 978 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 978 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 978 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 978 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175439 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.175439 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 993 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 993 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 993 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 993 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.175966 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.175966 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.275510 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.275510 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.205521 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.205521 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.205521 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.205521 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30887.500000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30887.500000 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35487.654321 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35487.654321 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32741.293532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32741.293532 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32741.293532 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.205438 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.205438 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.205438 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.205438 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 44280.487805 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 44280.487805 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50802.469136 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 50802.469136 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46870.098039 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46870.098039 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46870.098039 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 85 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.333333 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 62 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 62 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 57 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 57 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 119 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 119 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 119 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 119 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 61 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 24 # number of WriteReq MSHR misses @@ -649,75 +650,75 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 85 system.cpu.dcache.demand_mshr_misses::total 85 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 85 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2417000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2417000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 953500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 953500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3370500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 3370500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3370500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 3370500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.089181 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.089181 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3349500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3349500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1349000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4698500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 4698500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4698500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 4698500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.087268 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.087268 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081633 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081633 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.086912 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.086912 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.086912 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39622.950820 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39622.950820 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39729.166667 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 39652.941176 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 39652.941176 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.085599 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.085599 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.085599 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.085599 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54909.836066 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54909.836066 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 56208.333333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 56208.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 55276.470588 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 55276.470588 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 55276.470588 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 55276.470588 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 120.198004 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 121.264296 # Cycle average of tags in use system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 249 # Sample count of references to valid blocks. +system.cpu.l2cache.sampled_refs 248 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 92.103751 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 28.094254 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.002811 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000857 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.003668 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_misses::cpu.inst 188 # number of ReadReq misses +system.cpu.l2cache.occ_blocks::cpu.inst 92.675015 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 28.589281 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.002828 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000872 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.003701 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_misses::cpu.inst 187 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 61 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 249 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 248 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 24 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 24 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 188 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 187 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 85 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 273 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 188 # number of overall misses +system.cpu.l2cache.demand_misses::total 272 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 187 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 85 # number of overall misses -system.cpu.l2cache.overall_misses::total 273 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 5749500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2356000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 8105500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 928000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 928000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 5749500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 3284000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 9033500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 5749500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 3284000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 9033500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 188 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 272 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8931000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3288500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 12219500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1323500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 1323500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 8931000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 4612000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 13543000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 8931000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 4612000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 13543000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 187 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 61 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 249 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 248 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 24 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 24 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 188 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 187 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 85 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 273 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 188 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 272 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 187 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 85 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 273 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 272 # number of overall (read+write) accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses @@ -729,17 +730,17 @@ system.cpu.l2cache.demand_miss_rate::total 1 # system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 1 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 30582.446809 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 38622.950820 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 32552.208835 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38666.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38666.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 33089.743590 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 30582.446809 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 38635.294118 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 33089.743590 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47759.358289 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53909.836066 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49272.177419 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 55145.833333 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 55145.833333 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47759.358289 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54258.823529 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49790.441176 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47759.358289 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54258.823529 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49790.441176 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -748,28 +749,28 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 188 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 187 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 61 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 249 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 248 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 24 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 24 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 188 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 187 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 85 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 273 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 188 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 272 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 187 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 85 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 273 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 5087760 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2153056 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 7240816 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 847024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 847024 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 5087760 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3000080 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 8087840 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 5087760 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3000080 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 8087840 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_misses::total 272 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 6582780 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2536058 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 9118838 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1027024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1027024 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 6582780 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3563082 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 10145862 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 6582780 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3563082 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 10145862 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses @@ -781,17 +782,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 1 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 27062.553191 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 35296 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29079.582329 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35292.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35292.666667 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 27062.553191 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35295.058824 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 29625.787546 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35202.032086 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41574.721311 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36769.508065 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42792.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42792.666667 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35202.032086 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 41918.611765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37300.963235 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 122d34e0f..ccb8279d9 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10062000 # Number of ticks simulated -final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13414500 # Number of ticks simulated +final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 57856 # Simulator instruction rate (inst/s) -host_op_rate 72170 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 126623534 # Simulator tick rate (ticks/s) -host_mem_usage 231188 # Number of bytes of host memory used +host_inst_rate 59216 # Simulator instruction rate (inst/s) +host_op_rate 73866 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 172781643 # Simulator tick rate (ticks/s) +host_mem_usage 231444 # Number of bytes of host memory used host_seconds 0.08 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 398 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 398 # Total number of read requests seen +system.physmem.num_reads::total 400 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25472 # Total number of bytes read from memory +system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25600 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis @@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 10004500 # Total gap between requests +system.physmem.totGap 13356500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 398 # Categorize read packet sizes +system.physmem.readPktSize::6 401 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2567898 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests -system.physmem.totBusLat 1592000 # Total cycles spent in databus access -system.physmem.totBankLat 6552000 # Total cycles spent in bank access -system.physmem.avgQLat 6452.01 # Average queueing delay per request -system.physmem.avgBankLat 16462.31 # Average bank access latency per request +system.physmem.totQLat 2497399 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests +system.physmem.totBusLat 1604000 # Total cycles spent in databus access +system.physmem.totBankLat 6636000 # Total cycles spent in bank access +system.physmem.avgQLat 6227.93 # Average queueing delay per request +system.physmem.avgBankLat 16548.63 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26914.32 # Average memory access latency -system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26776.56 # Average memory access latency +system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.82 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.06 # Average read queue length over time +system.physmem.busUtil 11.93 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.80 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 323 # Number of row buffer hits during reads +system.physmem.readRowHits 326 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 25136.93 # Average gap between requests +system.physmem.avgGap 33307.98 # Average gap between requests system.cpu.checker.dtb.inst_hits 0 # ITB inst hits system.cpu.checker.dtb.inst_misses 0 # ITB inst misses system.cpu.checker.dtb.read_hits 0 # DTB read hits @@ -273,243 +273,245 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 20125 # number of cpu cycles simulated +system.cpu.numCycles 26830 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2519 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits +system.cpu.BPredUnit.lookups 2508 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2441 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2242 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2440 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2245 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 46 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer +system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle +system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8888 # Type of FU issued -system.cpu.iq.rate 0.441640 # Inst issue rate -system.cpu.iq.fu_busy_cnt 223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8896 # Type of FU issued +system.cpu.iq.rate 0.331569 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3261 # number of memory reference insts executed -system.cpu.iew.exec_branches 1428 # Number of branches executed -system.cpu.iew.exec_stores 1173 # Number of stores executed -system.cpu.iew.exec_rate 0.421615 # Inst execution rate -system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8062 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3862 # num instructions producing a value -system.cpu.iew.wb_consumers 7771 # num instructions consuming a value +system.cpu.iew.exec_nop 1 # number of nop insts executed +system.cpu.iew.exec_refs 3284 # number of memory reference insts executed +system.cpu.iew.exec_branches 1437 # Number of branches executed +system.cpu.iew.exec_stores 1174 # Number of stores executed +system.cpu.iew.exec_rate 0.316996 # Inst execution rate +system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8071 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3897 # num instructions producing a value +system.cpu.iew.wb_consumers 7827 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back +system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -520,307 +522,307 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22426 # The number of ROB reads -system.cpu.rob.rob_writes 23541 # The number of ROB writes -system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23385 # The number of ROB reads +system.cpu.rob.rob_writes 23680 # The number of ROB writes +system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.378808 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.378808 # CPI: Total CPI of All Threads -system.cpu.ipc 0.228373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.228373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39006 # number of integer regfile reads -system.cpu.int_regfile_writes 7962 # number of integer regfile writes +system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39120 # number of integer regfile reads +system.cpu.int_regfile_writes 7969 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15230 # number of misc regfile reads +system.cpu.misc_regfile_reads 15172 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 152.520984 # Cycle average of tags in use -system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.396610 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use +system.cpu.icache.total_refs 1570 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.520984 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074473 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074473 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits -system.cpu.icache.overall_hits::total 1592 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 358 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 358 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 358 # number of overall misses -system.cpu.icache.overall_misses::total 358 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11241000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11241000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11241000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11241000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11241000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11241000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183590 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183590 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183590 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183590 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183590 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183590 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31399.441341 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31399.441341 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31399.441341 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31399.441341 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits +system.cpu.icache.overall_hits::total 1570 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses +system.cpu.icache.overall_misses::total 373 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9141000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9141000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9141000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9141000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9141000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9141000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.151282 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.151282 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.151282 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30986.440678 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30986.440678 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14464500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14464500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14464500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14464500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14464500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14464500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153371 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153371 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153371 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48538.590604 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48538.590604 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.982117 # Cycle average of tags in use -system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.986301 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.306986 # Cycle average of tags in use +system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.982117 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021480 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021480 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1717 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1717 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2309 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2309 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2309 # number of overall hits -system.cpu.dcache.overall_hits::total 2309 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 185 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 185 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 321 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 321 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2324 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2324 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2324 # number of overall hits +system.cpu.dcache.overall_hits::total 2324 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 506 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 506 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 506 # number of overall misses -system.cpu.dcache.overall_misses::total 506 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5690000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5690000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10922000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 53000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 53000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16612000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16612000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16612000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16612000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1902 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses +system.cpu.dcache.overall_misses::total 518 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2815 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2815 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2815 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2815 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097266 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097266 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.351588 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.351588 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.179751 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.179751 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.179751 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.179751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30756.756757 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30756.756757 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34024.922118 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34024.922118 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32830.039526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32830.039526 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3250000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3250000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5169000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5169000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054679 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054679 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2418500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2418500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7324500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7324500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7324500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7324500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054951 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051865 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051865 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051865 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051865 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45690.476190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45690.476190 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35404.109589 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35404.109589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35404.109589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35404.109589 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.052076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.052076 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46283.018868 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46283.018868 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57583.333333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57583.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 191.265427 # Cycle average of tags in use -system.cpu.l2cache.total_refs 37 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.103933 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 186.094427 # Cycle average of tags in use +system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.274623 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.990804 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004403 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001434 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005837 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 37 # number of overall hits +system.cpu.l2cache.occ_blocks::cpu.inst 140.048248 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.046179 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004274 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001405 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits +system.cpu.l2cache.overall_hits::total 41 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 84 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses -system.cpu.l2cache.overall_misses::total 404 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8824000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3115500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11939500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1876000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8824000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4991500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13815500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8824000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4991500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13815500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 405 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13965500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4578500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2375500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2375500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13965500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6954000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20919500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13965500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6954000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20919500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 404 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942373 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.807692 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.907268 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 446 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 446 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932886 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.801887 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942373 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863014 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916100 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942373 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863014 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916100 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31741.007194 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37089.285714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 32982.044199 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 44666.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 44666.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31741.007194 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34196.782178 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31741.007194 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34196.782178 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -829,59 +831,56 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7843874 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2768060 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10611934 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1736536 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1736536 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7843874 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4504596 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12348470 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7843874 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4504596 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12348470 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.769231 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892231 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index f60a54b23..62de1d1aa 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,47 +1,47 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10062000 # Number of ticks simulated -final_tick 10062000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000013 # Number of seconds simulated +sim_ticks 13414500 # Number of ticks simulated +final_tick 13414500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 70596 # Simulator instruction rate (inst/s) -host_op_rate 88057 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 154493805 # Simulator tick rate (ticks/s) -host_mem_usage 230168 # Number of bytes of host memory used +host_inst_rate 64991 # Simulator instruction rate (inst/s) +host_op_rate 81070 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 189628588 # Simulator tick rate (ticks/s) +host_mem_usage 230428 # Number of bytes of host memory used host_seconds 0.07 # Real time elapsed on the host sim_insts 4596 # Number of instructions simulated sim_ops 5734 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 17792 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 7808 # Number of bytes read from this memory -system.physmem.bytes_read::total 25472 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 25600 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 17792 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 17792 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 278 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 122 # Number of read requests responded to by this memory -system.physmem.num_reads::total 398 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1755515802 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 775988869 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2531504671 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1755515802 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1755515802 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1755515802 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 775988869 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2531504671 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 398 # Total number of read requests seen +system.physmem.num_reads::total 400 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1326325991 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 582056730 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1908382720 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1326325991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1326325991 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1326325991 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 582056730 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1908382720 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 401 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 398 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 25472 # Total number of bytes read from memory +system.physmem.cpureqs 401 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 25600 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 25472 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 25600 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed system.physmem.perBankRdReqs::0 48 # Track reads on a per bank basis -system.physmem.perBankRdReqs::1 43 # Track reads on a per bank basis -system.physmem.perBankRdReqs::2 44 # Track reads on a per bank basis -system.physmem.perBankRdReqs::3 12 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 25 # Track reads on a per bank basis -system.physmem.perBankRdReqs::5 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::1 44 # Track reads on a per bank basis +system.physmem.perBankRdReqs::2 45 # Track reads on a per bank basis +system.physmem.perBankRdReqs::3 11 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 24 # Track reads on a per bank basis +system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 62 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 10 # Track reads on a per bank basis @@ -50,7 +50,7 @@ system.physmem.perBankRdReqs::10 28 # Tr system.physmem.perBankRdReqs::11 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::12 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 1 # Track reads on a per bank basis -system.physmem.perBankRdReqs::14 15 # Track reads on a per bank basis +system.physmem.perBankRdReqs::14 16 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 2 # Track reads on a per bank basis system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 10004500 # Total gap between requests +system.physmem.totGap 13356500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 398 # Categorize read packet sizes +system.physmem.readPktSize::6 401 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,10 +98,10 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 190 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 129 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 23 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 202 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 47 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2567898 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 10711898 # Sum of mem lat for all requests -system.physmem.totBusLat 1592000 # Total cycles spent in databus access -system.physmem.totBankLat 6552000 # Total cycles spent in bank access -system.physmem.avgQLat 6452.01 # Average queueing delay per request -system.physmem.avgBankLat 16462.31 # Average bank access latency per request +system.physmem.totQLat 2497399 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10737399 # Sum of mem lat for all requests +system.physmem.totBusLat 1604000 # Total cycles spent in databus access +system.physmem.totBankLat 6636000 # Total cycles spent in bank access +system.physmem.avgQLat 6227.93 # Average queueing delay per request +system.physmem.avgBankLat 16548.63 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26914.32 # Average memory access latency -system.physmem.avgRdBW 2531.50 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26776.56 # Average memory access latency +system.physmem.avgRdBW 1908.38 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2531.50 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1908.38 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.82 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.06 # Average read queue length over time +system.physmem.busUtil 11.93 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.80 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 323 # Number of row buffer hits during reads +system.physmem.readRowHits 326 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.16 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.30 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 25136.93 # Average gap between requests +system.physmem.avgGap 33307.98 # Average gap between requests system.cpu.dtb.inst_hits 0 # ITB inst hits system.cpu.dtb.inst_misses 0 # ITB inst misses system.cpu.dtb.read_hits 0 # DTB read hits @@ -228,243 +228,245 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 20125 # number of cpu cycles simulated +system.cpu.numCycles 26830 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2519 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1814 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 492 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1994 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 720 # Number of BTB hits +system.cpu.BPredUnit.lookups 2508 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1799 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 498 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1974 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 704 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 266 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 57 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 6589 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12264 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2519 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 986 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2669 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1615 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 1986 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.RASInCorrect 59 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 7071 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12196 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2508 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 970 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2652 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1649 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 2420 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1950 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 283 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 12344 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.244977 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.643916 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 7 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 1943 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 295 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.153249 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.570575 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9675 78.38% 78.38% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 218 1.77% 80.14% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 198 1.60% 81.75% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 234 1.90% 83.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 218 1.77% 85.41% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 293 2.37% 87.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 104 0.84% 88.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 141 1.14% 89.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1263 10.23% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10627 80.03% 80.03% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 220 1.66% 81.69% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 202 1.52% 83.21% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 225 1.69% 84.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 209 1.57% 86.47% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 282 2.12% 88.60% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 101 0.76% 89.36% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 141 1.06% 90.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1272 9.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 12344 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.125168 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.609391 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6607 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2275 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2441 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 79 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 942 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 382 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 13351 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 557 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 942 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6879 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 421 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 1584 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2242 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 276 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12528 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 23 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 224 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 12573 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 56963 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 56691 # Number of integer rename lookups -system.cpu.rename.fp_rename_lookups 272 # Number of floating rename lookups +system.cpu.fetch.rateDist::total 13279 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.093477 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.454566 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7059 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 2739 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2440 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 72 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 969 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 383 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 13357 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 554 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 969 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7319 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 464 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2037 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2245 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 245 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12559 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 194 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 12597 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57182 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 56886 # Number of integer rename lookups +system.cpu.rename.fp_rename_lookups 296 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5681 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6892 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 46 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 44 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 786 # count of insts added to the skid buffer +system.cpu.rename.UndoneMaps 6916 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 49 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 46 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 809 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2771 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1566 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 43 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 22 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 11233 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 56 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8888 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 106 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5186 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 14443 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 18 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 12344 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.720026 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.398788 # Number of insts issued each cycle +system.cpu.memDep0.insertedStores 1606 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 40 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 23 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 11289 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 54 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8896 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 98 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 5254 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14761 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 16 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 13279 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.669930 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.363134 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 8706 70.53% 70.53% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1401 11.35% 81.88% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 791 6.41% 88.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 558 4.52% 92.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 454 3.68% 96.48% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 254 2.06% 98.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 127 1.03% 99.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 41 0.33% 99.90% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 12 0.10% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 9645 72.63% 72.63% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1397 10.52% 83.15% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 791 5.96% 89.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 553 4.16% 93.28% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 448 3.37% 96.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 269 2.03% 98.67% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 121 0.91% 99.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 45 0.34% 99.92% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 10 0.08% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 12344 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13279 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 5 2.24% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.24% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 144 64.57% 66.82% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 74 33.18% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 1.86% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.86% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 140 65.12% 66.98% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 71 33.02% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5378 60.51% 60.51% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.59% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.62% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2274 25.59% 86.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1226 13.79% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5371 60.38% 60.38% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 7 0.08% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.45% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.03% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2303 25.89% 86.38% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1212 13.62% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8888 # Type of FU issued -system.cpu.iq.rate 0.441640 # Inst issue rate -system.cpu.iq.fu_busy_cnt 223 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.025090 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30413 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 16476 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8046 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8896 # Type of FU issued +system.cpu.iq.rate 0.331569 # Inst issue rate +system.cpu.iq.fu_busy_cnt 215 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.024168 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 31348 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 16565 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8055 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 36 # Number of floating instruction queue reads -system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes +system.cpu.iq.fp_inst_queue_writes 48 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses system.cpu.iq.int_alu_accesses 9091 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 20 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 59 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1570 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 20 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 627 # Number of stores squashed +system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 667 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 942 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 240 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 19 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11289 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewSquashCycles 969 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 273 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 24 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11344 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 97 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2771 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1566 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 43 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 9 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewDispStoreInsts 1606 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 41 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 20 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 99 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 285 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 384 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8485 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2088 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 403 # Number of squashed instructions skipped in execute +system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 286 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 387 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8505 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2110 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 391 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3261 # number of memory reference insts executed -system.cpu.iew.exec_branches 1428 # Number of branches executed -system.cpu.iew.exec_stores 1173 # Number of stores executed -system.cpu.iew.exec_rate 0.421615 # Inst execution rate -system.cpu.iew.wb_sent 8213 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8062 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3862 # num instructions producing a value -system.cpu.iew.wb_consumers 7771 # num instructions consuming a value +system.cpu.iew.exec_nop 1 # number of nop insts executed +system.cpu.iew.exec_refs 3284 # number of memory reference insts executed +system.cpu.iew.exec_branches 1437 # Number of branches executed +system.cpu.iew.exec_stores 1174 # Number of stores executed +system.cpu.iew.exec_rate 0.316996 # Inst execution rate +system.cpu.iew.wb_sent 8217 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8071 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3897 # num instructions producing a value +system.cpu.iew.wb_consumers 7827 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.400596 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.496976 # average fanout of values written-back +system.cpu.iew.wb_rate 0.300820 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.497892 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5560 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5615 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 38 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 335 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 11403 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.502850 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.330846 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 339 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12311 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.465762 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.295726 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 9072 79.56% 79.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1121 9.83% 89.39% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 403 3.53% 92.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 263 2.31% 95.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 172 1.51% 96.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 166 1.46% 98.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 56 0.49% 98.68% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 36 0.32% 99.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 114 1.00% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10015 81.35% 81.35% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1085 8.81% 90.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 395 3.21% 93.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 260 2.11% 95.48% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 181 1.47% 96.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 168 1.36% 98.32% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 52 0.42% 98.74% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 37 0.30% 99.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 118 0.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 11403 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 12311 # Number of insts commited each cycle system.cpu.commit.committedInsts 4596 # Number of instructions committed system.cpu.commit.committedOps 5734 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -475,307 +477,307 @@ system.cpu.commit.branches 1008 # Nu system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4980 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. -system.cpu.commit.bw_lim_events 114 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 118 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 22426 # The number of ROB reads -system.cpu.rob.rob_writes 23541 # The number of ROB writes -system.cpu.timesIdled 200 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7781 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23385 # The number of ROB reads +system.cpu.rob.rob_writes 23680 # The number of ROB writes +system.cpu.timesIdled 222 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13551 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 4596 # Number of Instructions Simulated system.cpu.committedOps 5734 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 4596 # Number of Instructions Simulated -system.cpu.cpi 4.378808 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.378808 # CPI: Total CPI of All Threads -system.cpu.ipc 0.228373 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.228373 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 39006 # number of integer regfile reads -system.cpu.int_regfile_writes 7962 # number of integer regfile writes +system.cpu.cpi 5.837685 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.837685 # CPI: Total CPI of All Threads +system.cpu.ipc 0.171301 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.171301 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 39120 # number of integer regfile reads +system.cpu.int_regfile_writes 7969 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.misc_regfile_reads 15230 # number of misc regfile reads +system.cpu.misc_regfile_reads 15172 # number of misc regfile reads system.cpu.misc_regfile_writes 26 # number of misc regfile writes system.cpu.icache.replacements 4 # number of replacements -system.cpu.icache.tagsinuse 152.520984 # Cycle average of tags in use -system.cpu.icache.total_refs 1592 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.396610 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 148.334500 # Cycle average of tags in use +system.cpu.icache.total_refs 1570 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 298 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.268456 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 152.520984 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.074473 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.074473 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1592 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1592 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1592 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1592 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1592 # number of overall hits -system.cpu.icache.overall_hits::total 1592 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 358 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 358 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 358 # number of overall misses -system.cpu.icache.overall_misses::total 358 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 11241000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 11241000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 11241000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 11241000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 11241000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 11241000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1950 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1950 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1950 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1950 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1950 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.183590 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.183590 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.183590 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.183590 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.183590 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.183590 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31399.441341 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31399.441341 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31399.441341 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31399.441341 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31399.441341 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 148.334500 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.072429 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.072429 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1570 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1570 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1570 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1570 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1570 # number of overall hits +system.cpu.icache.overall_hits::total 1570 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 373 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 373 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 373 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 373 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 373 # number of overall misses +system.cpu.icache.overall_misses::total 373 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 17664000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 17664000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 17664000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 17664000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 17664000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 17664000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1943 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1943 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1943 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1943 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1943 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.191971 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.191971 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.191971 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.191971 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.191971 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.191971 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47356.568365 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47356.568365 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47356.568365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47356.568365 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47356.568365 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 120 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 63 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 63 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 63 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 63 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 63 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 63 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9141000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 9141000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9141000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 9141000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9141000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 9141000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.151282 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.151282 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.151282 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.151282 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30986.440678 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30986.440678 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30986.440678 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 30986.440678 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 75 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 75 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 75 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 75 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 75 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 298 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 298 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 298 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 298 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 298 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 298 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14464500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14464500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14464500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14464500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14464500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14464500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153371 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.153371 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153371 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.153371 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48538.590604 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48538.590604 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48538.590604 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48538.590604 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 87.982117 # Cycle average of tags in use -system.cpu.dcache.total_refs 2334 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 15.986301 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 86.306986 # Cycle average of tags in use +system.cpu.dcache.total_refs 2349 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 15.979592 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 87.982117 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021480 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021480 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1717 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1717 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 592 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 592 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 86.306986 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021071 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021071 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1728 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1728 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 596 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 596 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 13 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 13 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 12 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 12 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2309 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2309 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2309 # number of overall hits -system.cpu.dcache.overall_hits::total 2309 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 185 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 185 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 321 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 321 # number of WriteReq misses +system.cpu.dcache.demand_hits::cpu.data 2324 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2324 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2324 # number of overall hits +system.cpu.dcache.overall_hits::total 2324 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 201 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 201 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 317 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 317 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 506 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 506 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 506 # number of overall misses -system.cpu.dcache.overall_misses::total 506 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5690000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5690000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 10922000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 10922000 # number of WriteReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 53000 # number of LoadLockedReq miss cycles -system.cpu.dcache.LoadLockedReq_miss_latency::total 53000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16612000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16612000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16612000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16612000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1902 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1902 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 518 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 518 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 518 # number of overall misses +system.cpu.dcache.overall_misses::total 518 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8747500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8747500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15091000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15091000 # number of WriteReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 87500 # number of LoadLockedReq miss cycles +system.cpu.dcache.LoadLockedReq_miss_latency::total 87500 # number of LoadLockedReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23838500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23838500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23838500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23838500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1929 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1929 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 15 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 12 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 12 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2815 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2815 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2815 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2815 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.097266 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.097266 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.351588 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.351588 # miss rate for WriteReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2842 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2842 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2842 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2842 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.104199 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.104199 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.347207 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.347207 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.133333 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.133333 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.179751 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.179751 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.179751 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.179751 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 30756.756757 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 30756.756757 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34024.922118 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 34024.922118 # average WriteReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 26500 # average LoadLockedReq miss latency -system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 26500 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 32830.039526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 32830.039526 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 32830.039526 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.182266 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.182266 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.182266 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.182266 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43519.900498 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 43519.900498 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47605.678233 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47605.678233 # average WriteReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 43750 # average LoadLockedReq miss latency +system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 43750 # average LoadLockedReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46020.270270 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46020.270270 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46020.270270 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 81 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 81 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 279 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 279 # number of WriteReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 95 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 95 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 275 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 275 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 360 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 360 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 360 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 104 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 104 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 370 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 370 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 370 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 370 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 106 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 106 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 42 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3250000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3250000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1919000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5169000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5169000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5169000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054679 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054679 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 148 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 148 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 148 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 4906000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2418500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2418500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7324500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7324500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7324500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7324500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.054951 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.054951 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.051865 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.051865 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.051865 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.051865 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 31250 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 31250 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 45690.476190 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 45690.476190 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 35404.109589 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 35404.109589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 35404.109589 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 35404.109589 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.052076 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.052076 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.052076 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46283.018868 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46283.018868 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57583.333333 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57583.333333 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 49489.864865 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 49489.864865 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 191.265427 # Cycle average of tags in use -system.cpu.l2cache.total_refs 37 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 356 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.103933 # Average number of references to valid blocks. +system.cpu.l2cache.tagsinuse 186.094427 # Cycle average of tags in use +system.cpu.l2cache.total_refs 41 # Total number of references to valid blocks. +system.cpu.l2cache.sampled_refs 358 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.114525 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 144.274623 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 46.990804 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004403 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001434 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005837 # Average percentage of cache occupancy -system.cpu.l2cache.ReadReq_hits::cpu.inst 17 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 20 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::total 37 # number of ReadReq hits -system.cpu.l2cache.demand_hits::cpu.inst 17 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 20 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::total 37 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 17 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 20 # number of overall hits -system.cpu.l2cache.overall_hits::total 37 # number of overall hits +system.cpu.l2cache.occ_blocks::cpu.inst 140.048248 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 46.046179 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004274 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001405 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005679 # Average percentage of cache occupancy +system.cpu.l2cache.ReadReq_hits::cpu.inst 20 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 21 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::total 41 # number of ReadReq hits +system.cpu.l2cache.demand_hits::cpu.inst 20 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 21 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::total 41 # number of demand (read+write) hits +system.cpu.l2cache.overall_hits::cpu.inst 20 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 21 # number of overall hits +system.cpu.l2cache.overall_hits::total 41 # number of overall hits system.cpu.l2cache.ReadReq_misses::cpu.inst 278 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 84 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 362 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 85 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 363 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 42 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 42 # number of ReadExReq misses system.cpu.l2cache.demand_misses::cpu.inst 278 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 126 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 404 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 127 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 405 # number of demand (read+write) misses system.cpu.l2cache.overall_misses::cpu.inst 278 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 126 # number of overall misses -system.cpu.l2cache.overall_misses::total 404 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 8824000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3115500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 11939500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1876000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1876000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 8824000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4991500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 13815500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 8824000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4991500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 13815500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 104 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::cpu.data 127 # number of overall misses +system.cpu.l2cache.overall_misses::total 405 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 13965500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4578500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18544000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2375500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2375500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 13965500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6954000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 20919500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 13965500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6954000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 20919500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 298 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 106 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 404 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.942373 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.807692 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.907268 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 298 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 148 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 446 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 298 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 148 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 446 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.932886 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.801887 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.898515 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.942373 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.863014 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.916100 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.942373 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.863014 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.916100 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31741.007194 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37089.285714 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 32982.044199 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 44666.666667 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 44666.666667 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31741.007194 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34196.782178 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31741.007194 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39615.079365 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34196.782178 # average overall miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.932886 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.858108 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.908072 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.932886 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.858108 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.908072 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50235.611511 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53864.705882 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51085.399449 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 56559.523810 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 56559.523810 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51653.086420 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50235.611511 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 54755.905512 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51653.086420 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -784,59 +786,56 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 2 # number of ReadReq MSHR hits system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.l2cache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits -system.cpu.l2cache.demand_mshr_hits::cpu.inst 2 # number of demand (read+write) MSHR hits +system.cpu.l2cache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits system.cpu.l2cache.demand_mshr_hits::cpu.data 4 # number of demand (read+write) MSHR hits -system.cpu.l2cache.demand_mshr_hits::total 6 # number of demand (read+write) MSHR hits -system.cpu.l2cache.overall_mshr_hits::cpu.inst 2 # number of overall MSHR hits +system.cpu.l2cache.demand_mshr_hits::total 4 # number of demand (read+write) MSHR hits system.cpu.l2cache.overall_mshr_hits::cpu.data 4 # number of overall MSHR hits -system.cpu.l2cache.overall_mshr_hits::total 6 # number of overall MSHR hits -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 80 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses +system.cpu.l2cache.overall_mshr_hits::total 4 # number of overall MSHR hits +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 278 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 81 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 359 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 122 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 398 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 122 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 398 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 7843874 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2768060 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 10611934 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1736536 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1736536 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 7843874 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4504596 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 12348470 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 7843874 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4504596 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 12348470 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.769231 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.892231 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 123 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 401 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 123 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 401 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10474409 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3438066 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13912475 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1855540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1855540 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10474409 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5293606 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 15768015 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10474409 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5293606 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 15768015 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764151 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.888614 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.902494 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.935593 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.835616 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.902494 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28419.833333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34600.750000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 29808.803371 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 41346.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 41346.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28419.833333 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36922.918033 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31026.306533 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.899103 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.932886 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.831081 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.899103 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37677.730216 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42445.259259 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38753.412256 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 44179.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 44179.523810 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37677.730216 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43037.447154 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39321.733167 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt index 8aae2e3f0..02dd2c613 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000019 # Number of seconds simulated -sim_ticks 19373000 # Number of ticks simulated -final_tick 19373000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 18578000 # Number of ticks simulated +final_tick 18578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 54522 # Simulator instruction rate (inst/s) -host_op_rate 54510 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 181593348 # Simulator tick rate (ticks/s) -host_mem_usage 216696 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 97793 # Simulator instruction rate (inst/s) +host_op_rate 97754 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 312246493 # Simulator tick rate (ticks/s) +host_mem_usage 216964 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5814 # Number of instructions simulated sim_ops 5814 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 20288 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 20288 # Nu system.physmem.num_reads::cpu.inst 317 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 455 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1047230682 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 455892221 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1503122903 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1047230682 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1047230682 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1047230682 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 455892221 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1503122903 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1092044354 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 475401012 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1567445365 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1092044354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1092044354 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1092044354 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 475401012 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1567445365 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 455 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 455 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19298000 # Total gap between requests +system.physmem.totGap 18503000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,9 +98,9 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 311 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 114 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 292 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 24 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 5 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2404453 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 12694453 # Sum of mem lat for all requests +system.physmem.totQLat 2353954 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12657954 # Sum of mem lat for all requests system.physmem.totBusLat 1820000 # Total cycles spent in databus access -system.physmem.totBankLat 8470000 # Total cycles spent in bank access -system.physmem.avgQLat 5284.51 # Average queueing delay per request -system.physmem.avgBankLat 18615.38 # Average bank access latency per request +system.physmem.totBankLat 8484000 # Total cycles spent in bank access +system.physmem.avgQLat 5173.53 # Average queueing delay per request +system.physmem.avgBankLat 18646.15 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27899.90 # Average memory access latency -system.physmem.avgRdBW 1503.12 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 27819.68 # Average memory access latency +system.physmem.avgRdBW 1567.45 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1503.12 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1567.45 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.39 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.66 # Average read queue length over time +system.physmem.busUtil 9.80 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.68 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 357 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 78.46 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42413.19 # Average gap between requests +system.physmem.avgGap 40665.93 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -204,7 +204,7 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 38747 # number of cpu cycles simulated +system.cpu.numCycles 37157 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.branch_predictor.lookups 1146 # Number of BP lookups @@ -217,13 +217,13 @@ system.cpu.branch_predictor.RASInCorrect 32 # Nu system.cpu.branch_predictor.BTBHitPct 34.843206 # BTB Hit Percentage system.cpu.branch_predictor.predictedTaken 393 # Number of Branches Predicted As Taken (True). system.cpu.branch_predictor.predictedNotTaken 753 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5096 # Number of Reads from Int. Register File +system.cpu.regfile_manager.intRegFileReads 5127 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3396 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 8492 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 8523 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 3 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 1 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 4 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1320 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1290 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 2235 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 260 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 336 # Number of Branches Incorrectly Predicted As Not Taken). @@ -234,12 +234,12 @@ system.cpu.execution_unit.executions 3144 # Nu system.cpu.mult_div_unit.multiplies 3 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 1 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9675 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9465 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 483 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 33362 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 5385 # Number of cycles cpu stages are processed. -system.cpu.activity 13.897850 # Percentage of cycles cpu is active +system.cpu.timesIdled 477 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 31782 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 5375 # Number of cycles cpu stages are processed. +system.cpu.activity 14.465646 # Percentage of cycles cpu is active system.cpu.comLoads 1163 # Number of Load instructions committed system.cpu.comStores 925 # Number of Store instructions committed system.cpu.comBranches 915 # Number of Branches instructions committed @@ -251,144 +251,144 @@ system.cpu.committedInsts 5814 # Nu system.cpu.committedOps 5814 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5814 # Number of Instructions committed (Total) -system.cpu.cpi 6.664431 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.390953 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.664431 # CPI: Total CPI of All Threads -system.cpu.ipc 0.150050 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.390953 # CPI: Total CPI of All Threads +system.cpu.ipc 0.156471 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.150050 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 35122 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 3625 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 9.355563 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 35925 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 2822 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 7.283145 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 35963 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 2784 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 7.185072 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 37505 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 1242 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 3.205409 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 35843 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 2904 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 7.494774 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.156471 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 33517 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 3640 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 9.796270 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 34336 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 2821 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 7.592109 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 34391 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 2766 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 7.444089 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 35931 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 1226 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 3.299513 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 34254 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 2903 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 7.812794 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 13 # number of replacements -system.cpu.icache.tagsinuse 148.105671 # Cycle average of tags in use +system.cpu.icache.tagsinuse 149.857420 # Cycle average of tags in use system.cpu.icache.total_refs 410 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 319 # Sample count of references to valid blocks. system.cpu.icache.avg_refs 1.285266 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 148.105671 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.072317 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.072317 # Average percentage of cache occupancy +system.cpu.icache.occ_blocks::cpu.inst 149.857420 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.073173 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.073173 # Average percentage of cache occupancy system.cpu.icache.ReadReq_hits::cpu.inst 410 # number of ReadReq hits system.cpu.icache.ReadReq_hits::total 410 # number of ReadReq hits system.cpu.icache.demand_hits::cpu.inst 410 # number of demand (read+write) hits system.cpu.icache.demand_hits::total 410 # number of demand (read+write) hits system.cpu.icache.overall_hits::cpu.inst 410 # number of overall hits system.cpu.icache.overall_hits::total 410 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 344 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 344 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 344 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 344 # number of overall misses -system.cpu.icache.overall_misses::total 344 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18000000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18000000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18000000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18000000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18000000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18000000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 754 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 754 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 754 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 754 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 754 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.456233 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.456233 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.456233 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.456233 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.456233 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.456233 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52325.581395 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 52325.581395 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 52325.581395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 52325.581395 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 52325.581395 # average overall miss latency +system.cpu.icache.ReadReq_misses::cpu.inst 346 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 346 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 346 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 346 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 346 # number of overall misses +system.cpu.icache.overall_misses::total 346 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18065500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18065500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18065500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18065500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18065500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18065500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 756 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 756 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 756 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 756 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 756 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 756 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.457672 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.457672 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.457672 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.457672 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.457672 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.457672 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52212.427746 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 52212.427746 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 52212.427746 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 52212.427746 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 52212.427746 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 34 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 34 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 25 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 25 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 25 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 25 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 25 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 25 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 27 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 27 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 27 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 27 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 27 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 27 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 319 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 319 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 319 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 319 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 319 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 319 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16448000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 16448000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16448000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 16448000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16448000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 16448000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.423077 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.423077 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.423077 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51561.128527 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51561.128527 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51561.128527 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 51561.128527 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16466000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16466000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16466000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16466000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16466000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16466000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.421958 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.421958 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.421958 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.421958 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51617.554859 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51617.554859 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51617.554859 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51617.554859 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 89.430963 # Cycle average of tags in use -system.cpu.dcache.total_refs 1834 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 89.860913 # Cycle average of tags in use +system.cpu.dcache.total_refs 1644 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.289855 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 11.913043 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 89.430963 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.021834 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.021834 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1072 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1072 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 762 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 762 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1834 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1834 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1834 # number of overall hits -system.cpu.dcache.overall_hits::total 1834 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 91 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 91 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 163 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 163 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 254 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 254 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 254 # number of overall misses -system.cpu.dcache.overall_misses::total 254 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5497500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5497500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 8188000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 8188000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 13685500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 13685500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 13685500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 13685500 # number of overall miss cycles +system.cpu.dcache.occ_blocks::cpu.data 89.860913 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.021939 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.021939 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1070 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1070 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 574 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 574 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 1644 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1644 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1644 # number of overall hits +system.cpu.dcache.overall_hits::total 1644 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 93 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 93 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 351 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 351 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 444 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 444 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 444 # number of overall misses +system.cpu.dcache.overall_misses::total 444 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 5589000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 5589000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14658500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14658500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 20247500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 20247500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 20247500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 20247500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) @@ -397,38 +397,38 @@ system.cpu.dcache.demand_accesses::cpu.data 2088 # system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078246 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.078246 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.176216 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.176216 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.121648 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.121648 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.121648 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.121648 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60412.087912 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 60412.087912 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 50233.128834 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 50233.128834 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 53879.921260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 53879.921260 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 53879.921260 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 2069 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 23 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 89.956522 # average number of cycles each access was blocked +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079966 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.079966 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.379459 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.379459 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.212644 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.212644 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.212644 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.212644 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60096.774194 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 60096.774194 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41762.108262 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 41762.108262 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 45602.477477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 45602.477477 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 45602.477477 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 99 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 99 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 4 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 4 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 112 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 112 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 116 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 116 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 116 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 6 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 6 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 300 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 300 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 306 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 306 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 306 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -437,14 +437,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5201000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 5201000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2605000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2605000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7806000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7806000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7806000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7806000 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5155000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5155000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2618500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7773500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7773500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7773500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7773500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses @@ -453,26 +453,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59781.609195 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59781.609195 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51078.431373 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51078.431373 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56565.217391 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 56565.217391 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59252.873563 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59252.873563 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51343.137255 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51343.137255 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56329.710145 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56329.710145 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 205.347343 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 207.494837 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 404 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.004950 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 149.740781 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 55.606562 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004570 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001697 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006267 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 151.607312 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 55.887525 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004627 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001706 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006332 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -490,17 +490,17 @@ system.cpu.l2cache.demand_misses::total 455 # nu system.cpu.l2cache.overall_misses::cpu.inst 317 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 455 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16102500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5107500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 21210000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2551000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2551000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 16102500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7658500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 23761000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 16102500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7658500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 23761000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16120500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5061500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 21182000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2564500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2564500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16120500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7626000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 23746500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16120500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7626000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 23746500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 319 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 406 # number of ReadReq accesses(hits+misses) @@ -523,17 +523,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995624 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993730 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995624 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50796.529968 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58706.896552 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 52500 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50019.607843 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50019.607843 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 52221.978022 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50796.529968 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55496.376812 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 52221.978022 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 50853.312303 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 58178.160920 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 52430.693069 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50284.313725 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50284.313725 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 52190.109890 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 50853.312303 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55260.869565 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 52190.109890 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -553,17 +553,17 @@ system.cpu.l2cache.demand_mshr_misses::total 455 system.cpu.l2cache.overall_mshr_misses::cpu.inst 317 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 455 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12097521 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4026597 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16124118 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1915572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1915572 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12097521 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5942169 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 18039690 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12097521 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5942169 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 18039690 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12117017 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3982094 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16099111 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1929572 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1929572 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12117017 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5911666 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18028683 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12117017 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5911666 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18028683 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995074 # mshr miss rate for ReadReq accesses @@ -575,17 +575,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995624 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993730 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995624 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38162.526814 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46282.724138 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39911.183168 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37560.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37560.235294 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38162.526814 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43059.195652 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39647.670330 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38224.028391 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45771.195402 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39849.284653 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37834.745098 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37834.745098 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38224.028391 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42838.159420 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39623.479121 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt index 85090bc10..7222464d9 100644 --- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12097500 # Number of ticks simulated -final_tick 12097500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16437500 # Number of ticks simulated +final_tick 16437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 46391 # Simulator instruction rate (inst/s) -host_op_rate 46381 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 108798708 # Simulator tick rate (ticks/s) -host_mem_usage 217720 # Number of bytes of host memory used -host_seconds 0.11 # Real time elapsed on the host +host_inst_rate 79981 # Simulator instruction rate (inst/s) +host_op_rate 79951 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 254800448 # Simulator tick rate (ticks/s) +host_mem_usage 217976 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host sim_insts 5156 # Number of instructions simulated sim_ops 5156 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 21696 # Nu system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory system.physmem.num_reads::total 480 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1793428394 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 745939244 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2539367638 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1793428394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1793428394 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1793428394 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 745939244 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2539367638 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1319908745 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 548988593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1868897338 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1319908745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1319908745 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1319908745 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 548988593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1868897338 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 480 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 12035000 # Total gap between requests +system.physmem.totGap 16357500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,12 +98,12 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 255 # What read queue length does an incoming req see system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3039980 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13667980 # Sum of mem lat for all requests +system.physmem.totQLat 2266480 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12950480 # Sum of mem lat for all requests system.physmem.totBusLat 1920000 # Total cycles spent in databus access -system.physmem.totBankLat 8708000 # Total cycles spent in bank access -system.physmem.avgQLat 6333.29 # Average queueing delay per request -system.physmem.avgBankLat 18141.67 # Average bank access latency per request +system.physmem.totBankLat 8764000 # Total cycles spent in bank access +system.physmem.avgQLat 4721.83 # Average queueing delay per request +system.physmem.avgBankLat 18258.33 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 28474.96 # Average memory access latency -system.physmem.avgRdBW 2539.37 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26980.17 # Average memory access latency +system.physmem.avgRdBW 1868.90 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2539.37 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1868.90 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 15.87 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.13 # Average read queue length over time +system.physmem.busUtil 11.68 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 380 # Number of row buffer hits during reads +system.physmem.readRowHits 378 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 79.17 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.75 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 25072.92 # Average gap between requests +system.physmem.avgGap 34078.12 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -204,243 +204,243 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 8 # Number of system calls -system.cpu.numCycles 24196 # number of cpu cycles simulated +system.cpu.numCycles 32876 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2174 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 1443 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 1705 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 494 # Number of BTB hits +system.cpu.BPredUnit.lookups 2145 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 1420 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 444 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 1692 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 498 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 283 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8516 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 13177 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 777 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 3260 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1345 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 699 # Number of cycles fetch has spent blocked +system.cpu.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 8858 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 13016 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2145 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 768 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 3241 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 897 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 157 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 260 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13523 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.974414 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.279455 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 2015 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.926867 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.227706 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10263 75.89% 75.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 1359 10.05% 85.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 113 0.84% 86.78% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 150 1.11% 87.89% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 301 2.23% 90.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 101 0.75% 90.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 159 1.18% 92.04% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 137 1.01% 93.05% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 940 6.95% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10802 76.92% 76.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 1358 9.67% 86.59% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 113 0.80% 87.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 147 1.05% 88.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 305 2.17% 90.61% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 111 0.79% 91.40% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 157 1.12% 92.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 126 0.90% 93.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 924 6.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13523 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.089850 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.544594 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 8657 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 898 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3079 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 45 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 844 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 154 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12246 # Number of instructions handled by decode +system.cpu.fetch.rateDist::total 14043 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065245 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.395912 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 8962 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1117 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3062 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 858 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 844 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 8855 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 196 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 599 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2928 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 101 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11668 # Number of instructions processed by rename -system.cpu.rename.LSQFullEvents 92 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 7112 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 13873 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 13869 # Number of integer rename lookups +system.cpu.rename.SquashCycles 858 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 9149 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2921 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11564 # Number of instructions processed by rename +system.cpu.rename.LSQFullEvents 95 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 7026 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 13727 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 13723 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3714 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 18 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 271 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2456 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1189 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 3628 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 17 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 273 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 9092 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 14 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8231 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3471 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 1958 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 4 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13523 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.608667 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.271089 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 9022 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3390 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 1898 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 14043 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.584063 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.245002 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 9982 73.81% 73.81% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1399 10.35% 84.16% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 867 6.41% 90.57% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 551 4.07% 94.65% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 358 2.65% 97.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 239 1.77% 99.06% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 85 0.63% 99.69% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 28 0.21% 99.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10483 74.65% 74.65% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1421 10.12% 84.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 877 6.25% 91.01% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 557 3.97% 94.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 353 2.51% 97.49% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 225 1.60% 99.10% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 84 0.60% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13523 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14043 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 3 2.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.00% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 95 63.33% 65.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 52 34.67% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 3 1.96% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 97 63.40% 65.36% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 53 34.64% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4866 59.12% 59.12% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.20% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.23% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2254 27.38% 86.61% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1102 13.39% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4842 59.03% 59.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.10% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.12% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2249 27.42% 86.56% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1102 13.44% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8231 # Type of FU issued -system.cpu.iq.rate 0.340180 # Inst issue rate -system.cpu.iq.fu_busy_cnt 150 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.018224 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30186 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 12584 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7378 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8202 # Type of FU issued +system.cpu.iq.rate 0.249483 # Inst issue rate +system.cpu.iq.fu_busy_cnt 153 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.018654 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30641 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 12433 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7364 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8379 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8353 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1293 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 264 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1275 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 844 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 139 # Number of cycles IEW is blocking +system.cpu.iew.iewSquashCycles 858 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 190 # Number of cycles IEW is blocking system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10561 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispatchedInsts 10500 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2456 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1189 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 14 # Number of dispatched non-speculative instructions +system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 364 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 474 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 7823 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 2103 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute +system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 363 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 471 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7830 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 2115 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 372 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1455 # number of nop insts executed -system.cpu.iew.exec_refs 3177 # number of memory reference insts executed -system.cpu.iew.exec_branches 1335 # Number of branches executed -system.cpu.iew.exec_stores 1074 # Number of stores executed -system.cpu.iew.exec_rate 0.323318 # Inst execution rate -system.cpu.iew.wb_sent 7479 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7380 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2890 # num instructions producing a value -system.cpu.iew.wb_consumers 4129 # num instructions consuming a value +system.cpu.iew.exec_nop 1465 # number of nop insts executed +system.cpu.iew.exec_refs 3191 # number of memory reference insts executed +system.cpu.iew.exec_branches 1342 # Number of branches executed +system.cpu.iew.exec_stores 1076 # Number of stores executed +system.cpu.iew.exec_rate 0.238168 # Inst execution rate +system.cpu.iew.wb_sent 7455 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7366 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2870 # num instructions producing a value +system.cpu.iew.wb_consumers 4099 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.305009 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.699927 # average fanout of values written-back +system.cpu.iew.wb_rate 0.224054 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.700171 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 4740 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4679 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 401 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12679 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.458475 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.250836 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 399 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 13185 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.440880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.228954 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10300 81.24% 81.24% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 973 7.67% 88.91% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 629 4.96% 93.87% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 317 2.50% 96.37% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 148 1.17% 97.54% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 88 0.69% 98.23% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 75 0.59% 98.82% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 43 0.34% 99.16% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.84% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10802 81.93% 81.93% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 977 7.41% 89.34% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 629 4.77% 94.11% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 318 2.41% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 150 1.14% 97.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 86 0.65% 98.31% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 74 0.56% 98.87% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.32% 99.19% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12679 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 13185 # Number of insts commited each cycle system.cpu.commit.committedInsts 5813 # Number of instructions committed system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -451,181 +451,181 @@ system.cpu.commit.branches 915 # Nu system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. system.cpu.commit.int_insts 5111 # Number of committed integer instructions. system.cpu.commit.function_calls 87 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 23113 # The number of ROB reads -system.cpu.rob.rob_writes 21959 # The number of ROB writes -system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 10673 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 23557 # The number of ROB reads +system.cpu.rob.rob_writes 21850 # The number of ROB writes +system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 18833 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5156 # Number of Instructions Simulated system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5156 # Number of Instructions Simulated -system.cpu.cpi 4.692785 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.692785 # CPI: Total CPI of All Threads -system.cpu.ipc 0.213093 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.213093 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 10646 # number of integer regfile reads -system.cpu.int_regfile_writes 5184 # number of integer regfile writes +system.cpu.cpi 6.376261 # CPI: Cycles Per Instruction +system.cpu.cpi_total 6.376261 # CPI: Total CPI of All Threads +system.cpu.ipc 0.156832 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.156832 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 10643 # number of integer regfile reads +system.cpu.int_regfile_writes 5150 # number of integer regfile writes system.cpu.fp_regfile_reads 3 # number of floating regfile reads system.cpu.fp_regfile_writes 1 # number of floating regfile writes -system.cpu.misc_regfile_reads 155 # number of misc regfile reads +system.cpu.misc_regfile_reads 154 # number of misc regfile reads system.cpu.icache.replacements 17 # number of replacements -system.cpu.icache.tagsinuse 162.253661 # Cycle average of tags in use -system.cpu.icache.total_refs 1552 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 164.359097 # Cycle average of tags in use +system.cpu.icache.total_refs 1560 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.538012 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 4.561404 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 162.253661 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.079225 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.079225 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1552 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1552 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1552 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1552 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1552 # number of overall hits -system.cpu.icache.overall_hits::total 1552 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 427 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 427 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 427 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 427 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 427 # number of overall misses -system.cpu.icache.overall_misses::total 427 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14343000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14343000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14343000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14343000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14343000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14343000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.215766 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.215766 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.215766 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.215766 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.215766 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.215766 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33590.163934 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33590.163934 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33590.163934 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33590.163934 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33590.163934 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 164.359097 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.080253 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.080253 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1560 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1560 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1560 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1560 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1560 # number of overall hits +system.cpu.icache.overall_hits::total 1560 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses +system.cpu.icache.overall_misses::total 455 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21541500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21541500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21541500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21541500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21541500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21541500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2015 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2015 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2015 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2015 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2015 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2015 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.225806 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.225806 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.225806 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.225806 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.225806 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.225806 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47343.956044 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47343.956044 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47343.956044 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47343.956044 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 85 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 85 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 85 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 85 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 85 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 85 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11802500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11802500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11802500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11802500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11802500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11802500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172815 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.172815 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172815 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.172815 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34510.233918 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34510.233918 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34510.233918 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34510.233918 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17063000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17063000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17063000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17063000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17063000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17063000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.169727 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.169727 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.169727 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49891.812865 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49891.812865 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 91.817694 # Cycle average of tags in use -system.cpu.dcache.total_refs 2445 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 91.458224 # Cycle average of tags in use +system.cpu.dcache.total_refs 2418 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 17.340426 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 17.148936 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 91.817694 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.022416 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.022416 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1868 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1868 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 577 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 577 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits -system.cpu.dcache.overall_hits::total 2445 # number of overall hits +system.cpu.dcache.occ_blocks::cpu.data 91.458224 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.022329 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.022329 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1846 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1846 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits +system.cpu.dcache.overall_hits::total 2418 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 348 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 348 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses -system.cpu.dcache.overall_misses::total 497 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5916000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5916000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9509000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9509000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 15425000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 15425000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 15425000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 15425000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 2017 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 2017 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses +system.cpu.dcache.overall_misses::total 502 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8305500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8305500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 15423499 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 15423499 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 23728999 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 23728999 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 23728999 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 23728999 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2942 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2942 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2942 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2942 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073872 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.073872 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.376216 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.376216 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.168933 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.168933 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.168933 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.168933 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 39704.697987 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 39704.697987 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27324.712644 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27324.712644 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 31036.217304 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 31036.217304 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 31036.217304 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2920 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2920 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2920 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2920 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074687 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.074687 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.171918 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.171918 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.171918 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.171918 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55741.610738 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55741.610738 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43692.631728 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 43692.631728 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47268.922311 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47268.922311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47268.922311 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47268.922311 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 489 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.454545 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 297 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 297 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 356 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 356 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 356 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 356 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 361 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 361 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses @@ -634,42 +634,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 141 system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3832000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1859000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 1859000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5691000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 5691000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5691000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 5691000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044621 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044621 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2754499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2754499 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8174499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8174499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045113 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045113 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.047927 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047927 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.047927 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42577.777778 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42577.777778 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36450.980392 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36450.980392 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 40361.702128 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 40361.702128 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048288 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.048288 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048288 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.048288 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60222.222222 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54009.784314 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54009.784314 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57975.170213 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57975.170213 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57975.170213 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57975.170213 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 222.617700 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 224.543944 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 164.369429 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 58.248271 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005016 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001778 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006794 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 166.808951 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 57.734994 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005091 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001762 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006853 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits @@ -687,17 +687,17 @@ system.cpu.l2cache.demand_misses::total 480 # nu system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses system.cpu.l2cache.overall_misses::total 480 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11455500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3737500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 15193000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 1807500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 1807500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 11455500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 5545000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 17000500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 11455500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 5545000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 17000500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16691000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5327000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 22018000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2702500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16691000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8029500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24720500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16691000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8029500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24720500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses) @@ -720,17 +720,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.993789 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33792.035398 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41527.777778 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 35414.918415 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 35441.176471 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 35441.176471 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 35417.708333 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33792.035398 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 39326.241135 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 35417.708333 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49235.988201 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59188.888889 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51324.009324 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52990.196078 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52990.196078 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51501.041667 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51501.041667 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -750,17 +750,17 @@ system.cpu.l2cache.demand_mshr_misses::total 480 system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10252004 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3439074 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13691078 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1635054 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1635054 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10252004 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5074128 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15326132 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10252004 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5074128 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15326132 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12421544 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4218076 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16639620 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12421544 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6289130 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18710674 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12421544 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6289130 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18710674 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses @@ -772,17 +772,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30241.899705 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 38211.933333 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31913.934732 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 32059.882353 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 32059.882353 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30241.899705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35986.723404 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31929.441667 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36641.722714 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46867.511111 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38786.993007 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt index 3c312e713..5e0f9ad46 100644 --- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000010 # Number of seconds simulated -sim_ticks 10184500 # Number of ticks simulated -final_tick 10184500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 14081500 # Number of ticks simulated +final_tick 14081500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 98086 # Simulator instruction rate (inst/s) -host_op_rate 98064 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 172399568 # Simulator tick rate (ticks/s) -host_mem_usage 213936 # Number of bytes of host memory used -host_seconds 0.06 # Real time elapsed on the host +host_inst_rate 87308 # Simulator instruction rate (inst/s) +host_op_rate 87279 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 212126284 # Simulator tick rate (ticks/s) +host_mem_usage 214180 # Number of bytes of host memory used +host_seconds 0.07 # Real time elapsed on the host sim_insts 5792 # Number of instructions simulated sim_ops 5792 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 22528 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 22464 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 6528 # Number of bytes read from this memory -system.physmem.bytes_read::total 29056 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 22528 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22528 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 352 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 28992 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 22464 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 22464 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 351 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 102 # Number of read requests responded to by this memory -system.physmem.num_reads::total 454 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2211988807 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 640974029 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2852962836 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2211988807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2211988807 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2211988807 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 640974029 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2852962836 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 454 # Total number of read requests seen +system.physmem.num_reads::total 453 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1595284593 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 463586976 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 2058871569 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1595284593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1595284593 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1595284593 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 463586976 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 2058871569 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 453 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 454 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 29056 # Total number of bytes read from memory +system.physmem.cpureqs 453 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 28992 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 29056 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 28992 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -42,7 +42,7 @@ system.physmem.perBankRdReqs::2 49 # Tr system.physmem.perBankRdReqs::3 21 # Track reads on a per bank basis system.physmem.perBankRdReqs::4 40 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 14 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 21 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 20 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 39 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 23 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 10067000 # Total gap between requests +system.physmem.totGap 13946000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 454 # Categorize read packet sizes +system.physmem.readPktSize::6 453 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 224 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 157 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 237 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 151 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 46 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,27 +164,27 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 2091454 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11313454 # Sum of mem lat for all requests -system.physmem.totBusLat 1816000 # Total cycles spent in databus access -system.physmem.totBankLat 7406000 # Total cycles spent in bank access -system.physmem.avgQLat 4606.73 # Average queueing delay per request -system.physmem.avgBankLat 16312.78 # Average bank access latency per request +system.physmem.totQLat 1940453 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11214453 # Sum of mem lat for all requests +system.physmem.totBusLat 1812000 # Total cycles spent in databus access +system.physmem.totBankLat 7462000 # Total cycles spent in bank access +system.physmem.avgQLat 4283.56 # Average queueing delay per request +system.physmem.avgBankLat 16472.41 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 24919.50 # Average memory access latency -system.physmem.avgRdBW 2852.96 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24755.97 # Average memory access latency +system.physmem.avgRdBW 2058.87 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2852.96 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 2058.87 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 17.83 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.11 # Average read queue length over time +system.physmem.busUtil 12.87 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.80 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 377 # Number of row buffer hits during reads +system.physmem.readRowHits 376 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.04 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.00 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 22174.01 # Average gap between requests +system.physmem.avgGap 30785.87 # Average gap between requests system.cpu.dtb.read_hits 0 # DTB read hits system.cpu.dtb.read_misses 0 # DTB read misses system.cpu.dtb.read_accesses 0 # DTB read accesses @@ -204,243 +204,244 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 9 # Number of system calls -system.cpu.numCycles 20370 # number of cpu cycles simulated +system.cpu.numCycles 28164 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 2504 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 2048 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 453 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2080 # Number of BTB lookups +system.cpu.BPredUnit.lookups 2468 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 2024 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 452 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2049 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 624 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 162 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 159 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 30 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 7226 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 14617 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2504 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 786 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 2424 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1424 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 732 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 1887 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 318 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 11348 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.288068 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.714156 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7429 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 14387 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2468 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 783 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 2394 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1429 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 964 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 2 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1877 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 322 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 11766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.222760 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.655950 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 8924 78.64% 78.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 176 1.55% 80.19% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 165 1.45% 81.64% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 138 1.22% 82.86% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 200 1.76% 84.62% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 150 1.32% 85.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 252 2.22% 88.17% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 109 0.96% 89.13% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1234 10.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 9372 79.65% 79.65% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 173 1.47% 81.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 165 1.40% 82.53% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 142 1.21% 83.73% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 200 1.70% 85.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 147 1.25% 86.68% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 252 2.14% 88.82% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 109 0.93% 89.75% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1206 10.25% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 11348 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.122926 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.717575 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 7362 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 868 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2237 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 77 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 804 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 358 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 166 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12862 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 473 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 804 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 7582 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 226 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 416 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2090 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 230 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 12157 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 192 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 10431 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 19827 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 19772 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 11766 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.087630 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.510829 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 7522 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 1142 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2216 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 80 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 806 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 353 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 161 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 12752 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 460 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 806 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 7732 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 454 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 444 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2079 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 251 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 12099 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 5 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 210 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 10388 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 19762 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 19707 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 55 # Number of floating rename lookups system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 5433 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 28 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 524 # count of insts added to the skid buffer +system.cpu.rename.UndoneMaps 5390 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 27 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 552 # count of insts added to the skid buffer system.cpu.memDep0.insertedLoads 2089 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1950 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1942 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 55 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 35 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10962 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10942 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 64 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 9314 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 176 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 4943 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 4190 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 9281 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 177 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4902 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 4209 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 48 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 11348 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.820761 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.558908 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 11766 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.788798 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.528040 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 7942 69.99% 69.99% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1067 9.40% 79.39% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 770 6.79% 86.17% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 514 4.53% 90.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 477 4.20% 94.91% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 338 2.98% 97.89% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 150 1.32% 99.21% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 53 0.47% 99.67% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 37 0.33% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 8334 70.83% 70.83% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1092 9.28% 80.11% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 789 6.71% 86.82% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 514 4.37% 91.19% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 473 4.02% 95.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 331 2.81% 98.02% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 146 1.24% 99.26% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 50 0.42% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 37 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 11348 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 11766 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 4 2.22% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.22% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 78 43.33% 45.56% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 98 54.44% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 4 2.26% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.26% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 77 43.50% 45.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 96 54.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5730 61.52% 61.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.52% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.52% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.54% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1859 19.96% 81.50% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1723 18.50% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 5705 61.47% 61.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 61.47% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 61.47% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 61.49% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1860 20.04% 81.53% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1714 18.47% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 9314 # Type of FU issued -system.cpu.iq.rate 0.457241 # Inst issue rate -system.cpu.iq.fu_busy_cnt 180 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.019326 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30270 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15941 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 8417 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 9281 # Type of FU issued +system.cpu.iq.rate 0.329534 # Inst issue rate +system.cpu.iq.fu_busy_cnt 177 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.019071 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30620 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 15880 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 8398 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 36 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 9460 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 9424 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 77 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address system.cpu.iew.lsq.thread0.squashedLoads 1128 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 8 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 904 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 896 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 804 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 11026 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewSquashCycles 806 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 266 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 11006 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch system.cpu.iew.iewDispLoadInsts 2089 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1950 # Number of dispatched store instructions +system.cpu.iew.iewDispStoreInsts 1942 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 8 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 78 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 302 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 380 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8807 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1716 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 507 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 79 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 304 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 383 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 8796 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1725 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 485 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3293 # number of memory reference insts executed -system.cpu.iew.exec_branches 1392 # Number of branches executed +system.cpu.iew.exec_refs 3302 # number of memory reference insts executed +system.cpu.iew.exec_branches 1388 # Number of branches executed system.cpu.iew.exec_stores 1577 # Number of stores executed -system.cpu.iew.exec_rate 0.432351 # Inst execution rate -system.cpu.iew.wb_sent 8605 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 8444 # cumulative count of insts written-back -system.cpu.iew.wb_producers 4397 # num instructions producing a value -system.cpu.iew.wb_consumers 7138 # num instructions consuming a value +system.cpu.iew.exec_rate 0.312314 # Inst execution rate +system.cpu.iew.wb_sent 8586 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 8425 # cumulative count of insts written-back +system.cpu.iew.wb_producers 4372 # num instructions producing a value +system.cpu.iew.wb_consumers 7073 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.414531 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.615999 # average fanout of values written-back +system.cpu.iew.wb_rate 0.299141 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.618125 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5240 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 5223 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards system.cpu.commit.branchMispredicts 292 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 10544 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.549317 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.355880 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::samples 10960 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.528467 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.329717 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 8175 77.53% 77.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 992 9.41% 86.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 623 5.91% 92.85% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 255 2.42% 95.27% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 176 1.67% 96.94% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 108 1.02% 97.96% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 67 0.64% 98.60% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 41 0.39% 98.99% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 107 1.01% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 8573 78.22% 78.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1014 9.25% 87.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 623 5.68% 93.16% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 252 2.30% 95.46% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 177 1.61% 97.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 110 1.00% 98.07% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 64 0.58% 98.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 42 0.38% 99.04% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 105 0.96% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 10544 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 10960 # Number of insts commited each cycle system.cpu.commit.committedInsts 5792 # Number of instructions committed system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -451,180 +452,180 @@ system.cpu.commit.branches 1037 # Nu system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. system.cpu.commit.int_insts 5698 # Number of committed integer instructions. system.cpu.commit.function_calls 103 # Number of function calls committed. -system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 105 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 21469 # The number of ROB reads -system.cpu.rob.rob_writes 22869 # The number of ROB writes -system.cpu.timesIdled 234 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 9022 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 21870 # The number of ROB reads +system.cpu.rob.rob_writes 22837 # The number of ROB writes +system.cpu.timesIdled 247 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 16398 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5792 # Number of Instructions Simulated system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5792 # Number of Instructions Simulated -system.cpu.cpi 3.516920 # CPI: Cycles Per Instruction -system.cpu.cpi_total 3.516920 # CPI: Total CPI of All Threads -system.cpu.ipc 0.284340 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.284340 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 13990 # number of integer regfile reads -system.cpu.int_regfile_writes 7309 # number of integer regfile writes +system.cpu.cpi 4.862569 # CPI: Cycles Per Instruction +system.cpu.cpi_total 4.862569 # CPI: Total CPI of All Threads +system.cpu.ipc 0.205653 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.205653 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 13961 # number of integer regfile reads +system.cpu.int_regfile_writes 7286 # number of integer regfile writes system.cpu.fp_regfile_reads 25 # number of floating regfile reads system.cpu.fp_regfile_writes 2 # number of floating regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 172.348292 # Cycle average of tags in use -system.cpu.icache.total_refs 1461 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 357 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 4.092437 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 171.601938 # Cycle average of tags in use +system.cpu.icache.total_refs 1437 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 356 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 4.036517 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 172.348292 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.084154 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.084154 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1461 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1461 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1461 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1461 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1461 # number of overall hits -system.cpu.icache.overall_hits::total 1461 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 426 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 426 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 426 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 426 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 426 # number of overall misses -system.cpu.icache.overall_misses::total 426 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13125000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13125000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13125000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13125000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13125000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13125000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1887 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1887 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1887 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1887 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1887 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.225755 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.225755 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.225755 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.225755 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.225755 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.225755 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 30809.859155 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 30809.859155 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 30809.859155 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 30809.859155 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 30809.859155 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 30809.859155 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 171.601938 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.083790 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.083790 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1437 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1437 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1437 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1437 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1437 # number of overall hits +system.cpu.icache.overall_hits::total 1437 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 440 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 440 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 440 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 440 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 440 # number of overall misses +system.cpu.icache.overall_misses::total 440 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 20404500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 20404500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 20404500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 20404500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 20404500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 20404500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1877 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1877 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1877 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1877 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1877 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1877 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.234417 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.234417 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.234417 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.234417 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.234417 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.234417 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 46373.863636 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 46373.863636 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 46373.863636 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 46373.863636 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 46373.863636 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 338 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 6 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 56.333333 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 69 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 69 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 69 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 69 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 69 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 357 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 357 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 357 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 357 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 357 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 357 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10853500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10853500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10853500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10853500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10853500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10853500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.189189 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.189189 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.189189 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.189189 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 30401.960784 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 30401.960784 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 30401.960784 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 30401.960784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 30401.960784 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 30401.960784 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 84 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 84 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 84 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 84 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 84 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 84 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 356 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 356 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 356 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 356 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 356 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 17051500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 17051500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17051500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 17051500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.189664 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.189664 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.189664 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.189664 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47897.471910 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47897.471910 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47897.471910 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 47897.471910 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 63.058180 # Cycle average of tags in use -system.cpu.dcache.total_refs 2201 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 63.108123 # Cycle average of tags in use +system.cpu.dcache.total_refs 2206 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 102 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 21.578431 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 21.627451 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 63.058180 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.015395 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.015395 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1483 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1483 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 718 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 718 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2201 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2201 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2201 # number of overall hits -system.cpu.dcache.overall_hits::total 2201 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 92 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 92 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 328 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 328 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 420 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 420 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 420 # number of overall misses -system.cpu.dcache.overall_misses::total 420 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3276500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3276500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9157000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9157000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12433500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12433500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12433500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12433500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1575 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1575 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.occ_blocks::cpu.data 63.108123 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.015407 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.015407 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1490 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1490 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 716 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 716 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 2206 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2206 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2206 # number of overall hits +system.cpu.dcache.overall_hits::total 2206 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 330 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 330 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 427 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 427 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 427 # number of overall misses +system.cpu.dcache.overall_misses::total 427 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 4870000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 4870000 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 14038497 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 14038497 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 18908497 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 18908497 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 18908497 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 18908497 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1587 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1587 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2621 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2621 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2621 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2621 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.058413 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.058413 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.313576 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.313576 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.160244 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.160244 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.160244 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.160244 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35614.130435 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 35614.130435 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 27917.682927 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 27917.682927 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 29603.571429 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 29603.571429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 29603.571429 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 29603.571429 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 2633 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2633 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2633 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2633 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.061122 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.061122 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.315488 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.315488 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.162172 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.162172 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.162172 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.162172 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 50206.185567 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 50206.185567 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42540.900000 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 42540.900000 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 44282.194379 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 44282.194379 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 44282.194379 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 416 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 83.200000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 37 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 37 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 281 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 281 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 318 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 318 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 318 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 318 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 283 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 283 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 325 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 325 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 325 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses @@ -633,103 +634,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 102 system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2135500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2135500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2069500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2069500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 4205000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 4205000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 4205000 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 4205000 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034921 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034921 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3072500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3072500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2817999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 2817999 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5890499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 5890499 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5890499 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 5890499 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.034657 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.034657 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038916 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.038916 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038916 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.038916 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 38827.272727 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 38827.272727 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44031.914894 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44031.914894 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 41225.490196 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 41225.490196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 41225.490196 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 41225.490196 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.038739 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.038739 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.038739 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.038739 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 55863.636364 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 55863.636364 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 59957.425532 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 59957.425532 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57749.990196 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57749.990196 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57749.990196 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57749.990196 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 202.511775 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.387362 # Cycle average of tags in use system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 407 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.012285 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 406 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.012315 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 171.159478 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.352298 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005223 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000957 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006180 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 170.963901 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 31.423461 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005217 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000959 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006176 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 5 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 5 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 5 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 5 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 5 # number of overall hits system.cpu.l2cache.overall_hits::total 5 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 352 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 351 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 55 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 407 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 406 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 352 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 351 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 102 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 454 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 352 # number of overall misses +system.cpu.l2cache.demand_misses::total 453 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 351 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 102 # number of overall misses -system.cpu.l2cache.overall_misses::total 454 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10491000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2079500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 12570500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2020500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2020500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10491000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 4100000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 14591000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10491000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 4100000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 14591000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 357 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 453 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16645000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3017000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19662000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2768500 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 2768500 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16645000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 5785500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22430500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16645000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 5785500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22430500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 356 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 412 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 411 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 357 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 356 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 459 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 357 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 458 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 356 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 459 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985994 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 458 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985955 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.987864 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.987835 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985994 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985955 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.989107 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985994 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.989083 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985955 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.989107 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 29803.977273 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 37809.090909 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 30885.749386 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 42989.361702 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 42989.361702 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 29803.977273 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40196.078431 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 32138.766520 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 29803.977273 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40196.078431 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 32138.766520 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.989083 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47421.652422 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54854.545455 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48428.571429 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 58904.255319 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 58904.255319 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47421.652422 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56720.588235 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49515.452539 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47421.652422 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56720.588235 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49515.452539 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -738,50 +739,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 352 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 351 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 407 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 406 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 352 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 351 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 454 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 352 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 453 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 351 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 454 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9262482 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1897546 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 11160028 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1863544 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1863544 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9262482 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3761090 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 13023572 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9262482 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3761090 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 13023572 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 453 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12250512 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2337054 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14587566 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2189544 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2189544 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12250512 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4526598 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16777110 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12250512 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4526598 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16777110 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987864 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.987835 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.989107 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985994 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.989083 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985955 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.989107 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 26313.869318 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 34500.836364 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 27420.216216 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39649.872340 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39649.872340 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 26313.869318 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 36873.431373 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 28686.281938 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.989083 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34901.743590 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42491.890909 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 35929.965517 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 46586.042553 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 46586.042553 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34901.743590 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44378.411765 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37035.562914 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt index 8df237734..0f666ffe1 100644 --- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17991500 # Number of ticks simulated -final_tick 17991500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000016 # Number of seconds simulated +sim_ticks 16282500 # Number of ticks simulated +final_tick 16282500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 44971 # Simulator instruction rate (inst/s) -host_op_rate 44961 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 151823718 # Simulator tick rate (ticks/s) -host_mem_usage 222708 # Number of bytes of host memory used +host_inst_rate 46082 # Simulator instruction rate (inst/s) +host_op_rate 46072 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 140796560 # Simulator tick rate (ticks/s) +host_mem_usage 222960 # Number of bytes of host memory used host_seconds 0.12 # Real time elapsed on the host sim_insts 5327 # Number of instructions simulated sim_ops 5327 # Number of ops (including micro ops) simulated @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 18496 # Nu system.physmem.num_reads::cpu.inst 289 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 134 # Number of read requests responded to by this memory system.physmem.num_reads::total 423 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1028041019 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 476669538 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1504710558 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1028041019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1028041019 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1028041019 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 476669538 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1504710558 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1135943498 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 526700445 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1662643943 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1135943498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1135943498 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1135943498 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 526700445 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1662643943 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 423 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 423 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 17940000 # Total gap between requests +system.physmem.totGap 16231000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 281 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 113 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 25 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 3 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 254 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 36 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,48 +164,48 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1964422 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11356422 # Sum of mem lat for all requests +system.physmem.totQLat 2301921 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11301921 # Sum of mem lat for all requests system.physmem.totBusLat 1692000 # Total cycles spent in databus access -system.physmem.totBankLat 7700000 # Total cycles spent in bank access -system.physmem.avgQLat 4644.02 # Average queueing delay per request -system.physmem.avgBankLat 18203.31 # Average bank access latency per request +system.physmem.totBankLat 7308000 # Total cycles spent in bank access +system.physmem.avgQLat 5441.89 # Average queueing delay per request +system.physmem.avgBankLat 17276.60 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 26847.33 # Average memory access latency -system.physmem.avgRdBW 1504.71 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26718.49 # Average memory access latency +system.physmem.avgRdBW 1662.64 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1504.71 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1662.64 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.40 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.63 # Average read queue length over time +system.physmem.busUtil 10.39 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.69 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 336 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 79.43 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 42411.35 # Average gap between requests +system.physmem.avgGap 38371.16 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 35984 # number of cpu cycles simulated +system.cpu.numCycles 32566 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 1634 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 1036 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 1630 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 1034 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 901 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 1169 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 438 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 1165 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 436 # Number of BTB hits system.cpu.branch_predictor.usedRAS 67 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 4 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 37.467921 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 505 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 1129 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 5626 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 37.424893 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 503 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 1127 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 5631 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 3988 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 9614 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 9619 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 1682 # Number of Registers Read Through Forwarding Logic +system.cpu.regfile_manager.regForwards 1675 # Number of Registers Read Through Forwarding Logic system.cpu.agen_unit.agens 1483 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 334 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 504 # Number of Branches Incorrectly Predicted As Not Taken). @@ -216,12 +216,12 @@ system.cpu.execution_unit.executions 3966 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 9941 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 9640 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 470 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 29760 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 6224 # Number of cycles cpu stages are processed. -system.cpu.activity 17.296576 # Percentage of cycles cpu is active +system.cpu.timesIdled 478 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 26364 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 6202 # Number of cycles cpu stages are processed. +system.cpu.activity 19.044402 # Percentage of cycles cpu is active system.cpu.comLoads 715 # Number of Load instructions committed system.cpu.comStores 673 # Number of Store instructions committed system.cpu.comBranches 1115 # Number of Branches instructions committed @@ -233,144 +233,144 @@ system.cpu.committedInsts 5327 # Nu system.cpu.committedOps 5327 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 5327 # Number of Instructions committed (Total) -system.cpu.cpi 6.755022 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 6.113385 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 6.755022 # CPI: Total CPI of All Threads -system.cpu.ipc 0.148038 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 6.113385 # CPI: Total CPI of All Threads +system.cpu.ipc 0.163576 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.148038 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 31416 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 4568 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 12.694531 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 32782 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 3202 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 8.898399 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 32940 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 3044 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 8.459315 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 35002 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 982 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 2.728991 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 32815 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 3169 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 8.806692 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.163576 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 28007 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 4559 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 13.999263 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 29377 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 3189 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 9.792422 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 29532 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 3034 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 9.316465 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 31591 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 975 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 2.993920 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 29408 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 3158 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 9.697230 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 138.057869 # Cycle average of tags in use -system.cpu.icache.total_refs 829 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 143.411463 # Cycle average of tags in use +system.cpu.icache.total_refs 814 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 291 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 2.848797 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 2.797251 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 138.057869 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.067411 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.067411 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 829 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 829 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 829 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 829 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 829 # number of overall hits -system.cpu.icache.overall_hits::total 829 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 348 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 348 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 348 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 348 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 348 # number of overall misses -system.cpu.icache.overall_misses::total 348 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18017500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18017500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18017500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18017500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18017500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18017500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1177 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1177 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1177 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1177 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1177 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1177 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.295667 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.295667 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.295667 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.295667 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.295667 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.295667 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 51774.425287 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 51774.425287 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 51774.425287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 51774.425287 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 51774.425287 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 143.411463 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.070025 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.070025 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 814 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 814 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 814 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 814 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 814 # number of overall hits +system.cpu.icache.overall_hits::total 814 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses +system.cpu.icache.overall_misses::total 364 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18418500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18418500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18418500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18418500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18418500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18418500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1178 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1178 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1178 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1178 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1178 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1178 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.308998 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.308998 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.308998 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.308998 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.308998 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.308998 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50600.274725 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 50600.274725 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 50600.274725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 50600.274725 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 50600.274725 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 148 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 3 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 49.333333 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 57 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 57 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 57 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 57 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 57 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 73 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 73 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 73 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 73 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 73 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 73 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 291 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 291 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 291 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 291 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 291 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 291 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15219500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 15219500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15219500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 15219500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15219500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 15219500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247239 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.247239 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247239 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.247239 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52300.687285 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52300.687285 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52300.687285 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52300.687285 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15194000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15194000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15194000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15194000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15194000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15194000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.247029 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.247029 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.247029 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52213.058419 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52213.058419 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52213.058419 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 52213.058419 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 83.298060 # Cycle average of tags in use -system.cpu.dcache.total_refs 1045 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 85.214129 # Cycle average of tags in use +system.cpu.dcache.total_refs 914 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 135 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 7.740741 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 6.770370 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 83.298060 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020336 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020336 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 85.214129 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020804 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020804 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 654 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 654 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 391 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 391 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1045 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1045 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1045 # number of overall hits -system.cpu.dcache.overall_hits::total 1045 # number of overall hits +system.cpu.dcache.WriteReq_hits::cpu.data 260 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 260 # number of WriteReq hits +system.cpu.dcache.demand_hits::cpu.data 914 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 914 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 914 # number of overall hits +system.cpu.dcache.overall_hits::total 914 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 61 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 61 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 282 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 282 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 343 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 343 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 343 # number of overall misses -system.cpu.dcache.overall_misses::total 343 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3323500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3323500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 13337500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 13337500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 16661000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 16661000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 16661000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 16661000 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 413 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 413 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 474 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 474 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 474 # number of overall misses +system.cpu.dcache.overall_misses::total 474 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3347500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3347500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19185000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19185000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22532500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22532500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22532500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22532500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 715 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 673 # number of WriteReq accesses(hits+misses) @@ -381,36 +381,36 @@ system.cpu.dcache.overall_accesses::cpu.data 1388 system.cpu.dcache.overall_accesses::total 1388 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085315 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.085315 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.419019 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.419019 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.247118 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.247118 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.247118 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.247118 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54483.606557 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 54483.606557 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47296.099291 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47296.099291 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48574.344023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48574.344023 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48574.344023 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3752 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 83.377778 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.613670 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.341499 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.341499 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.341499 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.341499 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 54877.049180 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 54877.049180 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46452.784504 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46452.784504 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47536.919831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47536.919831 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47536.919831 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 405 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 32 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 12.656250 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 7 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 7 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 201 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 201 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 208 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 208 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 208 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 208 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 332 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 332 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 339 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 339 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 339 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 54 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 81 # number of WriteReq MSHR misses @@ -419,14 +419,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 135 system.cpu.dcache.demand_mshr_misses::total 135 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 135 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 135 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2915000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3959500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3959500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6874500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6874500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6874500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6874500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2939000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2939000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4153500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4153500 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7092500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7092500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7092500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7092500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.075524 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.120357 # mshr miss rate for WriteReq accesses @@ -435,26 +435,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.097262 system.cpu.dcache.demand_mshr_miss_rate::total 0.097262 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.097262 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.097262 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53981.481481 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53981.481481 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 48882.716049 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 48882.716049 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 50922.222222 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 50922.222222 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54425.925926 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54425.925926 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 51277.777778 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 51277.777778 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52537.037037 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 52537.037037 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 163.809669 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 169.991473 # Cycle average of tags in use system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 342 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.008772 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 137.551022 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 26.258647 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004198 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000801 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.004999 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 142.874602 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 27.116871 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004360 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000828 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005188 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits @@ -475,17 +475,17 @@ system.cpu.l2cache.demand_misses::total 423 # nu system.cpu.l2cache.overall_misses::cpu.inst 289 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 134 # number of overall misses system.cpu.l2cache.overall_misses::total 423 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14901000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2848500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17749500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3876000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3876000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14901000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6724500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21625500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14901000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6724500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21625500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14875500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2872500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17748000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4070000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4070000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14875500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 6942500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21818000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14875500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 6942500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21818000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 291 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 54 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 345 # number of ReadReq accesses(hits+misses) @@ -508,17 +508,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.992958 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993127 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.992593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.992958 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51560.553633 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53745.283019 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51899.122807 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 47851.851852 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 47851.851852 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 51124.113475 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51560.553633 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50182.835821 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 51124.113475 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51472.318339 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 54198.113208 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 51894.736842 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 50246.913580 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 50246.913580 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 51579.196217 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51472.318339 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 51809.701493 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 51579.196217 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -538,17 +538,17 @@ system.cpu.l2cache.demand_mshr_misses::total 423 system.cpu.l2cache.overall_mshr_misses::cpu.inst 289 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 134 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 423 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11259441 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2182574 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13442015 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2846130 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2846130 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11259441 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5028704 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16288145 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11259441 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5028704 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16288145 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11235436 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2207572 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 13443008 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3066568 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3066568 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11235436 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5274140 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16509576 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11235436 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5274140 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16509576 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981481 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.991304 # mshr miss rate for ReadReq accesses @@ -560,17 +560,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.992958 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993127 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.992593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.992958 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38960.003460 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41180.641509 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39304.137427 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 35137.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 35137.407407 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38960.003460 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37527.641791 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38506.252955 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 38876.941176 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41652.301887 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39307.040936 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37858.864198 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37858.864198 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 38876.941176 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 39359.253731 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39029.730496 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt index 91efbc873..272509d41 100644 --- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000012 # Number of seconds simulated -sim_ticks 12009000 # Number of ticks simulated -final_tick 12009000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000015 # Number of seconds simulated +sim_ticks 15249000 # Number of ticks simulated +final_tick 15249000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 10920 # Simulator instruction rate (inst/s) -host_op_rate 19780 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 24373770 # Simulator tick rate (ticks/s) -host_mem_usage 225464 # Number of bytes of host memory used -host_seconds 0.49 # Real time elapsed on the host +host_inst_rate 41998 # Simulator instruction rate (inst/s) +host_op_rate 76065 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 119014725 # Simulator tick rate (ticks/s) +host_mem_usage 225728 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host sim_insts 5380 # Number of instructions simulated sim_ops 9745 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 145 # Number of read requests responded to by this memory system.physmem.num_reads::total 450 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1625447581 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 772753768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 2398201349 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1625447581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1625447581 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1625447581 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 772753768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 2398201349 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 1280083940 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 608564496 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1888648436 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1280083940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1280083940 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1280083940 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 608564496 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1888648436 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 451 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 451 # Reqs generatd by CPU via cache - shady @@ -46,9 +46,9 @@ system.physmem.perBankRdReqs::6 16 # Tr system.physmem.perBankRdReqs::7 14 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 22 # Track reads on a per bank basis system.physmem.perBankRdReqs::9 35 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 31 # Track reads on a per bank basis system.physmem.perBankRdReqs::11 40 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 13 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 12 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 17 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 34 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 17 # Track reads on a per bank basis @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 11990500 # Total gap between requests +system.physmem.totGap 15226500 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 221 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 57 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 18 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 230 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 155 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 56 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,264 +164,265 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3096951 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13440951 # Sum of mem lat for all requests +system.physmem.totQLat 1663951 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 11993951 # Sum of mem lat for all requests system.physmem.totBusLat 1804000 # Total cycles spent in databus access -system.physmem.totBankLat 8540000 # Total cycles spent in bank access -system.physmem.avgQLat 6866.85 # Average queueing delay per request -system.physmem.avgBankLat 18935.70 # Average bank access latency per request +system.physmem.totBankLat 8526000 # Total cycles spent in bank access +system.physmem.avgQLat 3689.47 # Average queueing delay per request +system.physmem.avgBankLat 18904.66 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 29802.55 # Average memory access latency -system.physmem.avgRdBW 2398.20 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 26594.13 # Average memory access latency +system.physmem.avgRdBW 1888.65 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 2398.20 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1888.65 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 14.99 # Data bus utilization in percentage -system.physmem.avgRdQLen 1.12 # Average read queue length over time +system.physmem.busUtil 11.80 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.79 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 353 # Number of row buffer hits during reads +system.physmem.readRowHits 354 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 78.27 # Row buffer hit rate for reads +system.physmem.readRowHitRate 78.49 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 26586.47 # Average gap between requests +system.physmem.avgGap 33761.64 # Average gap between requests system.cpu.workload.num_syscalls 11 # Number of system calls -system.cpu.numCycles 24019 # number of cpu cycles simulated +system.cpu.numCycles 30499 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 3185 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3185 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 589 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 2591 # Number of BTB lookups +system.cpu.BPredUnit.lookups 3124 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3124 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 575 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 2554 # Number of BTB lookups system.cpu.BPredUnit.BTBHits 779 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. system.cpu.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 8560 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 15317 # Number of instructions fetch has processed -system.cpu.fetch.Branches 3185 # Number of branches that fetch encountered +system.cpu.fetch.icacheStallCycles 9097 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 15002 # Number of instructions fetch has processed +system.cpu.fetch.Branches 3124 # Number of branches that fetch encountered system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4169 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 2596 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 2320 # Number of cycles fetch has spent blocked -system.cpu.fetch.MiscStallCycles 24 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 142 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 1999 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 297 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 17196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.587346 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 3.039622 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.Cycles 4073 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2573 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 3671 # Number of cycles fetch has spent blocked +system.cpu.fetch.MiscStallCycles 39 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 217 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 15 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 1972 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 311 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 19065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.398846 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.899430 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 13133 76.37% 76.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 180 1.05% 77.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 163 0.95% 78.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 205 1.19% 79.56% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 179 1.04% 80.60% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 184 1.07% 81.67% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 242 1.41% 83.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 193 1.12% 84.20% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2717 15.80% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 15096 79.18% 79.18% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 179 0.94% 80.12% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 149 0.78% 80.90% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 207 1.09% 81.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 179 0.94% 82.93% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 177 0.93% 83.86% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 231 1.21% 85.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 192 1.01% 86.07% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 2655 13.93% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 17196 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.132603 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.637703 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 9044 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 2277 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 3768 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1981 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 26083 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1981 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 9405 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1279 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 293 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 3524 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 714 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 24459 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 19 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 613 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 26793 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 58583 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 58567 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 19065 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.102430 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.491885 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 9663 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3644 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 3665 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1953 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 25430 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1953 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 10013 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 2382 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 508 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 3439 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 770 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 23869 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 12 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 27 # Number of times rename has blocked due to IQ full +system.cpu.rename.LSQFullEvents 648 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 26126 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 57405 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 57389 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 16 # Number of floating rename lookups system.cpu.rename.CommittedMaps 11060 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 15733 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 29 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 29 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2012 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2439 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1809 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 10 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 4 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 21719 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 34 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 18260 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 229 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11155 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 15144 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 21 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 17196 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 1.061875 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.899452 # Number of insts issued each cycle +system.cpu.rename.UndoneMaps 15066 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 31 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 31 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 2094 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2405 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1772 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 13 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 3 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 21302 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 37 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 17998 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 209 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 10762 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 14777 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 24 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 19065 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.944034 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.806602 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11700 68.04% 68.04% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1330 7.73% 75.77% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1020 5.93% 81.71% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 704 4.09% 85.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 773 4.50% 90.29% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 702 4.08% 94.38% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 638 3.71% 98.09% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 284 1.65% 99.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 45 0.26% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 13533 70.98% 70.98% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1394 7.31% 78.30% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1058 5.55% 83.84% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 719 3.77% 87.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 757 3.97% 91.59% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 676 3.55% 95.13% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 613 3.22% 98.35% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 275 1.44% 99.79% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 40 0.21% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 17196 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 19065 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 154 78.97% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 78.97% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 22 11.28% 90.26% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 19 9.74% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 132 74.58% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 74.58% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 23 12.99% 87.57% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 22 12.43% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available -system.cpu.iq.FU_type_0::No_OpClass 5 0.03% 0.03% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 14636 80.15% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.18% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2090 11.45% 91.63% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1529 8.37% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::No_OpClass 4 0.02% 0.02% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 14399 80.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 80.03% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2084 11.58% 91.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1511 8.40% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 18260 # Type of FU issued -system.cpu.iq.rate 0.760231 # Inst issue rate -system.cpu.iq.fu_busy_cnt 195 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.010679 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 54132 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32913 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 16722 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 17998 # Type of FU issued +system.cpu.iq.rate 0.590118 # Inst issue rate +system.cpu.iq.fu_busy_cnt 177 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.009834 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 55439 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32107 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 16514 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 8 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 4 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 18446 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 18167 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 4 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 141 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 180 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1387 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 23 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 875 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedLoads 1353 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 24 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu.iew.lsq.thread0.squashedStores 838 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 15 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1981 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 687 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 29 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 21753 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 45 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2439 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1809 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 30 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1953 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 1731 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 30 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 21339 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 34 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2405 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1772 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 33 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 71 # Number of branches that were predicted taken incorrectly +system.cpu.iew.memOrderViolationEvents 11 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 65 # Number of branches that were predicted taken incorrectly system.cpu.iew.predictedNotTakenIncorrect 652 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 723 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 17199 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1930 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1061 # Number of squashed instructions skipped in execute +system.cpu.iew.branchMispredicts 717 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 17023 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1944 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 975 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 0 # number of nop insts executed -system.cpu.iew.exec_refs 3340 # number of memory reference insts executed -system.cpu.iew.exec_branches 1687 # Number of branches executed -system.cpu.iew.exec_stores 1410 # Number of stores executed -system.cpu.iew.exec_rate 0.716058 # Inst execution rate -system.cpu.iew.wb_sent 16930 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 16726 # cumulative count of insts written-back -system.cpu.iew.wb_producers 10734 # num instructions producing a value -system.cpu.iew.wb_consumers 16630 # num instructions consuming a value +system.cpu.iew.exec_refs 3334 # number of memory reference insts executed +system.cpu.iew.exec_branches 1674 # Number of branches executed +system.cpu.iew.exec_stores 1390 # Number of stores executed +system.cpu.iew.exec_rate 0.558149 # Inst execution rate +system.cpu.iew.wb_sent 16747 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 16518 # cumulative count of insts written-back +system.cpu.iew.wb_producers 10593 # num instructions producing a value +system.cpu.iew.wb_consumers 16382 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.696365 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.645460 # average fanout of values written-back +system.cpu.iew.wb_rate 0.541592 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.646624 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12007 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 11593 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 13 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 606 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 15215 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.640486 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.512697 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 604 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 17112 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.569483 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.430880 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 11677 76.75% 76.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1319 8.67% 85.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 603 3.96% 89.38% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 704 4.63% 94.01% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 365 2.40% 96.40% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 135 0.89% 97.29% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 125 0.82% 98.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 73 0.48% 98.59% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 214 1.41% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 13541 79.13% 79.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1338 7.82% 86.95% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 619 3.62% 90.57% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 703 4.11% 94.68% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 373 2.18% 96.86% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 140 0.82% 97.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 121 0.71% 98.38% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 74 0.43% 98.81% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 203 1.19% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 15215 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 17112 # Number of insts commited each cycle system.cpu.commit.committedInsts 5380 # Number of instructions committed system.cpu.commit.committedOps 9745 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -432,124 +433,124 @@ system.cpu.commit.branches 1208 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 9650 # Number of committed integer instructions. system.cpu.commit.function_calls 0 # Number of function calls committed. -system.cpu.commit.bw_lim_events 214 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 203 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 36753 # The number of ROB reads -system.cpu.rob.rob_writes 45519 # The number of ROB writes -system.cpu.timesIdled 141 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 6823 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 38247 # The number of ROB reads +system.cpu.rob.rob_writes 44659 # The number of ROB writes +system.cpu.timesIdled 152 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 11434 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 5380 # Number of Instructions Simulated system.cpu.committedOps 9745 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 5380 # Number of Instructions Simulated -system.cpu.cpi 4.464498 # CPI: Cycles Per Instruction -system.cpu.cpi_total 4.464498 # CPI: Total CPI of All Threads -system.cpu.ipc 0.223989 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.223989 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 30259 # number of integer regfile reads -system.cpu.int_regfile_writes 18088 # number of integer regfile writes +system.cpu.cpi 5.668959 # CPI: Cycles Per Instruction +system.cpu.cpi_total 5.668959 # CPI: Total CPI of All Threads +system.cpu.ipc 0.176399 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.176399 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 29908 # number of integer regfile reads +system.cpu.int_regfile_writes 17845 # number of integer regfile writes system.cpu.fp_regfile_reads 4 # number of floating regfile reads -system.cpu.misc_regfile_reads 7500 # number of misc regfile reads +system.cpu.misc_regfile_reads 7467 # number of misc regfile reads system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 149.891095 # Cycle average of tags in use -system.cpu.icache.total_refs 1605 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 305 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 5.262295 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 145.993781 # Cycle average of tags in use +system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 306 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 5.117647 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 149.891095 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.073189 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.073189 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 1605 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1605 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1605 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1605 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1605 # number of overall hits -system.cpu.icache.overall_hits::total 1605 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses -system.cpu.icache.overall_misses::total 394 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 13338000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 13338000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 13338000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 13338000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 13338000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 13338000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 1999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 1999 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 1999 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 1999 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 1999 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.197099 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.197099 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.197099 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.197099 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.197099 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.197099 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 33852.791878 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 33852.791878 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 33852.791878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 33852.791878 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 33852.791878 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 145.993781 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.071286 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.071286 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits +system.cpu.icache.overall_hits::total 1566 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 406 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 406 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 406 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 406 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 406 # number of overall misses +system.cpu.icache.overall_misses::total 406 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 19356000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 19356000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 19356000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 19356000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 19356000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 19356000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 1972 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 1972 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 1972 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 1972 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 1972 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 1972 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.205882 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.205882 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.205882 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.205882 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.205882 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.205882 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47674.876847 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 47674.876847 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 47674.876847 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 47674.876847 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 47674.876847 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 47674.876847 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 302 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 7 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 43.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 100 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 100 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 100 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 100 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 100 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 100 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 306 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 306 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 306 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 306 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 306 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 306 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10626000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 10626000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10626000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 10626000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10626000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 10626000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.153077 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.153077 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.153077 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.153077 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34725.490196 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 34725.490196 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34725.490196 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 34725.490196 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15469000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 15469000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15469000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 15469000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15469000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 15469000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.155172 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.155172 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.155172 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.155172 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50552.287582 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50552.287582 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50552.287582 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 50552.287582 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50552.287582 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 50552.287582 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 84.879845 # Cycle average of tags in use -system.cpu.dcache.total_refs 2447 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 16.875862 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 83.489938 # Cycle average of tags in use +system.cpu.dcache.total_refs 2406 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 16.825175 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 84.879845 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.020723 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.020723 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 1589 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1589 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 83.489938 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.020383 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.020383 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 1548 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1548 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 858 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 858 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 2447 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2447 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2447 # number of overall hits -system.cpu.dcache.overall_hits::total 2447 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 2406 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2406 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2406 # number of overall hits +system.cpu.dcache.overall_hits::total 2406 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 132 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 132 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 76 # number of WriteReq misses @@ -558,43 +559,43 @@ system.cpu.dcache.demand_misses::cpu.data 208 # n system.cpu.dcache.demand_misses::total 208 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 208 # number of overall misses system.cpu.dcache.overall_misses::total 208 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5132000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5132000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 3133000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 3133000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 8265000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 8265000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 8265000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 8265000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6548500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6548500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 4231000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 4231000 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 10779500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 10779500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 10779500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 10779500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1680 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1680 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 934 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 934 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2655 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2655 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2655 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2655 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076700 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076700 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2614 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2614 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2614 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2614 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.078571 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.078571 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.081370 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.081370 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.078343 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.078343 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.078343 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.078343 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38878.787879 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 38878.787879 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41223.684211 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 41223.684211 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 39735.576923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 39735.576923 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 39735.576923 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.079572 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.079572 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.079572 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.079572 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 49609.848485 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 49609.848485 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55671.052632 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 55671.052632 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 51824.519231 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 51824.519231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 51824.519231 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 51824.519231 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 108 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 21.600000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed @@ -612,42 +613,42 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3278500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3278500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2981000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 2981000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6259500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6259500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6259500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6259500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040674 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040674 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3696500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3696500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4079000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4079000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7775500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7775500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7775500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7775500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.041667 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.041667 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.081370 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.081370 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.054991 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.054991 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.054991 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46835.714286 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46835.714286 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 39223.684211 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 39223.684211 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42873.287671 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 42873.287671 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055853 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055853 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055853 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055853 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 52807.142857 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 52807.142857 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53671.052632 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53671.052632 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53256.849315 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53256.849315 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53256.849315 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53256.849315 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 182.959089 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 179.176449 # Cycle average of tags in use system.cpu.l2cache.total_refs 1 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 373 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002681 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 374 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002674 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 149.880234 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 33.078855 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.004574 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001009 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.005583 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 146.139957 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 33.036492 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.004460 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001008 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.005468 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits @@ -665,17 +666,17 @@ system.cpu.l2cache.demand_misses::total 451 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses system.cpu.l2cache.overall_misses::total 451 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10319000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3209500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13528500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2905000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 2905000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10319000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6114500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16433500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10319000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6114500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16433500 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15152000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3773500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 18925500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4003000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4003000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 15152000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7776500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 22928500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 15152000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7776500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 22928500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 306 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 70 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 376 # number of ReadReq accesses(hits+misses) @@ -698,17 +699,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.997788 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996732 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.997788 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 33832.786885 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 45850 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 36076 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 38223.684211 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 38223.684211 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 36437.915743 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 33832.786885 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41880.136986 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 36437.915743 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49678.688525 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53907.142857 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 50468 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52671.052632 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52671.052632 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49678.688525 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 53263.698630 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50839.246120 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49678.688525 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 53263.698630 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50839.246120 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -728,17 +729,17 @@ system.cpu.l2cache.demand_mshr_misses::total 451 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 451 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9239430 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2977566 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12216996 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2628106 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2628106 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9239430 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5605672 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 14845102 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9239430 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5605672 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 14845102 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11317954 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2918074 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14236028 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3040610 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3040610 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11317954 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5958684 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 17276638 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11317954 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5958684 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 17276638 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997340 # mshr miss rate for ReadReq accesses @@ -750,17 +751,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.997788 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996732 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.997788 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 30293.213115 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 42536.657143 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 32578.656000 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34580.342105 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34580.342105 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 30293.213115 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38395.013699 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 32915.968958 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 37108.045902 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41686.771429 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37962.741333 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40008.026316 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40008.026316 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 37108.045902 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40812.904110 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38307.401330 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt index 9ebeed2de..6142b96e8 100644 --- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt +++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 16578000 # Number of ticks simulated -final_tick 16578000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000020 # Number of seconds simulated +sim_ticks 20334000 # Number of ticks simulated +final_tick 20334000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 76899 # Simulator instruction rate (inst/s) -host_op_rate 76894 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 100012302 # Simulator tick rate (ticks/s) -host_mem_usage 217664 # Number of bytes of host memory used -host_seconds 0.17 # Real time elapsed on the host +host_inst_rate 80964 # Simulator instruction rate (inst/s) +host_op_rate 80958 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 129154883 # Simulator tick rate (ticks/s) +host_mem_usage 217900 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host sim_insts 12745 # Number of instructions simulated sim_ops 12745 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 40000 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 22400 # Number of bytes read from this memory -system.physmem.bytes_read::total 62400 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 40000 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 40000 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 625 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 350 # Number of read requests responded to by this memory -system.physmem.num_reads::total 975 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 2412836289 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1351188322 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 3764024611 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 2412836289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 2412836289 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 2412836289 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1351188322 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 3764024611 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 975 # Total number of read requests seen +system.physmem.bytes_read::cpu.inst 39872 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 22784 # Number of bytes read from this memory +system.physmem.bytes_read::total 62656 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 39872 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 39872 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 623 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 356 # Number of read requests responded to by this memory +system.physmem.num_reads::total 979 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1960853743 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1120487853 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 3081341595 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1960853743 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1960853743 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1960853743 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1120487853 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 3081341595 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 979 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 975 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 62400 # Total number of bytes read from memory +system.physmem.cpureqs 979 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 62656 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 62400 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 62656 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -40,15 +40,15 @@ system.physmem.perBankRdReqs::0 73 # Tr system.physmem.perBankRdReqs::1 52 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 71 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 123 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 80 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 81 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 26 # Track reads on a per bank basis -system.physmem.perBankRdReqs::6 17 # Track reads on a per bank basis -system.physmem.perBankRdReqs::7 75 # Track reads on a per bank basis +system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis +system.physmem.perBankRdReqs::7 76 # Track reads on a per bank basis system.physmem.perBankRdReqs::8 74 # Track reads on a per bank basis -system.physmem.perBankRdReqs::9 28 # Track reads on a per bank basis -system.physmem.perBankRdReqs::10 71 # Track reads on a per bank basis -system.physmem.perBankRdReqs::11 98 # Track reads on a per bank basis -system.physmem.perBankRdReqs::12 74 # Track reads on a per bank basis +system.physmem.perBankRdReqs::9 27 # Track reads on a per bank basis +system.physmem.perBankRdReqs::10 72 # Track reads on a per bank basis +system.physmem.perBankRdReqs::11 99 # Track reads on a per bank basis +system.physmem.perBankRdReqs::12 76 # Track reads on a per bank basis system.physmem.perBankRdReqs::13 27 # Track reads on a per bank basis system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis system.physmem.perBankRdReqs::15 75 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 16446000 # Total gap between requests +system.physmem.totGap 20181000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 975 # Categorize read packet sizes +system.physmem.readPktSize::6 979 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,16 +98,16 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 159 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 326 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 237 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 124 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 63 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::5 32 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 16 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::7 8 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::8 6 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::9 4 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 247 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 340 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 206 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 122 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 49 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::5 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see @@ -164,47 +164,47 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 16512475 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 38892475 # Sum of mem lat for all requests -system.physmem.totBusLat 3900000 # Total cycles spent in databus access -system.physmem.totBankLat 18480000 # Total cycles spent in bank access -system.physmem.avgQLat 16935.87 # Average queueing delay per request -system.physmem.avgBankLat 18953.85 # Average bank access latency per request +system.physmem.totQLat 11431477 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 34163477 # Sum of mem lat for all requests +system.physmem.totBusLat 3916000 # Total cycles spent in databus access +system.physmem.totBankLat 18816000 # Total cycles spent in bank access +system.physmem.avgQLat 11676.69 # Average queueing delay per request +system.physmem.avgBankLat 19219.61 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 39889.72 # Average memory access latency -system.physmem.avgRdBW 3764.02 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 34896.30 # Average memory access latency +system.physmem.avgRdBW 3081.34 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 3764.02 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 3081.34 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 23.53 # Data bus utilization in percentage -system.physmem.avgRdQLen 2.35 # Average read queue length over time +system.physmem.busUtil 19.26 # Data bus utilization in percentage +system.physmem.avgRdQLen 1.68 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 738 # Number of row buffer hits during reads +system.physmem.readRowHits 740 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads +system.physmem.readRowHitRate 75.59 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 16867.69 # Average gap between requests +system.physmem.avgGap 20613.89 # Average gap between requests system.cpu.dtb.fetch_hits 0 # ITB hits system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 4074 # DTB read hits -system.cpu.dtb.read_misses 101 # DTB read misses +system.cpu.dtb.read_hits 4607 # DTB read hits +system.cpu.dtb.read_misses 109 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 4175 # DTB read accesses -system.cpu.dtb.write_hits 2120 # DTB write hits -system.cpu.dtb.write_misses 61 # DTB write misses +system.cpu.dtb.read_accesses 4716 # DTB read accesses +system.cpu.dtb.write_hits 2105 # DTB write hits +system.cpu.dtb.write_misses 77 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations -system.cpu.dtb.write_accesses 2181 # DTB write accesses -system.cpu.dtb.data_hits 6194 # DTB hits -system.cpu.dtb.data_misses 162 # DTB misses +system.cpu.dtb.write_accesses 2182 # DTB write accesses +system.cpu.dtb.data_hits 6712 # DTB hits +system.cpu.dtb.data_misses 186 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 6356 # DTB accesses -system.cpu.itb.fetch_hits 5134 # ITB hits -system.cpu.itb.fetch_misses 54 # ITB misses +system.cpu.dtb.data_accesses 6898 # DTB accesses +system.cpu.itb.fetch_hits 5687 # ITB hits +system.cpu.itb.fetch_misses 59 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 5188 # ITB accesses +system.cpu.itb.fetch_accesses 5746 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -219,359 +219,358 @@ system.cpu.itb.data_acv 0 # DT system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload0.num_syscalls 17 # Number of system calls system.cpu.workload1.num_syscalls 17 # Number of system calls -system.cpu.numCycles 33157 # number of cpu cycles simulated +system.cpu.numCycles 40669 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6335 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 3524 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1643 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 4675 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 824 # Number of BTB hits +system.cpu.BPredUnit.lookups 6981 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 3954 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1690 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5146 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 870 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 962 # Number of times the RAS was used to get a target. -system.cpu.BPredUnit.RASInCorrect 181 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 1485 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 35462 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6335 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1786 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 5973 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1719 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 45 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.CacheLines 5134 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 754 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 24653 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.438446 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.812361 # Number of instructions fetched each cycle (Total) +system.cpu.BPredUnit.usedRAS 937 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.RASInCorrect 198 # Number of incorrect RAS predictions. +system.cpu.fetch.icacheStallCycles 1717 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 38666 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6981 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1807 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 6508 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 2004 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 376 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.CacheLines 5687 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 915 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 27168 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.423218 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.808405 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 18680 75.77% 75.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 457 1.85% 77.63% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 358 1.45% 79.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 502 2.04% 81.11% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 454 1.84% 82.96% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 361 1.46% 84.42% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 481 1.95% 86.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 604 2.45% 88.82% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 2756 11.18% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 20660 76.05% 76.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 537 1.98% 78.02% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 399 1.47% 79.49% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 504 1.86% 81.35% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 464 1.71% 83.05% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 436 1.60% 84.66% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 485 1.79% 86.44% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 591 2.18% 88.62% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 3092 11.38% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 24653 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.191061 # Number of branch fetches per cycle -system.cpu.fetch.rate 1.069518 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 34329 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 6707 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5019 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 579 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 2403 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 637 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 388 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 30928 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 701 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 2403 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 34978 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 3976 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 854 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4893 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1933 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 28789 # Number of instructions processed by rename -system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 1945 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 21557 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 36008 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 35974 # Number of integer rename lookups +system.cpu.fetch.rateDist::total 27168 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.171654 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.950749 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 38149 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 6961 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5575 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 517 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 2929 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 646 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 395 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 33907 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 727 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 2929 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 38897 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 3834 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 984 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 5237 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 2250 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 31157 # Number of instructions processed by rename +system.cpu.rename.ROBFullEvents 57 # Number of times rename has blocked due to ROB full +system.cpu.rename.LSQFullEvents 2290 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 23416 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 38564 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 38530 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 34 # Number of floating rename lookups system.cpu.rename.CommittedMaps 9140 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 12417 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 55 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 43 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 5160 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2607 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1348 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.UndoneMaps 14276 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 53 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 41 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 6217 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3020 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1445 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 5 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.memDep1.insertedLoads 2616 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep1.insertedStores 1346 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep1.conflictingLoads 14 # Number of conflicting loads. +system.cpu.memDep1.insertedLoads 2972 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep1.insertedStores 1380 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep1.conflictingLoads 10 # Number of conflicting loads. system.cpu.memDep1.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 25414 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 51 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21500 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 112 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 11650 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6459 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 17 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 24653 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.872105 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.460410 # Number of insts issued each cycle +system.cpu.iq.iqInstsAdded 27184 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 71 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 22298 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 145 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 13301 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 8222 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 37 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 27168 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.820745 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.402255 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 15812 64.14% 64.14% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3038 12.32% 76.46% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2340 9.49% 85.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1493 6.06% 92.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 1014 4.11% 96.12% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 592 2.40% 98.52% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 274 1.11% 99.63% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 77 0.31% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 13 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 17752 65.34% 65.34% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3320 12.22% 77.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2545 9.37% 86.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1596 5.87% 92.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 1085 3.99% 96.80% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 559 2.06% 98.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 231 0.85% 99.71% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 61 0.22% 99.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 19 0.07% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 24653 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 27168 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 26 13.83% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 13.83% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 101 53.72% 67.55% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 61 32.45% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 13 6.70% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 6.70% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 118 60.82% 67.53% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 63 32.47% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 7329 68.16% 68.18% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 1 0.01% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 68.19% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 68.21% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2278 21.19% 89.40% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1140 10.60% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 7510 66.63% 66.65% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 1 0.01% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.66% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.68% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 2596 23.03% 89.71% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1160 10.29% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 10752 # Type of FU issued +system.cpu.iq.FU_type_0::total 11271 # Type of FU issued system.cpu.iq.FU_type_1::No_OpClass 2 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type_1::IntAlu 7287 67.80% 67.82% # Type of FU issued -system.cpu.iq.FU_type_1::IntMult 1 0.01% 67.83% # Type of FU issued -system.cpu.iq.FU_type_1::IntDiv 0 0.00% 67.83% # Type of FU issued -system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatMult 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMult 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShift 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 67.85% # Type of FU issued -system.cpu.iq.FU_type_1::MemRead 2302 21.42% 89.26% # Type of FU issued -system.cpu.iq.FU_type_1::MemWrite 1154 10.74% 100.00% # Type of FU issued +system.cpu.iq.FU_type_1::IntAlu 7311 66.30% 66.32% # Type of FU issued +system.cpu.iq.FU_type_1::IntMult 1 0.01% 66.33% # Type of FU issued +system.cpu.iq.FU_type_1::IntDiv 0 0.00% 66.33% # Type of FU issued +system.cpu.iq.FU_type_1::FloatAdd 2 0.02% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCmp 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::FloatCvt 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::FloatMult 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::FloatDiv 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::FloatSqrt 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAdd 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAddAcc 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdAlu 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCmp 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdCvt 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMisc 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMult 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdMultAcc 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShift 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdShiftAcc 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdSqrt 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAdd 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatAlu 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCmp 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatCvt 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatDiv 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMisc 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMult 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatMultAcc 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::SimdFloatSqrt 0 0.00% 66.35% # Type of FU issued +system.cpu.iq.FU_type_1::MemRead 2558 23.20% 89.54% # Type of FU issued +system.cpu.iq.FU_type_1::MemWrite 1153 10.46% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_1::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_1::total 10748 # Type of FU issued +system.cpu.iq.FU_type_1::total 11027 # Type of FU issued system.cpu.iq.FU_type::No_OpClass 4 0.02% 0.02% # Type of FU issued -system.cpu.iq.FU_type::IntAlu 14616 67.98% 68.00% # Type of FU issued -system.cpu.iq.FU_type::IntMult 2 0.01% 68.01% # Type of FU issued -system.cpu.iq.FU_type::IntDiv 0 0.00% 68.01% # Type of FU issued -system.cpu.iq.FU_type::FloatAdd 4 0.02% 68.03% # Type of FU issued -system.cpu.iq.FU_type::FloatCmp 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::FloatCvt 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::FloatMult 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::FloatDiv 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::FloatSqrt 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdAdd 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdAlu 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdCmp 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdCvt 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdMisc 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdMult 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdShift 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdSqrt 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 68.03% # Type of FU issued -system.cpu.iq.FU_type::MemRead 4580 21.30% 89.33% # Type of FU issued -system.cpu.iq.FU_type::MemWrite 2294 10.67% 100.00% # Type of FU issued +system.cpu.iq.FU_type::IntAlu 14821 66.47% 66.49% # Type of FU issued +system.cpu.iq.FU_type::IntMult 2 0.01% 66.49% # Type of FU issued +system.cpu.iq.FU_type::IntDiv 0 0.00% 66.49% # Type of FU issued +system.cpu.iq.FU_type::FloatAdd 4 0.02% 66.51% # Type of FU issued +system.cpu.iq.FU_type::FloatCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::FloatCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::FloatMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::FloatDiv 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::FloatSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdAdd 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdAddAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdAlu 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdMisc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdMultAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdShift 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdShiftAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAdd 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatAlu 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCmp 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatCvt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatDiv 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMisc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMult 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatMultAcc 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::SimdFloatSqrt 0 0.00% 66.51% # Type of FU issued +system.cpu.iq.FU_type::MemRead 5154 23.11% 89.63% # Type of FU issued +system.cpu.iq.FU_type::MemWrite 2313 10.37% 100.00% # Type of FU issued system.cpu.iq.FU_type::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type::total 21500 # Type of FU issued -system.cpu.iq.rate 0.648430 # Inst issue rate -system.cpu.iq.fu_busy_cnt::0 92 # FU busy when requested -system.cpu.iq.fu_busy_cnt::1 96 # FU busy when requested -system.cpu.iq.fu_busy_cnt::total 188 # FU busy when requested -system.cpu.iq.fu_busy_rate::0 0.004279 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::1 0.004465 # FU busy rate (busy events/executed inst) -system.cpu.iq.fu_busy_rate::total 0.008744 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 67911 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 37122 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19235 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type::total 22298 # Type of FU issued +system.cpu.iq.rate 0.548280 # Inst issue rate +system.cpu.iq.fu_busy_cnt::0 100 # FU busy when requested +system.cpu.iq.fu_busy_cnt::1 94 # FU busy when requested +system.cpu.iq.fu_busy_cnt::total 194 # FU busy when requested +system.cpu.iq.fu_busy_rate::0 0.004485 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::1 0.004216 # FU busy rate (busy events/executed inst) +system.cpu.iq.fu_busy_rate::total 0.008700 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 72061 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 40564 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19339 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 42 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 20 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 20 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21662 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 22466 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 22 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 68 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1424 # Number of loads squashed -system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu.iew.lsq.thread0.squashedLoads 1837 # Number of loads squashed +system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 483 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 580 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked -system.cpu.iew.lsq.thread1.forwLoads 72 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 295 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.forwLoads 77 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread1.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread1.squashedLoads 1433 # Number of loads squashed +system.cpu.iew.lsq.thread1.squashedLoads 1789 # Number of loads squashed system.cpu.iew.lsq.thread1.ignoredResponses 10 # Number of memory responses ignored because the instruction is squashed -system.cpu.iew.lsq.thread1.memOrderViolation 18 # Number of memory ordering violations -system.cpu.iew.lsq.thread1.squashedStores 481 # Number of stores squashed +system.cpu.iew.lsq.thread1.memOrderViolation 17 # Number of memory ordering violations +system.cpu.iew.lsq.thread1.squashedStores 515 # Number of stores squashed system.cpu.iew.lsq.thread1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread1.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread1.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread1.cacheBlocked 256 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 2403 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 2077 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 53 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25609 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 858 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 5223 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2694 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 51 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 37 # Number of times the IQ has become full, causing a stall -system.cpu.iew.iewLSQFullEvents 5 # Number of times the LSQ has become full, causing a stall -system.cpu.iew.memOrderViolationEvents 33 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 261 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 1201 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1462 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20081 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts::0 2080 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::1 2108 # Number of load instructions executed -system.cpu.iew.iewExecLoadInsts::total 4188 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1419 # Number of squashed instructions skipped in execute +system.cpu.iew.iewSquashCycles 2929 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 685 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 35 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 27441 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 749 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 5992 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2825 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 71 # Number of dispatched non-speculative instructions +system.cpu.iew.iewIQFullEvents 21 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewLSQFullEvents 3 # Number of times the LSQ has become full, causing a stall +system.cpu.iew.memOrderViolationEvents 32 # Number of memory order violations +system.cpu.iew.predictedTakenIncorrect 275 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 1233 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1508 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20701 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts::0 2373 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::1 2359 # Number of load instructions executed +system.cpu.iew.iewExecLoadInsts::total 4732 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1597 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp::0 0 # number of swp insts executed system.cpu.iew.exec_swp::1 0 # number of swp insts executed system.cpu.iew.exec_swp::total 0 # number of swp insts executed -system.cpu.iew.exec_nop::0 75 # number of nop insts executed -system.cpu.iew.exec_nop::1 69 # number of nop insts executed -system.cpu.iew.exec_nop::total 144 # number of nop insts executed -system.cpu.iew.exec_refs::0 3173 # number of memory reference insts executed -system.cpu.iew.exec_refs::1 3212 # number of memory reference insts executed -system.cpu.iew.exec_refs::total 6385 # number of memory reference insts executed -system.cpu.iew.exec_branches::0 1610 # Number of branches executed -system.cpu.iew.exec_branches::1 1659 # Number of branches executed -system.cpu.iew.exec_branches::total 3269 # Number of branches executed -system.cpu.iew.exec_stores::0 1093 # Number of stores executed -system.cpu.iew.exec_stores::1 1104 # Number of stores executed -system.cpu.iew.exec_stores::total 2197 # Number of stores executed -system.cpu.iew.exec_rate 0.605634 # Inst execution rate -system.cpu.iew.wb_sent::0 9747 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::1 9790 # cumulative count of insts sent to commit -system.cpu.iew.wb_sent::total 19537 # cumulative count of insts sent to commit -system.cpu.iew.wb_count::0 9617 # cumulative count of insts written-back -system.cpu.iew.wb_count::1 9638 # cumulative count of insts written-back -system.cpu.iew.wb_count::total 19255 # cumulative count of insts written-back -system.cpu.iew.wb_producers::0 5071 # num instructions producing a value -system.cpu.iew.wb_producers::1 5050 # num instructions producing a value -system.cpu.iew.wb_producers::total 10121 # num instructions producing a value -system.cpu.iew.wb_consumers::0 6666 # num instructions consuming a value -system.cpu.iew.wb_consumers::1 6567 # num instructions consuming a value -system.cpu.iew.wb_consumers::total 13233 # num instructions consuming a value +system.cpu.iew.exec_nop::0 114 # number of nop insts executed +system.cpu.iew.exec_nop::1 72 # number of nop insts executed +system.cpu.iew.exec_nop::total 186 # number of nop insts executed +system.cpu.iew.exec_refs::0 3487 # number of memory reference insts executed +system.cpu.iew.exec_refs::1 3445 # number of memory reference insts executed +system.cpu.iew.exec_refs::total 6932 # number of memory reference insts executed +system.cpu.iew.exec_branches::0 1642 # Number of branches executed +system.cpu.iew.exec_branches::1 1642 # Number of branches executed +system.cpu.iew.exec_branches::total 3284 # Number of branches executed +system.cpu.iew.exec_stores::0 1114 # Number of stores executed +system.cpu.iew.exec_stores::1 1086 # Number of stores executed +system.cpu.iew.exec_stores::total 2200 # Number of stores executed +system.cpu.iew.exec_rate 0.509012 # Inst execution rate +system.cpu.iew.wb_sent::0 9936 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::1 9721 # cumulative count of insts sent to commit +system.cpu.iew.wb_sent::total 19657 # cumulative count of insts sent to commit +system.cpu.iew.wb_count::0 9778 # cumulative count of insts written-back +system.cpu.iew.wb_count::1 9581 # cumulative count of insts written-back +system.cpu.iew.wb_count::total 19359 # cumulative count of insts written-back +system.cpu.iew.wb_producers::0 5047 # num instructions producing a value +system.cpu.iew.wb_producers::1 4925 # num instructions producing a value +system.cpu.iew.wb_producers::total 9972 # num instructions producing a value +system.cpu.iew.wb_consumers::0 6570 # num instructions consuming a value +system.cpu.iew.wb_consumers::1 6411 # num instructions consuming a value +system.cpu.iew.wb_consumers::total 12981 # num instructions consuming a value system.cpu.iew.wb_penalized::0 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::1 0 # number of instrctions required to write to 'other' IQ system.cpu.iew.wb_penalized::total 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate::0 0.290044 # insts written-back per cycle -system.cpu.iew.wb_rate::1 0.290678 # insts written-back per cycle -system.cpu.iew.wb_rate::total 0.580722 # insts written-back per cycle -system.cpu.iew.wb_fanout::0 0.760726 # average fanout of values written-back -system.cpu.iew.wb_fanout::1 0.768996 # average fanout of values written-back -system.cpu.iew.wb_fanout::total 0.764830 # average fanout of values written-back +system.cpu.iew.wb_rate::0 0.240429 # insts written-back per cycle +system.cpu.iew.wb_rate::1 0.235585 # insts written-back per cycle +system.cpu.iew.wb_rate::total 0.476014 # insts written-back per cycle +system.cpu.iew.wb_fanout::0 0.768189 # average fanout of values written-back +system.cpu.iew.wb_fanout::1 0.768211 # average fanout of values written-back +system.cpu.iew.wb_fanout::total 0.768200 # average fanout of values written-back system.cpu.iew.wb_penalized_rate::0 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::1 0 # fraction of instructions written-back that wrote to 'other' IQ system.cpu.iew.wb_penalized_rate::total 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 12822 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 14694 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1273 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 24601 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.519450 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.331680 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1316 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 27077 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.471950 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.251708 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 19177 77.95% 77.95% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 2699 10.97% 88.92% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1115 4.53% 93.46% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 469 1.91% 95.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 340 1.38% 96.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 279 1.13% 97.88% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 190 0.77% 98.65% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 108 0.44% 99.09% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 224 0.91% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 21479 79.33% 79.33% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 2818 10.41% 89.73% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1191 4.40% 94.13% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 503 1.86% 95.99% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 353 1.30% 97.29% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 251 0.93% 98.22% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 184 0.68% 98.90% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 85 0.31% 99.21% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 213 0.79% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 24601 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 27077 # Number of insts commited each cycle system.cpu.commit.committedInsts::0 6389 # Number of instructions committed system.cpu.commit.committedInsts::1 6390 # Number of instructions committed system.cpu.commit.committedInsts::total 12779 # Number of instructions committed @@ -602,27 +601,27 @@ system.cpu.commit.int_insts::total 12614 # Nu system.cpu.commit.function_calls::0 127 # Number of function calls committed. system.cpu.commit.function_calls::1 127 # Number of function calls committed. system.cpu.commit.function_calls::total 254 # Number of function calls committed. -system.cpu.commit.bw_lim_events 224 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 213 # number cycles where commit BW limit reached system.cpu.commit.bw_limited::0 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::1 0 # number of insts not committed due to BW limits system.cpu.commit.bw_limited::total 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 119315 # The number of ROB reads -system.cpu.rob.rob_writes 53622 # The number of ROB writes -system.cpu.timesIdled 272 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 8504 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 129384 # The number of ROB reads +system.cpu.rob.rob_writes 57896 # The number of ROB writes +system.cpu.timesIdled 318 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13501 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts::0 6372 # Number of Instructions Simulated system.cpu.committedInsts::1 6373 # Number of Instructions Simulated system.cpu.committedOps::0 6372 # Number of Ops (including micro ops) Simulated system.cpu.committedOps::1 6373 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 12745 # Number of Instructions Simulated -system.cpu.cpi::0 5.203547 # CPI: Cycles Per Instruction -system.cpu.cpi::1 5.202730 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.601569 # CPI: Total CPI of All Threads -system.cpu.ipc::0 0.192177 # IPC: Instructions Per Cycle -system.cpu.ipc::1 0.192207 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.384383 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 25429 # number of integer regfile reads -system.cpu.int_regfile_writes 14534 # number of integer regfile writes +system.cpu.cpi::0 6.382454 # CPI: Cycles Per Instruction +system.cpu.cpi::1 6.381453 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.190977 # CPI: Total CPI of All Threads +system.cpu.ipc::0 0.156680 # IPC: Instructions Per Cycle +system.cpu.ipc::1 0.156704 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.313384 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 26029 # number of integer regfile reads +system.cpu.int_regfile_writes 14619 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads system.cpu.fp_regfile_writes 4 # number of floating regfile writes system.cpu.misc_regfile_reads 2 # number of misc regfile reads @@ -630,323 +629,323 @@ system.cpu.misc_regfile_writes 2 # nu system.cpu.icache.replacements::0 6 # number of replacements system.cpu.icache.replacements::1 0 # number of replacements system.cpu.icache.replacements::total 6 # number of replacements -system.cpu.icache.tagsinuse 313.964791 # Cycle average of tags in use -system.cpu.icache.total_refs 4270 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 627 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 6.810207 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 309.378150 # Cycle average of tags in use +system.cpu.icache.total_refs 4652 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 625 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 7.443200 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 313.964791 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.153303 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.153303 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 4270 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4270 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4270 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4270 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4270 # number of overall hits -system.cpu.icache.overall_hits::total 4270 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 864 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 864 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 864 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 864 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 864 # number of overall misses -system.cpu.icache.overall_misses::total 864 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 38406500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 38406500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 38406500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 38406500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 38406500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 38406500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5134 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5134 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5134 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5134 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5134 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.168290 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.168290 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.168290 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.168290 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.168290 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.168290 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 44451.967593 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 44451.967593 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 44451.967593 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 44451.967593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 44451.967593 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 44451.967593 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.occ_blocks::cpu.inst 309.378150 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.151064 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.151064 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 4652 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4652 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4652 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4652 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4652 # number of overall hits +system.cpu.icache.overall_hits::total 4652 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 1030 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 1030 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 1030 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 1030 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 1030 # number of overall misses +system.cpu.icache.overall_misses::total 1030 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 56036996 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 56036996 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 56036996 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 56036996 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 56036996 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 56036996 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5682 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5682 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5682 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5682 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5682 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5682 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.181274 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.181274 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.181274 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.181274 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.181274 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.181274 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54404.850485 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 54404.850485 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 54404.850485 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 54404.850485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 54404.850485 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 54404.850485 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 2136 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 56 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 38.142857 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 237 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 237 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 237 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 237 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 237 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 237 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 627 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 627 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 627 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 627 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 627 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 627 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 29513000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 29513000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 29513000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 29513000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 29513000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 29513000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.122127 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.122127 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.122127 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.122127 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.122127 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.122127 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 47070.175439 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 47070.175439 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 47070.175439 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 47070.175439 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 47070.175439 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 47070.175439 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 405 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 405 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 405 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 405 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 405 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 405 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 625 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 625 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 625 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 37870497 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 37870497 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 37870497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 37870497 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 37870497 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 37870497 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.109996 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.109996 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.109996 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.109996 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60592.795200 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60592.795200 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60592.795200 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 60592.795200 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60592.795200 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 60592.795200 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements::0 0 # number of replacements system.cpu.dcache.replacements::1 0 # number of replacements system.cpu.dcache.replacements::total 0 # number of replacements -system.cpu.dcache.tagsinuse 214.758121 # Cycle average of tags in use -system.cpu.dcache.total_refs 4620 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 350 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 13.200000 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 213.566251 # Cycle average of tags in use +system.cpu.dcache.total_refs 4636 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 356 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 13.022472 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 214.758121 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.052431 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.052431 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3604 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3604 # number of ReadReq hits +system.cpu.dcache.occ_blocks::cpu.data 213.566251 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.052140 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.052140 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3620 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3620 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 1016 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 1016 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 4620 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4620 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4620 # number of overall hits -system.cpu.dcache.overall_hits::total 4620 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 337 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 337 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 4636 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4636 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4636 # number of overall hits +system.cpu.dcache.overall_hits::total 4636 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 336 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 336 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 714 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 714 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 1051 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 1051 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 1051 # number of overall misses -system.cpu.dcache.overall_misses::total 1051 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 21509500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 21509500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 23277500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 23277500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 44787000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 44787000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 44787000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 44787000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3941 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3941 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_misses::cpu.data 1050 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 1050 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 1050 # number of overall misses +system.cpu.dcache.overall_misses::total 1050 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 20070500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 20070500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 32974457 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 32974457 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 53044957 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 53044957 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 53044957 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 53044957 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3956 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3956 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1730 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1730 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 5671 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 5671 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 5671 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 5671 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.085511 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.085511 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 5686 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 5686 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 5686 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 5686 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.084934 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.084934 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.185329 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.185329 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.185329 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.185329 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63826.409496 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63826.409496 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 32601.540616 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 32601.540616 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 42613.701237 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 42613.701237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 42613.701237 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 42613.701237 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_miss_rate::cpu.data 0.184664 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.184664 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.184664 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.184664 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59733.630952 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59733.630952 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 46182.712885 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 46182.712885 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 50519.006667 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 50519.006667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 50519.006667 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 50519.006667 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 2851 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 107 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 26.644860 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 133 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 133 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 126 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 568 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 568 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 701 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 701 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 701 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 701 # number of overall MSHR hits -system.cpu.dcache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.dcache.ReadReq_mshr_misses::total 204 # number of ReadReq MSHR misses +system.cpu.dcache.demand_mshr_hits::cpu.data 694 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 694 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 694 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 694 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses +system.cpu.dcache.ReadReq_mshr_misses::total 210 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 146 # number of WriteReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::total 146 # number of WriteReq MSHR misses -system.cpu.dcache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses -system.cpu.dcache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.dcache.overall_mshr_misses::total 350 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14117500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 14117500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 6787000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 6787000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 20904500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 20904500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 20904500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 20904500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.051764 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.051764 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_misses::cpu.data 356 # number of demand (read+write) MSHR misses +system.cpu.dcache.demand_mshr_misses::total 356 # number of demand (read+write) MSHR misses +system.cpu.dcache.overall_mshr_misses::cpu.data 356 # number of overall MSHR misses +system.cpu.dcache.overall_mshr_misses::total 356 # number of overall MSHR misses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14343000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 14343000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8833995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 8833995 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 23176995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 23176995 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 23176995 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 23176995 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.053084 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.053084 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.061718 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.061718 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.061718 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.061718 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 69203.431373 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 69203.431373 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 46486.301370 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 46486.301370 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 59727.142857 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 59727.142857 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 59727.142857 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 59727.142857 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.062610 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.062610 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.062610 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.062610 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 68300 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 68300 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 60506.815068 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 60506.815068 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65103.918539 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 65103.918539 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 65103.918539 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 65103.918539 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements::0 0 # number of replacements system.cpu.l2cache.replacements::1 0 # number of replacements system.cpu.l2cache.replacements::total 0 # number of replacements -system.cpu.l2cache.tagsinuse 435.100631 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 429.985619 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 829 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.002413 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 833 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.002401 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 314.254634 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 120.845997 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.009590 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.003688 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.013278 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 309.894864 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 120.090755 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.009457 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.003665 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.013122 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 625 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 204 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 829 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 623 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 210 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 833 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 146 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 146 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 625 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 350 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 975 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 625 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 350 # number of overall misses -system.cpu.l2cache.overall_misses::total 975 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 28872500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 13901000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 42773500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6638500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 6638500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 28872500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 20539500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 49412000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 28872500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 20539500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 49412000 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 627 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::cpu.data 204 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 831 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.demand_misses::cpu.inst 623 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 356 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::total 979 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 623 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 356 # number of overall misses +system.cpu.l2cache.overall_misses::total 979 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 37222000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 14122000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 51344000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8685000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 8685000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 37222000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 22807000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 60029000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 37222000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 22807000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 60029000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 625 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::cpu.data 210 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 835 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 146 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 146 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 627 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::cpu.data 350 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 977 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 627 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.data 350 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 977 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996810 # miss rate for ReadReq accesses +system.cpu.l2cache.demand_accesses::cpu.inst 625 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.data 356 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::total 981 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 625 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.data 356 # number of overall (read+write) accesses +system.cpu.l2cache.overall_accesses::total 981 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996800 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.997593 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.997605 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996810 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996800 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.997953 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996810 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.997961 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996800 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.997953 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 46196 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 68142.156863 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 51596.501809 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 45469.178082 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 45469.178082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 46196 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 58684.285714 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 50678.974359 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 46196 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 58684.285714 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 50678.974359 # average overall miss latency -system.cpu.l2cache.blocked_cycles::no_mshrs 208 # number of cycles access was blocked +system.cpu.l2cache.overall_miss_rate::total 0.997961 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 59746.388443 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67247.619048 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 61637.454982 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59486.301370 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59486.301370 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59746.388443 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64064.606742 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 61316.649642 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59746.388443 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64064.606742 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 61316.649642 # average overall miss latency +system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.blocked::no_mshrs 13 # number of cycles access was blocked +system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.l2cache.avg_blocked_cycles::no_mshrs 16 # average number of cycles each access was blocked +system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 625 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 204 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 829 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 623 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 210 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 833 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 146 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 146 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 625 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 350 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 975 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 625 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 350 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 975 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 26807484 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 13234146 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 40041630 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6160108 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6160108 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 26807484 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 19394254 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 46201738 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 26807484 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 19394254 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 46201738 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 623 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 356 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 979 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 623 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 356 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 979 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 29496155 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 11535670 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 41031825 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6881648 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6881648 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29496155 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 18417318 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 47913473 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29496155 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 18417318 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 47913473 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997593 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997605 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.997953 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996810 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.997961 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996800 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.997953 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 42891.974400 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64873.264706 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 48301.121834 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 42192.520548 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 42192.520548 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42891.974400 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 55412.154286 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 47386.397949 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42891.974400 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 55412.154286 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 47386.397949 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.997961 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 47345.353130 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 54931.761905 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 49257.893157 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 47134.575342 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 47134.575342 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 47345.353130 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 51734.039326 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 48941.239019 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 47345.353130 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 51734.039326 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 48941.239019 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt index 9c26db577..165716ee5 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000024 # Number of seconds simulated -sim_ticks 24110500 # Number of ticks simulated -final_tick 24110500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 22522500 # Number of ticks simulated +final_tick 22522500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 94813 # Simulator instruction rate (inst/s) -host_op_rate 94805 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 150747979 # Simulator tick rate (ticks/s) -host_mem_usage 222632 # Number of bytes of host memory used -host_seconds 0.16 # Real time elapsed on the host +host_inst_rate 65265 # Simulator instruction rate (inst/s) +host_op_rate 65259 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 96930117 # Simulator tick rate (ticks/s) +host_mem_usage 222888 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host sim_insts 15162 # Number of instructions simulated sim_ops 15162 # Number of ops (including micro ops) simulated system.physmem.bytes_read::cpu.inst 19072 # Number of bytes read from this memory @@ -19,14 +19,14 @@ system.physmem.bytes_inst_read::total 19072 # Nu system.physmem.num_reads::cpu.inst 298 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory system.physmem.num_reads::total 436 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 791024657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 366313432 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1157338089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 791024657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 791024657 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 791024657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 366313432 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1157338089 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 846797647 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 392141192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1238938839 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 846797647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 846797647 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 846797647 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 392141192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1238938839 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 436 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen system.physmem.cpureqs 436 # Reqs generatd by CPU via cache - shady @@ -70,7 +70,7 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 24077000 # Total gap between requests +system.physmem.totGap 22489000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes @@ -98,11 +98,11 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 305 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 107 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 22 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 2 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 279 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 111 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 35 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 9 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see @@ -164,49 +164,49 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 1670434 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 11016434 # Sum of mem lat for all requests +system.physmem.totQLat 1783436 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 10779436 # Sum of mem lat for all requests system.physmem.totBusLat 1744000 # Total cycles spent in databus access -system.physmem.totBankLat 7602000 # Total cycles spent in bank access -system.physmem.avgQLat 3831.27 # Average queueing delay per request -system.physmem.avgBankLat 17435.78 # Average bank access latency per request +system.physmem.totBankLat 7252000 # Total cycles spent in bank access +system.physmem.avgQLat 4090.45 # Average queueing delay per request +system.physmem.avgBankLat 16633.03 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 25267.05 # Average memory access latency -system.physmem.avgRdBW 1157.34 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 24723.48 # Average memory access latency +system.physmem.avgRdBW 1238.94 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1157.34 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1238.94 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 7.23 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.46 # Average read queue length over time +system.physmem.busUtil 7.74 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.48 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time system.physmem.readRowHits 359 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.34 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 55222.48 # Average gap between requests +system.physmem.avgGap 51580.28 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 48222 # number of cpu cycles simulated +system.cpu.numCycles 45046 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.branch_predictor.lookups 5021 # Number of BP lookups -system.cpu.branch_predictor.condPredicted 3412 # Number of conditional branches predicted +system.cpu.branch_predictor.lookups 5017 # Number of BP lookups +system.cpu.branch_predictor.condPredicted 3408 # Number of conditional branches predicted system.cpu.branch_predictor.condIncorrect 2378 # Number of conditional branches incorrect -system.cpu.branch_predictor.BTBLookups 3518 # Number of BTB lookups -system.cpu.branch_predictor.BTBHits 2142 # Number of BTB hits +system.cpu.branch_predictor.BTBLookups 3514 # Number of BTB lookups +system.cpu.branch_predictor.BTBHits 2140 # Number of BTB hits system.cpu.branch_predictor.usedRAS 176 # Number of times the RAS was used to get a target. system.cpu.branch_predictor.RASInCorrect 5 # Number of incorrect RAS predictions. -system.cpu.branch_predictor.BTBHitPct 60.886868 # BTB Hit Percentage -system.cpu.branch_predictor.predictedTaken 2318 # Number of Branches Predicted As Taken (True). -system.cpu.branch_predictor.predictedNotTaken 2703 # Number of Branches Predicted As Not Taken (False). -system.cpu.regfile_manager.intRegFileReads 14367 # Number of Reads from Int. Register File +system.cpu.branch_predictor.BTBHitPct 60.899260 # BTB Hit Percentage +system.cpu.branch_predictor.predictedTaken 2316 # Number of Branches Predicted As Taken (True). +system.cpu.branch_predictor.predictedNotTaken 2701 # Number of Branches Predicted As Not Taken (False). +system.cpu.regfile_manager.intRegFileReads 14466 # Number of Reads from Int. Register File system.cpu.regfile_manager.intRegFileWrites 11099 # Number of Writes to Int. Register File -system.cpu.regfile_manager.intRegFileAccesses 25466 # Total Accesses (Read+Write) to the Int. Register File +system.cpu.regfile_manager.intRegFileAccesses 25565 # Total Accesses (Read+Write) to the Int. Register File system.cpu.regfile_manager.floatRegFileReads 0 # Number of Reads from FP Register File system.cpu.regfile_manager.floatRegFileWrites 0 # Number of Writes to FP Register File system.cpu.regfile_manager.floatRegFileAccesses 0 # Total Accesses (Read+Write) to the FP Register File -system.cpu.regfile_manager.regForwards 5027 # Number of Registers Read Through Forwarding Logic -system.cpu.agen_unit.agens 3931 # Number of Address Generations +system.cpu.regfile_manager.regForwards 4899 # Number of Registers Read Through Forwarding Logic +system.cpu.agen_unit.agens 3932 # Number of Address Generations system.cpu.execution_unit.predictedTakenIncorrect 1367 # Number of Branches Incorrectly Predicted As Taken. system.cpu.execution_unit.predictedNotTakenIncorrect 948 # Number of Branches Incorrectly Predicted As Not Taken). system.cpu.execution_unit.mispredicted 2315 # Number of Branches Incorrectly Predicted @@ -216,12 +216,12 @@ system.cpu.execution_unit.executions 11058 # Nu system.cpu.mult_div_unit.multiplies 0 # Number of Multipy Operations Executed system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed system.cpu.contextSwitches 1 # Number of context switches -system.cpu.threadCycles 22133 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) +system.cpu.threadCycles 21840 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread) system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode -system.cpu.timesIdled 497 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 30866 # Number of cycles cpu's stages were not processed -system.cpu.runCycles 17356 # Number of cycles cpu stages are processed. -system.cpu.activity 35.991871 # Percentage of cycles cpu is active +system.cpu.timesIdled 501 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 27681 # Number of cycles cpu's stages were not processed +system.cpu.runCycles 17365 # Number of cycles cpu stages are processed. +system.cpu.activity 38.549483 # Percentage of cycles cpu is active system.cpu.comLoads 2225 # Number of Load instructions committed system.cpu.comStores 1448 # Number of Store instructions committed system.cpu.comBranches 3358 # Number of Branches instructions committed @@ -233,146 +233,146 @@ system.cpu.committedInsts 15162 # Nu system.cpu.committedOps 15162 # Number of Ops committed (Per-Thread) system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread) system.cpu.committedInsts_total 15162 # Number of Instructions committed (Total) -system.cpu.cpi 3.180451 # CPI: Cycles Per Instruction (Per-Thread) +system.cpu.cpi 2.970980 # CPI: Cycles Per Instruction (Per-Thread) system.cpu.smt_cpi nan # CPI: Total SMT-CPI -system.cpu.cpi_total 3.180451 # CPI: Total CPI of All Threads -system.cpu.ipc 0.314421 # IPC: Instructions Per Cycle (Per-Thread) +system.cpu.cpi_total 2.970980 # CPI: Total CPI of All Threads +system.cpu.ipc 0.336589 # IPC: Instructions Per Cycle (Per-Thread) system.cpu.smt_ipc nan # IPC: Total SMT-IPC -system.cpu.ipc_total 0.314421 # IPC: Total IPC of All Threads -system.cpu.stage0.idleCycles 35090 # Number of cycles 0 instructions are processed. -system.cpu.stage0.runCycles 13132 # Number of cycles 1+ instructions are processed. -system.cpu.stage0.utilization 27.232384 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage1.idleCycles 39034 # Number of cycles 0 instructions are processed. -system.cpu.stage1.runCycles 9188 # Number of cycles 1+ instructions are processed. -system.cpu.stage1.utilization 19.053544 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage2.idleCycles 39406 # Number of cycles 0 instructions are processed. -system.cpu.stage2.runCycles 8816 # Number of cycles 1+ instructions are processed. -system.cpu.stage2.utilization 18.282112 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage3.idleCycles 45338 # Number of cycles 0 instructions are processed. -system.cpu.stage3.runCycles 2884 # Number of cycles 1+ instructions are processed. -system.cpu.stage3.utilization 5.980673 # Percentage of cycles stage was utilized (processing insts). -system.cpu.stage4.idleCycles 38904 # Number of cycles 0 instructions are processed. -system.cpu.stage4.runCycles 9318 # Number of cycles 1+ instructions are processed. -system.cpu.stage4.utilization 19.323131 # Percentage of cycles stage was utilized (processing insts). +system.cpu.ipc_total 0.336589 # IPC: Total IPC of All Threads +system.cpu.stage0.idleCycles 31894 # Number of cycles 0 instructions are processed. +system.cpu.stage0.runCycles 13152 # Number of cycles 1+ instructions are processed. +system.cpu.stage0.utilization 29.196821 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage1.idleCycles 35835 # Number of cycles 0 instructions are processed. +system.cpu.stage1.runCycles 9211 # Number of cycles 1+ instructions are processed. +system.cpu.stage1.utilization 20.447987 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage2.idleCycles 36237 # Number of cycles 0 instructions are processed. +system.cpu.stage2.runCycles 8809 # Number of cycles 1+ instructions are processed. +system.cpu.stage2.utilization 19.555565 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage3.idleCycles 42168 # Number of cycles 0 instructions are processed. +system.cpu.stage3.runCycles 2878 # Number of cycles 1+ instructions are processed. +system.cpu.stage3.utilization 6.389025 # Percentage of cycles stage was utilized (processing insts). +system.cpu.stage4.idleCycles 35732 # Number of cycles 0 instructions are processed. +system.cpu.stage4.runCycles 9314 # Number of cycles 1+ instructions are processed. +system.cpu.stage4.utilization 20.676642 # Percentage of cycles stage was utilized (processing insts). system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 166.100833 # Cycle average of tags in use -system.cpu.icache.total_refs 2586 # Total number of references to valid blocks. +system.cpu.icache.tagsinuse 171.605866 # Cycle average of tags in use +system.cpu.icache.total_refs 2584 # Total number of references to valid blocks. system.cpu.icache.sampled_refs 299 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 8.648829 # Average number of references to valid blocks. +system.cpu.icache.avg_refs 8.642140 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 166.100833 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.081104 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.081104 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 2586 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2586 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2586 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2586 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2586 # number of overall hits -system.cpu.icache.overall_hits::total 2586 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 369 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 369 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 369 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 369 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 369 # number of overall misses -system.cpu.icache.overall_misses::total 369 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 18278500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 18278500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 18278500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 18278500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 18278500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 18278500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2955 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2955 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2955 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2955 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2955 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.124873 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.124873 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.124873 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.124873 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.124873 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.124873 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 49535.230352 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 49535.230352 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 49535.230352 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 49535.230352 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 49535.230352 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 171.605866 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.083792 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.083792 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 2584 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2584 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2584 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2584 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2584 # number of overall hits +system.cpu.icache.overall_hits::total 2584 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 372 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 372 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 372 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 372 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 372 # number of overall misses +system.cpu.icache.overall_misses::total 372 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 18064500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 18064500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 18064500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 18064500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 18064500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 18064500 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2956 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2956 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2956 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2956 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2956 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.125846 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.125846 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.125846 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.125846 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.125846 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.125846 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 48560.483871 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 48560.483871 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 48560.483871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 48560.483871 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 48560.483871 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked_cycles::no_targets 85 # number of cycles access was blocked +system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.icache.blocked::no_targets 2 # number of cycles access was blocked +system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.icache.avg_blocked_cycles::no_targets 42.500000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 71 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 71 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 71 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 71 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 71 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 71 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 301 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 301 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 301 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 14783500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 14783500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14783500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 14783500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101861 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.101861 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101861 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.101861 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49114.617940 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49114.617940 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49114.617940 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 49114.617940 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 14600500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 14600500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 14600500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 14600500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 14600500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 14600500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.101827 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.101827 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.101827 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.101827 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48506.644518 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48506.644518 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48506.644518 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48506.644518 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 97.064476 # Cycle average of tags in use -system.cpu.dcache.total_refs 3314 # Total number of references to valid blocks. +system.cpu.dcache.tagsinuse 99.150895 # Cycle average of tags in use +system.cpu.dcache.total_refs 3193 # Total number of references to valid blocks. system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 24.014493 # Average number of references to valid blocks. +system.cpu.dcache.avg_refs 23.137681 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 97.064476 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.023697 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.023697 # Average percentage of cache occupancy +system.cpu.dcache.occ_blocks::cpu.data 99.150895 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024207 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024207 # Average percentage of cache occupancy system.cpu.dcache.ReadReq_hits::cpu.data 2167 # number of ReadReq hits system.cpu.dcache.ReadReq_hits::total 2167 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1141 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1141 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1020 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1020 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 3308 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 3308 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 3308 # number of overall hits -system.cpu.dcache.overall_hits::total 3308 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 3187 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 3187 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 3187 # number of overall hits +system.cpu.dcache.overall_hits::total 3187 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 58 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 58 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 301 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 301 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 359 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 359 # number of overall misses -system.cpu.dcache.overall_misses::total 359 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 3241000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 3241000 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14317500 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14317500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17558500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17558500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17558500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17558500 # number of overall miss cycles +system.cpu.dcache.WriteReq_misses::cpu.data 422 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 422 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 480 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 480 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 480 # number of overall misses +system.cpu.dcache.overall_misses::total 480 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 3300500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 3300500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19262500 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19262500 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 22563000 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 22563000 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 22563000 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 22563000 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 2225 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) @@ -385,36 +385,36 @@ system.cpu.dcache.overall_accesses::cpu.data 3667 system.cpu.dcache.overall_accesses::total 3667 # number of overall (read+write) accesses system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.026067 # miss rate for ReadReq accesses system.cpu.dcache.ReadReq_miss_rate::total 0.026067 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.208738 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.208738 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.097900 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.097900 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.097900 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.097900 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55879.310345 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 55879.310345 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47566.445183 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 47566.445183 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 48909.470752 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 48909.470752 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 48909.470752 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 48909.470752 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked_cycles::no_targets 3701 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_targets 45 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu.dcache.avg_blocked_cycles::no_targets 82.244444 # average number of cycles each access was blocked +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.292649 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.292649 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.130897 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.130897 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.130897 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.130897 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56905.172414 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 56905.172414 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 45645.734597 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 45645.734597 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 47006.250000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 47006.250000 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 47006.250000 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 680 # number of cycles access was blocked +system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 34 # number of cycles access was blocked +system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 20 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed system.cpu.dcache.ReadReq_mshr_hits::cpu.data 5 # number of ReadReq MSHR hits system.cpu.dcache.ReadReq_mshr_hits::total 5 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 216 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 216 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 221 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 221 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 221 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 221 # number of overall MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 337 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 337 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 342 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 342 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 342 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 342 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 # number of WriteReq MSHR misses @@ -423,14 +423,14 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 138 system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 138 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2840500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 2840500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4329000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 4329000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7169500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 7169500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7169500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 7169500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 2900000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4513000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4513000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7413000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 7413000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7413000 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 7413000 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 # mshr miss rate for WriteReq accesses @@ -439,26 +439,26 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53594.339623 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53594.339623 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 50929.411765 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 50929.411765 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 51952.898551 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 51952.898551 # average overall mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 54716.981132 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 54716.981132 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53094.117647 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53094.117647 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53717.391304 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 53717.391304 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 196.769171 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 202.986818 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. system.cpu.l2cache.sampled_refs 351 # Sample count of references to valid blocks. system.cpu.l2cache.avg_refs 0.005698 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 165.497362 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 31.271809 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.005051 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.000954 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.006005 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 170.969481 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 32.017336 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005218 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.000977 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006195 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits @@ -476,17 +476,17 @@ system.cpu.l2cache.demand_misses::total 437 # nu system.cpu.l2cache.overall_misses::cpu.inst 299 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 138 # number of overall misses system.cpu.l2cache.overall_misses::total 437 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14500500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2786000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 17286500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4241500 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 4241500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 14500500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 7027500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 21528000 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 14500500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 7027500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 21528000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 14317500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2845500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 17163000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4425000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4425000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 14317500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7270500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 21588000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 14317500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7270500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 21588000 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 301 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 53 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 354 # number of ReadReq accesses(hits+misses) @@ -509,17 +509,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.995444 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993355 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.995444 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48496.655518 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52566.037736 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 49109.375000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 49900 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 49900 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 49263.157895 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48496.655518 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 50923.913043 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 49263.157895 # average overall miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47884.615385 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53688.679245 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 48758.522727 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52058.823529 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52058.823529 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 49400.457666 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47884.615385 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52684.782609 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 49400.457666 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -539,17 +539,17 @@ system.cpu.l2cache.demand_mshr_misses::total 437 system.cpu.l2cache.overall_mshr_misses::cpu.inst 299 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 138 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 437 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10728482 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2122568 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12851050 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3166632 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3166632 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10728482 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5289200 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 16017682 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10728482 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5289200 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 16017682 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 10547482 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2181568 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12729050 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3382064 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3382064 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10547482 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5563632 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 16111114 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10547482 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5563632 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 16111114 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994350 # mshr miss rate for ReadReq accesses @@ -561,17 +561,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.995444 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993355 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.995444 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35881.210702 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40048.452830 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36508.664773 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 37254.494118 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 37254.494118 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35881.210702 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38327.536232 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36653.734554 # average overall mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35275.859532 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 41161.660377 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36162.073864 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39788.988235 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39788.988235 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35275.859532 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40316.173913 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 36867.537757 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt index a830552cf..39a395968 100644 --- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt +++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/stats.txt @@ -1,38 +1,38 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000020 # Number of seconds simulated -sim_ticks 19778500 # Number of ticks simulated -final_tick 19778500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000023 # Number of seconds simulated +sim_ticks 23428500 # Number of ticks simulated +final_tick 23428500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 52882 # Simulator instruction rate (inst/s) -host_op_rate 52877 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 72439157 # Simulator tick rate (ticks/s) -host_mem_usage 223656 # Number of bytes of host memory used +host_inst_rate 53742 # Simulator instruction rate (inst/s) +host_op_rate 53738 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 87205048 # Simulator tick rate (ticks/s) +host_mem_usage 223912 # Number of bytes of host memory used host_seconds 0.27 # Real time elapsed on the host sim_insts 14436 # Number of instructions simulated sim_ops 14436 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 9344 # Number of bytes read from this memory -system.physmem.bytes_read::total 30912 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 21568 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 337 # Number of read requests responded to by this memory +system.physmem.bytes_read::total 30848 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 146 # Number of read requests responded to by this memory -system.physmem.num_reads::total 483 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1090477033 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 472432186 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1562909220 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1090477033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1090477033 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1090477033 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 472432186 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1562909220 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 483 # Total number of read requests seen +system.physmem.num_reads::total 482 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 917856457 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 398830484 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1316686941 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 917856457 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 917856457 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 917856457 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 398830484 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1316686941 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 482 # Total number of read requests seen system.physmem.writeReqs 0 # Total number of write requests seen -system.physmem.cpureqs 483 # Reqs generatd by CPU via cache - shady -system.physmem.bytesRead 30912 # Total number of bytes read from memory +system.physmem.cpureqs 482 # Reqs generatd by CPU via cache - shady +system.physmem.bytesRead 30848 # Total number of bytes read from memory system.physmem.bytesWritten 0 # Total number of bytes written to memory -system.physmem.bytesConsumedRd 30912 # bytesRead derated as per pkt->getSize() +system.physmem.bytesConsumedRd 30848 # bytesRead derated as per pkt->getSize() system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed @@ -40,7 +40,7 @@ system.physmem.perBankRdReqs::0 70 # Tr system.physmem.perBankRdReqs::1 36 # Track reads on a per bank basis system.physmem.perBankRdReqs::2 24 # Track reads on a per bank basis system.physmem.perBankRdReqs::3 6 # Track reads on a per bank basis -system.physmem.perBankRdReqs::4 8 # Track reads on a per bank basis +system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis system.physmem.perBankRdReqs::5 44 # Track reads on a per bank basis system.physmem.perBankRdReqs::6 3 # Track reads on a per bank basis system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis @@ -70,14 +70,14 @@ system.physmem.perBankWrReqs::14 0 # Tr system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry -system.physmem.totGap 19726000 # Total gap between requests +system.physmem.totGap 23376000 # Total gap between requests system.physmem.readPktSize::0 0 # Categorize read packet sizes system.physmem.readPktSize::1 0 # Categorize read packet sizes system.physmem.readPktSize::2 0 # Categorize read packet sizes system.physmem.readPktSize::3 0 # Categorize read packet sizes system.physmem.readPktSize::4 0 # Categorize read packet sizes system.physmem.readPktSize::5 0 # Categorize read packet sizes -system.physmem.readPktSize::6 483 # Categorize read packet sizes +system.physmem.readPktSize::6 482 # Categorize read packet sizes system.physmem.readPktSize::7 0 # Categorize read packet sizes system.physmem.readPktSize::8 0 # Categorize read packet sizes system.physmem.writePktSize::0 0 # categorize write packet sizes @@ -98,13 +98,13 @@ system.physmem.neitherpktsize::5 0 # ca system.physmem.neitherpktsize::6 0 # categorize neither packet sizes system.physmem.neitherpktsize::7 0 # categorize neither packet sizes system.physmem.neitherpktsize::8 0 # categorize neither packet sizes -system.physmem.rdQLenPdf::0 271 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 137 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::2 54 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 274 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 145 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::2 45 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see @@ -164,262 +164,262 @@ system.physmem.wrQLenPdf::29 0 # Wh system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see -system.physmem.totQLat 3361480 # Total cycles spent in queuing delays -system.physmem.totMemAccLat 13231480 # Sum of mem lat for all requests -system.physmem.totBusLat 1932000 # Total cycles spent in databus access -system.physmem.totBankLat 7938000 # Total cycles spent in bank access -system.physmem.avgQLat 6959.59 # Average queueing delay per request -system.physmem.avgBankLat 16434.78 # Average bank access latency per request +system.physmem.totQLat 2488982 # Total cycles spent in queuing delays +system.physmem.totMemAccLat 12396982 # Sum of mem lat for all requests +system.physmem.totBusLat 1928000 # Total cycles spent in databus access +system.physmem.totBankLat 7980000 # Total cycles spent in bank access +system.physmem.avgQLat 5163.86 # Average queueing delay per request +system.physmem.avgBankLat 16556.02 # Average bank access latency per request system.physmem.avgBusLat 4000.00 # Average bus latency per request -system.physmem.avgMemAccLat 27394.37 # Average memory access latency -system.physmem.avgRdBW 1562.91 # Average achieved read bandwidth in MB/s +system.physmem.avgMemAccLat 25719.88 # Average memory access latency +system.physmem.avgRdBW 1316.69 # Average achieved read bandwidth in MB/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s -system.physmem.avgConsumedRdBW 1562.91 # Average consumed read bandwidth in MB/s +system.physmem.avgConsumedRdBW 1316.69 # Average consumed read bandwidth in MB/s system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s -system.physmem.busUtil 9.77 # Data bus utilization in percentage -system.physmem.avgRdQLen 0.67 # Average read queue length over time +system.physmem.busUtil 8.23 # Data bus utilization in percentage +system.physmem.avgRdQLen 0.53 # Average read queue length over time system.physmem.avgWrQLen 0.00 # Average write queue length over time -system.physmem.readRowHits 394 # Number of row buffer hits during reads +system.physmem.readRowHits 393 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 81.57 # Row buffer hit rate for reads +system.physmem.readRowHitRate 81.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 40840.58 # Average gap between requests +system.physmem.avgGap 48497.93 # Average gap between requests system.cpu.workload.num_syscalls 18 # Number of system calls -system.cpu.numCycles 39558 # number of cpu cycles simulated +system.cpu.numCycles 46858 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.BPredUnit.lookups 6961 # Number of BP lookups -system.cpu.BPredUnit.condPredicted 4635 # Number of conditional branches predicted -system.cpu.BPredUnit.condIncorrect 1124 # Number of conditional branches incorrect -system.cpu.BPredUnit.BTBLookups 5126 # Number of BTB lookups -system.cpu.BPredUnit.BTBHits 2626 # Number of BTB hits +system.cpu.BPredUnit.lookups 6941 # Number of BP lookups +system.cpu.BPredUnit.condPredicted 4630 # Number of conditional branches predicted +system.cpu.BPredUnit.condIncorrect 1121 # Number of conditional branches incorrect +system.cpu.BPredUnit.BTBLookups 5115 # Number of BTB lookups +system.cpu.BPredUnit.BTBHits 2636 # Number of BTB hits system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.BPredUnit.usedRAS 443 # Number of times the RAS was used to get a target. +system.cpu.BPredUnit.usedRAS 442 # Number of times the RAS was used to get a target. system.cpu.BPredUnit.RASInCorrect 168 # Number of incorrect RAS predictions. -system.cpu.fetch.icacheStallCycles 11957 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 32537 # Number of instructions fetch has processed -system.cpu.fetch.Branches 6961 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 3069 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 9617 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 3192 # Number of cycles fetch has spent squashing -system.cpu.fetch.BlockedCycles 7429 # Number of cycles fetch has spent blocked +system.cpu.fetch.icacheStallCycles 12393 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 32407 # Number of instructions fetch has processed +system.cpu.fetch.Branches 6941 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 3078 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 9616 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 3187 # Number of cycles fetch has spent squashing +system.cpu.fetch.BlockedCycles 8221 # Number of cycles fetch has spent blocked system.cpu.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 834 # Number of stall cycles due to pending traps -system.cpu.fetch.CacheLines 5561 # Number of cache lines fetched +system.cpu.fetch.PendingTrapStallCycles 943 # Number of stall cycles due to pending traps +system.cpu.fetch.CacheLines 5564 # Number of cache lines fetched system.cpu.fetch.IcacheSquashes 468 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 31813 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.022758 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.197280 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::samples 33142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.977823 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.154937 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 22196 69.77% 69.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 4753 14.94% 84.71% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 498 1.57% 86.28% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 475 1.49% 87.77% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 708 2.23% 89.99% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 718 2.26% 92.25% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 247 0.78% 93.03% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 285 0.90% 93.92% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1933 6.08% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 23526 70.99% 70.99% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 4767 14.38% 85.37% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 497 1.50% 86.87% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 473 1.43% 88.30% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 713 2.15% 90.45% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 723 2.18% 92.63% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 250 0.75% 93.38% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 284 0.86% 94.24% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1909 5.76% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 31813 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.175969 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.822514 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 12679 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 8183 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 8793 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 186 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 1972 # Number of cycles decode is squashing -system.cpu.decode.DecodedInsts 30371 # Number of instructions handled by decode -system.cpu.rename.SquashCycles 1972 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 13365 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 199 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 7520 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 8338 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 419 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 27570 # Number of instructions processed by rename +system.cpu.fetch.rateDist::total 33142 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.148128 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.691600 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 13096 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 9104 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 8780 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 197 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 1965 # Number of cycles decode is squashing +system.cpu.decode.DecodedInsts 30240 # Number of instructions handled by decode +system.cpu.rename.SquashCycles 1965 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 13789 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 355 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 8257 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 8329 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 447 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 27456 # Number of instructions processed by rename system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full -system.cpu.rename.LSQFullEvents 112 # Number of times rename has blocked due to LSQ full -system.cpu.rename.RenamedOperands 24556 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 51144 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 51144 # Number of integer rename lookups +system.cpu.rename.LSQFullEvents 134 # Number of times rename has blocked due to LSQ full +system.cpu.rename.RenamedOperands 24477 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 50943 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 50943 # Number of integer rename lookups system.cpu.rename.CommittedMaps 13819 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 10737 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 10658 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 696 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 697 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 2824 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 3648 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 2459 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 2830 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 3653 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 2437 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 4 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 23227 # Number of instructions added to the IQ (excludes non-spec) -system.cpu.iq.iqNonSpecInstsAdded 659 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 21740 # Number of instructions issued +system.cpu.iq.iqInstsAdded 23144 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqNonSpecInstsAdded 660 # Number of non-speculative instructions added to the IQ +system.cpu.iq.iqInstsIssued 21674 # Number of instructions issued system.cpu.iq.iqSquashedInstsIssued 113 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 8509 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 6060 # Number of squashed operands that are examined and possibly removed from graph -system.cpu.iq.iqSquashedNonSpecRemoved 184 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 31813 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.683368 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.298612 # Number of insts issued each cycle +system.cpu.iq.iqSquashedInstsExamined 8424 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 6018 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqSquashedNonSpecRemoved 185 # Number of squashed non-spec instructions that were removed +system.cpu.iq.issued_per_cycle::samples 33142 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.653974 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.274325 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 22340 70.22% 70.22% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 3583 11.26% 81.49% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 2473 7.77% 89.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 1697 5.33% 94.59% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 903 2.84% 97.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 492 1.55% 98.98% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 244 0.77% 99.75% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 64 0.20% 99.95% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 17 0.05% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 23639 71.33% 71.33% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 3658 11.04% 82.36% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 2441 7.37% 89.73% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 1702 5.14% 94.86% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 894 2.70% 97.56% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 488 1.47% 99.03% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 244 0.74% 99.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 60 0.18% 99.95% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 16 0.05% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 31813 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 33142 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 50 28.09% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.09% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 26 14.61% 42.70% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 102 57.30% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 49 28.16% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.16% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 26 14.94% 43.10% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 99 56.90% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 16052 73.84% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.84% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 3424 15.75% 89.59% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 2264 10.41% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 16000 73.82% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 73.82% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 3426 15.81% 89.63% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 2248 10.37% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 21740 # Type of FU issued -system.cpu.iq.rate 0.549573 # Inst issue rate -system.cpu.iq.fu_busy_cnt 178 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.008188 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 75584 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 32421 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 19938 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 21674 # Type of FU issued +system.cpu.iq.rate 0.462546 # Inst issue rate +system.cpu.iq.fu_busy_cnt 174 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.008028 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 76777 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 32254 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 19887 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 21918 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 21848 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 0 # Number of floating point alu accesses system.cpu.iew.lsq.thread0.forwLoads 26 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1423 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1428 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 27 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 1011 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 989 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.cacheBlocked 33 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 1972 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 103 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 4 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 25068 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 512 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 3648 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 2459 # Number of dispatched store instructions -system.cpu.iew.iewDispNonSpecInsts 659 # Number of dispatched non-speculative instructions +system.cpu.iew.iewSquashCycles 1965 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 238 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 24981 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 536 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 3653 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 2437 # Number of dispatched store instructions +system.cpu.iew.iewDispNonSpecInsts 660 # Number of dispatched non-speculative instructions system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 27 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 296 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 961 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 1257 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 20524 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 3260 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 1216 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 295 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 957 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 1252 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 20477 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 3262 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 1197 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 1182 # number of nop insts executed -system.cpu.iew.exec_refs 5396 # number of memory reference insts executed -system.cpu.iew.exec_branches 4297 # Number of branches executed -system.cpu.iew.exec_stores 2136 # Number of stores executed -system.cpu.iew.exec_rate 0.518833 # Inst execution rate -system.cpu.iew.wb_sent 20197 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 19938 # cumulative count of insts written-back -system.cpu.iew.wb_producers 9248 # num instructions producing a value -system.cpu.iew.wb_consumers 11357 # num instructions consuming a value +system.cpu.iew.exec_nop 1177 # number of nop insts executed +system.cpu.iew.exec_refs 5386 # number of memory reference insts executed +system.cpu.iew.exec_branches 4289 # Number of branches executed +system.cpu.iew.exec_stores 2124 # Number of stores executed +system.cpu.iew.exec_rate 0.437001 # Inst execution rate +system.cpu.iew.wb_sent 20145 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 19887 # cumulative count of insts written-back +system.cpu.iew.wb_producers 9217 # num instructions producing a value +system.cpu.iew.wb_consumers 11299 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.504019 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.814300 # average fanout of values written-back +system.cpu.iew.wb_rate 0.424410 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.815736 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 9816 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 9729 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 475 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 1124 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 29858 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.507804 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.195478 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 1121 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 31194 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.486055 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.173479 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 22523 75.43% 75.43% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 3989 13.36% 88.79% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 1473 4.93% 93.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 787 2.64% 96.36% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 343 1.15% 97.51% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 245 0.82% 98.33% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 323 1.08% 99.41% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 69 0.23% 99.64% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 106 0.36% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 23830 76.39% 76.39% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 4047 12.97% 89.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 1444 4.63% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 788 2.53% 96.52% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 343 1.10% 97.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 244 0.78% 98.40% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 322 1.03% 99.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 69 0.22% 99.66% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 107 0.34% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 29858 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::total 31194 # Number of insts commited each cycle system.cpu.commit.committedInsts 15162 # Number of instructions committed system.cpu.commit.committedOps 15162 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed @@ -430,68 +430,68 @@ system.cpu.commit.branches 3358 # Nu system.cpu.commit.fp_insts 0 # Number of committed floating point instructions. system.cpu.commit.int_insts 12174 # Number of committed integer instructions. system.cpu.commit.function_calls 187 # Number of function calls committed. -system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached +system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits -system.cpu.rob.rob_reads 53907 # The number of ROB reads -system.cpu.rob.rob_writes 51935 # The number of ROB writes -system.cpu.timesIdled 182 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 7745 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.rob.rob_reads 55155 # The number of ROB reads +system.cpu.rob.rob_writes 51753 # The number of ROB writes +system.cpu.timesIdled 205 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 13716 # Total number of cycles that the CPU has spent unscheduled due to idling system.cpu.committedInsts 14436 # Number of Instructions Simulated system.cpu.committedOps 14436 # Number of Ops (including micro ops) Simulated system.cpu.committedInsts_total 14436 # Number of Instructions Simulated -system.cpu.cpi 2.740233 # CPI: Cycles Per Instruction -system.cpu.cpi_total 2.740233 # CPI: Total CPI of All Threads -system.cpu.ipc 0.364933 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.364933 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 32646 # number of integer regfile reads -system.cpu.int_regfile_writes 18155 # number of integer regfile writes -system.cpu.misc_regfile_reads 7050 # number of misc regfile reads +system.cpu.cpi 3.245913 # CPI: Cycles Per Instruction +system.cpu.cpi_total 3.245913 # CPI: Total CPI of All Threads +system.cpu.ipc 0.308080 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.308080 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 32584 # number of integer regfile reads +system.cpu.int_regfile_writes 18115 # number of integer regfile writes +system.cpu.misc_regfile_reads 7035 # number of misc regfile reads system.cpu.misc_regfile_writes 569 # number of misc regfile writes system.cpu.icache.replacements 0 # number of replacements -system.cpu.icache.tagsinuse 200.987114 # Cycle average of tags in use -system.cpu.icache.total_refs 5096 # Total number of references to valid blocks. -system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. -system.cpu.icache.avg_refs 15.032448 # Average number of references to valid blocks. +system.cpu.icache.tagsinuse 194.443697 # Cycle average of tags in use +system.cpu.icache.total_refs 5086 # Total number of references to valid blocks. +system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks. +system.cpu.icache.avg_refs 15.047337 # Average number of references to valid blocks. system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.occ_blocks::cpu.inst 200.987114 # Average occupied blocks per requestor -system.cpu.icache.occ_percent::cpu.inst 0.098138 # Average percentage of cache occupancy -system.cpu.icache.occ_percent::total 0.098138 # Average percentage of cache occupancy -system.cpu.icache.ReadReq_hits::cpu.inst 5096 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 5096 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 5096 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 5096 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 5096 # number of overall hits -system.cpu.icache.overall_hits::total 5096 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 465 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 465 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 465 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 465 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 465 # number of overall misses -system.cpu.icache.overall_misses::total 465 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 14626000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 14626000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 14626000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 14626000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 14626000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 14626000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 5561 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 5561 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 5561 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 5561 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 5561 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 5561 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.083618 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.083618 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.083618 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.083618 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.083618 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.083618 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 31453.763441 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 31453.763441 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 31453.763441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 31453.763441 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 31453.763441 # average overall miss latency +system.cpu.icache.occ_blocks::cpu.inst 194.443697 # Average occupied blocks per requestor +system.cpu.icache.occ_percent::cpu.inst 0.094943 # Average percentage of cache occupancy +system.cpu.icache.occ_percent::total 0.094943 # Average percentage of cache occupancy +system.cpu.icache.ReadReq_hits::cpu.inst 5086 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 5086 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 5086 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 5086 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 5086 # number of overall hits +system.cpu.icache.overall_hits::total 5086 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 478 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 478 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 478 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 478 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 478 # number of overall misses +system.cpu.icache.overall_misses::total 478 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21903000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21903000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21903000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21903000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21903000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21903000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 5564 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 5564 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 5564 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 5564 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 5564 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 5564 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.085909 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.085909 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.085909 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.085909 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.085909 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.085909 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 45822.175732 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 45822.175732 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 45822.175732 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 45822.175732 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 45822.175732 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -500,114 +500,114 @@ system.cpu.icache.avg_blocked_cycles::no_mshrs nan system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 126 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 126 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 126 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 126 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 126 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 126 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11056500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 11056500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11056500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 11056500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11056500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 11056500 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060960 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060960 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060960 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.060960 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060960 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.060960 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 32615.044248 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 32615.044248 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 32615.044248 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 32615.044248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 32615.044248 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 32615.044248 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 140 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 140 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 140 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 140 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 140 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 140 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16530500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 16530500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16530500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 16530500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16530500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 16530500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.060748 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.060748 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.060748 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.060748 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.060748 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.060748 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 48906.804734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 48906.804734 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 48906.804734 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 48906.804734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 48906.804734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 48906.804734 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.dcache.replacements 0 # number of replacements -system.cpu.dcache.tagsinuse 102.726852 # Cycle average of tags in use -system.cpu.dcache.total_refs 4058 # Total number of references to valid blocks. -system.cpu.dcache.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.avg_refs 27.794521 # Average number of references to valid blocks. +system.cpu.dcache.tagsinuse 100.624732 # Cycle average of tags in use +system.cpu.dcache.total_refs 4052 # Total number of references to valid blocks. +system.cpu.dcache.sampled_refs 145 # Sample count of references to valid blocks. +system.cpu.dcache.avg_refs 27.944828 # Average number of references to valid blocks. system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.occ_blocks::cpu.data 102.726852 # Average occupied blocks per requestor -system.cpu.dcache.occ_percent::cpu.data 0.025080 # Average percentage of cache occupancy -system.cpu.dcache.occ_percent::total 0.025080 # Average percentage of cache occupancy -system.cpu.dcache.ReadReq_hits::cpu.data 3017 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 3017 # number of ReadReq hits -system.cpu.dcache.WriteReq_hits::cpu.data 1035 # number of WriteReq hits -system.cpu.dcache.WriteReq_hits::total 1035 # number of WriteReq hits +system.cpu.dcache.occ_blocks::cpu.data 100.624732 # Average occupied blocks per requestor +system.cpu.dcache.occ_percent::cpu.data 0.024567 # Average percentage of cache occupancy +system.cpu.dcache.occ_percent::total 0.024567 # Average percentage of cache occupancy +system.cpu.dcache.ReadReq_hits::cpu.data 3013 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 3013 # number of ReadReq hits +system.cpu.dcache.WriteReq_hits::cpu.data 1033 # number of WriteReq hits +system.cpu.dcache.WriteReq_hits::total 1033 # number of WriteReq hits system.cpu.dcache.SwapReq_hits::cpu.data 6 # number of SwapReq hits system.cpu.dcache.SwapReq_hits::total 6 # number of SwapReq hits -system.cpu.dcache.demand_hits::cpu.data 4052 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 4052 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 4052 # number of overall hits -system.cpu.dcache.overall_hits::total 4052 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 128 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 128 # number of ReadReq misses -system.cpu.dcache.WriteReq_misses::cpu.data 407 # number of WriteReq misses -system.cpu.dcache.WriteReq_misses::total 407 # number of WriteReq misses -system.cpu.dcache.demand_misses::cpu.data 535 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 535 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 535 # number of overall misses -system.cpu.dcache.overall_misses::total 535 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 5512500 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 5512500 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 14390000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 14390000 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 19902500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 19902500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 19902500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 19902500 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 3145 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 3145 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_hits::cpu.data 4046 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 4046 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 4046 # number of overall hits +system.cpu.dcache.overall_hits::total 4046 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 129 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 129 # number of ReadReq misses +system.cpu.dcache.WriteReq_misses::cpu.data 409 # number of WriteReq misses +system.cpu.dcache.WriteReq_misses::total 409 # number of WriteReq misses +system.cpu.dcache.demand_misses::cpu.data 538 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 538 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 538 # number of overall misses +system.cpu.dcache.overall_misses::total 538 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 6836500 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 6836500 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 19507474 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 19507474 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 26343974 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 26343974 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 26343974 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 26343974 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 3142 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 3142 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 1442 # number of WriteReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::cpu.data 6 # number of SwapReq accesses(hits+misses) system.cpu.dcache.SwapReq_accesses::total 6 # number of SwapReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 4587 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 4587 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 4587 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 4587 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040700 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.040700 # miss rate for ReadReq accesses -system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.282247 # miss rate for WriteReq accesses -system.cpu.dcache.WriteReq_miss_rate::total 0.282247 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.116634 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.116634 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.116634 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.116634 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 43066.406250 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 43066.406250 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 35356.265356 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 35356.265356 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 37200.934579 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 37200.934579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 37200.934579 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 37200.934579 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.demand_accesses::cpu.data 4584 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 4584 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 4584 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 4584 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.041057 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.041057 # miss rate for ReadReq accesses +system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.WriteReq_miss_rate::total 0.283634 # miss rate for WriteReq accesses +system.cpu.dcache.demand_miss_rate::cpu.data 0.117365 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.117365 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.117365 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.117365 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52996.124031 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 52996.124031 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 47695.535452 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 47695.535452 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 48966.494424 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 48966.494424 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 48966.494424 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 48966.494424 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 427 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 29 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 14.724138 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 65 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 65 # number of ReadReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::cpu.data 324 # number of WriteReq MSHR hits -system.cpu.dcache.WriteReq_mshr_hits::total 324 # number of WriteReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 389 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 389 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 389 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 389 # number of overall MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 66 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 66 # number of ReadReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::cpu.data 326 # number of WriteReq MSHR hits +system.cpu.dcache.WriteReq_mshr_hits::total 326 # number of WriteReq MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 392 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 392 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 392 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 392 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 63 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 83 # number of WriteReq MSHR misses @@ -616,103 +616,103 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3018500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 3018500 # number of ReadReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3172000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.WriteReq_mshr_miss_latency::total 3172000 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6190500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 6190500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6190500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 6190500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020032 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020032 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3776500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 3776500 # number of ReadReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4497000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.WriteReq_mshr_miss_latency::total 4497000 # number of WriteReq MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8273500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8273500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8273500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8273500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.020051 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.020051 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.057559 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.057559 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031829 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.031829 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031829 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.031829 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 47912.698413 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 47912.698413 # average ReadReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 38216.867470 # average WriteReq mshr miss latency -system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 38216.867470 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42400.684932 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 42400.684932 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42400.684932 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 42400.684932 # average overall mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.031850 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.031850 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.031850 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.031850 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 59944.444444 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 59944.444444 # average ReadReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54180.722892 # average WriteReq mshr miss latency +system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54180.722892 # average WriteReq mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 56667.808219 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 56667.808219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 56667.808219 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 56667.808219 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.replacements 0 # number of replacements -system.cpu.l2cache.tagsinuse 236.256243 # Cycle average of tags in use +system.cpu.l2cache.tagsinuse 229.081422 # Cycle average of tags in use system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. -system.cpu.l2cache.sampled_refs 400 # Sample count of references to valid blocks. -system.cpu.l2cache.avg_refs 0.005000 # Average number of references to valid blocks. +system.cpu.l2cache.sampled_refs 399 # Sample count of references to valid blocks. +system.cpu.l2cache.avg_refs 0.005013 # Average number of references to valid blocks. system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.occ_blocks::cpu.inst 200.252174 # Average occupied blocks per requestor -system.cpu.l2cache.occ_blocks::cpu.data 36.004069 # Average occupied blocks per requestor -system.cpu.l2cache.occ_percent::cpu.inst 0.006111 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::cpu.data 0.001099 # Average percentage of cache occupancy -system.cpu.l2cache.occ_percent::total 0.007210 # Average percentage of cache occupancy +system.cpu.l2cache.occ_blocks::cpu.inst 193.844447 # Average occupied blocks per requestor +system.cpu.l2cache.occ_blocks::cpu.data 35.236975 # Average occupied blocks per requestor +system.cpu.l2cache.occ_percent::cpu.inst 0.005916 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::cpu.data 0.001075 # Average percentage of cache occupancy +system.cpu.l2cache.occ_percent::total 0.006991 # Average percentage of cache occupancy system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits system.cpu.l2cache.overall_hits::total 2 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 337 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::cpu.data 63 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::total 400 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::total 399 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 83 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 83 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::cpu.data 146 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::total 483 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses +system.cpu.l2cache.demand_misses::total 482 # number of demand (read+write) misses +system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 146 # number of overall misses -system.cpu.l2cache.overall_misses::total 483 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 10715500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2955000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 13670500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3088000 # number of ReadExReq miss cycles -system.cpu.l2cache.ReadExReq_miss_latency::total 3088000 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 10715500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 6043000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 16758500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 10715500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 6043000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 16758500 # number of overall miss cycles -system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.overall_misses::total 482 # number of overall misses +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16172000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3755000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 19927000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4413000 # number of ReadExReq miss cycles +system.cpu.l2cache.ReadExReq_miss_latency::total 4413000 # number of ReadExReq miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 16172000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 8168000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 24340000 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 16172000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 8168000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 24340000 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 63 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 402 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 401 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 83 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 83 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 146 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 339 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 484 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 146 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994100 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.994083 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.995025 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.995012 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994100 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.994083 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.995876 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994100 # miss rate for overall accesses +system.cpu.l2cache.demand_miss_rate::total 0.995868 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.994083 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.995876 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 31796.735905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 46904.761905 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 34176.250000 # average ReadReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 37204.819277 # average ReadExReq miss latency -system.cpu.l2cache.ReadExReq_avg_miss_latency::total 37204.819277 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 31796.735905 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 41390.410959 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 34696.687371 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 31796.735905 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 41390.410959 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 34696.687371 # average overall miss latency +system.cpu.l2cache.overall_miss_rate::total 0.995868 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 48130.952381 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59603.174603 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 49942.355890 # average ReadReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 53168.674699 # average ReadExReq miss latency +system.cpu.l2cache.ReadExReq_avg_miss_latency::total 53168.674699 # average ReadExReq miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 48130.952381 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 55945.205479 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 50497.925311 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 48130.952381 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 55945.205479 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 50497.925311 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -721,50 +721,50 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 63 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 400 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 399 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 83 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 83 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.data 146 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 483 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 482 # number of demand (read+write) MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 483 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9509513 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2743056 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12252569 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2822546 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2822546 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9509513 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5565602 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 15075115 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9509513 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5565602 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 15075115 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::total 482 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11943516 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 2975060 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 14918576 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3394062 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3394062 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11943516 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6369122 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 18312638 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11943516 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6369122 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 18312638 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995025 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.995012 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.995876 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994100 # mshr miss rate for overall accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.995868 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.994083 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.995876 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 28218.139466 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 43540.571429 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 30631.422500 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 34006.578313 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 34006.578313 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 28218.139466 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38120.561644 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31211.418219 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 28218.139466 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38120.561644 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31211.418219 # average overall mshr miss latency +system.cpu.l2cache.overall_mshr_miss_rate::total 0.995868 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 35546.178571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 47223.174603 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 37389.914787 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40892.313253 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40892.313253 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 35546.178571 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43624.123288 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 37993.024896 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 35546.178571 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43624.123288 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 37993.024896 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt index a86401b30..e69de29bb 100644 --- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt +++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -1,730 +0,0 @@ - ----------- Begin Simulation Statistics ---------- -sim_seconds 0.000088 # Number of seconds simulated -sim_ticks 87707000 # Number of ticks simulated -final_tick 87707000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) -sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1518076 # Simulator instruction rate (inst/s) -host_op_rate 1518015 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 196560583 # Simulator tick rate (ticks/s) -host_mem_usage 1157868 # Number of bytes of host memory used -host_seconds 0.45 # Real time elapsed on the host -sim_insts 677327 # Number of instructions simulated -sim_ops 677327 # Number of ops (including micro ops) simulated -system.physmem.bytes_read::cpu0.inst 18048 # Number of bytes read from this memory -system.physmem.bytes_read::cpu0.data 10560 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.inst 3968 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.inst 128 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory -system.physmem.bytes_read::total 35776 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu0.inst 18048 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu1.inst 3968 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu2.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::cpu3.inst 128 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 22272 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu0.inst 282 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu0.data 165 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.inst 62 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.inst 2 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory -system.physmem.num_reads::total 559 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu0.inst 205776050 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu0.data 120400880 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.inst 45241543 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1.data 14594046 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.inst 1459405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.inst 1459405 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3.data 9486130 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 407903588 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu0.inst 205776050 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu1.inst 45241543 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu2.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu3.inst 1459405 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 253936402 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu0.inst 205776050 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0.data 120400880 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.inst 45241543 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1.data 14594046 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.inst 1459405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.inst 1459405 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3.data 9486130 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 407903588 # Total bandwidth to/from this memory (bytes/s) -system.cpu0.workload.num_syscalls 89 # Number of system calls -system.cpu0.numCycles 175415 # number of cpu cycles simulated -system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu0.committedInsts 175326 # Number of instructions committed -system.cpu0.committedOps 175326 # Number of ops (including micro ops) committed -system.cpu0.num_int_alu_accesses 120376 # Number of integer alu accesses -system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu0.num_func_calls 390 # number of times a function call or return occured -system.cpu0.num_conditional_control_insts 28824 # number of instructions that are conditional controls -system.cpu0.num_int_insts 120376 # number of integer instructions -system.cpu0.num_fp_insts 0 # number of float instructions -system.cpu0.num_int_register_reads 349286 # number of times the integer registers were read -system.cpu0.num_int_register_writes 121983 # number of times the integer registers were written -system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu0.num_mem_refs 82397 # number of memory refs -system.cpu0.num_load_insts 54591 # Number of load instructions -system.cpu0.num_store_insts 27806 # Number of store instructions -system.cpu0.num_idle_cycles 0 # Number of idle cycles -system.cpu0.num_busy_cycles 175415 # Number of busy cycles -system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu0.idle_fraction 0 # Percentage of idle cycles -system.cpu0.icache.replacements 215 # number of replacements -system.cpu0.icache.tagsinuse 222.772698 # Cycle average of tags in use -system.cpu0.icache.total_refs 174921 # Total number of references to valid blocks. -system.cpu0.icache.sampled_refs 467 # Sample count of references to valid blocks. -system.cpu0.icache.avg_refs 374.563169 # Average number of references to valid blocks. -system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.icache.occ_blocks::cpu0.inst 222.772698 # Average occupied blocks per requestor -system.cpu0.icache.occ_percent::cpu0.inst 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.occ_percent::total 0.435103 # Average percentage of cache occupancy -system.cpu0.icache.ReadReq_hits::cpu0.inst 174921 # number of ReadReq hits -system.cpu0.icache.ReadReq_hits::total 174921 # number of ReadReq hits -system.cpu0.icache.demand_hits::cpu0.inst 174921 # number of demand (read+write) hits -system.cpu0.icache.demand_hits::total 174921 # number of demand (read+write) hits -system.cpu0.icache.overall_hits::cpu0.inst 174921 # number of overall hits -system.cpu0.icache.overall_hits::total 174921 # number of overall hits -system.cpu0.icache.ReadReq_misses::cpu0.inst 467 # number of ReadReq misses -system.cpu0.icache.ReadReq_misses::total 467 # number of ReadReq misses -system.cpu0.icache.demand_misses::cpu0.inst 467 # number of demand (read+write) misses -system.cpu0.icache.demand_misses::total 467 # number of demand (read+write) misses -system.cpu0.icache.overall_misses::cpu0.inst 467 # number of overall misses -system.cpu0.icache.overall_misses::total 467 # number of overall misses -system.cpu0.icache.ReadReq_accesses::cpu0.inst 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.ReadReq_accesses::total 175388 # number of ReadReq accesses(hits+misses) -system.cpu0.icache.demand_accesses::cpu0.inst 175388 # number of demand (read+write) accesses -system.cpu0.icache.demand_accesses::total 175388 # number of demand (read+write) accesses -system.cpu0.icache.overall_accesses::cpu0.inst 175388 # number of overall (read+write) accesses -system.cpu0.icache.overall_accesses::total 175388 # number of overall (read+write) accesses -system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.ReadReq_miss_rate::total 0.002663 # miss rate for ReadReq accesses -system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002663 # miss rate for demand accesses -system.cpu0.icache.demand_miss_rate::total 0.002663 # miss rate for demand accesses -system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002663 # miss rate for overall accesses -system.cpu0.icache.overall_miss_rate::total 0.002663 # miss rate for overall accesses -system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.icache.fast_writes 0 # number of fast writes performed -system.cpu0.icache.cache_copies 0 # number of cache copies performed -system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.dcache.replacements 2 # number of replacements -system.cpu0.dcache.tagsinuse 150.745494 # Cycle average of tags in use -system.cpu0.dcache.total_refs 81883 # Total number of references to valid blocks. -system.cpu0.dcache.sampled_refs 167 # Sample count of references to valid blocks. -system.cpu0.dcache.avg_refs 490.317365 # Average number of references to valid blocks. -system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.dcache.occ_blocks::cpu0.data 150.745494 # Average occupied blocks per requestor -system.cpu0.dcache.occ_percent::cpu0.data 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.occ_percent::total 0.294425 # Average percentage of cache occupancy -system.cpu0.dcache.ReadReq_hits::cpu0.data 54430 # number of ReadReq hits -system.cpu0.dcache.ReadReq_hits::total 54430 # number of ReadReq hits -system.cpu0.dcache.WriteReq_hits::cpu0.data 27578 # number of WriteReq hits -system.cpu0.dcache.WriteReq_hits::total 27578 # number of WriteReq hits -system.cpu0.dcache.SwapReq_hits::cpu0.data 15 # number of SwapReq hits -system.cpu0.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu0.dcache.demand_hits::cpu0.data 82008 # number of demand (read+write) hits -system.cpu0.dcache.demand_hits::total 82008 # number of demand (read+write) hits -system.cpu0.dcache.overall_hits::cpu0.data 82008 # number of overall hits -system.cpu0.dcache.overall_hits::total 82008 # number of overall hits -system.cpu0.dcache.ReadReq_misses::cpu0.data 151 # number of ReadReq misses -system.cpu0.dcache.ReadReq_misses::total 151 # number of ReadReq misses -system.cpu0.dcache.WriteReq_misses::cpu0.data 177 # number of WriteReq misses -system.cpu0.dcache.WriteReq_misses::total 177 # number of WriteReq misses -system.cpu0.dcache.SwapReq_misses::cpu0.data 27 # number of SwapReq misses -system.cpu0.dcache.SwapReq_misses::total 27 # number of SwapReq misses -system.cpu0.dcache.demand_misses::cpu0.data 328 # number of demand (read+write) misses -system.cpu0.dcache.demand_misses::total 328 # number of demand (read+write) misses -system.cpu0.dcache.overall_misses::cpu0.data 328 # number of overall misses -system.cpu0.dcache.overall_misses::total 328 # number of overall misses -system.cpu0.dcache.ReadReq_accesses::cpu0.data 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.ReadReq_accesses::total 54581 # number of ReadReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::cpu0.data 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.WriteReq_accesses::total 27755 # number of WriteReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses) -system.cpu0.dcache.demand_accesses::cpu0.data 82336 # number of demand (read+write) accesses -system.cpu0.dcache.demand_accesses::total 82336 # number of demand (read+write) accesses -system.cpu0.dcache.overall_accesses::cpu0.data 82336 # number of overall (read+write) accesses -system.cpu0.dcache.overall_accesses::total 82336 # number of overall (read+write) accesses -system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.ReadReq_miss_rate::total 0.002767 # miss rate for ReadReq accesses -system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.WriteReq_miss_rate::total 0.006377 # miss rate for WriteReq accesses -system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.SwapReq_miss_rate::total 0.642857 # miss rate for SwapReq accesses -system.cpu0.dcache.demand_miss_rate::cpu0.data 0.003984 # miss rate for demand accesses -system.cpu0.dcache.demand_miss_rate::total 0.003984 # miss rate for demand accesses -system.cpu0.dcache.overall_miss_rate::cpu0.data 0.003984 # miss rate for overall accesses -system.cpu0.dcache.overall_miss_rate::total 0.003984 # miss rate for overall accesses -system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu0.dcache.fast_writes 0 # number of fast writes performed -system.cpu0.dcache.cache_copies 0 # number of cache copies performed -system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks -system.cpu0.dcache.writebacks::total 1 # number of writebacks -system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.numCycles 173295 # number of cpu cycles simulated -system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu1.committedInsts 167398 # Number of instructions committed -system.cpu1.committedOps 167398 # Number of ops (including micro ops) committed -system.cpu1.num_int_alu_accesses 109926 # Number of integer alu accesses -system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu1.num_func_calls 633 # number of times a function call or return occured -system.cpu1.num_conditional_control_insts 32743 # number of instructions that are conditional controls -system.cpu1.num_int_insts 109926 # number of integer instructions -system.cpu1.num_fp_insts 0 # number of float instructions -system.cpu1.num_int_register_reads 270038 # number of times the integer registers were read -system.cpu1.num_int_register_writes 100721 # number of times the integer registers were written -system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu1.num_mem_refs 53394 # number of memory refs -system.cpu1.num_load_insts 40652 # Number of load instructions -system.cpu1.num_store_insts 12742 # Number of store instructions -system.cpu1.num_idle_cycles 7873.724337 # Number of idle cycles -system.cpu1.num_busy_cycles 165421.275663 # Number of busy cycles -system.cpu1.not_idle_fraction 0.954565 # Percentage of non-idle cycles -system.cpu1.idle_fraction 0.045435 # Percentage of idle cycles -system.cpu1.icache.replacements 278 # number of replacements -system.cpu1.icache.tagsinuse 76.751702 # Cycle average of tags in use -system.cpu1.icache.total_refs 167072 # Total number of references to valid blocks. -system.cpu1.icache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu1.icache.avg_refs 466.681564 # Average number of references to valid blocks. -system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.icache.occ_blocks::cpu1.inst 76.751702 # Average occupied blocks per requestor -system.cpu1.icache.occ_percent::cpu1.inst 0.149906 # Average percentage of cache occupancy -system.cpu1.icache.occ_percent::total 0.149906 # Average percentage of cache occupancy -system.cpu1.icache.ReadReq_hits::cpu1.inst 167072 # number of ReadReq hits -system.cpu1.icache.ReadReq_hits::total 167072 # number of ReadReq hits -system.cpu1.icache.demand_hits::cpu1.inst 167072 # number of demand (read+write) hits -system.cpu1.icache.demand_hits::total 167072 # number of demand (read+write) hits -system.cpu1.icache.overall_hits::cpu1.inst 167072 # number of overall hits -system.cpu1.icache.overall_hits::total 167072 # number of overall hits -system.cpu1.icache.ReadReq_misses::cpu1.inst 358 # number of ReadReq misses -system.cpu1.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu1.icache.demand_misses::cpu1.inst 358 # number of demand (read+write) misses -system.cpu1.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu1.icache.overall_misses::cpu1.inst 358 # number of overall misses -system.cpu1.icache.overall_misses::total 358 # number of overall misses -system.cpu1.icache.ReadReq_accesses::cpu1.inst 167430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.ReadReq_accesses::total 167430 # number of ReadReq accesses(hits+misses) -system.cpu1.icache.demand_accesses::cpu1.inst 167430 # number of demand (read+write) accesses -system.cpu1.icache.demand_accesses::total 167430 # number of demand (read+write) accesses -system.cpu1.icache.overall_accesses::cpu1.inst 167430 # number of overall (read+write) accesses -system.cpu1.icache.overall_accesses::total 167430 # number of overall (read+write) accesses -system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.ReadReq_miss_rate::total 0.002138 # miss rate for ReadReq accesses -system.cpu1.icache.demand_miss_rate::cpu1.inst 0.002138 # miss rate for demand accesses -system.cpu1.icache.demand_miss_rate::total 0.002138 # miss rate for demand accesses -system.cpu1.icache.overall_miss_rate::cpu1.inst 0.002138 # miss rate for overall accesses -system.cpu1.icache.overall_miss_rate::total 0.002138 # miss rate for overall accesses -system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.icache.fast_writes 0 # number of fast writes performed -system.cpu1.icache.cache_copies 0 # number of cache copies performed -system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.dcache.replacements 0 # number of replacements -system.cpu1.dcache.tagsinuse 30.316999 # Cycle average of tags in use -system.cpu1.dcache.total_refs 26731 # Total number of references to valid blocks. -system.cpu1.dcache.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu1.dcache.avg_refs 1028.115385 # Average number of references to valid blocks. -system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.dcache.occ_blocks::cpu1.data 30.316999 # Average occupied blocks per requestor -system.cpu1.dcache.occ_percent::cpu1.data 0.059213 # Average percentage of cache occupancy -system.cpu1.dcache.occ_percent::total 0.059213 # Average percentage of cache occupancy -system.cpu1.dcache.ReadReq_hits::cpu1.data 40470 # number of ReadReq hits -system.cpu1.dcache.ReadReq_hits::total 40470 # number of ReadReq hits -system.cpu1.dcache.WriteReq_hits::cpu1.data 12563 # number of WriteReq hits -system.cpu1.dcache.WriteReq_hits::total 12563 # number of WriteReq hits -system.cpu1.dcache.SwapReq_hits::cpu1.data 14 # number of SwapReq hits -system.cpu1.dcache.SwapReq_hits::total 14 # number of SwapReq hits -system.cpu1.dcache.demand_hits::cpu1.data 53033 # number of demand (read+write) hits -system.cpu1.dcache.demand_hits::total 53033 # number of demand (read+write) hits -system.cpu1.dcache.overall_hits::cpu1.data 53033 # number of overall hits -system.cpu1.dcache.overall_hits::total 53033 # number of overall hits -system.cpu1.dcache.ReadReq_misses::cpu1.data 174 # number of ReadReq misses -system.cpu1.dcache.ReadReq_misses::total 174 # number of ReadReq misses -system.cpu1.dcache.WriteReq_misses::cpu1.data 106 # number of WriteReq misses -system.cpu1.dcache.WriteReq_misses::total 106 # number of WriteReq misses -system.cpu1.dcache.SwapReq_misses::cpu1.data 57 # number of SwapReq misses -system.cpu1.dcache.SwapReq_misses::total 57 # number of SwapReq misses -system.cpu1.dcache.demand_misses::cpu1.data 280 # number of demand (read+write) misses -system.cpu1.dcache.demand_misses::total 280 # number of demand (read+write) misses -system.cpu1.dcache.overall_misses::cpu1.data 280 # number of overall misses -system.cpu1.dcache.overall_misses::total 280 # number of overall misses -system.cpu1.dcache.ReadReq_accesses::cpu1.data 40644 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.ReadReq_accesses::total 40644 # number of ReadReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::cpu1.data 12669 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.WriteReq_accesses::total 12669 # number of WriteReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::cpu1.data 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.SwapReq_accesses::total 71 # number of SwapReq accesses(hits+misses) -system.cpu1.dcache.demand_accesses::cpu1.data 53313 # number of demand (read+write) accesses -system.cpu1.dcache.demand_accesses::total 53313 # number of demand (read+write) accesses -system.cpu1.dcache.overall_accesses::cpu1.data 53313 # number of overall (read+write) accesses -system.cpu1.dcache.overall_accesses::total 53313 # number of overall (read+write) accesses -system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.004281 # miss rate for ReadReq accesses -system.cpu1.dcache.ReadReq_miss_rate::total 0.004281 # miss rate for ReadReq accesses -system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.008367 # miss rate for WriteReq accesses -system.cpu1.dcache.WriteReq_miss_rate::total 0.008367 # miss rate for WriteReq accesses -system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.SwapReq_miss_rate::total 0.802817 # miss rate for SwapReq accesses -system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005252 # miss rate for demand accesses -system.cpu1.dcache.demand_miss_rate::total 0.005252 # miss rate for demand accesses -system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005252 # miss rate for overall accesses -system.cpu1.dcache.overall_miss_rate::total 0.005252 # miss rate for overall accesses -system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu1.dcache.fast_writes 0 # number of fast writes performed -system.cpu1.dcache.cache_copies 0 # number of cache copies performed -system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.numCycles 173295 # number of cpu cycles simulated -system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu2.committedInsts 167334 # Number of instructions committed -system.cpu2.committedOps 167334 # Number of ops (including micro ops) committed -system.cpu2.num_int_alu_accesses 113333 # Number of integer alu accesses -system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu2.num_func_calls 633 # number of times a function call or return occured -system.cpu2.num_conditional_control_insts 31007 # number of instructions that are conditional controls -system.cpu2.num_int_insts 113333 # number of integer instructions -system.cpu2.num_fp_insts 0 # number of float instructions -system.cpu2.num_int_register_reads 290613 # number of times the integer registers were read -system.cpu2.num_int_register_writes 109308 # number of times the integer registers were written -system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu2.num_mem_refs 58537 # number of memory refs -system.cpu2.num_load_insts 42362 # Number of load instructions -system.cpu2.num_store_insts 16175 # Number of store instructions -system.cpu2.num_idle_cycles 7936.951217 # Number of idle cycles -system.cpu2.num_busy_cycles 165358.048783 # Number of busy cycles -system.cpu2.not_idle_fraction 0.954200 # Percentage of non-idle cycles -system.cpu2.idle_fraction 0.045800 # Percentage of idle cycles -system.cpu2.icache.replacements 278 # number of replacements -system.cpu2.icache.tagsinuse 74.781015 # Cycle average of tags in use -system.cpu2.icache.total_refs 167008 # Total number of references to valid blocks. -system.cpu2.icache.sampled_refs 358 # Sample count of references to valid blocks. -system.cpu2.icache.avg_refs 466.502793 # Average number of references to valid blocks. -system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.icache.occ_blocks::cpu2.inst 74.781015 # Average occupied blocks per requestor -system.cpu2.icache.occ_percent::cpu2.inst 0.146057 # Average percentage of cache occupancy -system.cpu2.icache.occ_percent::total 0.146057 # Average percentage of cache occupancy -system.cpu2.icache.ReadReq_hits::cpu2.inst 167008 # number of ReadReq hits -system.cpu2.icache.ReadReq_hits::total 167008 # number of ReadReq hits -system.cpu2.icache.demand_hits::cpu2.inst 167008 # number of demand (read+write) hits -system.cpu2.icache.demand_hits::total 167008 # number of demand (read+write) hits -system.cpu2.icache.overall_hits::cpu2.inst 167008 # number of overall hits -system.cpu2.icache.overall_hits::total 167008 # number of overall hits -system.cpu2.icache.ReadReq_misses::cpu2.inst 358 # number of ReadReq misses -system.cpu2.icache.ReadReq_misses::total 358 # number of ReadReq misses -system.cpu2.icache.demand_misses::cpu2.inst 358 # number of demand (read+write) misses -system.cpu2.icache.demand_misses::total 358 # number of demand (read+write) misses -system.cpu2.icache.overall_misses::cpu2.inst 358 # number of overall misses -system.cpu2.icache.overall_misses::total 358 # number of overall misses -system.cpu2.icache.ReadReq_accesses::cpu2.inst 167366 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.ReadReq_accesses::total 167366 # number of ReadReq accesses(hits+misses) -system.cpu2.icache.demand_accesses::cpu2.inst 167366 # number of demand (read+write) accesses -system.cpu2.icache.demand_accesses::total 167366 # number of demand (read+write) accesses -system.cpu2.icache.overall_accesses::cpu2.inst 167366 # number of overall (read+write) accesses -system.cpu2.icache.overall_accesses::total 167366 # number of overall (read+write) accesses -system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.ReadReq_miss_rate::total 0.002139 # miss rate for ReadReq accesses -system.cpu2.icache.demand_miss_rate::cpu2.inst 0.002139 # miss rate for demand accesses -system.cpu2.icache.demand_miss_rate::total 0.002139 # miss rate for demand accesses -system.cpu2.icache.overall_miss_rate::cpu2.inst 0.002139 # miss rate for overall accesses -system.cpu2.icache.overall_miss_rate::total 0.002139 # miss rate for overall accesses -system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.icache.fast_writes 0 # number of fast writes performed -system.cpu2.icache.cache_copies 0 # number of cache copies performed -system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.dcache.replacements 0 # number of replacements -system.cpu2.dcache.tagsinuse 29.605505 # Cycle average of tags in use -system.cpu2.dcache.total_refs 33613 # Total number of references to valid blocks. -system.cpu2.dcache.sampled_refs 26 # Sample count of references to valid blocks. -system.cpu2.dcache.avg_refs 1292.807692 # Average number of references to valid blocks. -system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.dcache.occ_blocks::cpu2.data 29.605505 # Average occupied blocks per requestor -system.cpu2.dcache.occ_percent::cpu2.data 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.occ_percent::total 0.057823 # Average percentage of cache occupancy -system.cpu2.dcache.ReadReq_hits::cpu2.data 42194 # number of ReadReq hits -system.cpu2.dcache.ReadReq_hits::total 42194 # number of ReadReq hits -system.cpu2.dcache.WriteReq_hits::cpu2.data 15998 # number of WriteReq hits -system.cpu2.dcache.WriteReq_hits::total 15998 # number of WriteReq hits -system.cpu2.dcache.SwapReq_hits::cpu2.data 11 # number of SwapReq hits -system.cpu2.dcache.SwapReq_hits::total 11 # number of SwapReq hits -system.cpu2.dcache.demand_hits::cpu2.data 58192 # number of demand (read+write) hits -system.cpu2.dcache.demand_hits::total 58192 # number of demand (read+write) hits -system.cpu2.dcache.overall_hits::cpu2.data 58192 # number of overall hits -system.cpu2.dcache.overall_hits::total 58192 # number of overall hits -system.cpu2.dcache.ReadReq_misses::cpu2.data 160 # number of ReadReq misses -system.cpu2.dcache.ReadReq_misses::total 160 # number of ReadReq misses -system.cpu2.dcache.WriteReq_misses::cpu2.data 109 # number of WriteReq misses -system.cpu2.dcache.WriteReq_misses::total 109 # number of WriteReq misses -system.cpu2.dcache.SwapReq_misses::cpu2.data 55 # number of SwapReq misses -system.cpu2.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu2.dcache.demand_misses::cpu2.data 269 # number of demand (read+write) misses -system.cpu2.dcache.demand_misses::total 269 # number of demand (read+write) misses -system.cpu2.dcache.overall_misses::cpu2.data 269 # number of overall misses -system.cpu2.dcache.overall_misses::total 269 # number of overall misses -system.cpu2.dcache.ReadReq_accesses::cpu2.data 42354 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.ReadReq_accesses::total 42354 # number of ReadReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::cpu2.data 16107 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.WriteReq_accesses::total 16107 # number of WriteReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::cpu2.data 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.SwapReq_accesses::total 66 # number of SwapReq accesses(hits+misses) -system.cpu2.dcache.demand_accesses::cpu2.data 58461 # number of demand (read+write) accesses -system.cpu2.dcache.demand_accesses::total 58461 # number of demand (read+write) accesses -system.cpu2.dcache.overall_accesses::cpu2.data 58461 # number of overall (read+write) accesses -system.cpu2.dcache.overall_accesses::total 58461 # number of overall (read+write) accesses -system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.003778 # miss rate for ReadReq accesses -system.cpu2.dcache.ReadReq_miss_rate::total 0.003778 # miss rate for ReadReq accesses -system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.006767 # miss rate for WriteReq accesses -system.cpu2.dcache.WriteReq_miss_rate::total 0.006767 # miss rate for WriteReq accesses -system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.SwapReq_miss_rate::total 0.833333 # miss rate for SwapReq accesses -system.cpu2.dcache.demand_miss_rate::cpu2.data 0.004601 # miss rate for demand accesses -system.cpu2.dcache.demand_miss_rate::total 0.004601 # miss rate for demand accesses -system.cpu2.dcache.overall_miss_rate::cpu2.data 0.004601 # miss rate for overall accesses -system.cpu2.dcache.overall_miss_rate::total 0.004601 # miss rate for overall accesses -system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu2.dcache.fast_writes 0 # number of fast writes performed -system.cpu2.dcache.cache_copies 0 # number of cache copies performed -system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.numCycles 173294 # number of cpu cycles simulated -system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started -system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu3.committedInsts 167269 # Number of instructions committed -system.cpu3.committedOps 167269 # Number of ops (including micro ops) committed -system.cpu3.num_int_alu_accesses 111554 # Number of integer alu accesses -system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses -system.cpu3.num_func_calls 633 # number of times a function call or return occured -system.cpu3.num_conditional_control_insts 31865 # number of instructions that are conditional controls -system.cpu3.num_int_insts 111554 # number of integer instructions -system.cpu3.num_fp_insts 0 # number of float instructions -system.cpu3.num_int_register_reads 280060 # number of times the integer registers were read -system.cpu3.num_int_register_writes 104916 # number of times the integer registers were written -system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read -system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu3.num_mem_refs 55900 # number of memory refs -system.cpu3.num_load_insts 41466 # Number of load instructions -system.cpu3.num_store_insts 14434 # Number of store instructions -system.cpu3.num_idle_cycles 8001.119846 # Number of idle cycles -system.cpu3.num_busy_cycles 165292.880154 # Number of busy cycles -system.cpu3.not_idle_fraction 0.953829 # Percentage of non-idle cycles -system.cpu3.idle_fraction 0.046171 # Percentage of idle cycles -system.cpu3.icache.replacements 279 # number of replacements -system.cpu3.icache.tagsinuse 72.874497 # Cycle average of tags in use -system.cpu3.icache.total_refs 166942 # Total number of references to valid blocks. -system.cpu3.icache.sampled_refs 359 # Sample count of references to valid blocks. -system.cpu3.icache.avg_refs 465.019499 # Average number of references to valid blocks. -system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.icache.occ_blocks::cpu3.inst 72.874497 # Average occupied blocks per requestor -system.cpu3.icache.occ_percent::cpu3.inst 0.142333 # Average percentage of cache occupancy -system.cpu3.icache.occ_percent::total 0.142333 # Average percentage of cache occupancy -system.cpu3.icache.ReadReq_hits::cpu3.inst 166942 # number of ReadReq hits -system.cpu3.icache.ReadReq_hits::total 166942 # number of ReadReq hits -system.cpu3.icache.demand_hits::cpu3.inst 166942 # number of demand (read+write) hits -system.cpu3.icache.demand_hits::total 166942 # number of demand (read+write) hits -system.cpu3.icache.overall_hits::cpu3.inst 166942 # number of overall hits -system.cpu3.icache.overall_hits::total 166942 # number of overall hits -system.cpu3.icache.ReadReq_misses::cpu3.inst 359 # number of ReadReq misses -system.cpu3.icache.ReadReq_misses::total 359 # number of ReadReq misses -system.cpu3.icache.demand_misses::cpu3.inst 359 # number of demand (read+write) misses -system.cpu3.icache.demand_misses::total 359 # number of demand (read+write) misses -system.cpu3.icache.overall_misses::cpu3.inst 359 # number of overall misses -system.cpu3.icache.overall_misses::total 359 # number of overall misses -system.cpu3.icache.ReadReq_accesses::cpu3.inst 167301 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.ReadReq_accesses::total 167301 # number of ReadReq accesses(hits+misses) -system.cpu3.icache.demand_accesses::cpu3.inst 167301 # number of demand (read+write) accesses -system.cpu3.icache.demand_accesses::total 167301 # number of demand (read+write) accesses -system.cpu3.icache.overall_accesses::cpu3.inst 167301 # number of overall (read+write) accesses -system.cpu3.icache.overall_accesses::total 167301 # number of overall (read+write) accesses -system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.ReadReq_miss_rate::total 0.002146 # miss rate for ReadReq accesses -system.cpu3.icache.demand_miss_rate::cpu3.inst 0.002146 # miss rate for demand accesses -system.cpu3.icache.demand_miss_rate::total 0.002146 # miss rate for demand accesses -system.cpu3.icache.overall_miss_rate::cpu3.inst 0.002146 # miss rate for overall accesses -system.cpu3.icache.overall_miss_rate::total 0.002146 # miss rate for overall accesses -system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.icache.fast_writes 0 # number of fast writes performed -system.cpu3.icache.cache_copies 0 # number of cache copies performed -system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.dcache.replacements 0 # number of replacements -system.cpu3.dcache.tagsinuse 28.795404 # Cycle average of tags in use -system.cpu3.dcache.total_refs 30236 # Total number of references to valid blocks. -system.cpu3.dcache.sampled_refs 27 # Sample count of references to valid blocks. -system.cpu3.dcache.avg_refs 1119.851852 # Average number of references to valid blocks. -system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.dcache.occ_blocks::cpu3.data 28.795404 # Average occupied blocks per requestor -system.cpu3.dcache.occ_percent::cpu3.data 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.occ_percent::total 0.056241 # Average percentage of cache occupancy -system.cpu3.dcache.ReadReq_hits::cpu3.data 41301 # number of ReadReq hits -system.cpu3.dcache.ReadReq_hits::total 41301 # number of ReadReq hits -system.cpu3.dcache.WriteReq_hits::cpu3.data 14260 # number of WriteReq hits -system.cpu3.dcache.WriteReq_hits::total 14260 # number of WriteReq hits -system.cpu3.dcache.SwapReq_hits::cpu3.data 15 # number of SwapReq hits -system.cpu3.dcache.SwapReq_hits::total 15 # number of SwapReq hits -system.cpu3.dcache.demand_hits::cpu3.data 55561 # number of demand (read+write) hits -system.cpu3.dcache.demand_hits::total 55561 # number of demand (read+write) hits -system.cpu3.dcache.overall_hits::cpu3.data 55561 # number of overall hits -system.cpu3.dcache.overall_hits::total 55561 # number of overall hits -system.cpu3.dcache.ReadReq_misses::cpu3.data 157 # number of ReadReq misses -system.cpu3.dcache.ReadReq_misses::total 157 # number of ReadReq misses -system.cpu3.dcache.WriteReq_misses::cpu3.data 102 # number of WriteReq misses -system.cpu3.dcache.WriteReq_misses::total 102 # number of WriteReq misses -system.cpu3.dcache.SwapReq_misses::cpu3.data 55 # number of SwapReq misses -system.cpu3.dcache.SwapReq_misses::total 55 # number of SwapReq misses -system.cpu3.dcache.demand_misses::cpu3.data 259 # number of demand (read+write) misses -system.cpu3.dcache.demand_misses::total 259 # number of demand (read+write) misses -system.cpu3.dcache.overall_misses::cpu3.data 259 # number of overall misses -system.cpu3.dcache.overall_misses::total 259 # number of overall misses -system.cpu3.dcache.ReadReq_accesses::cpu3.data 41458 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.ReadReq_accesses::total 41458 # number of ReadReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::cpu3.data 14362 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.WriteReq_accesses::total 14362 # number of WriteReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::cpu3.data 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.SwapReq_accesses::total 70 # number of SwapReq accesses(hits+misses) -system.cpu3.dcache.demand_accesses::cpu3.data 55820 # number of demand (read+write) accesses -system.cpu3.dcache.demand_accesses::total 55820 # number of demand (read+write) accesses -system.cpu3.dcache.overall_accesses::cpu3.data 55820 # number of overall (read+write) accesses -system.cpu3.dcache.overall_accesses::total 55820 # number of overall (read+write) accesses -system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.003787 # miss rate for ReadReq accesses -system.cpu3.dcache.ReadReq_miss_rate::total 0.003787 # miss rate for ReadReq accesses -system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.007102 # miss rate for WriteReq accesses -system.cpu3.dcache.WriteReq_miss_rate::total 0.007102 # miss rate for WriteReq accesses -system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.SwapReq_miss_rate::total 0.785714 # miss rate for SwapReq accesses -system.cpu3.dcache.demand_miss_rate::cpu3.data 0.004640 # miss rate for demand accesses -system.cpu3.dcache.demand_miss_rate::total 0.004640 # miss rate for demand accesses -system.cpu3.dcache.overall_miss_rate::cpu3.data 0.004640 # miss rate for overall accesses -system.cpu3.dcache.overall_miss_rate::total 0.004640 # miss rate for overall accesses -system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked -system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.cpu3.dcache.fast_writes 0 # number of fast writes performed -system.cpu3.dcache.cache_copies 0 # number of cache copies performed -system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.replacements 0 # number of replacements -system.l2c.tagsinuse 366.582542 # Cycle average of tags in use -system.l2c.total_refs 1220 # Total number of references to valid blocks. -system.l2c.sampled_refs 421 # Sample count of references to valid blocks. -system.l2c.avg_refs 2.897862 # Average number of references to valid blocks. -system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 0.966439 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.inst 239.426226 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0.data 55.207595 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.inst 59.511852 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1.data 6.721145 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.inst 1.930661 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2.data 0.935410 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.inst 0.977573 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3.data 0.905640 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.inst 0.003653 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0.data 0.000842 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.inst 0.000908 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1.data 0.000103 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.inst 0.000015 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.005594 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0.inst 185 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.inst 296 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1.data 3 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.inst 356 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.inst 357 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3.data 9 # number of ReadReq hits -system.l2c.ReadReq_hits::total 1220 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits -system.l2c.Writeback_hits::total 1 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits -system.l2c.demand_hits::cpu0.inst 185 # number of demand (read+write) hits -system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.inst 296 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1.data 3 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.inst 356 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.inst 357 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3.data 9 # number of demand (read+write) hits -system.l2c.demand_hits::total 1220 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0.inst 185 # number of overall hits -system.l2c.overall_hits::cpu0.data 5 # number of overall hits -system.l2c.overall_hits::cpu1.inst 296 # number of overall hits -system.l2c.overall_hits::cpu1.data 3 # number of overall hits -system.l2c.overall_hits::cpu2.inst 356 # number of overall hits -system.l2c.overall_hits::cpu2.data 9 # number of overall hits -system.l2c.overall_hits::cpu3.inst 357 # number of overall hits -system.l2c.overall_hits::cpu3.data 9 # number of overall hits -system.l2c.overall_hits::total 1220 # number of overall hits -system.l2c.ReadReq_misses::cpu0.inst 282 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu0.data 66 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.inst 62 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.inst 2 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses -system.l2c.ReadReq_misses::total 423 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0.data 29 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2.data 19 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3.data 18 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 84 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0.data 99 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 136 # number of ReadExReq misses -system.l2c.demand_misses::cpu0.inst 282 # number of demand (read+write) misses -system.l2c.demand_misses::cpu0.data 165 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.inst 62 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.inst 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.inst 2 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses -system.l2c.demand_misses::total 559 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0.inst 282 # number of overall misses -system.l2c.overall_misses::cpu0.data 165 # number of overall misses -system.l2c.overall_misses::cpu1.inst 62 # number of overall misses -system.l2c.overall_misses::cpu1.data 20 # number of overall misses -system.l2c.overall_misses::cpu2.inst 2 # number of overall misses -system.l2c.overall_misses::cpu2.data 13 # number of overall misses -system.l2c.overall_misses::cpu3.inst 2 # number of overall misses -system.l2c.overall_misses::cpu3.data 13 # number of overall misses -system.l2c.overall_misses::total 559 # number of overall misses -system.l2c.ReadReq_accesses::cpu0.inst 467 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu0.data 71 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.inst 358 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.inst 359 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3.data 10 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 1643 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0.data 31 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2.data 19 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3.data 18 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 86 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0.data 99 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 136 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0.inst 467 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu0.data 170 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1.data 23 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.inst 358 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.inst 359 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3.data 22 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 1779 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0.inst 467 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu0.data 170 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1.data 23 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.inst 358 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.inst 359 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3.data 22 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 1779 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0.inst 0.603854 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu0.data 0.929577 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.inst 0.173184 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1.data 0.700000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.inst 0.005587 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.inst 0.005571 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3.data 0.100000 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.257456 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0.data 0.935484 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.976744 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0.inst 0.603854 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu0.data 0.970588 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.inst 0.173184 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1.data 0.869565 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.inst 0.005587 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.inst 0.005571 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3.data 0.590909 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.314221 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0.inst 0.603854 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu0.data 0.970588 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.inst 0.173184 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1.data 0.869565 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.inst 0.005587 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.inst 0.005571 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3.data 0.590909 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.314221 # miss rate for overall accesses -system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked -system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked -system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked -system.l2c.fast_writes 0 # number of fast writes performed -system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate - ----------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt index 9268efa23..cd5a28936 100644 --- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt +++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest/stats.txt @@ -1,634 +1,634 @@ ---------- Begin Simulation Statistics ---------- -sim_seconds 0.000753 # Number of seconds simulated -sim_ticks 753126500 # Number of ticks simulated -final_tick 753126500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_seconds 0.000759 # Number of seconds simulated +sim_ticks 758619000 # Number of ticks simulated +final_tick 758619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_tick_rate 111238456 # Simulator tick rate (ticks/s) -host_mem_usage 391924 # Number of bytes of host memory used -host_seconds 6.77 # Real time elapsed on the host -system.physmem.bytes_read::cpu0 90167 # Number of bytes read from this memory -system.physmem.bytes_read::cpu1 90714 # Number of bytes read from this memory -system.physmem.bytes_read::cpu2 93247 # Number of bytes read from this memory -system.physmem.bytes_read::cpu3 94741 # Number of bytes read from this memory -system.physmem.bytes_read::cpu4 86405 # Number of bytes read from this memory -system.physmem.bytes_read::cpu5 91776 # Number of bytes read from this memory -system.physmem.bytes_read::cpu6 89783 # Number of bytes read from this memory -system.physmem.bytes_read::cpu7 85071 # Number of bytes read from this memory -system.physmem.bytes_read::total 721904 # Number of bytes read from this memory -system.physmem.bytes_written::writebacks 471360 # Number of bytes written to this memory -system.physmem.bytes_written::cpu0 5341 # Number of bytes written to this memory -system.physmem.bytes_written::cpu1 5232 # Number of bytes written to this memory -system.physmem.bytes_written::cpu2 5319 # Number of bytes written to this memory -system.physmem.bytes_written::cpu3 5446 # Number of bytes written to this memory -system.physmem.bytes_written::cpu4 5378 # Number of bytes written to this memory -system.physmem.bytes_written::cpu5 5389 # Number of bytes written to this memory -system.physmem.bytes_written::cpu6 5299 # Number of bytes written to this memory -system.physmem.bytes_written::cpu7 5260 # Number of bytes written to this memory -system.physmem.bytes_written::total 514024 # Number of bytes written to this memory +host_tick_rate 151805189 # Simulator tick rate (ticks/s) +host_mem_usage 345224 # Number of bytes of host memory used +host_seconds 5.00 # Real time elapsed on the host +system.physmem.bytes_read::cpu0 93443 # Number of bytes read from this memory +system.physmem.bytes_read::cpu1 93419 # Number of bytes read from this memory +system.physmem.bytes_read::cpu2 89535 # Number of bytes read from this memory +system.physmem.bytes_read::cpu3 90172 # Number of bytes read from this memory +system.physmem.bytes_read::cpu4 93283 # Number of bytes read from this memory +system.physmem.bytes_read::cpu5 92172 # Number of bytes read from this memory +system.physmem.bytes_read::cpu6 94553 # Number of bytes read from this memory +system.physmem.bytes_read::cpu7 91950 # Number of bytes read from this memory +system.physmem.bytes_read::total 738527 # Number of bytes read from this memory +system.physmem.bytes_written::writebacks 485568 # Number of bytes written to this memory +system.physmem.bytes_written::cpu0 5315 # Number of bytes written to this memory +system.physmem.bytes_written::cpu1 5220 # Number of bytes written to this memory +system.physmem.bytes_written::cpu2 5162 # Number of bytes written to this memory +system.physmem.bytes_written::cpu3 5331 # Number of bytes written to this memory +system.physmem.bytes_written::cpu4 5296 # Number of bytes written to this memory +system.physmem.bytes_written::cpu5 5419 # Number of bytes written to this memory +system.physmem.bytes_written::cpu6 5320 # Number of bytes written to this memory +system.physmem.bytes_written::cpu7 5436 # Number of bytes written to this memory +system.physmem.bytes_written::total 528067 # Number of bytes written to this memory system.physmem.num_reads::cpu0 11039 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu1 11019 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu2 11284 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu3 11077 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu4 10805 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu5 11199 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu6 10970 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu7 11109 # Number of read requests responded to by this memory -system.physmem.num_reads::total 88502 # Number of read requests responded to by this memory -system.physmem.num_writes::writebacks 7365 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu0 5341 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu1 5232 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu2 5319 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu3 5446 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu4 5378 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu5 5389 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu6 5299 # Number of write requests responded to by this memory -system.physmem.num_writes::cpu7 5260 # Number of write requests responded to by this memory -system.physmem.num_writes::total 50029 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu0 119723579 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu1 120449885 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu2 123813197 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu3 125796928 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu4 114728402 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu5 121860006 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu6 119213704 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu7 112957119 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 958542821 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 625870953 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu0 7091770 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu1 6947040 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu2 7062559 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu3 7231189 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu4 7140899 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu5 7155504 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu6 7036003 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu7 6984218 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 682520134 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 625870953 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu0 126815349 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu1 127396925 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu2 130875756 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu3 133028117 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu4 121869301 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu5 129015511 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu6 126249707 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu7 119941338 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1641062956 # Total bandwidth to/from this memory (bytes/s) -system.l2c.replacements 15498 # number of replacements -system.l2c.tagsinuse 803.451409 # Cycle average of tags in use -system.l2c.total_refs 150823 # Total number of references to valid blocks. -system.l2c.sampled_refs 16301 # Sample count of references to valid blocks. -system.l2c.avg_refs 9.252377 # Average number of references to valid blocks. +system.physmem.num_reads::cpu1 11015 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu2 11163 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu3 11170 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu4 11194 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu5 11154 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu6 11141 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu7 11121 # Number of read requests responded to by this memory +system.physmem.num_reads::total 88997 # Number of read requests responded to by this memory +system.physmem.num_writes::writebacks 7587 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu0 5315 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu1 5220 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu2 5162 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu3 5331 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu4 5296 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu5 5419 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu6 5320 # Number of write requests responded to by this memory +system.physmem.num_writes::cpu7 5436 # Number of write requests responded to by this memory +system.physmem.num_writes::total 50086 # Number of write requests responded to by this memory +system.physmem.bw_read::cpu0 123175138 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu1 123143502 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu2 118023672 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu3 118863356 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu4 122964228 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu5 121499725 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu6 124638323 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu7 121207088 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 973515032 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_write::writebacks 640068335 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu0 7006152 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu1 6880924 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu2 6804470 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu3 7027243 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu4 6981106 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu5 7143243 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu6 7012743 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu7 7165652 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 696089869 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 640068335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu0 130181290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu1 130024426 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu2 124828142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu3 125890599 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu4 129945335 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu5 128642968 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu6 131651066 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu7 128372740 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1669604900 # Total bandwidth to/from this memory (bytes/s) +system.l2c.replacements 15559 # number of replacements +system.l2c.tagsinuse 800.707629 # Cycle average of tags in use +system.l2c.total_refs 151038 # Total number of references to valid blocks. +system.l2c.sampled_refs 16357 # Sample count of references to valid blocks. +system.l2c.avg_refs 9.233845 # Average number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.occ_blocks::writebacks 740.977974 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu0 7.980396 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu1 7.585151 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu2 8.326366 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu3 7.791550 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu4 7.277354 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu5 7.805973 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu6 7.956689 # Average occupied blocks per requestor -system.l2c.occ_blocks::cpu7 7.749957 # Average occupied blocks per requestor -system.l2c.occ_percent::writebacks 0.723611 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu0 0.007793 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu1 0.007407 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu2 0.008131 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu3 0.007609 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu4 0.007107 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu5 0.007623 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu6 0.007770 # Average percentage of cache occupancy -system.l2c.occ_percent::cpu7 0.007568 # Average percentage of cache occupancy -system.l2c.occ_percent::total 0.784621 # Average percentage of cache occupancy -system.l2c.ReadReq_hits::cpu0 10718 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu1 10624 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu2 10900 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu3 10791 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu4 10648 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu5 10876 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu6 10598 # number of ReadReq hits -system.l2c.ReadReq_hits::cpu7 10892 # number of ReadReq hits -system.l2c.ReadReq_hits::total 86047 # number of ReadReq hits -system.l2c.Writeback_hits::writebacks 76684 # number of Writeback hits -system.l2c.Writeback_hits::total 76684 # number of Writeback hits -system.l2c.UpgradeReq_hits::cpu0 327 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu1 379 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu2 347 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu3 352 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu4 359 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu5 389 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu6 362 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::cpu7 354 # number of UpgradeReq hits -system.l2c.UpgradeReq_hits::total 2869 # number of UpgradeReq hits -system.l2c.ReadExReq_hits::cpu0 2022 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu1 1993 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu2 2049 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu3 2057 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu4 1996 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu5 2073 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu6 2040 # number of ReadExReq hits -system.l2c.ReadExReq_hits::cpu7 2058 # number of ReadExReq hits -system.l2c.ReadExReq_hits::total 16288 # number of ReadExReq hits -system.l2c.demand_hits::cpu0 12740 # number of demand (read+write) hits -system.l2c.demand_hits::cpu1 12617 # number of demand (read+write) hits -system.l2c.demand_hits::cpu2 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu3 12848 # number of demand (read+write) hits -system.l2c.demand_hits::cpu4 12644 # number of demand (read+write) hits -system.l2c.demand_hits::cpu5 12949 # number of demand (read+write) hits -system.l2c.demand_hits::cpu6 12638 # number of demand (read+write) hits -system.l2c.demand_hits::cpu7 12950 # number of demand (read+write) hits -system.l2c.demand_hits::total 102335 # number of demand (read+write) hits -system.l2c.overall_hits::cpu0 12740 # number of overall hits -system.l2c.overall_hits::cpu1 12617 # number of overall hits -system.l2c.overall_hits::cpu2 12949 # number of overall hits -system.l2c.overall_hits::cpu3 12848 # number of overall hits -system.l2c.overall_hits::cpu4 12644 # number of overall hits -system.l2c.overall_hits::cpu5 12949 # number of overall hits -system.l2c.overall_hits::cpu6 12638 # number of overall hits -system.l2c.overall_hits::cpu7 12950 # number of overall hits -system.l2c.overall_hits::total 102335 # number of overall hits -system.l2c.ReadReq_misses::cpu0 829 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu1 817 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu2 838 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu3 845 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu4 778 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu5 836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu6 836 # number of ReadReq misses -system.l2c.ReadReq_misses::cpu7 763 # number of ReadReq misses -system.l2c.ReadReq_misses::total 6542 # number of ReadReq misses -system.l2c.UpgradeReq_misses::cpu0 1906 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu1 1857 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu2 1865 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu3 1898 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu4 1862 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu5 1875 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu6 1833 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::cpu7 1819 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 14915 # number of UpgradeReq misses -system.l2c.ReadExReq_misses::cpu0 4259 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu1 4029 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu2 4260 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu3 4288 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu4 4087 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu5 4203 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu6 4290 # number of ReadExReq misses -system.l2c.ReadExReq_misses::cpu7 4312 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 33728 # number of ReadExReq misses -system.l2c.demand_misses::cpu0 5088 # number of demand (read+write) misses -system.l2c.demand_misses::cpu1 4846 # number of demand (read+write) misses -system.l2c.demand_misses::cpu2 5098 # number of demand (read+write) misses -system.l2c.demand_misses::cpu3 5133 # number of demand (read+write) misses -system.l2c.demand_misses::cpu4 4865 # number of demand (read+write) misses -system.l2c.demand_misses::cpu5 5039 # number of demand (read+write) misses -system.l2c.demand_misses::cpu6 5126 # number of demand (read+write) misses -system.l2c.demand_misses::cpu7 5075 # number of demand (read+write) misses -system.l2c.demand_misses::total 40270 # number of demand (read+write) misses -system.l2c.overall_misses::cpu0 5088 # number of overall misses -system.l2c.overall_misses::cpu1 4846 # number of overall misses -system.l2c.overall_misses::cpu2 5098 # number of overall misses -system.l2c.overall_misses::cpu3 5133 # number of overall misses -system.l2c.overall_misses::cpu4 4865 # number of overall misses -system.l2c.overall_misses::cpu5 5039 # number of overall misses -system.l2c.overall_misses::cpu6 5126 # number of overall misses -system.l2c.overall_misses::cpu7 5075 # number of overall misses -system.l2c.overall_misses::total 40270 # number of overall misses -system.l2c.ReadReq_miss_latency::cpu0 72627487 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu1 68308474 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu2 75006474 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu3 70533471 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu4 66613974 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu5 67813479 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu6 73978476 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::cpu7 69040973 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_latency::total 563922808 # number of ReadReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu0 54756455 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu1 53319972 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu2 53416959 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu3 57331458 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu4 53682456 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu5 54000963 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu6 51801955 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::cpu7 51941959 # number of UpgradeReq miss cycles -system.l2c.UpgradeReq_miss_latency::total 430252177 # number of UpgradeReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu0 241663349 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu1 231681341 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu2 241380832 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu3 244014828 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu4 232261321 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu5 242148860 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu6 245082818 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::cpu7 243371325 # number of ReadExReq miss cycles -system.l2c.ReadExReq_miss_latency::total 1921604674 # number of ReadExReq miss cycles -system.l2c.demand_miss_latency::cpu0 314290836 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu1 299989815 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu2 316387306 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu3 314548299 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu4 298875295 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu5 309962339 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu6 319061294 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::cpu7 312412298 # number of demand (read+write) miss cycles -system.l2c.demand_miss_latency::total 2485527482 # number of demand (read+write) miss cycles -system.l2c.overall_miss_latency::cpu0 314290836 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu1 299989815 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu2 316387306 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu3 314548299 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu4 298875295 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu5 309962339 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu6 319061294 # number of overall miss cycles -system.l2c.overall_miss_latency::cpu7 312412298 # number of overall miss cycles -system.l2c.overall_miss_latency::total 2485527482 # number of overall miss cycles -system.l2c.ReadReq_accesses::cpu0 11547 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu1 11441 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu2 11738 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu3 11636 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu4 11426 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu5 11712 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu6 11434 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::cpu7 11655 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 92589 # number of ReadReq accesses(hits+misses) -system.l2c.Writeback_accesses::writebacks 76684 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 76684 # number of Writeback accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu0 2233 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu1 2236 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu2 2212 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu3 2250 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu4 2221 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu5 2264 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu6 2195 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::cpu7 2173 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 17784 # number of UpgradeReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu0 6281 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu1 6022 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu2 6309 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu3 6345 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu4 6083 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu5 6276 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu6 6330 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::cpu7 6370 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 50016 # number of ReadExReq accesses(hits+misses) -system.l2c.demand_accesses::cpu0 17828 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu1 17463 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu2 18047 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu3 17981 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu4 17509 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu5 17988 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu6 17764 # number of demand (read+write) accesses -system.l2c.demand_accesses::cpu7 18025 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 142605 # number of demand (read+write) accesses -system.l2c.overall_accesses::cpu0 17828 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu1 17463 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu2 18047 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu3 17981 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu4 17509 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu5 17988 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu6 17764 # number of overall (read+write) accesses -system.l2c.overall_accesses::cpu7 18025 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 142605 # number of overall (read+write) accesses -system.l2c.ReadReq_miss_rate::cpu0 0.071794 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu1 0.071410 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu2 0.071392 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu3 0.072619 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu4 0.068090 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu5 0.071380 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu6 0.073115 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::cpu7 0.065465 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 0.070656 # miss rate for ReadReq accesses -system.l2c.UpgradeReq_miss_rate::cpu0 0.853560 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu1 0.830501 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu2 0.843128 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu3 0.843556 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu4 0.838361 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu5 0.828180 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu6 0.835080 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::cpu7 0.837092 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_miss_rate::total 0.838675 # miss rate for UpgradeReq accesses -system.l2c.ReadExReq_miss_rate::cpu0 0.678077 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu1 0.669047 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu2 0.675226 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu3 0.675808 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu4 0.671872 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu5 0.669694 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu6 0.677725 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::cpu7 0.676923 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_miss_rate::total 0.674344 # miss rate for ReadExReq accesses -system.l2c.demand_miss_rate::cpu0 0.285394 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu1 0.277501 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu2 0.282485 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu3 0.285468 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu4 0.277857 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu5 0.280131 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu6 0.288561 # miss rate for demand accesses -system.l2c.demand_miss_rate::cpu7 0.281553 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 0.282388 # miss rate for demand accesses -system.l2c.overall_miss_rate::cpu0 0.285394 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu1 0.277501 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu2 0.282485 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu3 0.285468 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu4 0.277857 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu5 0.280131 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu6 0.288561 # miss rate for overall accesses -system.l2c.overall_miss_rate::cpu7 0.281553 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 0.282388 # miss rate for overall accesses -system.l2c.ReadReq_avg_miss_latency::cpu0 87608.548854 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu1 83608.903305 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu2 89506.532220 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu3 83471.563314 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu4 85622.074550 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu5 81116.601675 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu6 88491 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::cpu7 90486.203145 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 86200.368083 # average ReadReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu0 28728.465373 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu1 28712.962843 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu2 28641.801072 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu3 30206.247629 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu4 28830.534909 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu5 28800.513600 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu6 28260.750136 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::cpu7 28555.227598 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 28846.944485 # average UpgradeReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu0 56741.805353 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu1 57503.435344 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu2 56662.167136 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu3 56906.443097 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu4 56829.293125 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu5 57613.338092 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu6 57128.862005 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::cpu7 56440.474258 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 56973.573114 # average ReadExReq miss latency -system.l2c.demand_avg_miss_latency::cpu0 61770.997642 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu1 61904.625464 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu2 62061.064339 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu3 61279.621859 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu4 61433.770812 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu5 61512.668982 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu6 62243.717128 # average overall miss latency -system.l2c.demand_avg_miss_latency::cpu7 61559.073498 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 61721.566476 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu0 61770.997642 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu1 61904.625464 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu2 62061.064339 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu3 61279.621859 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu4 61433.770812 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu5 61512.668982 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu6 62243.717128 # average overall miss latency -system.l2c.overall_avg_miss_latency::cpu7 61559.073498 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 61721.566476 # average overall miss latency -system.l2c.blocked_cycles::no_mshrs 205 # number of cycles access was blocked +system.l2c.occ_blocks::writebacks 736.955948 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0 7.896049 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1 7.875266 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2 7.499139 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3 7.819632 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu4 8.127236 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu5 8.346952 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu6 8.379667 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu7 7.807741 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.719684 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0 0.007711 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1 0.007691 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2 0.007323 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3 0.007636 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu4 0.007937 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu5 0.008151 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu6 0.008183 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu7 0.007625 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.781941 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0 10425 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1 10868 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2 10852 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3 10879 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu4 10927 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu5 10945 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu6 10774 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu7 10623 # number of ReadReq hits +system.l2c.ReadReq_hits::total 86293 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 76698 # number of Writeback hits +system.l2c.Writeback_hits::total 76698 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0 362 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu1 360 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu2 388 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu3 372 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu4 362 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu5 365 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu6 360 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::cpu7 369 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2938 # number of UpgradeReq hits +system.l2c.ReadExReq_hits::cpu0 2007 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu1 2095 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu2 1980 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu3 2070 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu4 2022 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu5 2061 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu6 1961 # number of ReadExReq hits +system.l2c.ReadExReq_hits::cpu7 2103 # number of ReadExReq hits +system.l2c.ReadExReq_hits::total 16299 # number of ReadExReq hits +system.l2c.demand_hits::cpu0 12432 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1 12963 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2 12832 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3 12949 # number of demand (read+write) hits +system.l2c.demand_hits::cpu4 12949 # number of demand (read+write) hits +system.l2c.demand_hits::cpu5 13006 # number of demand (read+write) hits +system.l2c.demand_hits::cpu6 12735 # number of demand (read+write) hits +system.l2c.demand_hits::cpu7 12726 # number of demand (read+write) hits +system.l2c.demand_hits::total 102592 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0 12432 # number of overall hits +system.l2c.overall_hits::cpu1 12963 # number of overall hits +system.l2c.overall_hits::cpu2 12832 # number of overall hits +system.l2c.overall_hits::cpu3 12949 # number of overall hits +system.l2c.overall_hits::cpu4 12949 # number of overall hits +system.l2c.overall_hits::cpu5 13006 # number of overall hits +system.l2c.overall_hits::cpu6 12735 # number of overall hits +system.l2c.overall_hits::cpu7 12726 # number of overall hits +system.l2c.overall_hits::total 102592 # number of overall hits +system.l2c.ReadReq_misses::cpu0 852 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1 872 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2 800 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3 819 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu4 876 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu5 871 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu6 869 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu7 848 # number of ReadReq misses +system.l2c.ReadReq_misses::total 6807 # number of ReadReq misses +system.l2c.UpgradeReq_misses::cpu0 1921 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu1 1804 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu2 1923 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu3 1810 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu4 1803 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu5 1840 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu6 1866 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::cpu7 1868 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 14835 # number of UpgradeReq misses +system.l2c.ReadExReq_misses::cpu0 4250 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu1 4373 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu2 4213 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu3 4295 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu4 4281 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu5 4251 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu6 4294 # number of ReadExReq misses +system.l2c.ReadExReq_misses::cpu7 4308 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 34265 # number of ReadExReq misses +system.l2c.demand_misses::cpu0 5102 # number of demand (read+write) misses +system.l2c.demand_misses::cpu1 5245 # number of demand (read+write) misses +system.l2c.demand_misses::cpu2 5013 # number of demand (read+write) misses +system.l2c.demand_misses::cpu3 5114 # number of demand (read+write) misses +system.l2c.demand_misses::cpu4 5157 # number of demand (read+write) misses +system.l2c.demand_misses::cpu5 5122 # number of demand (read+write) misses +system.l2c.demand_misses::cpu6 5163 # number of demand (read+write) misses +system.l2c.demand_misses::cpu7 5156 # number of demand (read+write) misses +system.l2c.demand_misses::total 41072 # number of demand (read+write) misses +system.l2c.overall_misses::cpu0 5102 # number of overall misses +system.l2c.overall_misses::cpu1 5245 # number of overall misses +system.l2c.overall_misses::cpu2 5013 # number of overall misses +system.l2c.overall_misses::cpu3 5114 # number of overall misses +system.l2c.overall_misses::cpu4 5157 # number of overall misses +system.l2c.overall_misses::cpu5 5122 # number of overall misses +system.l2c.overall_misses::cpu6 5163 # number of overall misses +system.l2c.overall_misses::cpu7 5156 # number of overall misses +system.l2c.overall_misses::total 41072 # number of overall misses +system.l2c.ReadReq_miss_latency::cpu0 50457953 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu1 52232944 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu2 47803944 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu3 49059449 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu4 51558931 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu5 52310430 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu6 51043945 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::cpu7 50050941 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_latency::total 404518537 # number of ReadReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu0 54750899 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu1 49983404 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu2 56149902 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu3 53493906 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu4 50935912 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu5 51769923 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu6 53458903 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::cpu7 54181398 # number of UpgradeReq miss cycles +system.l2c.UpgradeReq_miss_latency::total 424724247 # number of UpgradeReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu0 228244633 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu1 234983117 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu2 226986626 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu3 231330611 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu4 230611636 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu5 229068598 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu6 231365116 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::cpu7 232157113 # number of ReadExReq miss cycles +system.l2c.ReadExReq_miss_latency::total 1844747450 # number of ReadExReq miss cycles +system.l2c.demand_miss_latency::cpu0 278702586 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu1 287216061 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu2 274790570 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu3 280390060 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu4 282170567 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu5 281379028 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu6 282409061 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::cpu7 282208054 # number of demand (read+write) miss cycles +system.l2c.demand_miss_latency::total 2249265987 # number of demand (read+write) miss cycles +system.l2c.overall_miss_latency::cpu0 278702586 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu1 287216061 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu2 274790570 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu3 280390060 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu4 282170567 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu5 281379028 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu6 282409061 # number of overall miss cycles +system.l2c.overall_miss_latency::cpu7 282208054 # number of overall miss cycles +system.l2c.overall_miss_latency::total 2249265987 # number of overall miss cycles +system.l2c.ReadReq_accesses::cpu0 11277 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu1 11740 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2 11652 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3 11698 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu4 11803 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu5 11816 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu6 11643 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu7 11471 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 93100 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 76698 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 76698 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0 2283 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu1 2164 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu2 2311 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu3 2182 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu4 2165 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu5 2205 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu6 2226 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu7 2237 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 17773 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0 6257 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1 6468 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2 6193 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu3 6365 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu4 6303 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu5 6312 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu6 6255 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu7 6411 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 50564 # number of ReadExReq accesses(hits+misses) +system.l2c.demand_accesses::cpu0 17534 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu1 18208 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu2 17845 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu3 18063 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu4 18106 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu5 18128 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu6 17898 # number of demand (read+write) accesses +system.l2c.demand_accesses::cpu7 17882 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 143664 # number of demand (read+write) accesses +system.l2c.overall_accesses::cpu0 17534 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1 18208 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2 17845 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3 18063 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu4 18106 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu5 18128 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu6 17898 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu7 17882 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 143664 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0 0.075552 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1 0.074276 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2 0.068658 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3 0.070012 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu4 0.074218 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu5 0.073714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu6 0.074637 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu7 0.073926 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 0.073115 # miss rate for ReadReq accesses +system.l2c.UpgradeReq_miss_rate::cpu0 0.841437 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu1 0.833641 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu2 0.832107 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu3 0.829514 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu4 0.832794 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu5 0.834467 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu6 0.838275 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::cpu7 0.835047 # miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_miss_rate::total 0.834693 # miss rate for UpgradeReq accesses +system.l2c.ReadExReq_miss_rate::cpu0 0.679239 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1 0.676098 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2 0.680284 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3 0.674784 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu4 0.679200 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu5 0.673479 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu6 0.686491 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu7 0.671970 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::total 0.677656 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0 0.290978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1 0.288060 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2 0.280919 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3 0.283120 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu4 0.284823 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu5 0.282546 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu6 0.288468 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu7 0.288335 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 0.285889 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0 0.290978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1 0.288060 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2 0.280919 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3 0.283120 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu4 0.284823 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu5 0.282546 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu6 0.288468 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu7 0.288335 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 0.285889 # miss rate for overall accesses +system.l2c.ReadReq_avg_miss_latency::cpu0 59222.949531 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu1 59900.165138 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu2 59754.930000 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu3 59901.647131 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu4 58857.227169 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu5 60057.898967 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu6 58738.716916 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::cpu7 59022.336085 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 59426.845453 # average ReadReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu0 28501.248829 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu1 27706.986696 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu2 29199.117005 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu3 29554.644199 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu4 28250.644481 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu5 28135.827717 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu6 28648.929796 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::cpu7 29005.031049 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 28629.878463 # average UpgradeReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu0 53704.619529 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu1 53734.991310 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu2 53877.670544 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu3 53860.444936 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu4 53868.637234 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu5 53885.814632 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu6 53881.023754 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::cpu7 53889.766249 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 53837.660878 # average ReadExReq miss latency +system.l2c.demand_avg_miss_latency::cpu0 54626.143865 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu1 54759.973499 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu2 54815.593457 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu3 54827.935080 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu4 54716.030056 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu5 54935.382273 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu6 54698.636645 # average overall miss latency +system.l2c.demand_avg_miss_latency::cpu7 54733.912723 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 54763.975141 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu0 54626.143865 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu1 54759.973499 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu2 54815.593457 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu3 54827.935080 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu4 54716.030056 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu5 54935.382273 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu6 54698.636645 # average overall miss latency +system.l2c.overall_avg_miss_latency::cpu7 54733.912723 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 54763.975141 # average overall miss latency +system.l2c.blocked_cycles::no_mshrs 10793 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.l2c.blocked::no_mshrs 34 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 1480 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.avg_blocked_cycles::no_mshrs 6.029412 # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_mshrs 7.292568 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.l2c.fast_writes 0 # number of fast writes performed system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.writebacks::writebacks 7365 # number of writebacks -system.l2c.writebacks::total 7365 # number of writebacks -system.l2c.ReadReq_mshr_hits::cpu0 12 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu1 6 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu2 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu3 8 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu4 10 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu5 4 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu6 5 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::cpu7 7 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits -system.l2c.UpgradeReq_mshr_hits::cpu0 1 # number of UpgradeReq MSHR hits +system.l2c.writebacks::writebacks 7587 # number of writebacks +system.l2c.writebacks::total 7587 # number of writebacks +system.l2c.ReadReq_mshr_hits::cpu0 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu1 7 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu2 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu3 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu4 5 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu5 6 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu6 10 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::cpu7 9 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_hits::total 60 # number of ReadReq MSHR hits system.l2c.UpgradeReq_mshr_hits::cpu3 1 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_hits::cpu6 1 # number of UpgradeReq MSHR hits system.l2c.UpgradeReq_mshr_hits::total 2 # number of UpgradeReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu0 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu1 2 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu0 7 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu1 6 # number of ReadExReq MSHR hits system.l2c.ReadExReq_mshr_hits::cpu2 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu3 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu4 4 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu5 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu6 2 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::cpu7 3 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_hits::total 22 # number of ReadExReq MSHR hits -system.l2c.demand_mshr_hits::cpu0 16 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu1 8 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu2 7 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu3 11 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu4 14 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu5 6 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::cpu6 7 # number of demand (read+write) MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu3 4 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu4 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu5 6 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu6 3 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::cpu7 1 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_hits::total 32 # number of ReadExReq MSHR hits +system.l2c.demand_mshr_hits::cpu0 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu1 13 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu2 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu3 14 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu4 8 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu5 12 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_hits::cpu6 13 # number of demand (read+write) MSHR hits system.l2c.demand_mshr_hits::cpu7 10 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_hits::total 79 # number of demand (read+write) MSHR hits -system.l2c.overall_mshr_hits::cpu0 16 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu1 8 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu2 7 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu3 11 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu4 14 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu5 6 # number of overall MSHR hits -system.l2c.overall_mshr_hits::cpu6 7 # number of overall MSHR hits +system.l2c.demand_mshr_hits::total 92 # number of demand (read+write) MSHR hits +system.l2c.overall_mshr_hits::cpu0 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu1 13 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu2 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu3 14 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu4 8 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu5 12 # number of overall MSHR hits +system.l2c.overall_mshr_hits::cpu6 13 # number of overall MSHR hits system.l2c.overall_mshr_hits::cpu7 10 # number of overall MSHR hits -system.l2c.overall_mshr_hits::total 79 # number of overall MSHR hits -system.l2c.ReadReq_mshr_misses::cpu0 817 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu1 811 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu2 833 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu3 837 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu4 768 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu5 832 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu6 831 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::cpu7 756 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_misses::total 6485 # number of ReadReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu0 1905 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu1 1857 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu2 1865 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu3 1897 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu4 1862 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu5 1875 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu6 1833 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::cpu7 1819 # number of UpgradeReq MSHR misses -system.l2c.UpgradeReq_mshr_misses::total 14913 # number of UpgradeReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu0 4255 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu1 4027 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu2 4258 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu3 4285 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu4 4083 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu5 4201 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu6 4288 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::cpu7 4309 # number of ReadExReq MSHR misses -system.l2c.ReadExReq_mshr_misses::total 33706 # number of ReadExReq MSHR misses -system.l2c.demand_mshr_misses::cpu0 5072 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu1 4838 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu2 5091 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu3 5122 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu4 4851 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu5 5033 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu6 5119 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::cpu7 5065 # number of demand (read+write) MSHR misses -system.l2c.demand_mshr_misses::total 40191 # number of demand (read+write) MSHR misses -system.l2c.overall_mshr_misses::cpu0 5072 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu1 4838 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu2 5091 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu3 5122 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu4 4851 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu5 5033 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu6 5119 # number of overall MSHR misses -system.l2c.overall_mshr_misses::cpu7 5065 # number of overall MSHR misses -system.l2c.overall_mshr_misses::total 40191 # number of overall MSHR misses -system.l2c.ReadReq_mshr_miss_latency::cpu0 62233988 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu1 58293474 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu2 64591474 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu3 59635471 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu4 57012474 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu5 57238479 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu6 63446976 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::cpu7 59031473 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_latency::total 481483809 # number of ReadReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78461421 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu1 76760937 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu2 77303426 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu3 78549924 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu4 76789922 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu5 77341424 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu6 75742929 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::cpu7 75130926 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_latency::total 616080909 # number of UpgradeReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu0 189411849 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu1 182830341 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu2 189356832 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu3 191977328 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu4 182678822 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu5 190853860 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu6 192540318 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::cpu7 191094825 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_latency::total 1510744175 # number of ReadExReq MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu0 251645837 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu1 241123815 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu2 253948306 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu3 251612799 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu4 239691296 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu5 248092339 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu6 255987294 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::cpu7 250126298 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_latency::total 1992227984 # number of demand (read+write) MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu0 251645837 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu1 241123815 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu2 253948306 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu3 251612799 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu4 239691296 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu5 248092339 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu6 255987294 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::cpu7 250126298 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_latency::total 1992227984 # number of overall MSHR miss cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 411426099 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 414392619 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 419713103 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 412462117 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 406761621 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 421965569 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 407663587 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 419790595 # number of ReadReq MSHR uncacheable cycles -system.l2c.ReadReq_mshr_uncacheable_latency::total 3314175310 # number of ReadReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 231152983 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 227958986 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 229754991 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 235704484 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 234071489 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 230948990 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 231546487 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 229152485 # number of WriteReq MSHR uncacheable cycles -system.l2c.WriteReq_mshr_uncacheable_latency::total 1850290895 # number of WriteReq MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu0 642579082 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu1 642351605 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu2 649468094 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu3 648166601 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu4 640833110 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu5 652914559 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu6 639210074 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::cpu7 648943080 # number of overall MSHR uncacheable cycles -system.l2c.overall_mshr_uncacheable_latency::total 5164466205 # number of overall MSHR uncacheable cycles -system.l2c.ReadReq_mshr_miss_rate::cpu0 0.070754 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu1 0.070885 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu2 0.070966 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu3 0.071932 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu4 0.067215 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu5 0.071038 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu6 0.072678 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::cpu7 0.064865 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 0.070041 # mshr miss rate for ReadReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.853112 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.830501 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.843128 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.843111 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.838361 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.828180 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.835080 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.837092 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 0.838563 # mshr miss rate for UpgradeReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.677440 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.668715 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.674909 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.675335 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.671215 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.669375 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.677409 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.676452 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 0.673904 # mshr miss rate for ReadExReq accesses -system.l2c.demand_mshr_miss_rate::cpu0 0.284496 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu1 0.277043 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu2 0.282097 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu3 0.284856 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu4 0.277058 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu5 0.279798 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu6 0.288167 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::cpu7 0.280999 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 0.281834 # mshr miss rate for demand accesses -system.l2c.overall_mshr_miss_rate::cpu0 0.284496 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu1 0.277043 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu2 0.282097 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu3 0.284856 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu4 0.277058 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu5 0.279798 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu6 0.288167 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::cpu7 0.280999 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 0.281834 # mshr miss rate for overall accesses -system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 76173.791922 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 71878.512947 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 77540.785114 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 71249.069295 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 74234.992188 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 68796.248798 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 76350.151625 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 78083.958995 # average ReadReq mshr miss latency -system.l2c.ReadReq_avg_mshr_miss_latency::total 74245.768543 # average ReadReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41187.097638 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41335.991922 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 41449.558177 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41407.445440 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41240.559613 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41248.759467 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 41321.837971 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41303.422760 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41311.668276 # average UpgradeReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 44515.123149 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 45401.127638 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 44470.838891 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 44802.176896 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 44741.323047 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 45430.578434 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 44902.126399 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 44347.835925 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency::total 44821.223966 # average ReadExReq mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu0 49614.715497 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu1 49839.564903 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu2 49881.812218 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu3 49123.935767 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu4 49410.698000 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu5 49293.133121 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu6 50007.285407 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::cpu7 49383.276999 # average overall mshr miss latency -system.l2c.demand_avg_mshr_miss_latency::total 49569.007589 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu0 49614.715497 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu1 49839.564903 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu2 49881.812218 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu3 49123.935767 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu4 49410.698000 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu5 49293.133121 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu6 50007.285407 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::cpu7 49383.276999 # average overall mshr miss latency -system.l2c.overall_avg_mshr_miss_latency::total 49569.007589 # average overall mshr miss latency +system.l2c.overall_mshr_hits::total 92 # number of overall MSHR hits +system.l2c.ReadReq_mshr_misses::cpu0 845 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu1 865 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu2 794 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu3 809 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu4 871 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu5 865 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu6 859 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::cpu7 839 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_misses::total 6747 # number of ReadReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu0 1921 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu1 1804 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu2 1923 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu3 1809 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu4 1803 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu5 1840 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu6 1865 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::cpu7 1868 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_mshr_misses::total 14833 # number of UpgradeReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu0 4243 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu1 4367 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu2 4211 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu3 4291 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu4 4278 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu5 4245 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu6 4291 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::cpu7 4307 # number of ReadExReq MSHR misses +system.l2c.ReadExReq_mshr_misses::total 34233 # number of ReadExReq MSHR misses +system.l2c.demand_mshr_misses::cpu0 5088 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu1 5232 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu2 5005 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu3 5100 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu4 5149 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu5 5110 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu6 5150 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::cpu7 5146 # number of demand (read+write) MSHR misses +system.l2c.demand_mshr_misses::total 40980 # number of demand (read+write) MSHR misses +system.l2c.overall_mshr_misses::cpu0 5088 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu1 5232 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu2 5005 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu3 5100 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu4 5149 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu5 5110 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu6 5150 # number of overall MSHR misses +system.l2c.overall_mshr_misses::cpu7 5146 # number of overall MSHR misses +system.l2c.overall_mshr_misses::total 40980 # number of overall MSHR misses +system.l2c.ReadReq_mshr_miss_latency::cpu0 39952953 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu1 41536444 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu2 37955945 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu3 38925950 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu4 40835431 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu5 41565931 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu6 40269445 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::cpu7 39637942 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_latency::total 320680041 # number of ReadReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu0 78868808 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu1 73978329 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu2 78794825 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu3 74230834 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu4 74073835 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu5 75455362 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu6 76452812 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::cpu7 76637320 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_latency::total 608492125 # number of UpgradeReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu0 176592133 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu1 181884117 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2 175861127 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3 179102612 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu4 178683137 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu5 177427598 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu6 179259117 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu7 179911613 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 1428721454 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0 216545086 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1 223420561 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2 213817072 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3 218028562 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu4 219518568 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu5 218993529 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu6 219528562 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu7 219549555 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::total 1749401495 # number of demand (read+write) MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0 216545086 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1 223420561 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2 213817072 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3 218028562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu4 219518568 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu5 218993529 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu6 219528562 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu7 219549555 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 1749401495 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu0 402081632 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu1 400575089 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu2 409123618 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu3 408517090 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu4 408283130 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu5 406615614 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu6 405150633 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::cpu7 405778615 # number of ReadReq MSHR uncacheable cycles +system.l2c.ReadReq_mshr_uncacheable_latency::total 3246125421 # number of ReadReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu0 225621486 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu1 222590493 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu2 219789492 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu3 227766486 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu4 225717983 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu5 229461987 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu6 226436485 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::cpu7 231064489 # number of WriteReq MSHR uncacheable cycles +system.l2c.WriteReq_mshr_uncacheable_latency::total 1808448901 # number of WriteReq MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu0 627703118 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu1 623165582 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu2 628913110 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu3 636283576 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu4 634001113 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu5 636077601 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu6 631587118 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::cpu7 636843104 # number of overall MSHR uncacheable cycles +system.l2c.overall_mshr_uncacheable_latency::total 5054574322 # number of overall MSHR uncacheable cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0 0.074931 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1 0.073680 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2 0.068143 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3 0.069157 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu4 0.073795 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu5 0.073206 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu6 0.073778 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu7 0.073141 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 0.072470 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.841437 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.833641 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.832107 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.829056 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.832794 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.834467 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.837826 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.835047 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 0.834581 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0 0.678121 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1 0.675170 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2 0.679961 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3 0.674156 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu4 0.678724 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu5 0.672529 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu6 0.686011 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu7 0.671814 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 0.677023 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 0.285249 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0 0.290179 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1 0.287346 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2 0.280471 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3 0.282345 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu4 0.284381 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu5 0.281884 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu6 0.287742 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu7 0.287775 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 0.285249 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0 47281.601183 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1 48019.010405 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 47803.457179 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3 48116.131026 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu4 46883.388060 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu5 48053.099422 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu6 46879.447031 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu7 47244.269368 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::total 47529.278346 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 41056.120770 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 41007.942905 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40974.947998 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 41034.181316 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 41083.657793 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 41008.348913 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40993.464879 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 41026.402570 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::total 41022.862873 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41619.640113 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41649.671857 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2 41762.319402 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41739.131205 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu4 41767.914212 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41796.842874 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu6 41775.604055 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu7 41771.909218 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::total 41735.210294 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0 42559.961871 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1 42702.706613 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2 42720.693706 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3 42750.698431 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu4 42633.242960 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu5 42855.876517 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu6 42626.905243 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu7 42664.118733 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::total 42689.153123 # average overall mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency @@ -657,114 +657,114 @@ system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.num_reads 98761 # number of read accesses completed -system.cpu0.num_writes 53242 # number of write accesses completed +system.cpu0.num_reads 97622 # number of read accesses completed +system.cpu0.num_writes 53016 # number of write accesses completed system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.l1c.replacements 22316 # number of replacements -system.cpu0.l1c.tagsinuse 389.737995 # Cycle average of tags in use -system.cpu0.l1c.total_refs 13032 # Total number of references to valid blocks. -system.cpu0.l1c.sampled_refs 22724 # Sample count of references to valid blocks. -system.cpu0.l1c.avg_refs 0.573491 # Average number of references to valid blocks. +system.cpu0.l1c.replacements 21387 # number of replacements +system.cpu0.l1c.tagsinuse 393.959213 # Cycle average of tags in use +system.cpu0.l1c.total_refs 13124 # Total number of references to valid blocks. +system.cpu0.l1c.sampled_refs 21798 # Sample count of references to valid blocks. +system.cpu0.l1c.avg_refs 0.602074 # Average number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.occ_blocks::cpu0 389.737995 # Average occupied blocks per requestor -system.cpu0.l1c.occ_percent::cpu0 0.761207 # Average percentage of cache occupancy -system.cpu0.l1c.occ_percent::total 0.761207 # Average percentage of cache occupancy -system.cpu0.l1c.ReadReq_hits::cpu0 8451 # number of ReadReq hits -system.cpu0.l1c.ReadReq_hits::total 8451 # number of ReadReq hits -system.cpu0.l1c.WriteReq_hits::cpu0 1130 # number of WriteReq hits -system.cpu0.l1c.WriteReq_hits::total 1130 # number of WriteReq hits -system.cpu0.l1c.demand_hits::cpu0 9581 # number of demand (read+write) hits -system.cpu0.l1c.demand_hits::total 9581 # number of demand (read+write) hits -system.cpu0.l1c.overall_hits::cpu0 9581 # number of overall hits -system.cpu0.l1c.overall_hits::total 9581 # number of overall hits -system.cpu0.l1c.ReadReq_misses::cpu0 35764 # number of ReadReq misses -system.cpu0.l1c.ReadReq_misses::total 35764 # number of ReadReq misses -system.cpu0.l1c.WriteReq_misses::cpu0 22786 # number of WriteReq misses -system.cpu0.l1c.WriteReq_misses::total 22786 # number of WriteReq misses -system.cpu0.l1c.demand_misses::cpu0 58550 # number of demand (read+write) misses -system.cpu0.l1c.demand_misses::total 58550 # number of demand (read+write) misses -system.cpu0.l1c.overall_misses::cpu0 58550 # number of overall misses -system.cpu0.l1c.overall_misses::total 58550 # number of overall misses -system.cpu0.l1c.ReadReq_miss_latency::cpu0 4595217343 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_latency::total 4595217343 # number of ReadReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::cpu0 3140614125 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_latency::total 3140614125 # number of WriteReq miss cycles -system.cpu0.l1c.demand_miss_latency::cpu0 7735831468 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_latency::total 7735831468 # number of demand (read+write) miss cycles -system.cpu0.l1c.overall_miss_latency::cpu0 7735831468 # number of overall miss cycles -system.cpu0.l1c.overall_miss_latency::total 7735831468 # number of overall miss cycles -system.cpu0.l1c.ReadReq_accesses::cpu0 44215 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_accesses::total 44215 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::cpu0 23916 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_accesses::total 23916 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.demand_accesses::cpu0 68131 # number of demand (read+write) accesses -system.cpu0.l1c.demand_accesses::total 68131 # number of demand (read+write) accesses -system.cpu0.l1c.overall_accesses::cpu0 68131 # number of overall (read+write) accesses -system.cpu0.l1c.overall_accesses::total 68131 # number of overall (read+write) accesses -system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.808866 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_miss_rate::total 0.808866 # miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.952751 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_miss_rate::total 0.952751 # miss rate for WriteReq accesses -system.cpu0.l1c.demand_miss_rate::cpu0 0.859374 # miss rate for demand accesses -system.cpu0.l1c.demand_miss_rate::total 0.859374 # miss rate for demand accesses -system.cpu0.l1c.overall_miss_rate::cpu0 0.859374 # miss rate for overall accesses -system.cpu0.l1c.overall_miss_rate::total 0.859374 # miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 128487.231378 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_miss_latency::total 128487.231378 # average ReadReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 137830.866541 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_miss_latency::total 137830.866541 # average WriteReq miss latency -system.cpu0.l1c.demand_avg_miss_latency::cpu0 132123.509274 # average overall miss latency -system.cpu0.l1c.demand_avg_miss_latency::total 132123.509274 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::cpu0 132123.509274 # average overall miss latency -system.cpu0.l1c.overall_avg_miss_latency::total 132123.509274 # average overall miss latency -system.cpu0.l1c.blocked_cycles::no_mshrs 1390817 # number of cycles access was blocked +system.cpu0.l1c.occ_blocks::cpu0 393.959213 # Average occupied blocks per requestor +system.cpu0.l1c.occ_percent::cpu0 0.769452 # Average percentage of cache occupancy +system.cpu0.l1c.occ_percent::total 0.769452 # Average percentage of cache occupancy +system.cpu0.l1c.ReadReq_hits::cpu0 8513 # number of ReadReq hits +system.cpu0.l1c.ReadReq_hits::total 8513 # number of ReadReq hits +system.cpu0.l1c.WriteReq_hits::cpu0 1098 # number of WriteReq hits +system.cpu0.l1c.WriteReq_hits::total 1098 # number of WriteReq hits +system.cpu0.l1c.demand_hits::cpu0 9611 # number of demand (read+write) hits +system.cpu0.l1c.demand_hits::total 9611 # number of demand (read+write) hits +system.cpu0.l1c.overall_hits::cpu0 9611 # number of overall hits +system.cpu0.l1c.overall_hits::total 9611 # number of overall hits +system.cpu0.l1c.ReadReq_misses::cpu0 35379 # number of ReadReq misses +system.cpu0.l1c.ReadReq_misses::total 35379 # number of ReadReq misses +system.cpu0.l1c.WriteReq_misses::cpu0 22892 # number of WriteReq misses +system.cpu0.l1c.WriteReq_misses::total 22892 # number of WriteReq misses +system.cpu0.l1c.demand_misses::cpu0 58271 # number of demand (read+write) misses +system.cpu0.l1c.demand_misses::total 58271 # number of demand (read+write) misses +system.cpu0.l1c.overall_misses::cpu0 58271 # number of overall misses +system.cpu0.l1c.overall_misses::total 58271 # number of overall misses +system.cpu0.l1c.ReadReq_miss_latency::cpu0 1332854037 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_latency::total 1332854037 # number of ReadReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::cpu0 1090035309 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_latency::total 1090035309 # number of WriteReq miss cycles +system.cpu0.l1c.demand_miss_latency::cpu0 2422889346 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_latency::total 2422889346 # number of demand (read+write) miss cycles +system.cpu0.l1c.overall_miss_latency::cpu0 2422889346 # number of overall miss cycles +system.cpu0.l1c.overall_miss_latency::total 2422889346 # number of overall miss cycles +system.cpu0.l1c.ReadReq_accesses::cpu0 43892 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_accesses::total 43892 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::cpu0 23990 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_accesses::total 23990 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.demand_accesses::cpu0 67882 # number of demand (read+write) accesses +system.cpu0.l1c.demand_accesses::total 67882 # number of demand (read+write) accesses +system.cpu0.l1c.overall_accesses::cpu0 67882 # number of overall (read+write) accesses +system.cpu0.l1c.overall_accesses::total 67882 # number of overall (read+write) accesses +system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.806047 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_miss_rate::total 0.806047 # miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.954231 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_miss_rate::total 0.954231 # miss rate for WriteReq accesses +system.cpu0.l1c.demand_miss_rate::cpu0 0.858416 # miss rate for demand accesses +system.cpu0.l1c.demand_miss_rate::total 0.858416 # miss rate for demand accesses +system.cpu0.l1c.overall_miss_rate::cpu0 0.858416 # miss rate for overall accesses +system.cpu0.l1c.overall_miss_rate::total 0.858416 # miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 37673.592724 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_miss_latency::total 37673.592724 # average ReadReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 47616.429713 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_miss_latency::total 47616.429713 # average WriteReq miss latency +system.cpu0.l1c.demand_avg_miss_latency::cpu0 41579.676786 # average overall miss latency +system.cpu0.l1c.demand_avg_miss_latency::total 41579.676786 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::cpu0 41579.676786 # average overall miss latency +system.cpu0.l1c.overall_avg_miss_latency::total 41579.676786 # average overall miss latency +system.cpu0.l1c.blocked_cycles::no_mshrs 1432667 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked::no_mshrs 63512 # number of cycles access was blocked +system.cpu0.l1c.blocked::no_mshrs 66221 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.898492 # average number of cycles each access was blocked +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 21.634633 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.writebacks::writebacks 9722 # number of writebacks -system.cpu0.l1c.writebacks::total 9722 # number of writebacks -system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35764 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_misses::total 35764 # number of ReadReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22786 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_misses::total 22786 # number of WriteReq MSHR misses -system.cpu0.l1c.demand_mshr_misses::cpu0 58550 # number of demand (read+write) MSHR misses -system.cpu0.l1c.demand_mshr_misses::total 58550 # number of demand (read+write) MSHR misses -system.cpu0.l1c.overall_mshr_misses::cpu0 58550 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_misses::total 58550 # number of overall MSHR misses -system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 4523701343 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_latency::total 4523701343 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 3095050125 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_latency::total 3095050125 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::cpu0 7618751468 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_latency::total 7618751468 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::cpu0 7618751468 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_latency::total 7618751468 # number of overall MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1332951909 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1332951909 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 956448961 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 956448961 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 2289400870 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.overall_mshr_uncacheable_latency::total 2289400870 # number of overall MSHR uncacheable cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.808866 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.808866 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.952751 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.952751 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.859374 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_miss_rate::total 0.859374 # mshr miss rate for demand accesses -system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.859374 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_miss_rate::total 0.859374 # mshr miss rate for overall accesses -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 126487.566911 # average ReadReq mshr miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 126487.566911 # average ReadReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 135831.217634 # average WriteReq mshr miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 135831.217634 # average WriteReq mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 130123.850863 # average overall mshr miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency::total 130123.850863 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 130123.850863 # average overall mshr miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency::total 130123.850863 # average overall mshr miss latency +system.cpu0.l1c.writebacks::writebacks 9284 # number of writebacks +system.cpu0.l1c.writebacks::total 9284 # number of writebacks +system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35379 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_misses::total 35379 # number of ReadReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::cpu0 22892 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_misses::total 22892 # number of WriteReq MSHR misses +system.cpu0.l1c.demand_mshr_misses::cpu0 58271 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_misses::total 58271 # number of demand (read+write) MSHR misses +system.cpu0.l1c.overall_mshr_misses::cpu0 58271 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_misses::total 58271 # number of overall MSHR misses +system.cpu0.l1c.ReadReq_mshr_miss_latency::cpu0 1262100037 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_latency::total 1262100037 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::cpu0 1044251309 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_latency::total 1044251309 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::cpu0 2306351346 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_latency::total 2306351346 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::cpu0 2306351346 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_latency::total 2306351346 # number of overall MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 709848172 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 709848172 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::cpu0 441878494 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency::total 441878494 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 1151726666 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_uncacheable_latency::total 1151726666 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.806047 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.806047 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.954231 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.954231 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.demand_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_miss_rate::total 0.858416 # mshr miss rate for demand accesses +system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858416 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_miss_rate::total 0.858416 # mshr miss rate for overall accesses +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 35673.705786 # average ReadReq mshr miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 35673.705786 # average ReadReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 45616.429713 # average WriteReq mshr miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 45616.429713 # average WriteReq mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 39579.745431 # average overall mshr miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency::total 39579.745431 # average overall mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency @@ -772,114 +772,114 @@ system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.num_reads 96397 # number of read accesses completed -system.cpu1.num_writes 52047 # number of write accesses completed +system.cpu1.num_reads 98743 # number of read accesses completed +system.cpu1.num_writes 53079 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.l1c.replacements 21248 # number of replacements -system.cpu1.l1c.tagsinuse 388.599667 # Cycle average of tags in use -system.cpu1.l1c.total_refs 12959 # Total number of references to valid blocks. -system.cpu1.l1c.sampled_refs 21596 # Sample count of references to valid blocks. -system.cpu1.l1c.avg_refs 0.600065 # Average number of references to valid blocks. +system.cpu1.l1c.replacements 22269 # number of replacements +system.cpu1.l1c.tagsinuse 395.693103 # Cycle average of tags in use +system.cpu1.l1c.total_refs 13156 # Total number of references to valid blocks. +system.cpu1.l1c.sampled_refs 22645 # Sample count of references to valid blocks. +system.cpu1.l1c.avg_refs 0.580967 # Average number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.occ_blocks::cpu1 388.599667 # Average occupied blocks per requestor -system.cpu1.l1c.occ_percent::cpu1 0.758984 # Average percentage of cache occupancy -system.cpu1.l1c.occ_percent::total 0.758984 # Average percentage of cache occupancy -system.cpu1.l1c.ReadReq_hits::cpu1 8521 # number of ReadReq hits -system.cpu1.l1c.ReadReq_hits::total 8521 # number of ReadReq hits -system.cpu1.l1c.WriteReq_hits::cpu1 1037 # number of WriteReq hits -system.cpu1.l1c.WriteReq_hits::total 1037 # number of WriteReq hits -system.cpu1.l1c.demand_hits::cpu1 9558 # number of demand (read+write) hits -system.cpu1.l1c.demand_hits::total 9558 # number of demand (read+write) hits -system.cpu1.l1c.overall_hits::cpu1 9558 # number of overall hits -system.cpu1.l1c.overall_hits::total 9558 # number of overall hits -system.cpu1.l1c.ReadReq_misses::cpu1 34759 # number of ReadReq misses -system.cpu1.l1c.ReadReq_misses::total 34759 # number of ReadReq misses -system.cpu1.l1c.WriteReq_misses::cpu1 22425 # number of WriteReq misses -system.cpu1.l1c.WriteReq_misses::total 22425 # number of WriteReq misses -system.cpu1.l1c.demand_misses::cpu1 57184 # number of demand (read+write) misses -system.cpu1.l1c.demand_misses::total 57184 # number of demand (read+write) misses -system.cpu1.l1c.overall_misses::cpu1 57184 # number of overall misses -system.cpu1.l1c.overall_misses::total 57184 # number of overall misses -system.cpu1.l1c.ReadReq_miss_latency::cpu1 4505667082 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_latency::total 4505667082 # number of ReadReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::cpu1 3159000290 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_latency::total 3159000290 # number of WriteReq miss cycles -system.cpu1.l1c.demand_miss_latency::cpu1 7664667372 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_latency::total 7664667372 # number of demand (read+write) miss cycles -system.cpu1.l1c.overall_miss_latency::cpu1 7664667372 # number of overall miss cycles -system.cpu1.l1c.overall_miss_latency::total 7664667372 # number of overall miss cycles -system.cpu1.l1c.ReadReq_accesses::cpu1 43280 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_accesses::total 43280 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::cpu1 23462 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_accesses::total 23462 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.demand_accesses::cpu1 66742 # number of demand (read+write) accesses -system.cpu1.l1c.demand_accesses::total 66742 # number of demand (read+write) accesses -system.cpu1.l1c.overall_accesses::cpu1 66742 # number of overall (read+write) accesses -system.cpu1.l1c.overall_accesses::total 66742 # number of overall (read+write) accesses -system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.803119 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_miss_rate::total 0.803119 # miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.955801 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_miss_rate::total 0.955801 # miss rate for WriteReq accesses -system.cpu1.l1c.demand_miss_rate::cpu1 0.856792 # miss rate for demand accesses -system.cpu1.l1c.demand_miss_rate::total 0.856792 # miss rate for demand accesses -system.cpu1.l1c.overall_miss_rate::cpu1 0.856792 # miss rate for overall accesses -system.cpu1.l1c.overall_miss_rate::total 0.856792 # miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 129625.912195 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_miss_latency::total 129625.912195 # average ReadReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 140869.578149 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_miss_latency::total 140869.578149 # average WriteReq miss latency -system.cpu1.l1c.demand_avg_miss_latency::cpu1 134035.173685 # average overall miss latency -system.cpu1.l1c.demand_avg_miss_latency::total 134035.173685 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::cpu1 134035.173685 # average overall miss latency -system.cpu1.l1c.overall_avg_miss_latency::total 134035.173685 # average overall miss latency -system.cpu1.l1c.blocked_cycles::no_mshrs 1387894 # number of cycles access was blocked +system.cpu1.l1c.occ_blocks::cpu1 395.693103 # Average occupied blocks per requestor +system.cpu1.l1c.occ_percent::cpu1 0.772838 # Average percentage of cache occupancy +system.cpu1.l1c.occ_percent::total 0.772838 # Average percentage of cache occupancy +system.cpu1.l1c.ReadReq_hits::cpu1 8677 # number of ReadReq hits +system.cpu1.l1c.ReadReq_hits::total 8677 # number of ReadReq hits +system.cpu1.l1c.WriteReq_hits::cpu1 1112 # number of WriteReq hits +system.cpu1.l1c.WriteReq_hits::total 1112 # number of WriteReq hits +system.cpu1.l1c.demand_hits::cpu1 9789 # number of demand (read+write) hits +system.cpu1.l1c.demand_hits::total 9789 # number of demand (read+write) hits +system.cpu1.l1c.overall_hits::cpu1 9789 # number of overall hits +system.cpu1.l1c.overall_hits::total 9789 # number of overall hits +system.cpu1.l1c.ReadReq_misses::cpu1 35979 # number of ReadReq misses +system.cpu1.l1c.ReadReq_misses::total 35979 # number of ReadReq misses +system.cpu1.l1c.WriteReq_misses::cpu1 22841 # number of WriteReq misses +system.cpu1.l1c.WriteReq_misses::total 22841 # number of WriteReq misses +system.cpu1.l1c.demand_misses::cpu1 58820 # number of demand (read+write) misses +system.cpu1.l1c.demand_misses::total 58820 # number of demand (read+write) misses +system.cpu1.l1c.overall_misses::cpu1 58820 # number of overall misses +system.cpu1.l1c.overall_misses::total 58820 # number of overall misses +system.cpu1.l1c.ReadReq_miss_latency::cpu1 1346712982 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_latency::total 1346712982 # number of ReadReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::cpu1 1084415887 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_latency::total 1084415887 # number of WriteReq miss cycles +system.cpu1.l1c.demand_miss_latency::cpu1 2431128869 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_latency::total 2431128869 # number of demand (read+write) miss cycles +system.cpu1.l1c.overall_miss_latency::cpu1 2431128869 # number of overall miss cycles +system.cpu1.l1c.overall_miss_latency::total 2431128869 # number of overall miss cycles +system.cpu1.l1c.ReadReq_accesses::cpu1 44656 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_accesses::total 44656 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::cpu1 23953 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_accesses::total 23953 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.demand_accesses::cpu1 68609 # number of demand (read+write) accesses +system.cpu1.l1c.demand_accesses::total 68609 # number of demand (read+write) accesses +system.cpu1.l1c.overall_accesses::cpu1 68609 # number of overall (read+write) accesses +system.cpu1.l1c.overall_accesses::total 68609 # number of overall (read+write) accesses +system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.805692 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_miss_rate::total 0.805692 # miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953576 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_miss_rate::total 0.953576 # miss rate for WriteReq accesses +system.cpu1.l1c.demand_miss_rate::cpu1 0.857322 # miss rate for demand accesses +system.cpu1.l1c.demand_miss_rate::total 0.857322 # miss rate for demand accesses +system.cpu1.l1c.overall_miss_rate::cpu1 0.857322 # miss rate for overall accesses +system.cpu1.l1c.overall_miss_rate::total 0.857322 # miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 37430.528419 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_miss_latency::total 37430.528419 # average ReadReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 47476.725494 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_miss_latency::total 47476.725494 # average WriteReq miss latency +system.cpu1.l1c.demand_avg_miss_latency::cpu1 41331.670673 # average overall miss latency +system.cpu1.l1c.demand_avg_miss_latency::total 41331.670673 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::cpu1 41331.670673 # average overall miss latency +system.cpu1.l1c.overall_avg_miss_latency::total 41331.670673 # average overall miss latency +system.cpu1.l1c.blocked_cycles::no_mshrs 1432282 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked::no_mshrs 62397 # number of cycles access was blocked +system.cpu1.l1c.blocked::no_mshrs 66708 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 22.242960 # average number of cycles each access was blocked +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 21.470918 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.writebacks::writebacks 9378 # number of writebacks -system.cpu1.l1c.writebacks::total 9378 # number of writebacks -system.cpu1.l1c.ReadReq_mshr_misses::cpu1 34759 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_misses::total 34759 # number of ReadReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22425 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_misses::total 22425 # number of WriteReq MSHR misses -system.cpu1.l1c.demand_mshr_misses::cpu1 57184 # number of demand (read+write) MSHR misses -system.cpu1.l1c.demand_mshr_misses::total 57184 # number of demand (read+write) MSHR misses -system.cpu1.l1c.overall_mshr_misses::cpu1 57184 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_misses::total 57184 # number of overall MSHR misses -system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 4436169082 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_latency::total 4436169082 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 3114154290 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_latency::total 3114154290 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::cpu1 7550323372 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_latency::total 7550323372 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::cpu1 7550323372 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_latency::total 7550323372 # number of overall MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 1384263931 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 1384263931 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 908274469 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 908274469 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 2292538400 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.overall_mshr_uncacheable_latency::total 2292538400 # number of overall MSHR uncacheable cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.803119 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.803119 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.955801 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.955801 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.856792 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_miss_rate::total 0.856792 # mshr miss rate for demand accesses -system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.856792 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_miss_rate::total 0.856792 # mshr miss rate for overall accesses -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 127626.487586 # average ReadReq mshr miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 127626.487586 # average ReadReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 138869.756522 # average WriteReq mshr miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 138869.756522 # average WriteReq mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 132035.593383 # average overall mshr miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency::total 132035.593383 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 132035.593383 # average overall mshr miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency::total 132035.593383 # average overall mshr miss latency +system.cpu1.l1c.writebacks::writebacks 9759 # number of writebacks +system.cpu1.l1c.writebacks::total 9759 # number of writebacks +system.cpu1.l1c.ReadReq_mshr_misses::cpu1 35979 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_misses::total 35979 # number of ReadReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::cpu1 22841 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_misses::total 22841 # number of WriteReq MSHR misses +system.cpu1.l1c.demand_mshr_misses::cpu1 58820 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_misses::total 58820 # number of demand (read+write) MSHR misses +system.cpu1.l1c.overall_mshr_misses::cpu1 58820 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_misses::total 58820 # number of overall MSHR misses +system.cpu1.l1c.ReadReq_mshr_miss_latency::cpu1 1274756982 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_latency::total 1274756982 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::cpu1 1038739887 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_latency::total 1038739887 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::cpu1 2313496869 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_latency::total 2313496869 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::cpu1 2313496869 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_latency::total 2313496869 # number of overall MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::cpu1 702867762 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency::total 702867762 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::cpu1 426288670 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency::total 426288670 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::cpu1 1129156432 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_uncacheable_latency::total 1129156432 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate::cpu1 0.805692 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_miss_rate::total 0.805692 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::cpu1 0.953576 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_miss_rate::total 0.953576 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.demand_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_miss_rate::total 0.857322 # mshr miss rate for demand accesses +system.cpu1.l1c.overall_mshr_miss_rate::cpu1 0.857322 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_miss_rate::total 0.857322 # mshr miss rate for overall accesses +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::cpu1 35430.584007 # average ReadReq mshr miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency::total 35430.584007 # average ReadReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::cpu1 45476.988179 # average WriteReq mshr miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency::total 45476.988179 # average WriteReq mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::cpu1 39331.806681 # average overall mshr miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency::total 39331.806681 # average overall mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu1 inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency @@ -887,114 +887,114 @@ system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::cpu1 inf # average overall mshr uncacheable latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.num_reads 100000 # number of read accesses completed -system.cpu2.num_writes 53454 # number of write accesses completed +system.cpu2.num_reads 98534 # number of read accesses completed +system.cpu2.num_writes 52787 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.l1c.replacements 22874 # number of replacements -system.cpu2.l1c.tagsinuse 393.105668 # Cycle average of tags in use -system.cpu2.l1c.total_refs 13406 # Total number of references to valid blocks. -system.cpu2.l1c.sampled_refs 23291 # Sample count of references to valid blocks. -system.cpu2.l1c.avg_refs 0.575587 # Average number of references to valid blocks. +system.cpu2.l1c.replacements 21873 # number of replacements +system.cpu2.l1c.tagsinuse 394.149978 # Cycle average of tags in use +system.cpu2.l1c.total_refs 13285 # Total number of references to valid blocks. +system.cpu2.l1c.sampled_refs 22270 # Sample count of references to valid blocks. +system.cpu2.l1c.avg_refs 0.596542 # Average number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.occ_blocks::cpu2 393.105668 # Average occupied blocks per requestor -system.cpu2.l1c.occ_percent::cpu2 0.767785 # Average percentage of cache occupancy -system.cpu2.l1c.occ_percent::total 0.767785 # Average percentage of cache occupancy -system.cpu2.l1c.ReadReq_hits::cpu2 8773 # number of ReadReq hits -system.cpu2.l1c.ReadReq_hits::total 8773 # number of ReadReq hits -system.cpu2.l1c.WriteReq_hits::cpu2 1158 # number of WriteReq hits -system.cpu2.l1c.WriteReq_hits::total 1158 # number of WriteReq hits -system.cpu2.l1c.demand_hits::cpu2 9931 # number of demand (read+write) hits -system.cpu2.l1c.demand_hits::total 9931 # number of demand (read+write) hits -system.cpu2.l1c.overall_hits::cpu2 9931 # number of overall hits -system.cpu2.l1c.overall_hits::total 9931 # number of overall hits -system.cpu2.l1c.ReadReq_misses::cpu2 36255 # number of ReadReq misses -system.cpu2.l1c.ReadReq_misses::total 36255 # number of ReadReq misses -system.cpu2.l1c.WriteReq_misses::cpu2 22757 # number of WriteReq misses -system.cpu2.l1c.WriteReq_misses::total 22757 # number of WriteReq misses -system.cpu2.l1c.demand_misses::cpu2 59012 # number of demand (read+write) misses -system.cpu2.l1c.demand_misses::total 59012 # number of demand (read+write) misses -system.cpu2.l1c.overall_misses::cpu2 59012 # number of overall misses -system.cpu2.l1c.overall_misses::total 59012 # number of overall misses -system.cpu2.l1c.ReadReq_miss_latency::cpu2 4588921928 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_latency::total 4588921928 # number of ReadReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::cpu2 3096881635 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_latency::total 3096881635 # number of WriteReq miss cycles -system.cpu2.l1c.demand_miss_latency::cpu2 7685803563 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_latency::total 7685803563 # number of demand (read+write) miss cycles -system.cpu2.l1c.overall_miss_latency::cpu2 7685803563 # number of overall miss cycles -system.cpu2.l1c.overall_miss_latency::total 7685803563 # number of overall miss cycles -system.cpu2.l1c.ReadReq_accesses::cpu2 45028 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_accesses::total 45028 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::cpu2 23915 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_accesses::total 23915 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.demand_accesses::cpu2 68943 # number of demand (read+write) accesses -system.cpu2.l1c.demand_accesses::total 68943 # number of demand (read+write) accesses -system.cpu2.l1c.overall_accesses::cpu2 68943 # number of overall (read+write) accesses -system.cpu2.l1c.overall_accesses::total 68943 # number of overall (read+write) accesses -system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.805166 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_miss_rate::total 0.805166 # miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.951579 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_miss_rate::total 0.951579 # miss rate for WriteReq accesses -system.cpu2.l1c.demand_miss_rate::cpu2 0.855953 # miss rate for demand accesses -system.cpu2.l1c.demand_miss_rate::total 0.855953 # miss rate for demand accesses -system.cpu2.l1c.overall_miss_rate::cpu2 0.855953 # miss rate for overall accesses -system.cpu2.l1c.overall_miss_rate::total 0.855953 # miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 126573.491325 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_miss_latency::total 126573.491325 # average ReadReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 136084.793031 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_miss_latency::total 136084.793031 # average WriteReq miss latency -system.cpu2.l1c.demand_avg_miss_latency::cpu2 130241.367230 # average overall miss latency -system.cpu2.l1c.demand_avg_miss_latency::total 130241.367230 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::cpu2 130241.367230 # average overall miss latency -system.cpu2.l1c.overall_avg_miss_latency::total 130241.367230 # average overall miss latency -system.cpu2.l1c.blocked_cycles::no_mshrs 1394100 # number of cycles access was blocked +system.cpu2.l1c.occ_blocks::cpu2 394.149978 # Average occupied blocks per requestor +system.cpu2.l1c.occ_percent::cpu2 0.769824 # Average percentage of cache occupancy +system.cpu2.l1c.occ_percent::total 0.769824 # Average percentage of cache occupancy +system.cpu2.l1c.ReadReq_hits::cpu2 8620 # number of ReadReq hits +system.cpu2.l1c.ReadReq_hits::total 8620 # number of ReadReq hits +system.cpu2.l1c.WriteReq_hits::cpu2 1112 # number of WriteReq hits +system.cpu2.l1c.WriteReq_hits::total 1112 # number of WriteReq hits +system.cpu2.l1c.demand_hits::cpu2 9732 # number of demand (read+write) hits +system.cpu2.l1c.demand_hits::total 9732 # number of demand (read+write) hits +system.cpu2.l1c.overall_hits::cpu2 9732 # number of overall hits +system.cpu2.l1c.overall_hits::total 9732 # number of overall hits +system.cpu2.l1c.ReadReq_misses::cpu2 35901 # number of ReadReq misses +system.cpu2.l1c.ReadReq_misses::total 35901 # number of ReadReq misses +system.cpu2.l1c.WriteReq_misses::cpu2 22666 # number of WriteReq misses +system.cpu2.l1c.WriteReq_misses::total 22666 # number of WriteReq misses +system.cpu2.l1c.demand_misses::cpu2 58567 # number of demand (read+write) misses +system.cpu2.l1c.demand_misses::total 58567 # number of demand (read+write) misses +system.cpu2.l1c.overall_misses::cpu2 58567 # number of overall misses +system.cpu2.l1c.overall_misses::total 58567 # number of overall misses +system.cpu2.l1c.ReadReq_miss_latency::cpu2 1333102057 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_latency::total 1333102057 # number of ReadReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::cpu2 1080309021 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_latency::total 1080309021 # number of WriteReq miss cycles +system.cpu2.l1c.demand_miss_latency::cpu2 2413411078 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_latency::total 2413411078 # number of demand (read+write) miss cycles +system.cpu2.l1c.overall_miss_latency::cpu2 2413411078 # number of overall miss cycles +system.cpu2.l1c.overall_miss_latency::total 2413411078 # number of overall miss cycles +system.cpu2.l1c.ReadReq_accesses::cpu2 44521 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_accesses::total 44521 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::cpu2 23778 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_accesses::total 23778 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.demand_accesses::cpu2 68299 # number of demand (read+write) accesses +system.cpu2.l1c.demand_accesses::total 68299 # number of demand (read+write) accesses +system.cpu2.l1c.overall_accesses::cpu2 68299 # number of overall (read+write) accesses +system.cpu2.l1c.overall_accesses::total 68299 # number of overall (read+write) accesses +system.cpu2.l1c.ReadReq_miss_rate::cpu2 0.806384 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_miss_rate::total 0.806384 # miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_miss_rate::cpu2 0.953234 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_miss_rate::total 0.953234 # miss rate for WriteReq accesses +system.cpu2.l1c.demand_miss_rate::cpu2 0.857509 # miss rate for demand accesses +system.cpu2.l1c.demand_miss_rate::total 0.857509 # miss rate for demand accesses +system.cpu2.l1c.overall_miss_rate::cpu2 0.857509 # miss rate for overall accesses +system.cpu2.l1c.overall_miss_rate::total 0.857509 # miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_miss_latency::cpu2 37132.727696 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_miss_latency::total 37132.727696 # average ReadReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::cpu2 47662.093929 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_miss_latency::total 47662.093929 # average WriteReq miss latency +system.cpu2.l1c.demand_avg_miss_latency::cpu2 41207.695084 # average overall miss latency +system.cpu2.l1c.demand_avg_miss_latency::total 41207.695084 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::cpu2 41207.695084 # average overall miss latency +system.cpu2.l1c.overall_avg_miss_latency::total 41207.695084 # average overall miss latency +system.cpu2.l1c.blocked_cycles::no_mshrs 1432337 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked::no_mshrs 64388 # number of cycles access was blocked +system.cpu2.l1c.blocked::no_mshrs 66669 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.651550 # average number of cycles each access was blocked +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 21.484303 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.writebacks::writebacks 9909 # number of writebacks -system.cpu2.l1c.writebacks::total 9909 # number of writebacks -system.cpu2.l1c.ReadReq_mshr_misses::cpu2 36255 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_misses::total 36255 # number of ReadReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22757 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_misses::total 22757 # number of WriteReq MSHR misses -system.cpu2.l1c.demand_mshr_misses::cpu2 59012 # number of demand (read+write) MSHR misses -system.cpu2.l1c.demand_mshr_misses::total 59012 # number of demand (read+write) MSHR misses -system.cpu2.l1c.overall_mshr_misses::cpu2 59012 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_misses::total 59012 # number of overall MSHR misses -system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 4516419928 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_latency::total 4516419928 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 3051379635 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_latency::total 3051379635 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::cpu2 7567799563 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_latency::total 7567799563 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::cpu2 7567799563 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_latency::total 7567799563 # number of overall MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 1394051277 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 1394051277 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 902954372 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 902954372 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 2297005649 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.overall_mshr_uncacheable_latency::total 2297005649 # number of overall MSHR uncacheable cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.805166 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.805166 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.951579 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.951579 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.855953 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_miss_rate::total 0.855953 # mshr miss rate for demand accesses -system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.855953 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_miss_rate::total 0.855953 # mshr miss rate for overall accesses -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 124573.711985 # average ReadReq mshr miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 124573.711985 # average ReadReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 134085.320341 # average WriteReq mshr miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 134085.320341 # average WriteReq mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 128241.706145 # average overall mshr miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency::total 128241.706145 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 128241.706145 # average overall mshr miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency::total 128241.706145 # average overall mshr miss latency +system.cpu2.l1c.writebacks::writebacks 9470 # number of writebacks +system.cpu2.l1c.writebacks::total 9470 # number of writebacks +system.cpu2.l1c.ReadReq_mshr_misses::cpu2 35901 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_misses::total 35901 # number of ReadReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::cpu2 22666 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_misses::total 22666 # number of WriteReq MSHR misses +system.cpu2.l1c.demand_mshr_misses::cpu2 58567 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_misses::total 58567 # number of demand (read+write) MSHR misses +system.cpu2.l1c.overall_mshr_misses::cpu2 58567 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_misses::total 58567 # number of overall MSHR misses +system.cpu2.l1c.ReadReq_mshr_miss_latency::cpu2 1261304057 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_latency::total 1261304057 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::cpu2 1034981021 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_latency::total 1034981021 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::cpu2 2296285078 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_latency::total 2296285078 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::cpu2 2296285078 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_latency::total 2296285078 # number of overall MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::cpu2 719957534 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency::total 719957534 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::cpu2 417914602 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency::total 417914602 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::cpu2 1137872136 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_uncacheable_latency::total 1137872136 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate::cpu2 0.806384 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_miss_rate::total 0.806384 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::cpu2 0.953234 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_miss_rate::total 0.953234 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.demand_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_miss_rate::total 0.857509 # mshr miss rate for demand accesses +system.cpu2.l1c.overall_mshr_miss_rate::cpu2 0.857509 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_miss_rate::total 0.857509 # mshr miss rate for overall accesses +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::cpu2 35132.839113 # average ReadReq mshr miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency::total 35132.839113 # average ReadReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::cpu2 45662.270405 # average WriteReq mshr miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency::total 45662.270405 # average WriteReq mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::cpu2 39207.831680 # average overall mshr miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency::total 39207.831680 # average overall mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu2 inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency @@ -1002,114 +1002,114 @@ system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.num_reads 98905 # number of read accesses completed -system.cpu3.num_writes 53947 # number of write accesses completed +system.cpu3.num_reads 99583 # number of read accesses completed +system.cpu3.num_writes 53448 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.l1c.replacements 22486 # number of replacements -system.cpu3.l1c.tagsinuse 391.587362 # Cycle average of tags in use -system.cpu3.l1c.total_refs 13348 # Total number of references to valid blocks. -system.cpu3.l1c.sampled_refs 22882 # Sample count of references to valid blocks. -system.cpu3.l1c.avg_refs 0.583341 # Average number of references to valid blocks. +system.cpu3.l1c.replacements 22221 # number of replacements +system.cpu3.l1c.tagsinuse 395.683952 # Cycle average of tags in use +system.cpu3.l1c.total_refs 13227 # Total number of references to valid blocks. +system.cpu3.l1c.sampled_refs 22614 # Sample count of references to valid blocks. +system.cpu3.l1c.avg_refs 0.584903 # Average number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.occ_blocks::cpu3 391.587362 # Average occupied blocks per requestor -system.cpu3.l1c.occ_percent::cpu3 0.764819 # Average percentage of cache occupancy -system.cpu3.l1c.occ_percent::total 0.764819 # Average percentage of cache occupancy -system.cpu3.l1c.ReadReq_hits::cpu3 8745 # number of ReadReq hits -system.cpu3.l1c.ReadReq_hits::total 8745 # number of ReadReq hits -system.cpu3.l1c.WriteReq_hits::cpu3 1178 # number of WriteReq hits -system.cpu3.l1c.WriteReq_hits::total 1178 # number of WriteReq hits -system.cpu3.l1c.demand_hits::cpu3 9923 # number of demand (read+write) hits -system.cpu3.l1c.demand_hits::total 9923 # number of demand (read+write) hits -system.cpu3.l1c.overall_hits::cpu3 9923 # number of overall hits -system.cpu3.l1c.overall_hits::total 9923 # number of overall hits -system.cpu3.l1c.ReadReq_misses::cpu3 36044 # number of ReadReq misses -system.cpu3.l1c.ReadReq_misses::total 36044 # number of ReadReq misses -system.cpu3.l1c.WriteReq_misses::cpu3 22870 # number of WriteReq misses -system.cpu3.l1c.WriteReq_misses::total 22870 # number of WriteReq misses -system.cpu3.l1c.demand_misses::cpu3 58914 # number of demand (read+write) misses -system.cpu3.l1c.demand_misses::total 58914 # number of demand (read+write) misses -system.cpu3.l1c.overall_misses::cpu3 58914 # number of overall misses -system.cpu3.l1c.overall_misses::total 58914 # number of overall misses -system.cpu3.l1c.ReadReq_miss_latency::cpu3 4630744245 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_latency::total 4630744245 # number of ReadReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::cpu3 3061222174 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_latency::total 3061222174 # number of WriteReq miss cycles -system.cpu3.l1c.demand_miss_latency::cpu3 7691966419 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_latency::total 7691966419 # number of demand (read+write) miss cycles -system.cpu3.l1c.overall_miss_latency::cpu3 7691966419 # number of overall miss cycles -system.cpu3.l1c.overall_miss_latency::total 7691966419 # number of overall miss cycles -system.cpu3.l1c.ReadReq_accesses::cpu3 44789 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_accesses::total 44789 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::cpu3 24048 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_accesses::total 24048 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.demand_accesses::cpu3 68837 # number of demand (read+write) accesses -system.cpu3.l1c.demand_accesses::total 68837 # number of demand (read+write) accesses -system.cpu3.l1c.overall_accesses::cpu3 68837 # number of overall (read+write) accesses -system.cpu3.l1c.overall_accesses::total 68837 # number of overall (read+write) accesses -system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.804751 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_miss_rate::total 0.804751 # miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.951015 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_miss_rate::total 0.951015 # miss rate for WriteReq accesses -system.cpu3.l1c.demand_miss_rate::cpu3 0.855848 # miss rate for demand accesses -system.cpu3.l1c.demand_miss_rate::total 0.855848 # miss rate for demand accesses -system.cpu3.l1c.overall_miss_rate::cpu3 0.855848 # miss rate for overall accesses -system.cpu3.l1c.overall_miss_rate::total 0.855848 # miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 128474.759877 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_miss_latency::total 128474.759877 # average ReadReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 133853.177700 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_miss_latency::total 133853.177700 # average WriteReq miss latency -system.cpu3.l1c.demand_avg_miss_latency::cpu3 130562.623808 # average overall miss latency -system.cpu3.l1c.demand_avg_miss_latency::total 130562.623808 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::cpu3 130562.623808 # average overall miss latency -system.cpu3.l1c.overall_avg_miss_latency::total 130562.623808 # average overall miss latency -system.cpu3.l1c.blocked_cycles::no_mshrs 1375135 # number of cycles access was blocked +system.cpu3.l1c.occ_blocks::cpu3 395.683952 # Average occupied blocks per requestor +system.cpu3.l1c.occ_percent::cpu3 0.772820 # Average percentage of cache occupancy +system.cpu3.l1c.occ_percent::total 0.772820 # Average percentage of cache occupancy +system.cpu3.l1c.ReadReq_hits::cpu3 8699 # number of ReadReq hits +system.cpu3.l1c.ReadReq_hits::total 8699 # number of ReadReq hits +system.cpu3.l1c.WriteReq_hits::cpu3 1092 # number of WriteReq hits +system.cpu3.l1c.WriteReq_hits::total 1092 # number of WriteReq hits +system.cpu3.l1c.demand_hits::cpu3 9791 # number of demand (read+write) hits +system.cpu3.l1c.demand_hits::total 9791 # number of demand (read+write) hits +system.cpu3.l1c.overall_hits::cpu3 9791 # number of overall hits +system.cpu3.l1c.overall_hits::total 9791 # number of overall hits +system.cpu3.l1c.ReadReq_misses::cpu3 35935 # number of ReadReq misses +system.cpu3.l1c.ReadReq_misses::total 35935 # number of ReadReq misses +system.cpu3.l1c.WriteReq_misses::cpu3 23086 # number of WriteReq misses +system.cpu3.l1c.WriteReq_misses::total 23086 # number of WriteReq misses +system.cpu3.l1c.demand_misses::cpu3 59021 # number of demand (read+write) misses +system.cpu3.l1c.demand_misses::total 59021 # number of demand (read+write) misses +system.cpu3.l1c.overall_misses::cpu3 59021 # number of overall misses +system.cpu3.l1c.overall_misses::total 59021 # number of overall misses +system.cpu3.l1c.ReadReq_miss_latency::cpu3 1329205475 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_latency::total 1329205475 # number of ReadReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::cpu3 1090244238 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_latency::total 1090244238 # number of WriteReq miss cycles +system.cpu3.l1c.demand_miss_latency::cpu3 2419449713 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_latency::total 2419449713 # number of demand (read+write) miss cycles +system.cpu3.l1c.overall_miss_latency::cpu3 2419449713 # number of overall miss cycles +system.cpu3.l1c.overall_miss_latency::total 2419449713 # number of overall miss cycles +system.cpu3.l1c.ReadReq_accesses::cpu3 44634 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_accesses::total 44634 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::cpu3 24178 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_accesses::total 24178 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.demand_accesses::cpu3 68812 # number of demand (read+write) accesses +system.cpu3.l1c.demand_accesses::total 68812 # number of demand (read+write) accesses +system.cpu3.l1c.overall_accesses::cpu3 68812 # number of overall (read+write) accesses +system.cpu3.l1c.overall_accesses::total 68812 # number of overall (read+write) accesses +system.cpu3.l1c.ReadReq_miss_rate::cpu3 0.805104 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_miss_rate::total 0.805104 # miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_miss_rate::cpu3 0.954835 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_miss_rate::total 0.954835 # miss rate for WriteReq accesses +system.cpu3.l1c.demand_miss_rate::cpu3 0.857714 # miss rate for demand accesses +system.cpu3.l1c.demand_miss_rate::total 0.857714 # miss rate for demand accesses +system.cpu3.l1c.overall_miss_rate::cpu3 0.857714 # miss rate for overall accesses +system.cpu3.l1c.overall_miss_rate::total 0.857714 # miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_miss_latency::cpu3 36989.160289 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_miss_latency::total 36989.160289 # average ReadReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::cpu3 47225.341679 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_miss_latency::total 47225.341679 # average WriteReq miss latency +system.cpu3.l1c.demand_avg_miss_latency::cpu3 40993.031514 # average overall miss latency +system.cpu3.l1c.demand_avg_miss_latency::total 40993.031514 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::cpu3 40993.031514 # average overall miss latency +system.cpu3.l1c.overall_avg_miss_latency::total 40993.031514 # average overall miss latency +system.cpu3.l1c.blocked_cycles::no_mshrs 1431757 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked::no_mshrs 63801 # number of cycles access was blocked +system.cpu3.l1c.blocked::no_mshrs 67125 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.553502 # average number of cycles each access was blocked +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 21.329713 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.writebacks::writebacks 9848 # number of writebacks -system.cpu3.l1c.writebacks::total 9848 # number of writebacks -system.cpu3.l1c.ReadReq_mshr_misses::cpu3 36044 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_misses::total 36044 # number of ReadReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::cpu3 22870 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_misses::total 22870 # number of WriteReq MSHR misses -system.cpu3.l1c.demand_mshr_misses::cpu3 58914 # number of demand (read+write) MSHR misses -system.cpu3.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses -system.cpu3.l1c.overall_mshr_misses::cpu3 58914 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses -system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 4558664245 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_latency::total 4558664245 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 3015496174 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_latency::total 3015496174 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::cpu3 7574160419 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_latency::total 7574160419 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::cpu3 7574160419 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_latency::total 7574160419 # number of overall MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 1332002539 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 1332002539 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 965663255 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 965663255 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 2297665794 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.overall_mshr_uncacheable_latency::total 2297665794 # number of overall MSHR uncacheable cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.804751 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.804751 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.951015 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.951015 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.855848 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_miss_rate::total 0.855848 # mshr miss rate for demand accesses -system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.855848 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_miss_rate::total 0.855848 # mshr miss rate for overall accesses -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 126474.981828 # average ReadReq mshr miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 126474.981828 # average ReadReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 131853.789856 # average WriteReq mshr miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 131853.789856 # average WriteReq mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 128562.997233 # average overall mshr miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency::total 128562.997233 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 128562.997233 # average overall mshr miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency::total 128562.997233 # average overall mshr miss latency +system.cpu3.l1c.writebacks::writebacks 9875 # number of writebacks +system.cpu3.l1c.writebacks::total 9875 # number of writebacks +system.cpu3.l1c.ReadReq_mshr_misses::cpu3 35935 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_misses::total 35935 # number of ReadReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::cpu3 23086 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_misses::total 23086 # number of WriteReq MSHR misses +system.cpu3.l1c.demand_mshr_misses::cpu3 59021 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_misses::total 59021 # number of demand (read+write) MSHR misses +system.cpu3.l1c.overall_mshr_misses::cpu3 59021 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_misses::total 59021 # number of overall MSHR misses +system.cpu3.l1c.ReadReq_mshr_miss_latency::cpu3 1257339475 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_latency::total 1257339475 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::cpu3 1044074238 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_latency::total 1044074238 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::cpu3 2301413713 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_latency::total 2301413713 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::cpu3 2301413713 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_latency::total 2301413713 # number of overall MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::cpu3 714868620 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency::total 714868620 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::cpu3 436247033 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency::total 436247033 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::cpu3 1151115653 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_uncacheable_latency::total 1151115653 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate::cpu3 0.805104 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_miss_rate::total 0.805104 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::cpu3 0.954835 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_miss_rate::total 0.954835 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.demand_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_miss_rate::total 0.857714 # mshr miss rate for demand accesses +system.cpu3.l1c.overall_mshr_miss_rate::cpu3 0.857714 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_miss_rate::total 0.857714 # mshr miss rate for overall accesses +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::cpu3 34989.271602 # average ReadReq mshr miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency::total 34989.271602 # average ReadReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::cpu3 45225.428312 # average WriteReq mshr miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency::total 45225.428312 # average WriteReq mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::cpu3 38993.133173 # average overall mshr miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency::total 38993.133173 # average overall mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu3 inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency @@ -1117,114 +1117,114 @@ system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.num_reads 96174 # number of read accesses completed -system.cpu4.num_writes 51853 # number of write accesses completed +system.cpu4.num_reads 100000 # number of read accesses completed +system.cpu4.num_writes 53418 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.l1c.replacements 21569 # number of replacements -system.cpu4.l1c.tagsinuse 388.492426 # Cycle average of tags in use -system.cpu4.l1c.total_refs 12628 # Total number of references to valid blocks. -system.cpu4.l1c.sampled_refs 21966 # Sample count of references to valid blocks. -system.cpu4.l1c.avg_refs 0.574888 # Average number of references to valid blocks. +system.cpu4.l1c.replacements 22068 # number of replacements +system.cpu4.l1c.tagsinuse 394.143159 # Cycle average of tags in use +system.cpu4.l1c.total_refs 13375 # Total number of references to valid blocks. +system.cpu4.l1c.sampled_refs 22471 # Sample count of references to valid blocks. +system.cpu4.l1c.avg_refs 0.595212 # Average number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.occ_blocks::cpu4 388.492426 # Average occupied blocks per requestor -system.cpu4.l1c.occ_percent::cpu4 0.758774 # Average percentage of cache occupancy -system.cpu4.l1c.occ_percent::total 0.758774 # Average percentage of cache occupancy -system.cpu4.l1c.ReadReq_hits::cpu4 8239 # number of ReadReq hits -system.cpu4.l1c.ReadReq_hits::total 8239 # number of ReadReq hits -system.cpu4.l1c.WriteReq_hits::cpu4 990 # number of WriteReq hits -system.cpu4.l1c.WriteReq_hits::total 990 # number of WriteReq hits -system.cpu4.l1c.demand_hits::cpu4 9229 # number of demand (read+write) hits -system.cpu4.l1c.demand_hits::total 9229 # number of demand (read+write) hits -system.cpu4.l1c.overall_hits::cpu4 9229 # number of overall hits -system.cpu4.l1c.overall_hits::total 9229 # number of overall hits -system.cpu4.l1c.ReadReq_misses::cpu4 34929 # number of ReadReq misses -system.cpu4.l1c.ReadReq_misses::total 34929 # number of ReadReq misses -system.cpu4.l1c.WriteReq_misses::cpu4 22565 # number of WriteReq misses -system.cpu4.l1c.WriteReq_misses::total 22565 # number of WriteReq misses -system.cpu4.l1c.demand_misses::cpu4 57494 # number of demand (read+write) misses -system.cpu4.l1c.demand_misses::total 57494 # number of demand (read+write) misses -system.cpu4.l1c.overall_misses::cpu4 57494 # number of overall misses -system.cpu4.l1c.overall_misses::total 57494 # number of overall misses -system.cpu4.l1c.ReadReq_miss_latency::cpu4 4583503891 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_latency::total 4583503891 # number of ReadReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::cpu4 3126262139 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_latency::total 3126262139 # number of WriteReq miss cycles -system.cpu4.l1c.demand_miss_latency::cpu4 7709766030 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_latency::total 7709766030 # number of demand (read+write) miss cycles -system.cpu4.l1c.overall_miss_latency::cpu4 7709766030 # number of overall miss cycles -system.cpu4.l1c.overall_miss_latency::total 7709766030 # number of overall miss cycles -system.cpu4.l1c.ReadReq_accesses::cpu4 43168 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_accesses::total 43168 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::cpu4 23555 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_accesses::total 23555 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.demand_accesses::cpu4 66723 # number of demand (read+write) accesses -system.cpu4.l1c.demand_accesses::total 66723 # number of demand (read+write) accesses -system.cpu4.l1c.overall_accesses::cpu4 66723 # number of overall (read+write) accesses -system.cpu4.l1c.overall_accesses::total 66723 # number of overall (read+write) accesses -system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.809141 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_miss_rate::total 0.809141 # miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.957971 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_miss_rate::total 0.957971 # miss rate for WriteReq accesses -system.cpu4.l1c.demand_miss_rate::cpu4 0.861682 # miss rate for demand accesses -system.cpu4.l1c.demand_miss_rate::total 0.861682 # miss rate for demand accesses -system.cpu4.l1c.overall_miss_rate::cpu4 0.861682 # miss rate for overall accesses -system.cpu4.l1c.overall_miss_rate::total 0.861682 # miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 131223.450170 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_miss_latency::total 131223.450170 # average ReadReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 138544.743585 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_miss_latency::total 138544.743585 # average WriteReq miss latency -system.cpu4.l1c.demand_avg_miss_latency::cpu4 134096.880196 # average overall miss latency -system.cpu4.l1c.demand_avg_miss_latency::total 134096.880196 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::cpu4 134096.880196 # average overall miss latency -system.cpu4.l1c.overall_avg_miss_latency::total 134096.880196 # average overall miss latency -system.cpu4.l1c.blocked_cycles::no_mshrs 1393760 # number of cycles access was blocked +system.cpu4.l1c.occ_blocks::cpu4 394.143159 # Average occupied blocks per requestor +system.cpu4.l1c.occ_percent::cpu4 0.769811 # Average percentage of cache occupancy +system.cpu4.l1c.occ_percent::total 0.769811 # Average percentage of cache occupancy +system.cpu4.l1c.ReadReq_hits::cpu4 8810 # number of ReadReq hits +system.cpu4.l1c.ReadReq_hits::total 8810 # number of ReadReq hits +system.cpu4.l1c.WriteReq_hits::cpu4 1141 # number of WriteReq hits +system.cpu4.l1c.WriteReq_hits::total 1141 # number of WriteReq hits +system.cpu4.l1c.demand_hits::cpu4 9951 # number of demand (read+write) hits +system.cpu4.l1c.demand_hits::total 9951 # number of demand (read+write) hits +system.cpu4.l1c.overall_hits::cpu4 9951 # number of overall hits +system.cpu4.l1c.overall_hits::total 9951 # number of overall hits +system.cpu4.l1c.ReadReq_misses::cpu4 36179 # number of ReadReq misses +system.cpu4.l1c.ReadReq_misses::total 36179 # number of ReadReq misses +system.cpu4.l1c.WriteReq_misses::cpu4 22735 # number of WriteReq misses +system.cpu4.l1c.WriteReq_misses::total 22735 # number of WriteReq misses +system.cpu4.l1c.demand_misses::cpu4 58914 # number of demand (read+write) misses +system.cpu4.l1c.demand_misses::total 58914 # number of demand (read+write) misses +system.cpu4.l1c.overall_misses::cpu4 58914 # number of overall misses +system.cpu4.l1c.overall_misses::total 58914 # number of overall misses +system.cpu4.l1c.ReadReq_miss_latency::cpu4 1352891584 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_latency::total 1352891584 # number of ReadReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::cpu4 1067419012 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_latency::total 1067419012 # number of WriteReq miss cycles +system.cpu4.l1c.demand_miss_latency::cpu4 2420310596 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_latency::total 2420310596 # number of demand (read+write) miss cycles +system.cpu4.l1c.overall_miss_latency::cpu4 2420310596 # number of overall miss cycles +system.cpu4.l1c.overall_miss_latency::total 2420310596 # number of overall miss cycles +system.cpu4.l1c.ReadReq_accesses::cpu4 44989 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_accesses::total 44989 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::cpu4 23876 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_accesses::total 23876 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.demand_accesses::cpu4 68865 # number of demand (read+write) accesses +system.cpu4.l1c.demand_accesses::total 68865 # number of demand (read+write) accesses +system.cpu4.l1c.overall_accesses::cpu4 68865 # number of overall (read+write) accesses +system.cpu4.l1c.overall_accesses::total 68865 # number of overall (read+write) accesses +system.cpu4.l1c.ReadReq_miss_rate::cpu4 0.804174 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_miss_rate::total 0.804174 # miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_miss_rate::cpu4 0.952211 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_miss_rate::total 0.952211 # miss rate for WriteReq accesses +system.cpu4.l1c.demand_miss_rate::cpu4 0.855500 # miss rate for demand accesses +system.cpu4.l1c.demand_miss_rate::total 0.855500 # miss rate for demand accesses +system.cpu4.l1c.overall_miss_rate::cpu4 0.855500 # miss rate for overall accesses +system.cpu4.l1c.overall_miss_rate::total 0.855500 # miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_miss_latency::cpu4 37394.388568 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_miss_latency::total 37394.388568 # average ReadReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::cpu4 46950.473367 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_miss_latency::total 46950.473367 # average WriteReq miss latency +system.cpu4.l1c.demand_avg_miss_latency::cpu4 41082.095869 # average overall miss latency +system.cpu4.l1c.demand_avg_miss_latency::total 41082.095869 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::cpu4 41082.095869 # average overall miss latency +system.cpu4.l1c.overall_avg_miss_latency::total 41082.095869 # average overall miss latency +system.cpu4.l1c.blocked_cycles::no_mshrs 1431267 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked::no_mshrs 62546 # number of cycles access was blocked +system.cpu4.l1c.blocked::no_mshrs 66934 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 22.283759 # average number of cycles each access was blocked +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 21.383258 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.writebacks::writebacks 9434 # number of writebacks -system.cpu4.l1c.writebacks::total 9434 # number of writebacks -system.cpu4.l1c.ReadReq_mshr_misses::cpu4 34929 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_misses::total 34929 # number of ReadReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22565 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_misses::total 22565 # number of WriteReq MSHR misses -system.cpu4.l1c.demand_mshr_misses::cpu4 57494 # number of demand (read+write) MSHR misses -system.cpu4.l1c.demand_mshr_misses::total 57494 # number of demand (read+write) MSHR misses -system.cpu4.l1c.overall_mshr_misses::cpu4 57494 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_misses::total 57494 # number of overall MSHR misses -system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 4513651891 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_latency::total 4513651891 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 3081144139 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_latency::total 3081144139 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::cpu4 7594796030 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_latency::total 7594796030 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::cpu4 7594796030 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_latency::total 7594796030 # number of overall MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 1346430009 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 1346430009 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 963144394 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 963144394 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 2309574403 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.overall_mshr_uncacheable_latency::total 2309574403 # number of overall MSHR uncacheable cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.809141 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.809141 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.957971 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.957971 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.861682 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_miss_rate::total 0.861682 # mshr miss rate for demand accesses -system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.861682 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_miss_rate::total 0.861682 # mshr miss rate for overall accesses -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 129223.621947 # average ReadReq mshr miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 129223.621947 # average ReadReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 136545.275382 # average WriteReq mshr miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 136545.275382 # average WriteReq mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 132097.193272 # average overall mshr miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency::total 132097.193272 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 132097.193272 # average overall mshr miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency::total 132097.193272 # average overall mshr miss latency +system.cpu4.l1c.writebacks::writebacks 9521 # number of writebacks +system.cpu4.l1c.writebacks::total 9521 # number of writebacks +system.cpu4.l1c.ReadReq_mshr_misses::cpu4 36179 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_misses::total 36179 # number of ReadReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::cpu4 22735 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_misses::total 22735 # number of WriteReq MSHR misses +system.cpu4.l1c.demand_mshr_misses::cpu4 58914 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_misses::total 58914 # number of demand (read+write) MSHR misses +system.cpu4.l1c.overall_mshr_misses::cpu4 58914 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_misses::total 58914 # number of overall MSHR misses +system.cpu4.l1c.ReadReq_mshr_miss_latency::cpu4 1280533584 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_latency::total 1280533584 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::cpu4 1021953012 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_latency::total 1021953012 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::cpu4 2302486596 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_latency::total 2302486596 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::cpu4 2302486596 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_latency::total 2302486596 # number of overall MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::cpu4 712917081 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency::total 712917081 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::cpu4 441958565 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency::total 441958565 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::cpu4 1154875646 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_uncacheable_latency::total 1154875646 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate::cpu4 0.804174 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_miss_rate::total 0.804174 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::cpu4 0.952211 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_miss_rate::total 0.952211 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.demand_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_miss_rate::total 0.855500 # mshr miss rate for demand accesses +system.cpu4.l1c.overall_mshr_miss_rate::cpu4 0.855500 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_miss_rate::total 0.855500 # mshr miss rate for overall accesses +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::cpu4 35394.388568 # average ReadReq mshr miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency::total 35394.388568 # average ReadReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::cpu4 44950.649307 # average WriteReq mshr miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency::total 44950.649307 # average WriteReq mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::cpu4 39082.163764 # average overall mshr miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency::total 39082.163764 # average overall mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency @@ -1232,114 +1232,114 @@ system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.num_reads 98962 # number of read accesses completed -system.cpu5.num_writes 53362 # number of write accesses completed +system.cpu5.num_reads 99061 # number of read accesses completed +system.cpu5.num_writes 53322 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.l1c.replacements 22485 # number of replacements -system.cpu5.l1c.tagsinuse 390.064411 # Cycle average of tags in use -system.cpu5.l1c.total_refs 13538 # Total number of references to valid blocks. -system.cpu5.l1c.sampled_refs 22892 # Sample count of references to valid blocks. -system.cpu5.l1c.avg_refs 0.591386 # Average number of references to valid blocks. +system.cpu5.l1c.replacements 22382 # number of replacements +system.cpu5.l1c.tagsinuse 394.919460 # Cycle average of tags in use +system.cpu5.l1c.total_refs 13094 # Total number of references to valid blocks. +system.cpu5.l1c.sampled_refs 22775 # Sample count of references to valid blocks. +system.cpu5.l1c.avg_refs 0.574929 # Average number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.occ_blocks::cpu5 390.064411 # Average occupied blocks per requestor -system.cpu5.l1c.occ_percent::cpu5 0.761845 # Average percentage of cache occupancy -system.cpu5.l1c.occ_percent::total 0.761845 # Average percentage of cache occupancy -system.cpu5.l1c.ReadReq_hits::cpu5 8808 # number of ReadReq hits -system.cpu5.l1c.ReadReq_hits::total 8808 # number of ReadReq hits -system.cpu5.l1c.WriteReq_hits::cpu5 1142 # number of WriteReq hits -system.cpu5.l1c.WriteReq_hits::total 1142 # number of WriteReq hits -system.cpu5.l1c.demand_hits::cpu5 9950 # number of demand (read+write) hits -system.cpu5.l1c.demand_hits::total 9950 # number of demand (read+write) hits -system.cpu5.l1c.overall_hits::cpu5 9950 # number of overall hits -system.cpu5.l1c.overall_hits::total 9950 # number of overall hits -system.cpu5.l1c.ReadReq_misses::cpu5 35846 # number of ReadReq misses -system.cpu5.l1c.ReadReq_misses::total 35846 # number of ReadReq misses -system.cpu5.l1c.WriteReq_misses::cpu5 22890 # number of WriteReq misses -system.cpu5.l1c.WriteReq_misses::total 22890 # number of WriteReq misses -system.cpu5.l1c.demand_misses::cpu5 58736 # number of demand (read+write) misses -system.cpu5.l1c.demand_misses::total 58736 # number of demand (read+write) misses -system.cpu5.l1c.overall_misses::cpu5 58736 # number of overall misses -system.cpu5.l1c.overall_misses::total 58736 # number of overall misses -system.cpu5.l1c.ReadReq_miss_latency::cpu5 4553672386 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_latency::total 4553672386 # number of ReadReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::cpu5 3119643153 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_latency::total 3119643153 # number of WriteReq miss cycles -system.cpu5.l1c.demand_miss_latency::cpu5 7673315539 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_latency::total 7673315539 # number of demand (read+write) miss cycles -system.cpu5.l1c.overall_miss_latency::cpu5 7673315539 # number of overall miss cycles -system.cpu5.l1c.overall_miss_latency::total 7673315539 # number of overall miss cycles -system.cpu5.l1c.ReadReq_accesses::cpu5 44654 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_accesses::total 44654 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::cpu5 24032 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_accesses::total 24032 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.demand_accesses::cpu5 68686 # number of demand (read+write) accesses -system.cpu5.l1c.demand_accesses::total 68686 # number of demand (read+write) accesses -system.cpu5.l1c.overall_accesses::cpu5 68686 # number of overall (read+write) accesses -system.cpu5.l1c.overall_accesses::total 68686 # number of overall (read+write) accesses -system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.802750 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_miss_rate::total 0.802750 # miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.952480 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_miss_rate::total 0.952480 # miss rate for WriteReq accesses -system.cpu5.l1c.demand_miss_rate::cpu5 0.855138 # miss rate for demand accesses -system.cpu5.l1c.demand_miss_rate::total 0.855138 # miss rate for demand accesses -system.cpu5.l1c.overall_miss_rate::cpu5 0.855138 # miss rate for overall accesses -system.cpu5.l1c.overall_miss_rate::total 0.855138 # miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 127034.324220 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_miss_latency::total 127034.324220 # average ReadReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 136288.473263 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_miss_latency::total 136288.473263 # average WriteReq miss latency -system.cpu5.l1c.demand_avg_miss_latency::cpu5 130640.757610 # average overall miss latency -system.cpu5.l1c.demand_avg_miss_latency::total 130640.757610 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::cpu5 130640.757610 # average overall miss latency -system.cpu5.l1c.overall_avg_miss_latency::total 130640.757610 # average overall miss latency -system.cpu5.l1c.blocked_cycles::no_mshrs 1393328 # number of cycles access was blocked +system.cpu5.l1c.occ_blocks::cpu5 394.919460 # Average occupied blocks per requestor +system.cpu5.l1c.occ_percent::cpu5 0.771327 # Average percentage of cache occupancy +system.cpu5.l1c.occ_percent::total 0.771327 # Average percentage of cache occupancy +system.cpu5.l1c.ReadReq_hits::cpu5 8623 # number of ReadReq hits +system.cpu5.l1c.ReadReq_hits::total 8623 # number of ReadReq hits +system.cpu5.l1c.WriteReq_hits::cpu5 1083 # number of WriteReq hits +system.cpu5.l1c.WriteReq_hits::total 1083 # number of WriteReq hits +system.cpu5.l1c.demand_hits::cpu5 9706 # number of demand (read+write) hits +system.cpu5.l1c.demand_hits::total 9706 # number of demand (read+write) hits +system.cpu5.l1c.overall_hits::cpu5 9706 # number of overall hits +system.cpu5.l1c.overall_hits::total 9706 # number of overall hits +system.cpu5.l1c.ReadReq_misses::cpu5 35968 # number of ReadReq misses +system.cpu5.l1c.ReadReq_misses::total 35968 # number of ReadReq misses +system.cpu5.l1c.WriteReq_misses::cpu5 22960 # number of WriteReq misses +system.cpu5.l1c.WriteReq_misses::total 22960 # number of WriteReq misses +system.cpu5.l1c.demand_misses::cpu5 58928 # number of demand (read+write) misses +system.cpu5.l1c.demand_misses::total 58928 # number of demand (read+write) misses +system.cpu5.l1c.overall_misses::cpu5 58928 # number of overall misses +system.cpu5.l1c.overall_misses::total 58928 # number of overall misses +system.cpu5.l1c.ReadReq_miss_latency::cpu5 1339036093 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_latency::total 1339036093 # number of ReadReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::cpu5 1083656826 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_latency::total 1083656826 # number of WriteReq miss cycles +system.cpu5.l1c.demand_miss_latency::cpu5 2422692919 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_latency::total 2422692919 # number of demand (read+write) miss cycles +system.cpu5.l1c.overall_miss_latency::cpu5 2422692919 # number of overall miss cycles +system.cpu5.l1c.overall_miss_latency::total 2422692919 # number of overall miss cycles +system.cpu5.l1c.ReadReq_accesses::cpu5 44591 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_accesses::total 44591 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::cpu5 24043 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_accesses::total 24043 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.demand_accesses::cpu5 68634 # number of demand (read+write) accesses +system.cpu5.l1c.demand_accesses::total 68634 # number of demand (read+write) accesses +system.cpu5.l1c.overall_accesses::cpu5 68634 # number of overall (read+write) accesses +system.cpu5.l1c.overall_accesses::total 68634 # number of overall (read+write) accesses +system.cpu5.l1c.ReadReq_miss_rate::cpu5 0.806620 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_miss_rate::total 0.806620 # miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_miss_rate::cpu5 0.954956 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_miss_rate::total 0.954956 # miss rate for WriteReq accesses +system.cpu5.l1c.demand_miss_rate::cpu5 0.858583 # miss rate for demand accesses +system.cpu5.l1c.demand_miss_rate::total 0.858583 # miss rate for demand accesses +system.cpu5.l1c.overall_miss_rate::cpu5 0.858583 # miss rate for overall accesses +system.cpu5.l1c.overall_miss_rate::total 0.858583 # miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_miss_latency::cpu5 37228.539062 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_miss_latency::total 37228.539062 # average ReadReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::cpu5 47197.596951 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_miss_latency::total 47197.596951 # average WriteReq miss latency +system.cpu5.l1c.demand_avg_miss_latency::cpu5 41112.763355 # average overall miss latency +system.cpu5.l1c.demand_avg_miss_latency::total 41112.763355 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::cpu5 41112.763355 # average overall miss latency +system.cpu5.l1c.overall_avg_miss_latency::total 41112.763355 # average overall miss latency +system.cpu5.l1c.blocked_cycles::no_mshrs 1432391 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked::no_mshrs 63640 # number of cycles access was blocked +system.cpu5.l1c.blocked::no_mshrs 66951 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.893903 # average number of cycles each access was blocked +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 21.394617 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.writebacks::writebacks 9848 # number of writebacks -system.cpu5.l1c.writebacks::total 9848 # number of writebacks -system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35846 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_misses::total 35846 # number of ReadReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22890 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_misses::total 22890 # number of WriteReq MSHR misses -system.cpu5.l1c.demand_mshr_misses::cpu5 58736 # number of demand (read+write) MSHR misses -system.cpu5.l1c.demand_mshr_misses::total 58736 # number of demand (read+write) MSHR misses -system.cpu5.l1c.overall_mshr_misses::cpu5 58736 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_misses::total 58736 # number of overall MSHR misses -system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 4481994386 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_latency::total 4481994386 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 3073871153 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_latency::total 3073871153 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::cpu5 7555865539 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_latency::total 7555865539 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::cpu5 7555865539 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_latency::total 7555865539 # number of overall MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 1395127827 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 1395127827 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 940338919 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 940338919 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 2335466746 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.overall_mshr_uncacheable_latency::total 2335466746 # number of overall MSHR uncacheable cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.802750 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.802750 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.952480 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.952480 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.855138 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_miss_rate::total 0.855138 # mshr miss rate for demand accesses -system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.855138 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_miss_rate::total 0.855138 # mshr miss rate for overall accesses -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 125034.714780 # average ReadReq mshr miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 125034.714780 # average ReadReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 134288.822761 # average WriteReq mshr miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 134288.822761 # average WriteReq mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 128641.132168 # average overall mshr miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency::total 128641.132168 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 128641.132168 # average overall mshr miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency::total 128641.132168 # average overall mshr miss latency +system.cpu5.l1c.writebacks::writebacks 9691 # number of writebacks +system.cpu5.l1c.writebacks::total 9691 # number of writebacks +system.cpu5.l1c.ReadReq_mshr_misses::cpu5 35968 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_misses::total 35968 # number of ReadReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::cpu5 22960 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_misses::total 22960 # number of WriteReq MSHR misses +system.cpu5.l1c.demand_mshr_misses::cpu5 58928 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_misses::total 58928 # number of demand (read+write) MSHR misses +system.cpu5.l1c.overall_mshr_misses::cpu5 58928 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_misses::total 58928 # number of overall MSHR misses +system.cpu5.l1c.ReadReq_mshr_miss_latency::cpu5 1267104093 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_latency::total 1267104093 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::cpu5 1037740826 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_latency::total 1037740826 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::cpu5 2304844919 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_latency::total 2304844919 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::cpu5 2304844919 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_latency::total 2304844919 # number of overall MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::cpu5 711626590 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency::total 711626590 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::cpu5 438340423 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency::total 438340423 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::cpu5 1149967013 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_uncacheable_latency::total 1149967013 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate::cpu5 0.806620 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_miss_rate::total 0.806620 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::cpu5 0.954956 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_miss_rate::total 0.954956 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.demand_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_miss_rate::total 0.858583 # mshr miss rate for demand accesses +system.cpu5.l1c.overall_mshr_miss_rate::cpu5 0.858583 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_miss_rate::total 0.858583 # mshr miss rate for overall accesses +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::cpu5 35228.650272 # average ReadReq mshr miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency::total 35228.650272 # average ReadReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::cpu5 45197.771167 # average WriteReq mshr miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency::total 45197.771167 # average WriteReq mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::cpu5 39112.899114 # average overall mshr miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency::total 39112.899114 # average overall mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency @@ -1347,114 +1347,114 @@ system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.num_reads 97085 # number of read accesses completed -system.cpu6.num_writes 52397 # number of write accesses completed +system.cpu6.num_reads 98175 # number of read accesses completed +system.cpu6.num_writes 52998 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.l1c.replacements 21752 # number of replacements -system.cpu6.l1c.tagsinuse 389.740766 # Cycle average of tags in use -system.cpu6.l1c.total_refs 13001 # Total number of references to valid blocks. -system.cpu6.l1c.sampled_refs 22153 # Sample count of references to valid blocks. -system.cpu6.l1c.avg_refs 0.586873 # Average number of references to valid blocks. +system.cpu6.l1c.replacements 21915 # number of replacements +system.cpu6.l1c.tagsinuse 395.370816 # Cycle average of tags in use +system.cpu6.l1c.total_refs 13077 # Total number of references to valid blocks. +system.cpu6.l1c.sampled_refs 22297 # Sample count of references to valid blocks. +system.cpu6.l1c.avg_refs 0.586491 # Average number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.occ_blocks::cpu6 389.740766 # Average occupied blocks per requestor -system.cpu6.l1c.occ_percent::cpu6 0.761212 # Average percentage of cache occupancy -system.cpu6.l1c.occ_percent::total 0.761212 # Average percentage of cache occupancy -system.cpu6.l1c.ReadReq_hits::cpu6 8437 # number of ReadReq hits -system.cpu6.l1c.ReadReq_hits::total 8437 # number of ReadReq hits -system.cpu6.l1c.WriteReq_hits::cpu6 1082 # number of WriteReq hits -system.cpu6.l1c.WriteReq_hits::total 1082 # number of WriteReq hits -system.cpu6.l1c.demand_hits::cpu6 9519 # number of demand (read+write) hits -system.cpu6.l1c.demand_hits::total 9519 # number of demand (read+write) hits -system.cpu6.l1c.overall_hits::cpu6 9519 # number of overall hits -system.cpu6.l1c.overall_hits::total 9519 # number of overall hits -system.cpu6.l1c.ReadReq_misses::cpu6 35128 # number of ReadReq misses -system.cpu6.l1c.ReadReq_misses::total 35128 # number of ReadReq misses -system.cpu6.l1c.WriteReq_misses::cpu6 22626 # number of WriteReq misses -system.cpu6.l1c.WriteReq_misses::total 22626 # number of WriteReq misses -system.cpu6.l1c.demand_misses::cpu6 57754 # number of demand (read+write) misses -system.cpu6.l1c.demand_misses::total 57754 # number of demand (read+write) misses -system.cpu6.l1c.overall_misses::cpu6 57754 # number of overall misses -system.cpu6.l1c.overall_misses::total 57754 # number of overall misses -system.cpu6.l1c.ReadReq_miss_latency::cpu6 4550980379 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_latency::total 4550980379 # number of ReadReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::cpu6 3080862665 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_latency::total 3080862665 # number of WriteReq miss cycles -system.cpu6.l1c.demand_miss_latency::cpu6 7631843044 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_latency::total 7631843044 # number of demand (read+write) miss cycles -system.cpu6.l1c.overall_miss_latency::cpu6 7631843044 # number of overall miss cycles -system.cpu6.l1c.overall_miss_latency::total 7631843044 # number of overall miss cycles -system.cpu6.l1c.ReadReq_accesses::cpu6 43565 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_accesses::total 43565 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::cpu6 23708 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_accesses::total 23708 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.demand_accesses::cpu6 67273 # number of demand (read+write) accesses -system.cpu6.l1c.demand_accesses::total 67273 # number of demand (read+write) accesses -system.cpu6.l1c.overall_accesses::cpu6 67273 # number of overall (read+write) accesses -system.cpu6.l1c.overall_accesses::total 67273 # number of overall (read+write) accesses -system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.806335 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_miss_rate::total 0.806335 # miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954361 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_miss_rate::total 0.954361 # miss rate for WriteReq accesses -system.cpu6.l1c.demand_miss_rate::cpu6 0.858502 # miss rate for demand accesses -system.cpu6.l1c.demand_miss_rate::total 0.858502 # miss rate for demand accesses -system.cpu6.l1c.overall_miss_rate::cpu6 0.858502 # miss rate for overall accesses -system.cpu6.l1c.overall_miss_rate::total 0.858502 # miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 129554.212565 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_miss_latency::total 129554.212565 # average ReadReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 136164.707195 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_miss_latency::total 136164.707195 # average WriteReq miss latency -system.cpu6.l1c.demand_avg_miss_latency::cpu6 132143.973474 # average overall miss latency -system.cpu6.l1c.demand_avg_miss_latency::total 132143.973474 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::cpu6 132143.973474 # average overall miss latency -system.cpu6.l1c.overall_avg_miss_latency::total 132143.973474 # average overall miss latency -system.cpu6.l1c.blocked_cycles::no_mshrs 1372349 # number of cycles access was blocked +system.cpu6.l1c.occ_blocks::cpu6 395.370816 # Average occupied blocks per requestor +system.cpu6.l1c.occ_percent::cpu6 0.772209 # Average percentage of cache occupancy +system.cpu6.l1c.occ_percent::total 0.772209 # Average percentage of cache occupancy +system.cpu6.l1c.ReadReq_hits::cpu6 8591 # number of ReadReq hits +system.cpu6.l1c.ReadReq_hits::total 8591 # number of ReadReq hits +system.cpu6.l1c.WriteReq_hits::cpu6 1078 # number of WriteReq hits +system.cpu6.l1c.WriteReq_hits::total 1078 # number of WriteReq hits +system.cpu6.l1c.demand_hits::cpu6 9669 # number of demand (read+write) hits +system.cpu6.l1c.demand_hits::total 9669 # number of demand (read+write) hits +system.cpu6.l1c.overall_hits::cpu6 9669 # number of overall hits +system.cpu6.l1c.overall_hits::total 9669 # number of overall hits +system.cpu6.l1c.ReadReq_misses::cpu6 35673 # number of ReadReq misses +system.cpu6.l1c.ReadReq_misses::total 35673 # number of ReadReq misses +system.cpu6.l1c.WriteReq_misses::cpu6 22773 # number of WriteReq misses +system.cpu6.l1c.WriteReq_misses::total 22773 # number of WriteReq misses +system.cpu6.l1c.demand_misses::cpu6 58446 # number of demand (read+write) misses +system.cpu6.l1c.demand_misses::total 58446 # number of demand (read+write) misses +system.cpu6.l1c.overall_misses::cpu6 58446 # number of overall misses +system.cpu6.l1c.overall_misses::total 58446 # number of overall misses +system.cpu6.l1c.ReadReq_miss_latency::cpu6 1336174857 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_latency::total 1336174857 # number of ReadReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::cpu6 1084897863 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_latency::total 1084897863 # number of WriteReq miss cycles +system.cpu6.l1c.demand_miss_latency::cpu6 2421072720 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_latency::total 2421072720 # number of demand (read+write) miss cycles +system.cpu6.l1c.overall_miss_latency::cpu6 2421072720 # number of overall miss cycles +system.cpu6.l1c.overall_miss_latency::total 2421072720 # number of overall miss cycles +system.cpu6.l1c.ReadReq_accesses::cpu6 44264 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_accesses::total 44264 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::cpu6 23851 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_accesses::total 23851 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.demand_accesses::cpu6 68115 # number of demand (read+write) accesses +system.cpu6.l1c.demand_accesses::total 68115 # number of demand (read+write) accesses +system.cpu6.l1c.overall_accesses::cpu6 68115 # number of overall (read+write) accesses +system.cpu6.l1c.overall_accesses::total 68115 # number of overall (read+write) accesses +system.cpu6.l1c.ReadReq_miss_rate::cpu6 0.805915 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_miss_rate::total 0.805915 # miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_miss_rate::cpu6 0.954803 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_miss_rate::total 0.954803 # miss rate for WriteReq accesses +system.cpu6.l1c.demand_miss_rate::cpu6 0.858049 # miss rate for demand accesses +system.cpu6.l1c.demand_miss_rate::total 0.858049 # miss rate for demand accesses +system.cpu6.l1c.overall_miss_rate::cpu6 0.858049 # miss rate for overall accesses +system.cpu6.l1c.overall_miss_rate::total 0.858049 # miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_miss_latency::cpu6 37456.195358 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_miss_latency::total 37456.195358 # average ReadReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::cpu6 47639.654986 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_miss_latency::total 47639.654986 # average WriteReq miss latency +system.cpu6.l1c.demand_avg_miss_latency::cpu6 41424.096089 # average overall miss latency +system.cpu6.l1c.demand_avg_miss_latency::total 41424.096089 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::cpu6 41424.096089 # average overall miss latency +system.cpu6.l1c.overall_avg_miss_latency::total 41424.096089 # average overall miss latency +system.cpu6.l1c.blocked_cycles::no_mshrs 1432460 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked::no_mshrs 62634 # number of cycles access was blocked +system.cpu6.l1c.blocked::no_mshrs 66523 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.910608 # average number of cycles each access was blocked +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 21.533304 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.writebacks::writebacks 9668 # number of writebacks -system.cpu6.l1c.writebacks::total 9668 # number of writebacks -system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35128 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_misses::total 35128 # number of ReadReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22626 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_misses::total 22626 # number of WriteReq MSHR misses -system.cpu6.l1c.demand_mshr_misses::cpu6 57754 # number of demand (read+write) MSHR misses -system.cpu6.l1c.demand_mshr_misses::total 57754 # number of demand (read+write) MSHR misses -system.cpu6.l1c.overall_mshr_misses::cpu6 57754 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_misses::total 57754 # number of overall MSHR misses -system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 4480736379 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_latency::total 4480736379 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 3035616665 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_latency::total 3035616665 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::cpu6 7516353044 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_latency::total 7516353044 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::cpu6 7516353044 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_latency::total 7516353044 # number of overall MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 1387372518 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 1387372518 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 999274904 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 999274904 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 2386647422 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.overall_mshr_uncacheable_latency::total 2386647422 # number of overall MSHR uncacheable cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.806335 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.806335 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954361 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954361 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858502 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_miss_rate::total 0.858502 # mshr miss rate for demand accesses -system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858502 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_miss_rate::total 0.858502 # mshr miss rate for overall accesses -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 127554.554173 # average ReadReq mshr miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 127554.554173 # average ReadReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 134164.972377 # average WriteReq mshr miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 134164.972377 # average WriteReq mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 130144.285140 # average overall mshr miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency::total 130144.285140 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 130144.285140 # average overall mshr miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency::total 130144.285140 # average overall mshr miss latency +system.cpu6.l1c.writebacks::writebacks 9553 # number of writebacks +system.cpu6.l1c.writebacks::total 9553 # number of writebacks +system.cpu6.l1c.ReadReq_mshr_misses::cpu6 35673 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_misses::total 35673 # number of ReadReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::cpu6 22773 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_misses::total 22773 # number of WriteReq MSHR misses +system.cpu6.l1c.demand_mshr_misses::cpu6 58446 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_misses::total 58446 # number of demand (read+write) MSHR misses +system.cpu6.l1c.overall_mshr_misses::cpu6 58446 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_misses::total 58446 # number of overall MSHR misses +system.cpu6.l1c.ReadReq_mshr_miss_latency::cpu6 1264832857 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_latency::total 1264832857 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::cpu6 1039353863 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_latency::total 1039353863 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::cpu6 2304186720 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_latency::total 2304186720 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::cpu6 2304186720 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_latency::total 2304186720 # number of overall MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::cpu6 711871628 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency::total 711871628 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::cpu6 446494550 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency::total 446494550 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::cpu6 1158366178 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_uncacheable_latency::total 1158366178 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate::cpu6 0.805915 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_miss_rate::total 0.805915 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::cpu6 0.954803 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_miss_rate::total 0.954803 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.demand_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_miss_rate::total 0.858049 # mshr miss rate for demand accesses +system.cpu6.l1c.overall_mshr_miss_rate::cpu6 0.858049 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_miss_rate::total 0.858049 # mshr miss rate for overall accesses +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::cpu6 35456.307487 # average ReadReq mshr miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency::total 35456.307487 # average ReadReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::cpu6 45639.742809 # average WriteReq mshr miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency::total 45639.742809 # average WriteReq mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 39424.198748 # average overall mshr miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency::total 39424.198748 # average overall mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency @@ -1462,114 +1462,114 @@ system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.num_reads 98863 # number of read accesses completed -system.cpu7.num_writes 52856 # number of write accesses completed +system.cpu7.num_reads 98453 # number of read accesses completed +system.cpu7.num_writes 53303 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.l1c.replacements 22616 # number of replacements -system.cpu7.l1c.tagsinuse 391.615445 # Cycle average of tags in use -system.cpu7.l1c.total_refs 13178 # Total number of references to valid blocks. -system.cpu7.l1c.sampled_refs 23003 # Sample count of references to valid blocks. -system.cpu7.l1c.avg_refs 0.572882 # Average number of references to valid blocks. +system.cpu7.l1c.replacements 22126 # number of replacements +system.cpu7.l1c.tagsinuse 394.997672 # Cycle average of tags in use +system.cpu7.l1c.total_refs 13256 # Total number of references to valid blocks. +system.cpu7.l1c.sampled_refs 22544 # Sample count of references to valid blocks. +system.cpu7.l1c.avg_refs 0.588006 # Average number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.occ_blocks::cpu7 391.615445 # Average occupied blocks per requestor -system.cpu7.l1c.occ_percent::cpu7 0.764874 # Average percentage of cache occupancy -system.cpu7.l1c.occ_percent::total 0.764874 # Average percentage of cache occupancy -system.cpu7.l1c.ReadReq_hits::cpu7 8679 # number of ReadReq hits -system.cpu7.l1c.ReadReq_hits::total 8679 # number of ReadReq hits +system.cpu7.l1c.occ_blocks::cpu7 394.997672 # Average occupied blocks per requestor +system.cpu7.l1c.occ_percent::cpu7 0.771480 # Average percentage of cache occupancy +system.cpu7.l1c.occ_percent::total 0.771480 # Average percentage of cache occupancy +system.cpu7.l1c.ReadReq_hits::cpu7 8720 # number of ReadReq hits +system.cpu7.l1c.ReadReq_hits::total 8720 # number of ReadReq hits system.cpu7.l1c.WriteReq_hits::cpu7 1098 # number of WriteReq hits system.cpu7.l1c.WriteReq_hits::total 1098 # number of WriteReq hits -system.cpu7.l1c.demand_hits::cpu7 9777 # number of demand (read+write) hits -system.cpu7.l1c.demand_hits::total 9777 # number of demand (read+write) hits -system.cpu7.l1c.overall_hits::cpu7 9777 # number of overall hits -system.cpu7.l1c.overall_hits::total 9777 # number of overall hits -system.cpu7.l1c.ReadReq_misses::cpu7 35968 # number of ReadReq misses -system.cpu7.l1c.ReadReq_misses::total 35968 # number of ReadReq misses -system.cpu7.l1c.WriteReq_misses::cpu7 22753 # number of WriteReq misses -system.cpu7.l1c.WriteReq_misses::total 22753 # number of WriteReq misses -system.cpu7.l1c.demand_misses::cpu7 58721 # number of demand (read+write) misses -system.cpu7.l1c.demand_misses::total 58721 # number of demand (read+write) misses -system.cpu7.l1c.overall_misses::cpu7 58721 # number of overall misses -system.cpu7.l1c.overall_misses::total 58721 # number of overall misses -system.cpu7.l1c.ReadReq_miss_latency::cpu7 4555865271 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_latency::total 4555865271 # number of ReadReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::cpu7 3104187449 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_latency::total 3104187449 # number of WriteReq miss cycles -system.cpu7.l1c.demand_miss_latency::cpu7 7660052720 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_latency::total 7660052720 # number of demand (read+write) miss cycles -system.cpu7.l1c.overall_miss_latency::cpu7 7660052720 # number of overall miss cycles -system.cpu7.l1c.overall_miss_latency::total 7660052720 # number of overall miss cycles -system.cpu7.l1c.ReadReq_accesses::cpu7 44647 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_accesses::total 44647 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::cpu7 23851 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_accesses::total 23851 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.demand_accesses::cpu7 68498 # number of demand (read+write) accesses -system.cpu7.l1c.demand_accesses::total 68498 # number of demand (read+write) accesses -system.cpu7.l1c.overall_accesses::cpu7 68498 # number of overall (read+write) accesses -system.cpu7.l1c.overall_accesses::total 68498 # number of overall (read+write) accesses -system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.805608 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_miss_rate::total 0.805608 # miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.953964 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_miss_rate::total 0.953964 # miss rate for WriteReq accesses -system.cpu7.l1c.demand_miss_rate::cpu7 0.857266 # miss rate for demand accesses -system.cpu7.l1c.demand_miss_rate::total 0.857266 # miss rate for demand accesses -system.cpu7.l1c.overall_miss_rate::cpu7 0.857266 # miss rate for overall accesses -system.cpu7.l1c.overall_miss_rate::total 0.857266 # miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 126664.403664 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_miss_latency::total 126664.403664 # average ReadReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 136429.809212 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_miss_latency::total 136429.809212 # average WriteReq miss latency -system.cpu7.l1c.demand_avg_miss_latency::cpu7 130448.267570 # average overall miss latency -system.cpu7.l1c.demand_avg_miss_latency::total 130448.267570 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::cpu7 130448.267570 # average overall miss latency -system.cpu7.l1c.overall_avg_miss_latency::total 130448.267570 # average overall miss latency -system.cpu7.l1c.blocked_cycles::no_mshrs 1381368 # number of cycles access was blocked +system.cpu7.l1c.demand_hits::cpu7 9818 # number of demand (read+write) hits +system.cpu7.l1c.demand_hits::total 9818 # number of demand (read+write) hits +system.cpu7.l1c.overall_hits::cpu7 9818 # number of overall hits +system.cpu7.l1c.overall_hits::total 9818 # number of overall hits +system.cpu7.l1c.ReadReq_misses::cpu7 35443 # number of ReadReq misses +system.cpu7.l1c.ReadReq_misses::total 35443 # number of ReadReq misses +system.cpu7.l1c.WriteReq_misses::cpu7 23039 # number of WriteReq misses +system.cpu7.l1c.WriteReq_misses::total 23039 # number of WriteReq misses +system.cpu7.l1c.demand_misses::cpu7 58482 # number of demand (read+write) misses +system.cpu7.l1c.demand_misses::total 58482 # number of demand (read+write) misses +system.cpu7.l1c.overall_misses::cpu7 58482 # number of overall misses +system.cpu7.l1c.overall_misses::total 58482 # number of overall misses +system.cpu7.l1c.ReadReq_miss_latency::cpu7 1325635544 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_latency::total 1325635544 # number of ReadReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::cpu7 1095033308 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_latency::total 1095033308 # number of WriteReq miss cycles +system.cpu7.l1c.demand_miss_latency::cpu7 2420668852 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_latency::total 2420668852 # number of demand (read+write) miss cycles +system.cpu7.l1c.overall_miss_latency::cpu7 2420668852 # number of overall miss cycles +system.cpu7.l1c.overall_miss_latency::total 2420668852 # number of overall miss cycles +system.cpu7.l1c.ReadReq_accesses::cpu7 44163 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_accesses::total 44163 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::cpu7 24137 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_accesses::total 24137 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.demand_accesses::cpu7 68300 # number of demand (read+write) accesses +system.cpu7.l1c.demand_accesses::total 68300 # number of demand (read+write) accesses +system.cpu7.l1c.overall_accesses::cpu7 68300 # number of overall (read+write) accesses +system.cpu7.l1c.overall_accesses::total 68300 # number of overall (read+write) accesses +system.cpu7.l1c.ReadReq_miss_rate::cpu7 0.802550 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_miss_rate::total 0.802550 # miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_miss_rate::cpu7 0.954510 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_miss_rate::total 0.954510 # miss rate for WriteReq accesses +system.cpu7.l1c.demand_miss_rate::cpu7 0.856252 # miss rate for demand accesses +system.cpu7.l1c.demand_miss_rate::total 0.856252 # miss rate for demand accesses +system.cpu7.l1c.overall_miss_rate::cpu7 0.856252 # miss rate for overall accesses +system.cpu7.l1c.overall_miss_rate::total 0.856252 # miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_miss_latency::cpu7 37401.900065 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_miss_latency::total 37401.900065 # average ReadReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::cpu7 47529.550241 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_miss_latency::total 47529.550241 # average WriteReq miss latency +system.cpu7.l1c.demand_avg_miss_latency::cpu7 41391.690640 # average overall miss latency +system.cpu7.l1c.demand_avg_miss_latency::total 41391.690640 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::cpu7 41391.690640 # average overall miss latency +system.cpu7.l1c.overall_avg_miss_latency::total 41391.690640 # average overall miss latency +system.cpu7.l1c.blocked_cycles::no_mshrs 1432038 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked::no_mshrs 63977 # number of cycles access was blocked +system.cpu7.l1c.blocked::no_mshrs 66517 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.591634 # average number of cycles each access was blocked +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 21.528902 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.writebacks::writebacks 9880 # number of writebacks -system.cpu7.l1c.writebacks::total 9880 # number of writebacks -system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35968 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_misses::total 35968 # number of ReadReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::cpu7 22753 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_misses::total 22753 # number of WriteReq MSHR misses -system.cpu7.l1c.demand_mshr_misses::cpu7 58721 # number of demand (read+write) MSHR misses -system.cpu7.l1c.demand_mshr_misses::total 58721 # number of demand (read+write) MSHR misses -system.cpu7.l1c.overall_mshr_misses::cpu7 58721 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_misses::total 58721 # number of overall MSHR misses -system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 4483949271 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_latency::total 4483949271 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 3058683449 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_latency::total 3058683449 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::cpu7 7542632720 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_latency::total 7542632720 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::cpu7 7542632720 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_latency::total 7542632720 # number of overall MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1380003854 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1380003854 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 891969960 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 891969960 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 2271973814 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.overall_mshr_uncacheable_latency::total 2271973814 # number of overall MSHR uncacheable cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805608 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805608 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.953964 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.953964 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857266 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_miss_rate::total 0.857266 # mshr miss rate for demand accesses -system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857266 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_miss_rate::total 0.857266 # mshr miss rate for overall accesses -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 124664.959714 # average ReadReq mshr miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 124664.959714 # average ReadReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 134429.897112 # average WriteReq mshr miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 134429.897112 # average WriteReq mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 128448.642223 # average overall mshr miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency::total 128448.642223 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 128448.642223 # average overall mshr miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency::total 128448.642223 # average overall mshr miss latency +system.cpu7.l1c.writebacks::writebacks 9733 # number of writebacks +system.cpu7.l1c.writebacks::total 9733 # number of writebacks +system.cpu7.l1c.ReadReq_mshr_misses::cpu7 35443 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_misses::total 35443 # number of ReadReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::cpu7 23039 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_misses::total 23039 # number of WriteReq MSHR misses +system.cpu7.l1c.demand_mshr_misses::cpu7 58482 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_misses::total 58482 # number of demand (read+write) MSHR misses +system.cpu7.l1c.overall_mshr_misses::cpu7 58482 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_misses::total 58482 # number of overall MSHR misses +system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 1254751544 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_latency::total 1254751544 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1048957308 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1048957308 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::cpu7 2303708852 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_latency::total 2303708852 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::cpu7 2303708852 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_latency::total 2303708852 # number of overall MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 712119692 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 712119692 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 450587409 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 450587409 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 1162707101 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_uncacheable_latency::total 1162707101 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.802550 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.802550 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.954510 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.954510 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_miss_rate::total 0.856252 # mshr miss rate for demand accesses +system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.856252 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_miss_rate::total 0.856252 # mshr miss rate for overall accesses +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 35401.956494 # average ReadReq mshr miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 35401.956494 # average ReadReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 45529.637050 # average WriteReq mshr miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 45529.637050 # average WriteReq mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 39391.759037 # average overall mshr miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency::total 39391.759037 # average overall mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency |