diff options
Diffstat (limited to 'tests/quick')
3 files changed, 360 insertions, 360 deletions
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt index f228f639d..6eb08a8bc 100644 --- a/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/linux/minor-timing/stats.txt @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000038 # Number of seconds simulated -sim_ticks 37928000 # Number of ticks simulated -final_tick 37928000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 37930000 # Number of ticks simulated +final_tick 37930000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 174102 # Simulator instruction rate (inst/s) -host_op_rate 174036 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1031016392 # Simulator tick rate (ticks/s) -host_mem_usage 293404 # Number of bytes of host memory used +host_inst_rate 161486 # Simulator instruction rate (inst/s) +host_op_rate 161429 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 956403338 # Simulator tick rate (ticks/s) +host_mem_usage 294064 # Number of bytes of host memory used host_seconds 0.04 # Real time elapsed on the host sim_insts 6400 # Number of instructions simulated sim_ops 6400 # Number of ops (including micro ops) simulated @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 23296 # Nu system.physmem.num_reads::cpu.inst 364 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 169 # Number of read requests responded to by this memory system.physmem.num_reads::total 533 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 614216410 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 285171905 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 899388315 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 614216410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 614216410 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 614216410 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 285171905 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 899388315 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 614184023 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 285156868 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 899340891 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 614184023 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 614184023 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 614184023 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 285156868 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 899340891 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 533 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 533 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 37822500 # Total gap between requests +system.physmem.totGap 37824500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -206,9 +206,9 @@ system.physmem.totBusLat 2665000 # To system.physmem.avgQLat 6100.38 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst system.physmem.avgMemAccLat 24850.38 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 899.39 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgRdBW 899.34 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 899.39 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 899.34 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 7.03 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 437 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 81.99 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 70961.54 # Average gap between requests +system.physmem.avgGap 70965.29 # Average gap between requests system.physmem.pageHitRate 81.99 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 234360 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 127875 # Energy for precharge commands per rank (pJ) @@ -231,7 +231,7 @@ system.physmem_0.actBackEnergy 21404070 # En system.physmem_0.preBackEnergy 67500 # Energy for precharge background per rank (pJ) system.physmem_0.totalEnergy 25911645 # Total energy per rank (pJ) system.physmem_0.averagePower 825.080242 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 371750 # Time in different power states +system.physmem_0.memoryStateTime::IDLE 372750 # Time in different power states system.physmem_0.memoryStateTime::REF 1040000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_0.memoryStateTime::ACT 30362750 # Time in different power states @@ -250,13 +250,13 @@ system.physmem_1.memoryStateTime::REF 1040000 # Ti system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 28783000 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1968 # Number of BP lookups -system.cpu.branchPred.condPredicted 1205 # Number of conditional branches predicted +system.cpu.branchPred.lookups 1964 # Number of BP lookups +system.cpu.branchPred.condPredicted 1204 # Number of conditional branches predicted system.cpu.branchPred.condIncorrect 368 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1559 # Number of BTB lookups -system.cpu.branchPred.BTBHits 385 # Number of BTB hits +system.cpu.branchPred.BTBLookups 1555 # Number of BTB lookups +system.cpu.branchPred.BTBHits 382 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 24.695318 # BTB Hit Percentage +system.cpu.branchPred.BTBHitPct 24.565916 # BTB Hit Percentage system.cpu.branchPred.usedRAS 224 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 14 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks @@ -264,22 +264,22 @@ system.cpu.dtb.fetch_hits 0 # IT system.cpu.dtb.fetch_misses 0 # ITB misses system.cpu.dtb.fetch_acv 0 # ITB acv system.cpu.dtb.fetch_accesses 0 # ITB accesses -system.cpu.dtb.read_hits 1370 # DTB read hits +system.cpu.dtb.read_hits 1371 # DTB read hits system.cpu.dtb.read_misses 11 # DTB read misses system.cpu.dtb.read_acv 0 # DTB read access violations -system.cpu.dtb.read_accesses 1381 # DTB read accesses +system.cpu.dtb.read_accesses 1382 # DTB read accesses system.cpu.dtb.write_hits 884 # DTB write hits system.cpu.dtb.write_misses 3 # DTB write misses system.cpu.dtb.write_acv 0 # DTB write access violations system.cpu.dtb.write_accesses 887 # DTB write accesses -system.cpu.dtb.data_hits 2254 # DTB hits +system.cpu.dtb.data_hits 2255 # DTB hits system.cpu.dtb.data_misses 14 # DTB misses system.cpu.dtb.data_acv 0 # DTB access violations -system.cpu.dtb.data_accesses 2268 # DTB accesses -system.cpu.itb.fetch_hits 2639 # ITB hits +system.cpu.dtb.data_accesses 2269 # DTB accesses +system.cpu.itb.fetch_hits 2638 # ITB hits system.cpu.itb.fetch_misses 17 # ITB misses system.cpu.itb.fetch_acv 0 # ITB acv -system.cpu.itb.fetch_accesses 2656 # ITB accesses +system.cpu.itb.fetch_accesses 2655 # ITB accesses system.cpu.itb.read_hits 0 # DTB read hits system.cpu.itb.read_misses 0 # DTB read misses system.cpu.itb.read_acv 0 # DTB read access violations @@ -293,40 +293,40 @@ system.cpu.itb.data_misses 0 # DT system.cpu.itb.data_acv 0 # DTB access violations system.cpu.itb.data_accesses 0 # DTB accesses system.cpu.workload.num_syscalls 17 # Number of system calls -system.cpu.numCycles 75856 # number of cpu cycles simulated +system.cpu.numCycles 75860 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 6400 # Number of instructions committed system.cpu.committedOps 6400 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1110 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 11.852500 # CPI: cycles per instruction -system.cpu.ipc 0.084370 # IPC: instructions per cycle -system.cpu.tickCycles 12576 # Number of cycles that the object actually ticked -system.cpu.idleCycles 63280 # Total number of cycles that the object has spent stopped +system.cpu.cpi 11.853125 # CPI: cycles per instruction +system.cpu.ipc 0.084366 # IPC: instructions per cycle +system.cpu.tickCycles 12560 # Number of cycles that the object actually ticked +system.cpu.idleCycles 63300 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 103.896503 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1975 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 103.899066 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1976 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 169 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 11.686391 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 11.692308 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 103.896503 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.025365 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.025365 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 103.899066 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.025366 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.025366 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 169 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 147 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.041260 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4571 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4571 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1234 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1234 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4573 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4573 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1235 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1235 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 741 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 741 # number of WriteReq hits -system.cpu.dcache.demand_hits::cpu.data 1975 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1975 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1975 # number of overall hits -system.cpu.dcache.overall_hits::total 1975 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1976 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1976 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1976 # number of overall hits +system.cpu.dcache.overall_hits::total 1976 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 102 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 102 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 124 # number of WriteReq misses @@ -335,38 +335,38 @@ system.cpu.dcache.demand_misses::cpu.data 226 # n system.cpu.dcache.demand_misses::total 226 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 226 # number of overall misses system.cpu.dcache.overall_misses::total 226 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 8143750 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 8143750 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 9234250 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 9234250 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17378000 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17378000 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17378000 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17378000 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1336 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1336 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_miss_latency::cpu.data 8144750 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 8144750 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 9233750 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 9233750 # number of WriteReq miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 17378500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 17378500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 17378500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 17378500 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1337 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1337 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2201 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2201 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2201 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2201 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076347 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.076347 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2202 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2202 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2202 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2202 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076290 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.076290 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.143353 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.143353 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.102681 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.102681 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.102681 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.102681 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79840.686275 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 79840.686275 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74469.758065 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 74469.758065 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 76893.805310 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 76893.805310 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 76893.805310 # average overall miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.102634 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.102634 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.102634 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.102634 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 79850.490196 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 79850.490196 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 74465.725806 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 74465.725806 # average WriteReq miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 76896.017699 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 76896.017699 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 76896.017699 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -391,82 +391,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 169 system.cpu.dcache.demand_mshr_misses::total 169 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 169 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7563250 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 7563250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7564250 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 7564250 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5364250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 5364250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 12927500 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12927500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 12927500 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071856 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071856 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12928500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 12928500 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12928500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 12928500 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.071803 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.071803 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.076783 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076783 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.076783 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78783.854167 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78783.854167 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.076748 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.076748 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.076748 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78794.270833 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78794.270833 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73482.876712 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73482.876712 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76494.082840 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 76494.082840 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 76500 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 76500 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 0 # number of replacements -system.cpu.icache.tags.tagsinuse 175.733533 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 2274 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 175.739822 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 2273 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 365 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 6.230137 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 6.227397 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 175.733533 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.085807 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.085807 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 175.739822 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.085810 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.085810 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 365 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 260 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.178223 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 5643 # Number of tag accesses -system.cpu.icache.tags.data_accesses 5643 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 2274 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 2274 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 2274 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 2274 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 2274 # number of overall hits -system.cpu.icache.overall_hits::total 2274 # number of overall hits +system.cpu.icache.tags.tag_accesses 5641 # Number of tag accesses +system.cpu.icache.tags.data_accesses 5641 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 2273 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 2273 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 2273 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 2273 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 2273 # number of overall hits +system.cpu.icache.overall_hits::total 2273 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 365 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 365 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 365 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 365 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 365 # number of overall misses system.cpu.icache.overall_misses::total 365 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333250 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28333250 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28333250 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28333250 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28333250 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28333250 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2639 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2639 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2639 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2639 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2639 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2639 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138310 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.138310 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.138310 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.138310 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.138310 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.138310 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77625.342466 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 77625.342466 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 77625.342466 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 77625.342466 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 77625.342466 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28333750 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28333750 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28333750 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28333750 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28333750 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28333750 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2638 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2638 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2638 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2638 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2638 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2638 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.138362 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.138362 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.138362 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.138362 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.138362 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.138362 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77626.712329 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 77626.712329 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 77626.712329 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 77626.712329 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 77626.712329 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -481,36 +481,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 365 system.cpu.icache.demand_mshr_misses::total 365 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 365 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 365 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 27622250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 27622250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 27622250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138310 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.138310 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138310 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.138310 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75677.397260 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75677.397260 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75677.397260 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 75677.397260 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 27622750 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 27622750 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 27622750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 27622750 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 27622750 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 27622750 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.138362 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.138362 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.138362 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.138362 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75678.767123 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75678.767123 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75678.767123 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75678.767123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 233.387081 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 233.394654 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 460 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.002174 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.765541 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 57.621541 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 175.771828 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 57.622826 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005364 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001758 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.007122 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001759 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.007123 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 460 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 121 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 339 # Occupied blocks per task id @@ -534,17 +534,17 @@ system.cpu.l2cache.demand_misses::total 533 # nu system.cpu.l2cache.overall_misses::cpu.inst 364 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 169 # number of overall misses system.cpu.l2cache.overall_misses::total 533 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246250 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7465750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 34712000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 27246750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7466750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 34713500 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5290250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 5290250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 27246250 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 12756000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 40002250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 27246250 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 12756000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 40002250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 27246750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 12757000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 40003750 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 27246750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 12757000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 40003750 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 365 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 96 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 461 # number of ReadReq accesses(hits+misses) @@ -567,17 +567,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.998127 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997260 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.998127 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74852.335165 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77768.229167 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75460.869565 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74853.708791 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77778.645833 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75464.130435 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72469.178082 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72469.178082 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75051.125704 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74852.335165 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75479.289941 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75051.125704 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 75053.939962 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74853.708791 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75485.207101 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 75053.939962 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -597,17 +597,17 @@ system.cpu.l2cache.demand_mshr_misses::total 533 system.cpu.l2cache.overall_mshr_misses::cpu.inst 364 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 169 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 533 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6259250 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28945500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 22686750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6260250 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28947000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4378250 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4378250 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10637500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 33323750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686250 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10637500 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 33323750 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22686750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10638500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 33325250 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22686750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10638500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 33325250 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997831 # mshr miss rate for ReadReq accesses @@ -619,17 +619,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.998127 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997260 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.998127 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62324.862637 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65200.520833 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62925 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62326.236264 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65210.937500 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62928.260870 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 59976.027397 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 59976.027397 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62324.862637 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62943.786982 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62521.106942 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62326.236264 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 62949.704142 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62523.921201 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 461 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 461 # Transaction distribution @@ -678,7 +678,7 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 533 # Request fanout histogram -system.membus.reqLayer0.occupancy 604000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) system.membus.respLayer1.occupancy 2833250 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.5 # Layer utilization (%) diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt index a634edee1..7408970f9 100644 --- a/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/alpha/tru64/minor-timing/stats.txt @@ -4,10 +4,10 @@ sim_seconds 0.000020 # Nu sim_ticks 20287000 # Number of ticks simulated final_tick 20287000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 136939 # Simulator instruction rate (inst/s) -host_op_rate 136838 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1073215892 # Simulator tick rate (ticks/s) -host_mem_usage 292092 # Number of bytes of host memory used +host_inst_rate 140405 # Simulator instruction rate (inst/s) +host_op_rate 140306 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1100341704 # Simulator tick rate (ticks/s) +host_mem_usage 292772 # Number of bytes of host memory used host_seconds 0.02 # Real time elapsed on the host sim_insts 2585 # Number of instructions simulated sim_ops 2585 # Number of ops (including micro ops) simulated @@ -298,12 +298,12 @@ system.cpu.numWorkItemsStarted 0 # nu system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 2585 # Number of instructions committed system.cpu.committedOps 2585 # Number of ops (including micro ops) committed -system.cpu.discardedOps 595 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 594 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching system.cpu.cpi 15.695938 # CPI: cycles per instruction system.cpu.ipc 0.063711 # IPC: instructions per cycle -system.cpu.tickCycles 5396 # Number of cycles that the object actually ticked -system.cpu.idleCycles 35178 # Total number of cycles that the object has spent stopped +system.cpu.tickCycles 5391 # Number of cycles that the object actually ticked +system.cpu.idleCycles 35183 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements system.cpu.dcache.tags.tagsinuse 48.342007 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 692 # Total number of references to valid blocks. diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index 6403398b5..b37232811 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,14 +1,14 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 30321500 # Number of ticks simulated -final_tick 30321500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30323500 # Number of ticks simulated +final_tick 30323500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 50258 # Simulator instruction rate (inst/s) -host_op_rate 58824 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 330783185 # Simulator tick rate (ticks/s) -host_mem_usage 302404 # Number of bytes of host memory used -host_seconds 0.09 # Real time elapsed on the host +host_inst_rate 117134 # Simulator instruction rate (inst/s) +host_op_rate 137081 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 770805796 # Simulator tick rate (ticks/s) +host_mem_usage 310084 # Number of bytes of host memory used +host_seconds 0.04 # Real time elapsed on the host sim_insts 4605 # Number of instructions simulated sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 643767624 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 244842768 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 888610392 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 643767624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 643767624 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 643767624 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 244842768 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 888610392 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 643725164 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 244826620 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 888551783 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 643725164 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 643725164 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 643725164 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 244826620 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 888551783 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 30230000 # Total gap between requests +system.physmem.totGap 30232000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -200,15 +200,15 @@ system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # By system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2532750 # Total ticks spent queuing -system.physmem.totMemAccLat 10426500 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2542750 # Total ticks spent queuing +system.physmem.totMemAccLat 10436500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6016.03 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6039.79 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24766.03 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 888.61 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24789.79 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 888.55 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 888.61 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 888.55 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s system.physmem.busUtil 6.94 # Data bus utilization in percentage @@ -220,7 +220,7 @@ system.physmem.readRowHits 349 # Nu system.physmem.writeRowHits 0 # Number of row buffer hits during writes system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 71805.23 # Average gap between requests +system.physmem.avgGap 71809.98 # Average gap between requests system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) @@ -377,44 +377,44 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 60643 # number of cpu cycles simulated +system.cpu.numCycles 60647 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.committedInsts 4605 # Number of instructions committed system.cpu.committedOps 5391 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1105 # Number of ops (including micro ops) which were discarded before commit +system.cpu.discardedOps 1116 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.168947 # CPI: cycles per instruction -system.cpu.ipc 0.075936 # IPC: instructions per cycle -system.cpu.tickCycles 10594 # Number of cycles that the object actually ticked -system.cpu.idleCycles 50049 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.169815 # CPI: cycles per instruction +system.cpu.ipc 0.075931 # IPC: instructions per cycle +system.cpu.tickCycles 10567 # Number of cycles that the object actually ticked +system.cpu.idleCycles 50080 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.367225 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1917 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.373507 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.130137 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.136986 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.367225 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021086 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021086 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.373507 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021087 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021087 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4344 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4344 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4346 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4346 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1050 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1050 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits -system.cpu.dcache.overall_hits::total 1895 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits +system.cpu.dcache.overall_hits::total 1896 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses @@ -423,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7249991 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7249991 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7248241 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7248241 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12303491 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12303491 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12303491 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12303491 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 12301741 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12301741 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12301741 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12301741 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1165 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1165 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2077 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2077 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2077 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2077 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098797 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098797 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2078 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2078 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2078 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2078 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098712 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098712 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087626 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087626 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087626 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087626 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63043.400000 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63043.400000 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.087584 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087584 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087584 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087584 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63028.182609 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63028.182609 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67601.598901 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67601.598901 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67591.983516 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67591.983516 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67591.983516 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,43 +483,43 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6563508 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6563508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6562258 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6562258 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9742758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9742758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9742758 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9742758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088488 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088488 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9741508 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9741508 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9741508 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9741508 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088412 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088412 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070294 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070294 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63723.378641 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63723.378641 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070260 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070260 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070260 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63711.242718 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63711.242718 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66722.657534 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66722.657534 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.427928 # Cycle average of tags in use +system.cpu.icache.tags.tagsinuse 161.448164 # Cycle average of tags in use system.cpu.icache.tags.total_refs 1909 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. system.cpu.icache.tags.avg_refs 5.928571 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.427928 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078822 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078822 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.448164 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078832 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078832 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 106 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 213 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id system.cpu.icache.tags.tag_accesses 4784 # Number of tag accesses system.cpu.icache.tags.data_accesses 4784 # Number of data accesses @@ -535,12 +535,12 @@ system.cpu.icache.demand_misses::cpu.inst 322 # n system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23868000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23868000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23868000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23868000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23868000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23868000 # number of overall miss cycles +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23879500 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23879500 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23879500 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23879500 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23879500 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23879500 # number of overall miss cycles system.cpu.icache.ReadReq_accesses::cpu.inst 2231 # number of ReadReq accesses(hits+misses) system.cpu.icache.ReadReq_accesses::total 2231 # number of ReadReq accesses(hits+misses) system.cpu.icache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses @@ -553,12 +553,12 @@ system.cpu.icache.demand_miss_rate::cpu.inst 0.144330 system.cpu.icache.demand_miss_rate::total 0.144330 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.144330 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.144330 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74124.223602 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74124.223602 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74124.223602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74124.223602 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74159.937888 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74159.937888 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74159.937888 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74159.937888 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74159.937888 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,36 +573,36 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23250000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23250000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23250000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23250000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23250000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23250000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23261500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23261500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23261500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23261500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23261500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23261500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.144330 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.144330 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.144330 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72204.968944 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72204.968944 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72240.683230 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72240.683230 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72240.683230 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72240.683230 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.047415 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.068888 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.972747 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.074668 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.992766 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.076122 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004699 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001253 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005952 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001254 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005953 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id @@ -629,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22749500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6226500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 28976000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22761000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6225250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28986250 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22749500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9362750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32112250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22749500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9362750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32112250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22761000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9361500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32122500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22761000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9361500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32122500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) @@ -662,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74588.524590 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76870.370370 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75067.357513 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74626.229508 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76854.938272 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75093.911917 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 74853.729604 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 74853.729604 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74877.622378 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74626.229508 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75495.967742 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74877.622378 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -698,17 +698,17 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18927000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4781000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23708000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18938500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4780750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23719250 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18927000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26306750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18927000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26306750 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18938500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26318000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18938500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26318000 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses @@ -720,17 +720,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62055.737705 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65493.150685 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62719.576720 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62093.442623 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65489.726027 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62749.338624 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62093.442623 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63616.379310 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62513.064133 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution @@ -758,7 +758,7 @@ system.cpu.toL2Bus.reqLayer0.occupancy 234000 # La system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer1.occupancy 240992 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) system.membus.trans_dist::ReadReq 378 # Transaction distribution system.membus.trans_dist::ReadResp 378 # Transaction distribution @@ -779,9 +779,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2238750 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2238000 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- |