diff options
Diffstat (limited to 'tests/quick')
12 files changed, 1814 insertions, 1814 deletions
diff --git a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt index a4c548b0e..0b52af291 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/minor-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000030 # Number of seconds simulated -sim_ticks 30427500 # Number of ticks simulated -final_tick 30427500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 30321500 # Number of ticks simulated +final_tick 30321500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 90683 # Simulator instruction rate (inst/s) -host_op_rate 106136 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 599001910 # Simulator tick rate (ticks/s) -host_mem_usage 308040 # Number of bytes of host memory used -host_seconds 0.05 # Real time elapsed on the host -sim_insts 4604 # Number of instructions simulated -sim_ops 5390 # Number of ops (including micro ops) simulated +host_inst_rate 50258 # Simulator instruction rate (inst/s) +host_op_rate 58824 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 330783185 # Simulator tick rate (ticks/s) +host_mem_usage 302404 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +sim_insts 4605 # Number of instructions simulated +sim_ops 5391 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 19520 # Number of bytes read from this memory @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 19520 # Nu system.physmem.num_reads::cpu.inst 305 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 116 # Number of read requests responded to by this memory system.physmem.num_reads::total 421 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 641524936 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 243989812 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 885514748 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 641524936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 641524936 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 641524936 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 243989812 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 885514748 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 643767624 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 244842768 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 888610392 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 643767624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 643767624 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 643767624 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 244842768 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 888610392 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 421 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 421 # Number of DRAM read bursts, including those serviced by the write queue @@ -75,7 +75,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 30336000 # Total gap between requests +system.physmem.totGap 30230000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -187,50 +187,50 @@ system.physmem.wrQLenPdf::61 0 # Wh system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 401.269841 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 285.929811 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 324.144791 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 402.285714 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 286.758489 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 323.986232 # Bytes accessed per row activation system.physmem.bytesPerActivate::0-127 7 11.11% 11.11% # Bytes accessed per row activation system.physmem.bytesPerActivate::128-255 19 30.16% 41.27% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 14 22.22% 63.49% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 4 6.35% 69.84% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 13 20.63% 61.90% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 5 7.94% 69.84% # Bytes accessed per row activation system.physmem.bytesPerActivate::512-639 3 4.76% 74.60% # Bytes accessed per row activation system.physmem.bytesPerActivate::640-767 4 6.35% 80.95% # Bytes accessed per row activation system.physmem.bytesPerActivate::768-895 2 3.17% 84.13% # Bytes accessed per row activation system.physmem.bytesPerActivate::896-1023 1 1.59% 85.71% # Bytes accessed per row activation system.physmem.bytesPerActivate::1024-1151 9 14.29% 100.00% # Bytes accessed per row activation system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 2605000 # Total ticks spent queuing -system.physmem.totMemAccLat 10498750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totQLat 2532750 # Total ticks spent queuing +system.physmem.totMemAccLat 10426500 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2105000 # Total ticks spent in databus transfers -system.physmem.avgQLat 6187.65 # Average queueing delay per DRAM burst +system.physmem.avgQLat 6016.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 24937.65 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 885.51 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 24766.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 888.61 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 885.51 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 888.61 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 6.92 # Data bus utilization in percentage -system.physmem.busUtilRead 6.92 # Data bus utilization in percentage for reads +system.physmem.busUtil 6.94 # Data bus utilization in percentage +system.physmem.busUtilRead 6.94 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.22 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 348 # Number of row buffer hits during reads +system.physmem.readRowHits 349 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 82.66 # Row buffer hit rate for reads +system.physmem.readRowHitRate 82.90 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 72057.01 # Average gap between requests -system.physmem.pageHitRate 82.66 # Row buffer hit rate, read and write combined +system.physmem.avgGap 71805.23 # Average gap between requests +system.physmem.pageHitRate 82.90 # Row buffer hit rate, read and write combined system.physmem_0.actEnergy 272160 # Energy for activate commands per rank (pJ) system.physmem_0.preEnergy 148500 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 1934400 # Energy for read commands per rank (pJ) +system.physmem_0.readEnergy 1942200 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1525680 # Energy for refresh commands per rank (pJ) system.physmem_0.actBackEnergy 16099650 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 48750 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 20029140 # Total energy per rank (pJ) -system.physmem_0.averagePower 848.018629 # Core power per rank (mW) +system.physmem_0.totalEnergy 20036940 # Total energy per rank (pJ) +system.physmem_0.averagePower 848.348875 # Core power per rank (mW) system.physmem_0.memoryStateTime::IDLE 12500 # Time in different power states system.physmem_0.memoryStateTime::REF 780000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states @@ -245,19 +245,19 @@ system.physmem_1.actBackEnergy 15437025 # En system.physmem_1.preBackEnergy 630000 # Energy for precharge background per rank (pJ) system.physmem_1.totalEnergy 18485550 # Total energy per rank (pJ) system.physmem_1.averagePower 782.664197 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 2527750 # Time in different power states +system.physmem_1.memoryStateTime::IDLE 2433750 # Time in different power states system.physmem_1.memoryStateTime::REF 780000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states system.physmem_1.memoryStateTime::ACT 21873250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 1927 # Number of BP lookups -system.cpu.branchPred.condPredicted 1154 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 341 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 1597 # Number of BTB lookups -system.cpu.branchPred.BTBHits 326 # Number of BTB hits +system.cpu.branchPred.lookups 1918 # Number of BP lookups +system.cpu.branchPred.condPredicted 1150 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 336 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 1604 # Number of BTB lookups +system.cpu.branchPred.BTBHits 341 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 20.413275 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 222 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 21.259352 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 218 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 16 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -377,44 +377,44 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 60855 # number of cpu cycles simulated +system.cpu.numCycles 60643 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4604 # Number of instructions committed -system.cpu.committedOps 5390 # Number of ops (including micro ops) committed -system.cpu.discardedOps 1118 # Number of ops (including micro ops) which were discarded before commit +system.cpu.committedInsts 4605 # Number of instructions committed +system.cpu.committedOps 5391 # Number of ops (including micro ops) committed +system.cpu.discardedOps 1105 # Number of ops (including micro ops) which were discarded before commit system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching -system.cpu.cpi 13.217854 # CPI: cycles per instruction -system.cpu.ipc 0.075655 # IPC: instructions per cycle -system.cpu.tickCycles 10633 # Number of cycles that the object actually ticked -system.cpu.idleCycles 50222 # Total number of cycles that the object has spent stopped +system.cpu.cpi 13.168947 # CPI: cycles per instruction +system.cpu.ipc 0.075936 # IPC: instructions per cycle +system.cpu.tickCycles 10594 # Number of cycles that the object actually ticked +system.cpu.idleCycles 50049 # Total number of cycles that the object has spent stopped system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 86.476010 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1921 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 86.367225 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1917 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.157534 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.130137 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 86.476010 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021112 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021112 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 86.367225 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021086 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021086 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 37 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::1 108 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4352 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4352 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1053 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1053 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4344 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4344 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1049 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1049 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 846 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 846 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits -system.cpu.dcache.overall_hits::total 1899 # number of overall hits +system.cpu.dcache.demand_hits::cpu.data 1895 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1895 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1895 # number of overall hits +system.cpu.dcache.overall_hits::total 1895 # number of overall hits system.cpu.dcache.ReadReq_misses::cpu.data 115 # number of ReadReq misses system.cpu.dcache.ReadReq_misses::total 115 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 67 # number of WriteReq misses @@ -423,42 +423,42 @@ system.cpu.dcache.demand_misses::cpu.data 182 # n system.cpu.dcache.demand_misses::total 182 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 182 # number of overall misses system.cpu.dcache.overall_misses::total 182 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 7247491 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 7247491 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 7249991 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 7249991 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 5053500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 5053500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12300991 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12300991 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12300991 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12300991 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1168 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1168 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 12303491 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12303491 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12303491 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12303491 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2081 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2081 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2081 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2081 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098459 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.098459 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2077 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2077 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2077 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2077 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098797 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.098797 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.073384 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.073384 # miss rate for WriteReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.087458 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.087458 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.087458 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.087458 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63021.660870 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 63021.660870 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.087626 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.087626 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.087626 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.087626 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63043.400000 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 63043.400000 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 75425.373134 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 75425.373134 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 67587.862637 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 67587.862637 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 67587.862637 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67601.598901 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67601.598901 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67601.598901 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -483,82 +483,82 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 146 system.cpu.dcache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 146 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 146 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6561508 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6561508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6563508 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6563508 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3179250 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3179250 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9740758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 9740758 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9740758 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 9740758 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088185 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088185 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9742758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 9742758 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 9742758 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 9742758 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.088488 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.088488 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.070159 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070159 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.070159 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63703.961165 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63703.961165 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.070294 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.070294 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.070294 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 63723.378641 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 63723.378641 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73936.046512 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73936.046512 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66717.520548 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 66717.520548 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66731.219178 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 66731.219178 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 3 # number of replacements -system.cpu.icache.tags.tagsinuse 161.698962 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1920 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 161.427928 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1909 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 322 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.962733 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.928571 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 161.698962 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.078955 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.078955 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 161.427928 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.078822 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.078822 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 319 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::1 214 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::1 212 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.155762 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4806 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4806 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1920 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1920 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1920 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1920 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1920 # number of overall hits -system.cpu.icache.overall_hits::total 1920 # number of overall hits +system.cpu.icache.tags.tag_accesses 4784 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4784 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1909 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1909 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1909 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1909 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1909 # number of overall hits +system.cpu.icache.overall_hits::total 1909 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 322 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 322 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 322 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 322 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 322 # number of overall misses system.cpu.icache.overall_misses::total 322 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 23941750 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 23941750 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 23941750 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 23941750 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 23941750 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 23941750 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2242 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2242 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2242 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2242 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2242 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2242 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.143622 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.143622 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.143622 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.143622 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.143622 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.143622 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74353.260870 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 74353.260870 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 74353.260870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 74353.260870 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 74353.260870 # average overall miss latency +system.cpu.icache.ReadReq_miss_latency::cpu.inst 23868000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 23868000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 23868000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 23868000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 23868000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 23868000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2231 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2231 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2231 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2231 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2231 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2231 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.144330 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.144330 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.144330 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.144330 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.144330 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.144330 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74124.223602 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 74124.223602 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 74124.223602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 74124.223602 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 74124.223602 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -573,39 +573,39 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 322 system.cpu.icache.demand_mshr_misses::total 322 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 322 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 322 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23324250 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 23324250 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23324250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 23324250 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23324250 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 23324250 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.143622 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.143622 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.143622 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.143622 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72435.559006 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72435.559006 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72435.559006 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 72435.559006 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23250000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 23250000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23250000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 23250000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23250000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 23250000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.144330 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.144330 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.144330 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.144330 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72204.968944 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72204.968944 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72204.968944 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 72204.968944 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 195.346707 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 195.047415 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 378 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.103175 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 154.221063 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 41.125644 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004706 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001255 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005962 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 153.972747 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 41.074668 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004699 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001253 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005952 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 378 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::1 256 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 124 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::1 254 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011536 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 4165 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 4165 # Number of data accesses @@ -629,17 +629,17 @@ system.cpu.l2cache.demand_misses::total 429 # nu system.cpu.l2cache.overall_misses::cpu.inst 305 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 124 # number of overall misses system.cpu.l2cache.overall_misses::total 429 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22823750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6224500 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 29048250 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 22749500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 6226500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 28976000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3136250 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 3136250 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 22823750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 9360750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 32184500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 22823750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 9360750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 32184500 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 22749500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 9362750 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 32112250 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 22749500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9362750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 32112250 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 322 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 103 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 425 # number of ReadReq accesses(hits+misses) @@ -662,17 +662,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.916667 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.947205 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.849315 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.916667 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74831.967213 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76845.679012 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 75254.533679 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74588.524590 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76870.370370 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 75067.357513 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 72936.046512 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 72936.046512 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 75022.144522 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74831.967213 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75489.919355 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 75022.144522 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 74853.729604 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74588.524590 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 75506.048387 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 74853.729604 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -698,17 +698,17 @@ system.cpu.l2cache.demand_mshr_misses::total 421 system.cpu.l2cache.overall_mshr_misses::cpu.inst 305 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.data 116 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 421 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19001750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4779000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23780750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18927000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4781000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23708000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2598750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2598750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19001750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7377750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 26379500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19001750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7377750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 26379500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18927000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7379750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26306750 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18927000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7379750 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26306750 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.708738 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889412 # mshr miss rate for ReadReq accesses @@ -720,17 +720,17 @@ system.cpu.l2cache.demand_mshr_miss_rate::total 0.899573 system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.947205 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.794521 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.899573 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62300.819672 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65465.753425 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62912.037037 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 62055.737705 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65493.150685 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 62719.576720 # average ReadReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 60436.046512 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 60436.046512 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62300.819672 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63601.293103 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62659.144893 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 62055.737705 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63618.534483 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 62486.342043 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 425 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 425 # Transaction distribution @@ -758,7 +758,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 3 # system.cpu.toL2Bus.snoop_fanout::total 468 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 234000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 0.8 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 550250 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 550500 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 1.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 241242 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) @@ -781,9 +781,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 421 # Request fanout histogram -system.membus.reqLayer0.occupancy 490500 # Layer occupancy (ticks) +system.membus.reqLayer0.occupancy 490000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 1.6 # Layer utilization (%) -system.membus.respLayer1.occupancy 2238500 # Layer occupancy (ticks) +system.membus.respLayer1.occupancy 2238750 # Layer occupancy (ticks) system.membus.respLayer1.utilization 7.4 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt index 17ad77afe..94ce3d081 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/stats.txt @@ -1,48 +1,48 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000017 # Number of seconds simulated -sim_ticks 17307500 # Number of ticks simulated -final_tick 17307500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17398000 # Number of ticks simulated +final_tick 17398000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 36602 # Simulator instruction rate (inst/s) -host_op_rate 42863 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 137949898 # Simulator tick rate (ticks/s) -host_mem_usage 239992 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -sim_insts 4591 # Number of instructions simulated -sim_ops 5377 # Number of ops (including micro ops) simulated +host_inst_rate 32773 # Simulator instruction rate (inst/s) +host_op_rate 38377 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 124135140 # Simulator tick rate (ticks/s) +host_mem_usage 303432 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +sim_insts 4592 # Number of instructions simulated +sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17664 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 7744 # Number of bytes read from this memory -system.physmem.bytes_read::total 25408 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 7680 # Number of bytes read from this memory +system.physmem.bytes_read::total 25344 # Number of bytes read from this memory system.physmem.bytes_inst_read::cpu.inst 17664 # Number of instructions bytes read from this memory system.physmem.bytes_inst_read::total 17664 # Number of instructions bytes read from this memory system.physmem.num_reads::cpu.inst 276 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 121 # Number of read requests responded to by this memory -system.physmem.num_reads::total 397 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 1020598007 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 447436083 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1468034089 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 1020598007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 1020598007 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 1020598007 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 447436083 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1468034089 # Total bandwidth to/from this memory (bytes/s) -system.physmem.readReqs 397 # Number of read requests accepted +system.physmem.num_reads::cpu.data 120 # Number of read requests responded to by this memory +system.physmem.num_reads::total 396 # Number of read requests responded to by this memory +system.physmem.bw_read::cpu.inst 1015289114 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 441430049 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1456719163 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 1015289114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 1015289114 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 1015289114 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 441430049 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1456719163 # Total bandwidth to/from this memory (bytes/s) +system.physmem.readReqs 396 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted -system.physmem.readBursts 397 # Number of DRAM read bursts, including those serviced by the write queue +system.physmem.readBursts 396 # Number of DRAM read bursts, including those serviced by the write queue system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue -system.physmem.bytesReadDRAM 25408 # Total number of bytes read from DRAM +system.physmem.bytesReadDRAM 25344 # Total number of bytes read from DRAM system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue system.physmem.bytesWritten 0 # Total number of bytes written to DRAM -system.physmem.bytesReadSys 25408 # Total read bytes from the system interface side +system.physmem.bytesReadSys 25344 # Total read bytes from the system interface side system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write system.physmem.perBankRdBursts::0 90 # Per bank write bursts -system.physmem.perBankRdBursts::1 46 # Per bank write bursts +system.physmem.perBankRdBursts::1 45 # Per bank write bursts system.physmem.perBankRdBursts::2 20 # Per bank write bursts system.physmem.perBankRdBursts::3 43 # Per bank write bursts system.physmem.perBankRdBursts::4 18 # Per bank write bursts @@ -75,14 +75,14 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17240500 # Total gap between requests +system.physmem.totGap 17318000 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) system.physmem.readPktSize::3 0 # Read request sizes (log2) system.physmem.readPktSize::4 0 # Read request sizes (log2) system.physmem.readPktSize::5 0 # Read request sizes (log2) -system.physmem.readPktSize::6 397 # Read request sizes (log2) +system.physmem.readPktSize::6 396 # Read request sizes (log2) system.physmem.writePktSize::0 0 # Write request sizes (log2) system.physmem.writePktSize::1 0 # Write request sizes (log2) system.physmem.writePktSize::2 0 # Write request sizes (log2) @@ -90,10 +90,10 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 209 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 120 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 208 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 118 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see @@ -186,79 +186,79 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 63 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 388.063492 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 254.022879 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 340.382701 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 13 20.63% 20.63% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 16 25.40% 46.03% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 14.29% 60.32% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 7 11.11% 71.43% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 3 4.76% 76.19% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.17% 79.37% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 2 3.17% 82.54% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 1 1.59% 84.13% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 10 15.87% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 63 # Bytes accessed per row activation -system.physmem.totQLat 3336500 # Total ticks spent queuing -system.physmem.totMemAccLat 10780250 # Total ticks spent from burst creation until serviced by the DRAM -system.physmem.totBusLat 1985000 # Total ticks spent in databus transfers -system.physmem.avgQLat 8404.28 # Average queueing delay per DRAM burst +system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 410.033898 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 279.539573 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 339.305882 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 9 15.25% 15.25% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 16 27.12% 42.37% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 8 13.56% 55.93% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 9 15.25% 71.19% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.39% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 2 3.39% 77.97% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 2 3.39% 81.36% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.39% 84.75% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 9 15.25% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation +system.physmem.totQLat 3886750 # Total ticks spent queuing +system.physmem.totMemAccLat 11311750 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.totBusLat 1980000 # Total ticks spent in databus transfers +system.physmem.avgQLat 9815.03 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 27154.28 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1468.03 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 28565.03 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1456.72 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1468.03 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1456.72 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.47 # Data bus utilization in percentage -system.physmem.busUtilRead 11.47 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.38 # Data bus utilization in percentage +system.physmem.busUtilRead 11.38 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes -system.physmem.avgRdQLen 1.85 # Average read queue length when enqueuing +system.physmem.avgRdQLen 1.88 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 330 # Number of row buffer hits during reads +system.physmem.readRowHits 331 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 83.12 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.59 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43426.95 # Average gap between requests -system.physmem.pageHitRate 83.12 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 309960 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 169125 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2074800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43732.32 # Average gap between requests +system.physmem.pageHitRate 83.59 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 287280 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 156750 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2051400 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10792665 # Energy for active background per rank (pJ) -system.physmem_0.preBackEnergy 32250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14395920 # Total energy per rank (pJ) -system.physmem_0.averagePower 909.263856 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 11500 # Time in different power states +system.physmem_0.actBackEnergy 10748205 # Energy for active background per rank (pJ) +system.physmem_0.preBackEnergy 71250 # Energy for precharge background per rank (pJ) +system.physmem_0.totalEnergy 14332005 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.226907 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 62750 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15314750 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15263500 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states -system.physmem_1.actEnergy 151200 # Energy for activate commands per rank (pJ) -system.physmem_1.preEnergy 82500 # Energy for precharge commands per rank (pJ) -system.physmem_1.readEnergy 748800 # Energy for read commands per rank (pJ) +system.physmem_1.actEnergy 143640 # Energy for activate commands per rank (pJ) +system.physmem_1.preEnergy 78375 # Energy for precharge commands per rank (pJ) +system.physmem_1.readEnergy 741000 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10358325 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 414750 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12772695 # Total energy per rank (pJ) -system.physmem_1.averagePower 806.611620 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 897000 # Time in different power states +system.physmem_1.actBackEnergy 10299330 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 465000 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12744465 # Total energy per rank (pJ) +system.physmem_1.averagePower 804.955945 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 732000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14679500 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14594250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2634 # Number of BP lookups -system.cpu.branchPred.condPredicted 1633 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 480 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 2098 # Number of BTB lookups -system.cpu.branchPred.BTBHits 781 # Number of BTB hits +system.cpu.branchPred.lookups 2567 # Number of BP lookups +system.cpu.branchPred.condPredicted 1598 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 469 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 2080 # Number of BTB lookups +system.cpu.branchPred.BTBHits 778 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 37.225929 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 353 # Number of times the RAS was used to get a target. -system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. +system.cpu.branchPred.BTBHitPct 37.403846 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 334 # Number of times the RAS was used to get a target. +system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -377,7 +377,7 @@ system.cpu.checker.itb.hits 0 # DT system.cpu.checker.itb.misses 0 # DTB misses system.cpu.checker.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.checker.numCycles 5390 # number of cpu cycles simulated +system.cpu.checker.numCycles 5391 # number of cpu cycles simulated system.cpu.checker.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.checker.numWorkItemsCompleted 0 # number of work items this cpu completed system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -496,273 +496,273 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 34616 # number of cpu cycles simulated +system.cpu.numCycles 34797 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 7775 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 12462 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2634 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 1134 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 4935 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1009 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs -system.cpu.fetch.PendingTrapStallCycles 273 # Number of stall cycles due to pending traps -system.cpu.fetch.IcacheWaitRetryStallCycles 30 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 2063 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 315 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 13520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 1.090163 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 2.470015 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.icacheStallCycles 7703 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 12168 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2567 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 1112 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 4777 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 987 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.PendingTrapStallCycles 251 # Number of stall cycles due to pending traps +system.cpu.fetch.IcacheWaitRetryStallCycles 17 # Number of stall cycles due to full MSHR +system.cpu.fetch.CacheLines 2007 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 13242 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 1.084202 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 2.460827 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 10832 80.12% 80.12% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 265 1.96% 82.08% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 242 1.79% 83.87% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 236 1.75% 85.61% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::4 238 1.76% 87.37% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::5 290 2.14% 89.52% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::6 142 1.05% 90.57% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::7 172 1.27% 91.84% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::8 1103 8.16% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 10620 80.20% 80.20% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 274 2.07% 82.27% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 209 1.58% 83.85% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 222 1.68% 85.52% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::4 233 1.76% 87.28% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::5 323 2.44% 89.72% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::6 137 1.03% 90.76% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::7 162 1.22% 91.98% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::8 1062 8.02% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 13520 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.076092 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.360007 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 6427 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4469 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 2141 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 135 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 348 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 390 # Number of times decode resolved a branch -system.cpu.decode.BranchMispred 163 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 12076 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 476 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 348 # Number of cycles rename is squashing -system.cpu.rename.IdleCycles 6634 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 859 # Number of cycles rename is blocking -system.cpu.rename.serializeStallCycles 2379 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 2057 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 1243 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 11433 # Number of instructions processed by rename -system.cpu.rename.IQFullEvents 177 # Number of times rename has blocked due to IQ full +system.cpu.fetch.rateDist::total 13242 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.073771 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.349685 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 6338 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 4330 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 2103 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 133 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 338 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 384 # Number of times decode resolved a branch +system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction +system.cpu.decode.DecodedInsts 11850 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 468 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 338 # Number of cycles rename is squashing +system.cpu.rename.IdleCycles 6554 # Number of cycles rename is idle +system.cpu.rename.BlockCycles 692 # Number of cycles rename is blocking +system.cpu.rename.serializeStallCycles 2396 # count of cycles rename stalled for serializing inst +system.cpu.rename.RunCycles 2012 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 1250 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 11194 # Number of instructions processed by rename +system.cpu.rename.IQFullEvents 171 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 132 # Number of times rename has blocked due to LQ full -system.cpu.rename.SQFullEvents 1054 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 11789 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 52593 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 12687 # Number of integer rename lookups +system.cpu.rename.SQFullEvents 1066 # Number of times rename has blocked due to SQ full +system.cpu.rename.RenamedOperands 11323 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 51655 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 12441 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 88 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 6295 # Number of HB maps that are undone due to squashing -system.cpu.rename.serializingInsts 43 # count of serializing insts renamed -system.cpu.rename.tempSerializingInsts 37 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 434 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 2310 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1632 # Number of stores inserted to the mem dependence unit. -system.cpu.memDep0.conflictingLoads 32 # Number of conflicting loads. -system.cpu.memDep0.conflictingStores 28 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 10336 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.rename.UndoneMaps 5829 # Number of HB maps that are undone due to squashing +system.cpu.rename.serializingInsts 42 # count of serializing insts renamed +system.cpu.rename.tempSerializingInsts 36 # count of temporary serializing insts renamed +system.cpu.rename.skidInsts 409 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 2284 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1689 # Number of stores inserted to the mem dependence unit. +system.cpu.memDep0.conflictingLoads 38 # Number of conflicting loads. +system.cpu.memDep0.conflictingStores 34 # Number of conflicting stores. +system.cpu.iq.iqInstsAdded 10118 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 46 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 8345 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 56 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 5005 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 12819 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 8189 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 54 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 4786 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 12366 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 9 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 13520 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.617234 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 1.373407 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 13242 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.618411 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 1.365218 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 10276 76.01% 76.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1181 8.74% 84.74% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 737 5.45% 90.19% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 452 3.34% 93.54% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 368 2.72% 96.26% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::5 283 2.09% 98.35% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::6 137 1.01% 99.36% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::7 63 0.47% 99.83% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::8 23 0.17% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10034 75.77% 75.77% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1166 8.81% 84.58% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 746 5.63% 90.21% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 448 3.38% 93.60% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 359 2.71% 96.31% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::5 279 2.11% 98.41% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::6 131 0.99% 99.40% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::7 62 0.47% 99.87% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 13520 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 13242 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 9 5.33% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.33% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 80 47.34% 52.66% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 80 47.34% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 9 5.20% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 5.20% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 84 48.55% 53.76% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 80 46.24% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 5033 60.31% 60.31% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.38% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.42% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 2011 24.10% 84.52% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1292 15.48% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4931 60.21% 60.21% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 6 0.07% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.29% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 60.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.32% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.32% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1952 23.84% 84.16% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1297 15.84% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 8345 # Type of FU issued -system.cpu.iq.rate 0.241073 # Inst issue rate -system.cpu.iq.fu_busy_cnt 169 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.020252 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 30336 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 15278 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 7551 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 8189 # Type of FU issued +system.cpu.iq.rate 0.235336 # Inst issue rate +system.cpu.iq.fu_busy_cnt 173 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.021126 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 29748 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 14841 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 7422 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 99 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 128 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 32 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8471 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8319 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 43 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 25 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 24 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 1257 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 19 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 694 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 751 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding -system.cpu.iew.lsq.thread0.rescheduledLoads 39 # Number of loads that were rescheduled -system.cpu.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked +system.cpu.iew.lsq.thread0.rescheduledLoads 32 # Number of loads that were rescheduled +system.cpu.iew.lsq.thread0.cacheBlocked 4 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 348 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 819 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 18 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 10393 # Number of instructions dispatched to IQ -system.cpu.iew.iewDispSquashedInsts 110 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 2310 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1632 # Number of dispatched store instructions +system.cpu.iew.iewSquashCycles 338 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 662 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 13 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 10173 # Number of instructions dispatched to IQ +system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch +system.cpu.iew.iewDispLoadInsts 2284 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1689 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 34 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 14 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 10 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 2 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 19 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 112 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 251 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 363 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 8047 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1910 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 298 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 111 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 233 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 344 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 7858 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1841 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 331 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed -system.cpu.iew.exec_nop 11 # number of nop insts executed -system.cpu.iew.exec_refs 3142 # number of memory reference insts executed -system.cpu.iew.exec_branches 1452 # Number of branches executed -system.cpu.iew.exec_stores 1232 # Number of stores executed -system.cpu.iew.exec_rate 0.232465 # Inst execution rate -system.cpu.iew.wb_sent 7714 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 7583 # cumulative count of insts written-back -system.cpu.iew.wb_producers 3567 # num instructions producing a value -system.cpu.iew.wb_consumers 6985 # num instructions consuming a value +system.cpu.iew.exec_nop 9 # number of nop insts executed +system.cpu.iew.exec_refs 3070 # number of memory reference insts executed +system.cpu.iew.exec_branches 1431 # Number of branches executed +system.cpu.iew.exec_stores 1229 # Number of stores executed +system.cpu.iew.exec_rate 0.225824 # Inst execution rate +system.cpu.iew.wb_sent 7567 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 7454 # cumulative count of insts written-back +system.cpu.iew.wb_producers 3520 # num instructions producing a value +system.cpu.iew.wb_consumers 6887 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.219061 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.510666 # average fanout of values written-back +system.cpu.iew.wb_rate 0.214214 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.511108 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 5019 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 4794 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 324 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 12644 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.425261 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.266647 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 314 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 12404 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.433570 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.280415 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 10588 83.74% 83.74% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 887 7.02% 90.75% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 425 3.36% 94.12% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 213 1.68% 95.80% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 117 0.93% 96.73% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 214 1.69% 98.42% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 50 0.40% 98.81% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 37 0.29% 99.11% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 113 0.89% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 10350 83.44% 83.44% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 890 7.18% 90.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 420 3.39% 94.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 213 1.72% 95.72% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 118 0.95% 96.67% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 211 1.70% 98.37% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 49 0.40% 98.77% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 36 0.29% 99.06% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 117 0.94% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 12644 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4591 # Number of instructions committed -system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 12404 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4592 # Number of instructions committed +system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1965 # Number of memory references committed system.cpu.commit.loads 1027 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1007 # Number of branches committed +system.cpu.commit.branches 1008 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4624 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction @@ -771,122 +771,122 @@ system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Cl system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5377 # Class of committed instruction -system.cpu.commit.bw_lim_events 113 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22770 # The number of ROB reads -system.cpu.rob.rob_writes 21679 # The number of ROB writes -system.cpu.timesIdled 199 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 21096 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4591 # Number of Instructions Simulated -system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.539970 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.539970 # CPI: Total CPI of All Threads -system.cpu.ipc 0.132627 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.132627 # IPC: Total IPC of All Threads -system.cpu.int_regfile_reads 7923 # number of integer regfile reads -system.cpu.int_regfile_writes 4408 # number of integer regfile writes +system.cpu.commit.op_class_0::total 5378 # Class of committed instruction +system.cpu.commit.bw_lim_events 117 # number cycles where commit BW limit reached +system.cpu.rob.rob_reads 22302 # The number of ROB reads +system.cpu.rob.rob_writes 21197 # The number of ROB writes +system.cpu.timesIdled 195 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 21555 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4592 # Number of Instructions Simulated +system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.577744 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.577744 # CPI: Total CPI of All Threads +system.cpu.ipc 0.131965 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.131965 # IPC: Total IPC of All Threads +system.cpu.int_regfile_reads 7744 # number of integer regfile reads +system.cpu.int_regfile_writes 4257 # number of integer regfile writes system.cpu.fp_regfile_reads 32 # number of floating regfile reads -system.cpu.cc_regfile_reads 28677 # number of cc regfile reads -system.cpu.cc_regfile_writes 3298 # number of cc regfile writes -system.cpu.misc_regfile_reads 3185 # number of misc regfile reads +system.cpu.cc_regfile_reads 28092 # number of cc regfile reads +system.cpu.cc_regfile_writes 3277 # number of cc regfile writes +system.cpu.misc_regfile_reads 3176 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 87.291293 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 2178 # Total number of references to valid blocks. -system.cpu.dcache.tags.sampled_refs 146 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 14.917808 # Average number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 87.050512 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 2159 # Total number of references to valid blocks. +system.cpu.dcache.tags.sampled_refs 147 # Sample count of references to valid blocks. +system.cpu.dcache.tags.avg_refs 14.687075 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 87.291293 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.021311 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.021311 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_task_id_blocks::1024 146 # Occupied blocks per task id -system.cpu.dcache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id +system.cpu.dcache.tags.occ_blocks::cpu.data 87.050512 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.021253 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.021253 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_task_id_blocks::1024 147 # Occupied blocks per task id +system.cpu.dcache.tags.age_task_id_blocks_1024::0 57 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 # Occupied blocks per task id -system.cpu.dcache.tags.occ_task_id_percent::1024 0.035645 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 5532 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 5532 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1558 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1558 # number of ReadReq hits +system.cpu.dcache.tags.occ_task_id_percent::1024 0.035889 # Percentage of cache occupancy per task id +system.cpu.dcache.tags.tag_accesses 5463 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 5463 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1539 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1539 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 598 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 598 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 2156 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 2156 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 2156 # number of overall hits -system.cpu.dcache.overall_hits::total 2156 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 198 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 198 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 2137 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 2137 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 2137 # number of overall hits +system.cpu.dcache.overall_hits::total 2137 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 182 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 182 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 315 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 315 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 513 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 513 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 513 # number of overall misses -system.cpu.dcache.overall_misses::total 513 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 12309993 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 12309993 # number of ReadReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::cpu.data 22746000 # number of WriteReq miss cycles -system.cpu.dcache.WriteReq_miss_latency::total 22746000 # number of WriteReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 497 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 497 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 497 # number of overall misses +system.cpu.dcache.overall_misses::total 497 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 10876493 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 10876493 # number of ReadReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::cpu.data 22731000 # number of WriteReq miss cycles +system.cpu.dcache.WriteReq_miss_latency::total 22731000 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 144500 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 144500 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 35055993 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 35055993 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 35055993 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 35055993 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1756 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1756 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 33607493 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 33607493 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 33607493 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 33607493 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1721 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1721 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 13 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2669 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2669 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2669 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2669 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.112756 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.112756 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2634 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2634 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2634 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2634 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.105752 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.105752 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.345016 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.345016 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.153846 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.153846 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.192207 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.192207 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.192207 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.192207 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62171.681818 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 62171.681818 # average ReadReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72209.523810 # average WriteReq miss latency -system.cpu.dcache.WriteReq_avg_miss_latency::total 72209.523810 # average WriteReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.188686 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.188686 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.188686 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.188686 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 59760.950549 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 59760.950549 # average ReadReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 72161.904762 # average WriteReq miss latency +system.cpu.dcache.WriteReq_avg_miss_latency::total 72161.904762 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 72250 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 72250 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 68335.269006 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 68335.269006 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 68335.269006 # average overall miss latency -system.cpu.dcache.blocked_cycles::no_mshrs 129 # number of cycles access was blocked +system.cpu.dcache.demand_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 67620.710262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 67620.710262 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 67620.710262 # average overall miss latency +system.cpu.dcache.blocked_cycles::no_mshrs 125 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu.dcache.blocked::no_mshrs 2 # number of cycles access was blocked system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.dcache.avg_blocked_cycles::no_mshrs 43 # average number of cycles each access was blocked +system.cpu.dcache.avg_blocked_cycles::no_mshrs 62.500000 # average number of cycles each access was blocked system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 93 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 93 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 273 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 273 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 366 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 366 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 366 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 105 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 42 # number of WriteReq MSHR misses @@ -895,202 +895,202 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 147 system.cpu.dcache.demand_mshr_misses::total 147 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 147 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 147 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6906505 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6906505 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6879255 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 6879255 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3390500 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 3390500 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10297005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 10297005 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10297005 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 10297005 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.059795 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.059795 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10269755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 10269755 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10269755 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 10269755 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.061011 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.061011 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.046002 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.046002 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.055077 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055077 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.055077 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65776.238095 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65776.238095 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.055809 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.055809 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.055809 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 65516.714286 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 65516.714286 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80726.190476 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80726.190476 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70047.653061 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 70047.653061 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 69862.278912 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 69862.278912 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 149.998434 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 1659 # Total number of references to valid blocks. -system.cpu.icache.tags.sampled_refs 294 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 5.642857 # Average number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 149.166565 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. +system.cpu.icache.tags.sampled_refs 293 # Sample count of references to valid blocks. +system.cpu.icache.tags.avg_refs 5.505119 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 149.998434 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.073241 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.073241 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_task_id_blocks::1024 293 # Occupied blocks per task id -system.cpu.icache.tags.age_task_id_blocks_1024::0 169 # Occupied blocks per task id +system.cpu.icache.tags.occ_blocks::cpu.inst 149.166565 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.072835 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.072835 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_task_id_blocks::1024 292 # Occupied blocks per task id +system.cpu.icache.tags.age_task_id_blocks_1024::0 168 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 124 # Occupied blocks per task id -system.cpu.icache.tags.occ_task_id_percent::1024 0.143066 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 4420 # Number of tag accesses -system.cpu.icache.tags.data_accesses 4420 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 1659 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 1659 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 1659 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 1659 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 1659 # number of overall hits -system.cpu.icache.overall_hits::total 1659 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 404 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 404 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 404 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 404 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 404 # number of overall misses -system.cpu.icache.overall_misses::total 404 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 28289500 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 28289500 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 28289500 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 28289500 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 28289500 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 28289500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 2063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 2063 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 2063 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 2063 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 2063 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.195831 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.195831 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.195831 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.195831 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.195831 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.195831 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70023.514851 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 70023.514851 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 70023.514851 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 70023.514851 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 70023.514851 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 361 # number of cycles access was blocked +system.cpu.icache.tags.occ_task_id_percent::1024 0.142578 # Percentage of cache occupancy per task id +system.cpu.icache.tags.tag_accesses 4307 # Number of tag accesses +system.cpu.icache.tags.data_accesses 4307 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits +system.cpu.icache.overall_hits::total 1613 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 394 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 394 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 394 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 394 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 394 # number of overall misses +system.cpu.icache.overall_misses::total 394 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 28003250 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 28003250 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 28003250 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 28003250 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 28003250 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 28003250 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 2007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 2007 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 2007 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 2007 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 2007 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 2007 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.196313 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.196313 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.196313 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.196313 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.196313 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.196313 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 71074.238579 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 71074.238579 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 71074.238579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 71074.238579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 71074.238579 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 456 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 72.200000 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 91.200000 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 110 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 110 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 110 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 110 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 110 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 110 # number of overall MSHR hits -system.cpu.icache.ReadReq_mshr_misses::cpu.inst 294 # number of ReadReq MSHR misses -system.cpu.icache.ReadReq_mshr_misses::total 294 # number of ReadReq MSHR misses -system.cpu.icache.demand_mshr_misses::cpu.inst 294 # number of demand (read+write) MSHR misses -system.cpu.icache.demand_mshr_misses::total 294 # number of demand (read+write) MSHR misses -system.cpu.icache.overall_mshr_misses::cpu.inst 294 # number of overall MSHR misses -system.cpu.icache.overall_mshr_misses::total 294 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21612000 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 21612000 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21612000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 21612000 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21612000 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 21612000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.142511 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.142511 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.142511 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.142511 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 73510.204082 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 73510.204082 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 73510.204082 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 73510.204082 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses +system.cpu.icache.ReadReq_mshr_misses::total 293 # number of ReadReq MSHR misses +system.cpu.icache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses +system.cpu.icache.demand_mshr_misses::total 293 # number of demand (read+write) MSHR misses +system.cpu.icache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses +system.cpu.icache.overall_mshr_misses::total 293 # number of overall MSHR misses +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 22179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 22179000 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 22179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 22179000 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 22179000 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 22179000 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.145989 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.145989 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.145989 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.145989 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 75696.245734 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 75696.245734 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 75696.245734 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 75696.245734 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 186.994376 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 186.073007 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 39 # Total number of references to valid blocks. -system.cpu.l2cache.tags.sampled_refs 355 # Sample count of references to valid blocks. -system.cpu.l2cache.tags.avg_refs 0.109859 # Average number of references to valid blocks. +system.cpu.l2cache.tags.sampled_refs 354 # Sample count of references to valid blocks. +system.cpu.l2cache.tags.avg_refs 0.110169 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.852442 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 46.141935 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004298 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.001408 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.005707 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_task_id_blocks::1024 355 # Occupied blocks per task id -system.cpu.l2cache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id +system.cpu.l2cache.tags.occ_blocks::cpu.inst 140.074126 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.998881 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004275 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.001404 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.005678 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_task_id_blocks::1024 354 # Occupied blocks per task id +system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::1 161 # Occupied blocks per task id -system.cpu.l2cache.tags.occ_task_id_percent::1024 0.010834 # Percentage of cache occupancy per task id -system.cpu.l2cache.tags.tag_accesses 3925 # Number of tag accesses -system.cpu.l2cache.tags.data_accesses 3925 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 18 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 21 # 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number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 21706000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 9885750 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 31591750 # number of overall miss cycles +system.cpu.l2cache.ReadReq_accesses::cpu.inst 293 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 105 # number of ReadReq accesses(hits+misses) -system.cpu.l2cache.ReadReq_accesses::total 399 # number of ReadReq accesses(hits+misses) +system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::cpu.data 42 # number of ReadExReq accesses(hits+misses) system.cpu.l2cache.ReadExReq_accesses::total 42 # number of ReadExReq accesses(hits+misses) -system.cpu.l2cache.demand_accesses::cpu.inst 294 # number of demand (read+write) accesses +system.cpu.l2cache.demand_accesses::cpu.inst 293 # number of demand (read+write) accesses system.cpu.l2cache.demand_accesses::cpu.data 147 # number of demand (read+write) accesses -system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses -system.cpu.l2cache.overall_accesses::cpu.inst 294 # number of overall (read+write) accesses +system.cpu.l2cache.demand_accesses::total 440 # number of demand (read+write) accesses +system.cpu.l2cache.overall_accesses::cpu.inst 293 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 147 # number of overall (read+write) accesses -system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.938776 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.800000 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::total 0.902256 # miss rate for ReadReq accesses +system.cpu.l2cache.overall_accesses::total 440 # number of overall (read+write) accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.941980 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.790476 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::total 0.902010 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.938776 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.857143 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::total 0.911565 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.938776 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.857143 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::total 0.911565 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 76548.913043 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79127.976190 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 77150.694444 # average ReadReq miss latency +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.941980 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.850340 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::total 0.911364 # miss rate for demand accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.941980 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.850340 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::total 0.911364 # miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78644.927536 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 78786.144578 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 78677.576602 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79678.571429 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79678.571429 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 77414.800995 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 76548.913043 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79311.507937 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 77414.800995 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79086 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 78782.418953 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78644.927536 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79086 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 78782.418953 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1106,62 +1106,62 @@ system.cpu.l2cache.demand_mshr_hits::total 5 # system.cpu.l2cache.overall_mshr_hits::cpu.data 5 # number of overall MSHR hits system.cpu.l2cache.overall_mshr_hits::total 5 # number of overall MSHR hits system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 276 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 79 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::total 355 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 78 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::total 354 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 42 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 42 # number of ReadExReq MSHR misses system.cpu.l2cache.demand_mshr_misses::cpu.inst 276 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 121 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::total 397 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 120 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::total 396 # number of demand (read+write) MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.inst 276 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 121 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::total 397 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 17683000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5328000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23011000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 17683000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8152000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 25835000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 17683000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8152000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 25835000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.752381 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889724 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.overall_mshr_misses::cpu.data 120 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::total 396 # number of overall MSHR misses +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 18264000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5236000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 23500000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2824500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2824500 # number of ReadExReq MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 18264000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8060500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 26324500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 18264000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8060500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 26324500 # number of overall MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.742857 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.889447 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::total 0.900227 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.938776 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.823129 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::total 0.900227 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 64068.840580 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67443.037975 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 64819.718310 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67238.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67238.095238 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 64068.840580 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67371.900826 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 65075.566751 # average overall mshr miss latency +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::total 0.900000 # mshr miss rate for demand accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.941980 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.816327 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::total 0.900000 # mshr miss rate for overall accesses +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66173.913043 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67128.205128 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 66384.180791 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67250 # average ReadExReq mshr miss latency +system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67250 # average ReadExReq mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66173.913043 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67170.833333 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 66476.010101 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu.toL2Bus.trans_dist::ReadReq 399 # Transaction distribution +system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExReq 42 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadExResp 42 # Transaction distribution -system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 588 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 293 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_count::total 881 # Packet count per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18816 # Cumulative packet size per connected master and slave (bytes) -system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9344 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 586 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 294 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_count::total 880 # Packet count per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18752 # Cumulative packet size per connected master and slave (bytes) +system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9408 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.pkt_size::total 28160 # Cumulative packet size per connected master and slave (bytes) system.cpu.toL2Bus.snoops 0 # Total snoops (count) -system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::samples 440 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::mean 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram @@ -1170,40 +1170,40 @@ system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Re system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::5 441 100.00% 100.00% # Request fanout histogram +system.cpu.toL2Bus.snoop_fanout::5 440 100.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::6 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram system.cpu.toL2Bus.snoop_fanout::max_value 5 # Request fanout histogram -system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram -system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) +system.cpu.toL2Bus.snoop_fanout::total 440 # Request fanout histogram +system.cpu.toL2Bus.reqLayer0.occupancy 220000 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.3 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 495000 # Layer occupancy (ticks) -system.cpu.toL2Bus.respLayer0.utilization 2.9 # Layer utilization (%) -system.cpu.toL2Bus.respLayer1.occupancy 238495 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 493000 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) +system.cpu.toL2Bus.respLayer1.occupancy 239245 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%) -system.membus.trans_dist::ReadReq 355 # Transaction distribution -system.membus.trans_dist::ReadResp 355 # Transaction distribution +system.membus.trans_dist::ReadReq 354 # Transaction distribution +system.membus.trans_dist::ReadResp 354 # Transaction distribution system.membus.trans_dist::ReadExReq 42 # Transaction distribution system.membus.trans_dist::ReadExResp 42 # Transaction distribution -system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 794 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25408 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 25408 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_count::total 792 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 25344 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 25344 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 397 # Request fanout histogram +system.membus.snoop_fanout::samples 396 # Request fanout histogram system.membus.snoop_fanout::mean 0 # Request fanout histogram system.membus.snoop_fanout::stdev 0 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::0 397 100.00% 100.00% # Request fanout histogram +system.membus.snoop_fanout::0 396 100.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram -system.membus.snoop_fanout::total 397 # Request fanout histogram -system.membus.reqLayer0.occupancy 499500 # Layer occupancy (ticks) +system.membus.snoop_fanout::total 396 # Request fanout histogram +system.membus.reqLayer0.occupancy 497000 # Layer occupancy (ticks) system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) -system.membus.respLayer1.occupancy 2102000 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 12.1 # Layer utilization (%) +system.membus.respLayer1.occupancy 2092000 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt index 69573f93c..a58641eea 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000018 # Number of seconds simulated -sim_ticks 17911000 # Number of ticks simulated -final_tick 17911000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 17788000 # Number of ticks simulated +final_tick 17788000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 35404 # Simulator instruction rate (inst/s) -host_op_rate 41460 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 138087840 # Simulator tick rate (ticks/s) -host_mem_usage 236512 # Number of bytes of host memory used -host_seconds 0.13 # Real time elapsed on the host -sim_insts 4591 # Number of instructions simulated -sim_ops 5377 # Number of ops (including micro ops) simulated +host_inst_rate 23007 # Simulator instruction rate (inst/s) +host_op_rate 26942 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 89104120 # Simulator tick rate (ticks/s) +host_mem_usage 300104 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +sim_insts 4592 # Number of instructions simulated +sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 17344 # Number of bytes read from this memory @@ -23,16 +23,16 @@ system.physmem.num_reads::cpu.inst 271 # Nu system.physmem.num_reads::cpu.data 108 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.l2cache.prefetcher 27 # Number of read requests responded to by this memory system.physmem.num_reads::total 406 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 968343476 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 385908101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.l2cache.prefetcher 96477025 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 1450728603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 968343476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 968343476 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 968343476 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 385908101 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.l2cache.prefetcher 96477025 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 1450728603 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 975039352 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 388576568 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.l2cache.prefetcher 97144142 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 1460760063 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 975039352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 975039352 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 975039352 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 388576568 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.l2cache.prefetcher 97144142 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 1460760063 # Total bandwidth to/from this memory (bytes/s) system.physmem.readReqs 407 # Number of read requests accepted system.physmem.writeReqs 0 # Number of write requests accepted system.physmem.readBursts 407 # Number of DRAM read bursts, including those serviced by the write queue @@ -79,7 +79,7 @@ system.physmem.perBankWrBursts::14 0 # Pe system.physmem.perBankWrBursts::15 0 # Per bank write bursts system.physmem.numRdRetry 0 # Number of times read queue was full causing retry system.physmem.numWrRetry 0 # Number of times write queue was full causing retry -system.physmem.totGap 17897500 # Total gap between requests +system.physmem.totGap 17774500 # Total gap between requests system.physmem.readPktSize::0 0 # Read request sizes (log2) system.physmem.readPktSize::1 0 # Read request sizes (log2) system.physmem.readPktSize::2 0 # Read request sizes (log2) @@ -94,8 +94,8 @@ system.physmem.writePktSize::3 0 # Wr system.physmem.writePktSize::4 0 # Write request sizes (log2) system.physmem.writePktSize::5 0 # Write request sizes (log2) system.physmem.writePktSize::6 0 # Write request sizes (log2) -system.physmem.rdQLenPdf::0 225 # What read queue length does an incoming req see -system.physmem.rdQLenPdf::1 125 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::0 226 # What read queue length does an incoming req see +system.physmem.rdQLenPdf::1 124 # What read queue length does an incoming req see system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see system.physmem.rdQLenPdf::3 13 # What read queue length does an incoming req see system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see @@ -190,78 +190,78 @@ system.physmem.wrQLenPdf::60 0 # Wh system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see -system.physmem.bytesPerActivate::samples 57 # Bytes accessed per row activation -system.physmem.bytesPerActivate::mean 433.403509 # Bytes accessed per row activation -system.physmem.bytesPerActivate::gmean 294.791776 # Bytes accessed per row activation -system.physmem.bytesPerActivate::stdev 356.955773 # Bytes accessed per row activation -system.physmem.bytesPerActivate::0-127 6 10.53% 10.53% # Bytes accessed per row activation -system.physmem.bytesPerActivate::128-255 19 33.33% 43.86% # Bytes accessed per row activation -system.physmem.bytesPerActivate::256-383 9 15.79% 59.65% # Bytes accessed per row activation -system.physmem.bytesPerActivate::384-511 3 5.26% 64.91% # Bytes accessed per row activation -system.physmem.bytesPerActivate::512-639 2 3.51% 68.42% # Bytes accessed per row activation -system.physmem.bytesPerActivate::640-767 2 3.51% 71.93% # Bytes accessed per row activation -system.physmem.bytesPerActivate::768-895 4 7.02% 78.95% # Bytes accessed per row activation -system.physmem.bytesPerActivate::896-1023 3 5.26% 84.21% # Bytes accessed per row activation -system.physmem.bytesPerActivate::1024-1151 9 15.79% 100.00% # Bytes accessed per row activation -system.physmem.bytesPerActivate::total 57 # Bytes accessed per row activation -system.physmem.totQLat 3190492 # Total ticks spent queuing -system.physmem.totMemAccLat 10821742 # Total ticks spent from burst creation until serviced by the DRAM +system.physmem.bytesPerActivate::samples 59 # Bytes accessed per row activation +system.physmem.bytesPerActivate::mean 419.796610 # Bytes accessed per row activation +system.physmem.bytesPerActivate::gmean 279.431145 # Bytes accessed per row activation +system.physmem.bytesPerActivate::stdev 356.786751 # Bytes accessed per row activation +system.physmem.bytesPerActivate::0-127 8 13.56% 13.56% # Bytes accessed per row activation +system.physmem.bytesPerActivate::128-255 19 32.20% 45.76% # Bytes accessed per row activation +system.physmem.bytesPerActivate::256-383 9 15.25% 61.02% # Bytes accessed per row activation +system.physmem.bytesPerActivate::384-511 3 5.08% 66.10% # Bytes accessed per row activation +system.physmem.bytesPerActivate::512-639 2 3.39% 69.49% # Bytes accessed per row activation +system.physmem.bytesPerActivate::640-767 3 5.08% 74.58% # Bytes accessed per row activation +system.physmem.bytesPerActivate::768-895 3 5.08% 79.66% # Bytes accessed per row activation +system.physmem.bytesPerActivate::896-1023 2 3.39% 83.05% # Bytes accessed per row activation +system.physmem.bytesPerActivate::1024-1151 10 16.95% 100.00% # Bytes accessed per row activation +system.physmem.bytesPerActivate::total 59 # Bytes accessed per row activation +system.physmem.totQLat 3111242 # Total ticks spent queuing +system.physmem.totMemAccLat 10742492 # Total ticks spent from burst creation until serviced by the DRAM system.physmem.totBusLat 2035000 # Total ticks spent in databus transfers -system.physmem.avgQLat 7839.05 # Average queueing delay per DRAM burst +system.physmem.avgQLat 7644.33 # Average queueing delay per DRAM burst system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst -system.physmem.avgMemAccLat 26589.05 # Average memory access latency per DRAM burst -system.physmem.avgRdBW 1454.30 # Average DRAM read bandwidth in MiByte/s +system.physmem.avgMemAccLat 26394.33 # Average memory access latency per DRAM burst +system.physmem.avgRdBW 1464.36 # Average DRAM read bandwidth in MiByte/s system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s -system.physmem.avgRdBWSys 1454.30 # Average system read bandwidth in MiByte/s +system.physmem.avgRdBWSys 1464.36 # Average system read bandwidth in MiByte/s system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s -system.physmem.busUtil 11.36 # Data bus utilization in percentage -system.physmem.busUtilRead 11.36 # Data bus utilization in percentage for reads +system.physmem.busUtil 11.44 # Data bus utilization in percentage +system.physmem.busUtilRead 11.44 # Data bus utilization in percentage for reads system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing -system.physmem.readRowHits 342 # Number of row buffer hits during reads +system.physmem.readRowHits 340 # Number of row buffer hits during reads system.physmem.writeRowHits 0 # Number of row buffer hits during writes -system.physmem.readRowHitRate 84.03 # Row buffer hit rate for reads +system.physmem.readRowHitRate 83.54 # Row buffer hit rate for reads system.physmem.writeRowHitRate nan # Row buffer hit rate for writes -system.physmem.avgGap 43974.20 # Average gap between requests -system.physmem.pageHitRate 84.03 # Row buffer hit rate, read and write combined -system.physmem_0.actEnergy 279720 # Energy for activate commands per rank (pJ) -system.physmem_0.preEnergy 152625 # Energy for precharge commands per rank (pJ) -system.physmem_0.readEnergy 2035800 # Energy for read commands per rank (pJ) +system.physmem.avgGap 43671.99 # Average gap between requests +system.physmem.pageHitRate 83.54 # Row buffer hit rate, read and write combined +system.physmem_0.actEnergy 294840 # Energy for activate commands per rank (pJ) +system.physmem_0.preEnergy 160875 # Energy for precharge commands per rank (pJ) +system.physmem_0.readEnergy 2043600 # Energy for read commands per rank (pJ) system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_0.actBackEnergy 10796085 # Energy for active background per rank (pJ) +system.physmem_0.actBackEnergy 10829430 # Energy for active background per rank (pJ) system.physmem_0.preBackEnergy 29250 # Energy for precharge background per rank (pJ) -system.physmem_0.totalEnergy 14310600 # Total energy per rank (pJ) -system.physmem_0.averagePower 903.874941 # Core power per rank (mW) -system.physmem_0.memoryStateTime::IDLE 7000 # Time in different power states +system.physmem_0.totalEnergy 14375115 # Total energy per rank (pJ) +system.physmem_0.averagePower 905.162692 # Core power per rank (mW) +system.physmem_0.memoryStateTime::IDLE 243500 # Time in different power states system.physmem_0.memoryStateTime::REF 520000 # Time in different power states system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_0.memoryStateTime::ACT 15319250 # Time in different power states +system.physmem_0.memoryStateTime::ACT 15368000 # Time in different power states system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states system.physmem_1.actEnergy 128520 # Energy for activate commands per rank (pJ) system.physmem_1.preEnergy 70125 # Energy for precharge commands per rank (pJ) system.physmem_1.readEnergy 795600 # Energy for read commands per rank (pJ) system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) -system.physmem_1.actBackEnergy 10067625 # Energy for active background per rank (pJ) -system.physmem_1.preBackEnergy 668250 # Energy for precharge background per rank (pJ) -system.physmem_1.totalEnergy 12747240 # Total energy per rank (pJ) -system.physmem_1.averagePower 805.131217 # Core power per rank (mW) -system.physmem_1.memoryStateTime::IDLE 1195750 # Time in different power states +system.physmem_1.actBackEnergy 10100115 # Energy for active background per rank (pJ) +system.physmem_1.preBackEnergy 639750 # Energy for precharge background per rank (pJ) +system.physmem_1.totalEnergy 12751230 # Total energy per rank (pJ) +system.physmem_1.averagePower 805.383231 # Core power per rank (mW) +system.physmem_1.memoryStateTime::IDLE 1024000 # Time in different power states system.physmem_1.memoryStateTime::REF 520000 # Time in different power states system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states -system.physmem_1.memoryStateTime::ACT 14254250 # Time in different power states +system.physmem_1.memoryStateTime::ACT 14302250 # Time in different power states system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states -system.cpu.branchPred.lookups 2361 # Number of BP lookups -system.cpu.branchPred.condPredicted 1410 # Number of conditional branches predicted -system.cpu.branchPred.condIncorrect 506 # Number of conditional branches incorrect -system.cpu.branchPred.BTBLookups 871 # Number of BTB lookups -system.cpu.branchPred.BTBHits 476 # Number of BTB hits +system.cpu.branchPred.lookups 2340 # Number of BP lookups +system.cpu.branchPred.condPredicted 1388 # Number of conditional branches predicted +system.cpu.branchPred.condIncorrect 507 # Number of conditional branches incorrect +system.cpu.branchPred.BTBLookups 838 # Number of BTB lookups +system.cpu.branchPred.BTBHits 442 # Number of BTB hits system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. -system.cpu.branchPred.BTBHitPct 54.649828 # BTB Hit Percentage -system.cpu.branchPred.usedRAS 288 # Number of times the RAS was used to get a target. +system.cpu.branchPred.BTBHitPct 52.744630 # BTB Hit Percentage +system.cpu.branchPred.usedRAS 290 # Number of times the RAS was used to get a target. system.cpu.branchPred.RASInCorrect 55 # Number of incorrect RAS predictions. system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -381,84 +381,84 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 35823 # number of cpu cycles simulated +system.cpu.numCycles 35577 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.fetch.icacheStallCycles 6115 # Number of cycles fetch is stalled on an Icache miss -system.cpu.fetch.Insts 11289 # Number of instructions fetch has processed -system.cpu.fetch.Branches 2361 # Number of branches that fetch encountered -system.cpu.fetch.predictedBranches 764 # Number of branches that fetch has predicted taken -system.cpu.fetch.Cycles 8098 # Number of cycles fetch has run and was not squashing or blocked -system.cpu.fetch.SquashCycles 1055 # Number of cycles fetch has spent squashing -system.cpu.fetch.MiscStallCycles 130 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu.fetch.icacheStallCycles 6129 # Number of cycles fetch is stalled on an Icache miss +system.cpu.fetch.Insts 11284 # Number of instructions fetch has processed +system.cpu.fetch.Branches 2340 # Number of branches that fetch encountered +system.cpu.fetch.predictedBranches 732 # Number of branches that fetch has predicted taken +system.cpu.fetch.Cycles 7521 # Number of cycles fetch has run and was not squashing or blocked +system.cpu.fetch.SquashCycles 1057 # Number of cycles fetch has spent squashing +system.cpu.fetch.MiscStallCycles 129 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs system.cpu.fetch.PendingTrapStallCycles 303 # Number of stall cycles due to pending traps system.cpu.fetch.IcacheWaitRetryStallCycles 320 # Number of stall cycles due to full MSHR -system.cpu.fetch.CacheLines 3842 # Number of cache lines fetched -system.cpu.fetch.IcacheSquashes 178 # Number of outstanding Icache misses that were squashed -system.cpu.fetch.rateDist::samples 15493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::mean 0.850771 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::stdev 1.201734 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.CacheLines 3831 # Number of cache lines fetched +system.cpu.fetch.IcacheSquashes 176 # Number of outstanding Icache misses that were squashed +system.cpu.fetch.rateDist::samples 14930 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::mean 0.882251 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::stdev 1.211921 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::0 9287 59.94% 59.94% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::1 2459 15.87% 75.81% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::2 519 3.35% 79.16% # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::3 3228 20.84% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::0 8724 58.43% 58.43% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::1 2462 16.49% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::2 522 3.50% 78.42% # Number of instructions fetched each cycle (Total) +system.cpu.fetch.rateDist::3 3222 21.58% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) system.cpu.fetch.rateDist::max_value 3 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.rateDist::total 15493 # Number of instructions fetched each cycle (Total) -system.cpu.fetch.branchRate 0.065907 # Number of branch fetches per cycle -system.cpu.fetch.rate 0.315133 # Number of inst fetches per cycle -system.cpu.decode.IdleCycles 5846 # Number of cycles decode is idle -system.cpu.decode.BlockedCycles 4125 # Number of cycles decode is blocked -system.cpu.decode.RunCycles 5024 # Number of cycles decode is running -system.cpu.decode.UnblockCycles 132 # Number of cycles decode is unblocking -system.cpu.decode.SquashCycles 366 # Number of cycles decode is squashing -system.cpu.decode.BranchResolved 330 # Number of times decode resolved a branch +system.cpu.fetch.rateDist::total 14930 # Number of instructions fetched each cycle (Total) +system.cpu.fetch.branchRate 0.065773 # Number of branch fetches per cycle +system.cpu.fetch.rate 0.317171 # Number of inst fetches per cycle +system.cpu.decode.IdleCycles 5843 # Number of cycles decode is idle +system.cpu.decode.BlockedCycles 3543 # Number of cycles decode is blocked +system.cpu.decode.RunCycles 5049 # Number of cycles decode is running +system.cpu.decode.UnblockCycles 128 # Number of cycles decode is unblocking +system.cpu.decode.SquashCycles 367 # Number of cycles decode is squashing +system.cpu.decode.BranchResolved 329 # Number of times decode resolved a branch system.cpu.decode.BranchMispred 164 # Number of times decode detected a branch misprediction -system.cpu.decode.DecodedInsts 9854 # Number of instructions handled by decode -system.cpu.decode.SquashedInsts 1610 # Number of squashed instructions handled by decode -system.cpu.rename.SquashCycles 366 # Number of cycles rename is squashing +system.cpu.decode.DecodedInsts 9870 # Number of instructions handled by decode +system.cpu.decode.SquashedInsts 1626 # Number of squashed instructions handled by decode +system.cpu.rename.SquashCycles 367 # Number of cycles rename is squashing system.cpu.rename.IdleCycles 6916 # Number of cycles rename is idle -system.cpu.rename.BlockCycles 1543 # Number of cycles rename is blocking +system.cpu.rename.BlockCycles 964 # Number of cycles rename is blocking system.cpu.rename.serializeStallCycles 1980 # count of cycles rename stalled for serializing inst -system.cpu.rename.RunCycles 4080 # Number of cycles rename is running -system.cpu.rename.UnblockCycles 608 # Number of cycles rename is unblocking -system.cpu.rename.RenamedInsts 8873 # Number of instructions processed by rename -system.cpu.rename.SquashedInsts 401 # Number of squashed instructions processed by rename -system.cpu.rename.ROBFullEvents 15 # Number of times rename has blocked due to ROB full -system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full +system.cpu.rename.RunCycles 4098 # Number of cycles rename is running +system.cpu.rename.UnblockCycles 605 # Number of cycles rename is unblocking +system.cpu.rename.RenamedInsts 8889 # Number of instructions processed by rename +system.cpu.rename.SquashedInsts 403 # Number of squashed instructions processed by rename +system.cpu.rename.ROBFullEvents 14 # Number of times rename has blocked due to ROB full +system.cpu.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full system.cpu.rename.LQFullEvents 9 # Number of times rename has blocked due to LQ full system.cpu.rename.SQFullEvents 531 # Number of times rename has blocked due to SQ full -system.cpu.rename.RenamedOperands 9263 # Number of destination operands rename has renamed -system.cpu.rename.RenameLookups 40182 # Number of register rename lookups that rename has made -system.cpu.rename.int_rename_lookups 9732 # Number of integer rename lookups +system.cpu.rename.RenamedOperands 9240 # Number of destination operands rename has renamed +system.cpu.rename.RenameLookups 40319 # Number of register rename lookups that rename has made +system.cpu.rename.int_rename_lookups 9768 # Number of integer rename lookups system.cpu.rename.fp_rename_lookups 17 # Number of floating rename lookups system.cpu.rename.CommittedMaps 5494 # Number of HB maps that are committed -system.cpu.rename.UndoneMaps 3769 # Number of HB maps that are undone due to squashing +system.cpu.rename.UndoneMaps 3746 # Number of HB maps that are undone due to squashing system.cpu.rename.serializingInsts 30 # count of serializing insts renamed system.cpu.rename.tempSerializingInsts 28 # count of temporary serializing insts renamed -system.cpu.rename.skidInsts 309 # count of insts added to the skid buffer -system.cpu.memDep0.insertedLoads 1783 # Number of loads inserted to the mem dependence unit. -system.cpu.memDep0.insertedStores 1253 # Number of stores inserted to the mem dependence unit. +system.cpu.rename.skidInsts 299 # count of insts added to the skid buffer +system.cpu.memDep0.insertedLoads 1806 # Number of loads inserted to the mem dependence unit. +system.cpu.memDep0.insertedStores 1281 # Number of stores inserted to the mem dependence unit. system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. system.cpu.memDep0.conflictingStores 0 # Number of conflicting stores. -system.cpu.iq.iqInstsAdded 8340 # Number of instructions added to the IQ (excludes non-spec) +system.cpu.iq.iqInstsAdded 8360 # Number of instructions added to the IQ (excludes non-spec) system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ -system.cpu.iq.iqInstsIssued 7136 # Number of instructions issued -system.cpu.iq.iqSquashedInstsIssued 186 # Number of squashed instructions issued -system.cpu.iq.iqSquashedInstsExamined 3002 # Number of squashed instructions iterated over during squash; mainly for profiling -system.cpu.iq.iqSquashedOperandsExamined 7753 # Number of squashed operands that are examined and possibly removed from graph +system.cpu.iq.iqInstsIssued 7147 # Number of instructions issued +system.cpu.iq.iqSquashedInstsIssued 189 # Number of squashed instructions issued +system.cpu.iq.iqSquashedInstsExamined 3021 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu.iq.iqSquashedOperandsExamined 7902 # Number of squashed operands that are examined and possibly removed from graph system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed -system.cpu.iq.issued_per_cycle::samples 15493 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::mean 0.460595 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::stdev 0.852056 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::samples 14930 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::mean 0.478701 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::stdev 0.863585 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::0 11312 73.01% 73.01% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::1 1923 12.41% 85.43% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::2 1608 10.38% 95.80% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::3 603 3.89% 99.70% # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::4 47 0.30% 100.00% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::0 10739 71.93% 71.93% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::1 1936 12.97% 84.90% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::2 1601 10.72% 95.62% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::3 607 4.07% 99.69% # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::4 47 0.31% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% # Number of insts issued each cycle @@ -466,185 +466,185 @@ system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% # Nu system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle system.cpu.iq.issued_per_cycle::max_value 4 # Number of insts issued each cycle -system.cpu.iq.issued_per_cycle::total 15493 # Number of insts issued each cycle +system.cpu.iq.issued_per_cycle::total 14930 # Number of insts issued each cycle system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available -system.cpu.iq.fu_full::IntAlu 427 29.53% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntMult 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::IntDiv 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatMult 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMult 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShift 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.53% # attempts to use FU when none available -system.cpu.iq.fu_full::MemRead 469 32.43% 61.96% # attempts to use FU when none available -system.cpu.iq.fu_full::MemWrite 550 38.04% 100.00% # attempts to use FU when none available +system.cpu.iq.fu_full::IntAlu 420 29.23% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntMult 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::IntDiv 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatAdd 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCmp 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatCvt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatMult 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatDiv 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::FloatSqrt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAdd 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdAlu 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCmp 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdCvt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMisc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMult 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShift 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdSqrt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 29.23% # attempts to use FU when none available +system.cpu.iq.fu_full::MemRead 467 32.50% 61.73% # attempts to use FU when none available +system.cpu.iq.fu_full::MemWrite 550 38.27% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued -system.cpu.iq.FU_type_0::IntAlu 4484 62.84% 62.84% # Type of FU issued -system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.91% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.95% # Type of FU issued -system.cpu.iq.FU_type_0::MemRead 1571 22.02% 84.96% # Type of FU issued -system.cpu.iq.FU_type_0::MemWrite 1073 15.04% 100.00% # Type of FU issued +system.cpu.iq.FU_type_0::IntAlu 4466 62.49% 62.49% # Type of FU issued +system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.56% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.60% # Type of FU issued +system.cpu.iq.FU_type_0::MemRead 1589 22.23% 84.83% # Type of FU issued +system.cpu.iq.FU_type_0::MemWrite 1084 15.17% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued -system.cpu.iq.FU_type_0::total 7136 # Type of FU issued -system.cpu.iq.rate 0.199202 # Inst issue rate -system.cpu.iq.fu_busy_cnt 1446 # FU busy when requested -system.cpu.iq.fu_busy_rate 0.202635 # FU busy rate (busy events/executed inst) -system.cpu.iq.int_inst_queue_reads 31353 # Number of integer instruction queue reads -system.cpu.iq.int_inst_queue_writes 11372 # Number of integer instruction queue writes -system.cpu.iq.int_inst_queue_wakeup_accesses 6550 # Number of integer instruction queue wakeup accesses +system.cpu.iq.FU_type_0::total 7147 # Type of FU issued +system.cpu.iq.rate 0.200888 # Inst issue rate +system.cpu.iq.fu_busy_cnt 1437 # FU busy when requested +system.cpu.iq.fu_busy_rate 0.201063 # FU busy rate (busy events/executed inst) +system.cpu.iq.int_inst_queue_reads 30806 # Number of integer instruction queue reads +system.cpu.iq.int_inst_queue_writes 11411 # Number of integer instruction queue writes +system.cpu.iq.int_inst_queue_wakeup_accesses 6546 # Number of integer instruction queue wakeup accesses system.cpu.iq.fp_inst_queue_reads 44 # Number of floating instruction queue reads system.cpu.iq.fp_inst_queue_writes 16 # Number of floating instruction queue writes system.cpu.iq.fp_inst_queue_wakeup_accesses 16 # Number of floating instruction queue wakeup accesses -system.cpu.iq.int_alu_accesses 8554 # Number of integer alu accesses +system.cpu.iq.int_alu_accesses 8556 # Number of integer alu accesses system.cpu.iq.fp_alu_accesses 28 # Number of floating point alu accesses -system.cpu.iew.lsq.thread0.forwLoads 9 # Number of loads that had data forwarded from stores +system.cpu.iew.lsq.thread0.forwLoads 10 # Number of loads that had data forwarded from stores system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address -system.cpu.iew.lsq.thread0.squashedLoads 756 # Number of loads squashed +system.cpu.iew.lsq.thread0.squashedLoads 779 # Number of loads squashed system.cpu.iew.lsq.thread0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations -system.cpu.iew.lsq.thread0.squashedStores 315 # Number of stores squashed +system.cpu.iew.lsq.thread0.squashedStores 343 # Number of stores squashed system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding system.cpu.iew.lsq.thread0.rescheduledLoads 5 # Number of loads that were rescheduled system.cpu.iew.lsq.thread0.cacheBlocked 18 # Number of times an access to memory failed due to the cache being blocked system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle -system.cpu.iew.iewSquashCycles 366 # Number of cycles IEW is squashing -system.cpu.iew.iewBlockCycles 898 # Number of cycles IEW is blocking -system.cpu.iew.iewUnblockCycles 9 # Number of cycles IEW is unblocking -system.cpu.iew.iewDispatchedInsts 8393 # Number of instructions dispatched to IQ +system.cpu.iew.iewSquashCycles 367 # Number of cycles IEW is squashing +system.cpu.iew.iewBlockCycles 358 # Number of cycles IEW is blocking +system.cpu.iew.iewUnblockCycles 8 # Number of cycles IEW is unblocking +system.cpu.iew.iewDispatchedInsts 8413 # Number of instructions dispatched to IQ system.cpu.iew.iewDispSquashedInsts 0 # Number of squashed instructions skipped by dispatch -system.cpu.iew.iewDispLoadInsts 1783 # Number of dispatched load instructions -system.cpu.iew.iewDispStoreInsts 1253 # Number of dispatched store instructions +system.cpu.iew.iewDispLoadInsts 1806 # Number of dispatched load instructions +system.cpu.iew.iewDispStoreInsts 1281 # Number of dispatched store instructions system.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions -system.cpu.iew.iewIQFullEvents 3 # Number of times the IQ has become full, causing a stall +system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall system.cpu.iew.iewLSQFullEvents 4 # Number of times the LSQ has become full, causing a stall system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations -system.cpu.iew.predictedTakenIncorrect 68 # Number of branches that were predicted taken incorrectly -system.cpu.iew.predictedNotTakenIncorrect 291 # Number of branches that were predicted not taken incorrectly -system.cpu.iew.branchMispredicts 359 # Number of branch mispredicts detected at execute -system.cpu.iew.iewExecutedInsts 6736 # Number of executed instructions -system.cpu.iew.iewExecLoadInsts 1394 # Number of load instructions executed -system.cpu.iew.iewExecSquashedInsts 400 # Number of squashed instructions skipped in execute +system.cpu.iew.predictedTakenIncorrect 66 # Number of branches that were predicted taken incorrectly +system.cpu.iew.predictedNotTakenIncorrect 294 # Number of branches that were predicted not taken incorrectly +system.cpu.iew.branchMispredicts 360 # Number of branch mispredicts detected at execute +system.cpu.iew.iewExecutedInsts 6739 # Number of executed instructions +system.cpu.iew.iewExecLoadInsts 1406 # Number of load instructions executed +system.cpu.iew.iewExecSquashedInsts 408 # Number of squashed instructions skipped in execute system.cpu.iew.exec_swp 0 # number of swp insts executed system.cpu.iew.exec_nop 14 # number of nop insts executed -system.cpu.iew.exec_refs 2409 # number of memory reference insts executed -system.cpu.iew.exec_branches 1271 # Number of branches executed -system.cpu.iew.exec_stores 1015 # Number of stores executed -system.cpu.iew.exec_rate 0.188036 # Inst execution rate -system.cpu.iew.wb_sent 6609 # cumulative count of insts sent to commit -system.cpu.iew.wb_count 6566 # cumulative count of insts written-back -system.cpu.iew.wb_producers 2981 # num instructions producing a value -system.cpu.iew.wb_consumers 5387 # num instructions consuming a value +system.cpu.iew.exec_refs 2430 # number of memory reference insts executed +system.cpu.iew.exec_branches 1270 # Number of branches executed +system.cpu.iew.exec_stores 1024 # Number of stores executed +system.cpu.iew.exec_rate 0.189420 # Inst execution rate +system.cpu.iew.wb_sent 6605 # cumulative count of insts sent to commit +system.cpu.iew.wb_count 6562 # cumulative count of insts written-back +system.cpu.iew.wb_producers 2976 # num instructions producing a value +system.cpu.iew.wb_consumers 5371 # num instructions consuming a value system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ -system.cpu.iew.wb_rate 0.183290 # insts written-back per cycle -system.cpu.iew.wb_fanout 0.553369 # average fanout of values written-back +system.cpu.iew.wb_rate 0.184445 # insts written-back per cycle +system.cpu.iew.wb_fanout 0.554087 # average fanout of values written-back system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ -system.cpu.commit.commitSquashedInsts 2567 # The number of squashed insts skipped by commit +system.cpu.commit.commitSquashedInsts 2578 # The number of squashed insts skipped by commit system.cpu.commit.commitNonSpecStalls 37 # The number of times commit has been forced to stall to communicate backwards -system.cpu.commit.branchMispredicts 345 # The number of times a branch was mispredicted -system.cpu.commit.committed_per_cycle::samples 14953 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::mean 0.359593 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::stdev 1.005851 # Number of insts commited each cycle +system.cpu.commit.branchMispredicts 346 # The number of times a branch was mispredicted +system.cpu.commit.committed_per_cycle::samples 14390 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::mean 0.373732 # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::stdev 1.023936 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::0 12307 82.30% 82.30% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::1 1380 9.23% 91.53% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::2 605 4.05% 95.58% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::3 296 1.98% 97.56% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::4 166 1.11% 98.67% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::5 78 0.52% 99.19% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::6 46 0.31% 99.50% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::7 31 0.21% 99.71% # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::0 11747 81.63% 81.63% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::1 1377 9.57% 91.20% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::2 605 4.20% 95.41% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::3 294 2.04% 97.45% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::4 168 1.17% 98.62% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::5 77 0.54% 99.15% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::6 46 0.32% 99.47% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::7 32 0.22% 99.69% # Number of insts commited each cycle +system.cpu.commit.committed_per_cycle::8 44 0.31% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle -system.cpu.commit.committed_per_cycle::total 14953 # Number of insts commited each cycle -system.cpu.commit.committedInsts 4591 # Number of instructions committed -system.cpu.commit.committedOps 5377 # Number of ops (including micro ops) committed +system.cpu.commit.committed_per_cycle::total 14390 # Number of insts commited each cycle +system.cpu.commit.committedInsts 4592 # Number of instructions committed +system.cpu.commit.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.commit.swp_count 0 # Number of s/w prefetches committed system.cpu.commit.refs 1965 # Number of memory references committed system.cpu.commit.loads 1027 # Number of loads committed system.cpu.commit.membars 12 # Number of memory barriers committed -system.cpu.commit.branches 1007 # Number of branches committed +system.cpu.commit.branches 1008 # Number of branches committed system.cpu.commit.fp_insts 16 # Number of committed floating point instructions. system.cpu.commit.int_insts 4624 # Number of committed integer instructions. system.cpu.commit.function_calls 82 # Number of function calls committed. system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction -system.cpu.commit.op_class_0::IntAlu 3405 63.33% 63.33% # Class of committed instruction -system.cpu.commit.op_class_0::IntMult 4 0.07% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.40% # Class of committed instruction -system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.40% # Class of committed instruction +system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% # Class of committed instruction +system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% # Class of committed instruction +system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% # Class of committed instruction system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% # Class of committed instruction @@ -653,104 +653,104 @@ system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% # Cl system.cpu.commit.op_class_0::MemWrite 938 17.44% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction -system.cpu.commit.op_class_0::total 5377 # Class of committed instruction +system.cpu.commit.op_class_0::total 5378 # Class of committed instruction system.cpu.commit.bw_lim_events 44 # number cycles where commit BW limit reached -system.cpu.rob.rob_reads 22696 # The number of ROB reads -system.cpu.rob.rob_writes 16433 # The number of ROB writes -system.cpu.timesIdled 211 # Number of times that the entire CPU went into an idle state and unscheduled itself -system.cpu.idleCycles 20330 # Total number of cycles that the CPU has spent unscheduled due to idling -system.cpu.committedInsts 4591 # Number of Instructions Simulated -system.cpu.committedOps 5377 # Number of Ops (including micro ops) Simulated -system.cpu.cpi 7.802875 # CPI: Cycles Per Instruction -system.cpu.cpi_total 7.802875 # CPI: Total CPI of All Threads -system.cpu.ipc 0.128158 # IPC: Instructions Per Cycle -system.cpu.ipc_total 0.128158 # IPC: Total IPC of All Threads +system.cpu.rob.rob_reads 22145 # The number of ROB reads +system.cpu.rob.rob_writes 16457 # The number of ROB writes +system.cpu.timesIdled 212 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu.idleCycles 20647 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu.committedInsts 4592 # Number of Instructions Simulated +system.cpu.committedOps 5378 # Number of Ops (including micro ops) Simulated +system.cpu.cpi 7.747605 # CPI: Cycles Per Instruction +system.cpu.cpi_total 7.747605 # CPI: Total CPI of All Threads +system.cpu.ipc 0.129072 # IPC: Instructions Per Cycle +system.cpu.ipc_total 0.129072 # IPC: Total IPC of All Threads system.cpu.int_regfile_reads 6713 # number of integer regfile reads -system.cpu.int_regfile_writes 3756 # number of integer regfile writes +system.cpu.int_regfile_writes 3745 # number of integer regfile writes system.cpu.fp_regfile_reads 16 # number of floating regfile reads -system.cpu.cc_regfile_reads 23929 # number of cc regfile reads -system.cpu.cc_regfile_writes 2892 # number of cc regfile writes -system.cpu.misc_regfile_reads 2595 # number of misc regfile reads +system.cpu.cc_regfile_reads 23953 # number of cc regfile reads +system.cpu.cc_regfile_writes 2889 # number of cc regfile writes +system.cpu.misc_regfile_reads 2609 # number of misc regfile reads system.cpu.misc_regfile_writes 24 # number of misc regfile writes system.cpu.dcache.tags.replacements 1 # number of replacements -system.cpu.dcache.tags.tagsinuse 84.129086 # Cycle average of tags in use -system.cpu.dcache.tags.total_refs 1902 # Total number of references to valid blocks. +system.cpu.dcache.tags.tagsinuse 84.188922 # Cycle average of tags in use +system.cpu.dcache.tags.total_refs 1918 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. -system.cpu.dcache.tags.avg_refs 13.394366 # Average number of references to valid blocks. +system.cpu.dcache.tags.avg_refs 13.507042 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 84.129086 # Average occupied blocks per requestor -system.cpu.dcache.tags.occ_percent::cpu.data 0.164315 # Average percentage of cache occupancy -system.cpu.dcache.tags.occ_percent::total 0.164315 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_blocks::cpu.data 84.188922 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_percent::cpu.data 0.164431 # Average percentage of cache occupancy +system.cpu.dcache.tags.occ_percent::total 0.164431 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::0 53 # Occupied blocks per task id system.cpu.dcache.tags.age_task_id_blocks_1024::1 88 # Occupied blocks per task id system.cpu.dcache.tags.occ_task_id_percent::1024 0.275391 # Percentage of cache occupancy per task id -system.cpu.dcache.tags.tag_accesses 4674 # Number of tag accesses -system.cpu.dcache.tags.data_accesses 4674 # Number of data accesses -system.cpu.dcache.ReadReq_hits::cpu.data 1160 # number of ReadReq hits -system.cpu.dcache.ReadReq_hits::total 1160 # number of ReadReq hits +system.cpu.dcache.tags.tag_accesses 4696 # Number of tag accesses +system.cpu.dcache.tags.data_accesses 4696 # Number of data accesses +system.cpu.dcache.ReadReq_hits::cpu.data 1176 # number of ReadReq hits +system.cpu.dcache.ReadReq_hits::total 1176 # number of ReadReq hits system.cpu.dcache.WriteReq_hits::cpu.data 722 # number of WriteReq hits system.cpu.dcache.WriteReq_hits::total 722 # number of WriteReq hits system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 # number of LoadLockedReq hits system.cpu.dcache.LoadLockedReq_hits::total 9 # number of LoadLockedReq hits system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits -system.cpu.dcache.demand_hits::cpu.data 1882 # number of demand (read+write) hits -system.cpu.dcache.demand_hits::total 1882 # number of demand (read+write) hits -system.cpu.dcache.overall_hits::cpu.data 1882 # number of overall hits -system.cpu.dcache.overall_hits::total 1882 # number of overall hits -system.cpu.dcache.ReadReq_misses::cpu.data 171 # number of ReadReq misses -system.cpu.dcache.ReadReq_misses::total 171 # number of ReadReq misses +system.cpu.dcache.demand_hits::cpu.data 1898 # number of demand (read+write) hits +system.cpu.dcache.demand_hits::total 1898 # number of demand (read+write) hits +system.cpu.dcache.overall_hits::cpu.data 1898 # number of overall hits +system.cpu.dcache.overall_hits::total 1898 # number of overall hits +system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses +system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses system.cpu.dcache.WriteReq_misses::cpu.data 191 # number of WriteReq misses system.cpu.dcache.WriteReq_misses::total 191 # number of WriteReq misses system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses -system.cpu.dcache.demand_misses::cpu.data 362 # number of demand (read+write) misses -system.cpu.dcache.demand_misses::total 362 # number of demand (read+write) misses -system.cpu.dcache.overall_misses::cpu.data 362 # number of overall misses -system.cpu.dcache.overall_misses::total 362 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 9785742 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 9785742 # number of ReadReq miss cycles +system.cpu.dcache.demand_misses::cpu.data 357 # number of demand (read+write) misses +system.cpu.dcache.demand_misses::total 357 # number of demand (read+write) misses +system.cpu.dcache.overall_misses::cpu.data 357 # number of overall misses +system.cpu.dcache.overall_misses::total 357 # number of overall misses +system.cpu.dcache.ReadReq_miss_latency::cpu.data 9257492 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 9257492 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 7277250 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 7277250 # number of WriteReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 126000 # number of LoadLockedReq miss cycles system.cpu.dcache.LoadLockedReq_miss_latency::total 126000 # number of LoadLockedReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 17062992 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 17062992 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 17062992 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 17062992 # number of overall miss cycles -system.cpu.dcache.ReadReq_accesses::cpu.data 1331 # number of ReadReq accesses(hits+misses) -system.cpu.dcache.ReadReq_accesses::total 1331 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.demand_miss_latency::cpu.data 16534742 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 16534742 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 16534742 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 16534742 # number of overall miss cycles +system.cpu.dcache.ReadReq_accesses::cpu.data 1342 # number of ReadReq accesses(hits+misses) +system.cpu.dcache.ReadReq_accesses::total 1342 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) -system.cpu.dcache.demand_accesses::cpu.data 2244 # number of demand (read+write) accesses -system.cpu.dcache.demand_accesses::total 2244 # number of demand (read+write) accesses -system.cpu.dcache.overall_accesses::cpu.data 2244 # number of overall (read+write) accesses -system.cpu.dcache.overall_accesses::total 2244 # number of overall (read+write) accesses -system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.128475 # miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_miss_rate::total 0.128475 # miss rate for ReadReq accesses +system.cpu.dcache.demand_accesses::cpu.data 2255 # number of demand (read+write) accesses +system.cpu.dcache.demand_accesses::total 2255 # number of demand (read+write) accesses +system.cpu.dcache.overall_accesses::cpu.data 2255 # number of overall (read+write) accesses +system.cpu.dcache.overall_accesses::total 2255 # number of overall (read+write) accesses +system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.123696 # miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_miss_rate::total 0.123696 # miss rate for ReadReq accesses system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.WriteReq_miss_rate::total 0.209200 # miss rate for WriteReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 # miss rate for LoadLockedReq accesses system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 # miss rate for LoadLockedReq accesses -system.cpu.dcache.demand_miss_rate::cpu.data 0.161319 # miss rate for demand accesses -system.cpu.dcache.demand_miss_rate::total 0.161319 # miss rate for demand accesses -system.cpu.dcache.overall_miss_rate::cpu.data 0.161319 # miss rate for overall accesses -system.cpu.dcache.overall_miss_rate::total 0.161319 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 57226.561404 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 57226.561404 # average ReadReq miss latency +system.cpu.dcache.demand_miss_rate::cpu.data 0.158315 # miss rate for demand accesses +system.cpu.dcache.demand_miss_rate::total 0.158315 # miss rate for demand accesses +system.cpu.dcache.overall_miss_rate::cpu.data 0.158315 # miss rate for overall accesses +system.cpu.dcache.overall_miss_rate::total 0.158315 # miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55768.024096 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 55768.024096 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38100.785340 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 38100.785340 # average WriteReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 # average LoadLockedReq miss latency system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 # average LoadLockedReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 47135.337017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 47135.337017 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 47135.337017 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 46315.803922 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 46315.803922 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 46315.803922 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 46315.803922 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 717 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -759,16 +759,16 @@ system.cpu.dcache.avg_blocked_cycles::no_mshrs nan system.cpu.dcache.avg_blocked_cycles::no_targets 39.833333 # average number of cycles each access was blocked system.cpu.dcache.fast_writes 0 # number of fast writes performed system.cpu.dcache.cache_copies 0 # number of cache copies performed -system.cpu.dcache.ReadReq_mshr_hits::cpu.data 69 # number of ReadReq MSHR hits -system.cpu.dcache.ReadReq_mshr_hits::total 69 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits +system.cpu.dcache.ReadReq_mshr_hits::total 64 # number of ReadReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 # number of WriteReq MSHR hits system.cpu.dcache.WriteReq_mshr_hits::total 150 # number of WriteReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits -system.cpu.dcache.demand_mshr_hits::cpu.data 219 # number of demand (read+write) MSHR hits -system.cpu.dcache.demand_mshr_hits::total 219 # number of demand (read+write) MSHR hits -system.cpu.dcache.overall_mshr_hits::cpu.data 219 # number of overall MSHR hits -system.cpu.dcache.overall_mshr_hits::total 219 # number of overall MSHR hits +system.cpu.dcache.demand_mshr_hits::cpu.data 214 # number of demand (read+write) MSHR hits +system.cpu.dcache.demand_mshr_hits::total 214 # number of demand (read+write) MSHR hits +system.cpu.dcache.overall_mshr_hits::cpu.data 214 # number of overall MSHR hits +system.cpu.dcache.overall_mshr_hits::total 214 # number of overall MSHR hits system.cpu.dcache.ReadReq_mshr_misses::cpu.data 102 # number of ReadReq MSHR misses system.cpu.dcache.ReadReq_mshr_misses::total 102 # number of ReadReq MSHR misses system.cpu.dcache.WriteReq_mshr_misses::cpu.data 41 # number of WriteReq MSHR misses @@ -777,120 +777,120 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 143 system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6008755 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 6008755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5795755 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 5795755 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2367750 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 2367750 # number of WriteReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8376505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 8376505 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8376505 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 8376505 # number of overall MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076634 # mshr miss rate for ReadReq accesses -system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076634 # mshr miss rate for ReadReq accesses +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8163505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 8163505 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8163505 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 8163505 # number of overall MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076006 # mshr miss rate for ReadReq accesses +system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076006 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044907 # mshr miss rate for WriteReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044907 # mshr miss rate for WriteReq accesses -system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for demand accesses -system.cpu.dcache.demand_mshr_miss_rate::total 0.063725 # mshr miss rate for demand accesses -system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063725 # mshr miss rate for overall accesses -system.cpu.dcache.overall_mshr_miss_rate::total 0.063725 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 58909.362745 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 58909.362745 # average ReadReq mshr miss latency +system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.063415 # mshr miss rate for demand accesses +system.cpu.dcache.demand_mshr_miss_rate::total 0.063415 # mshr miss rate for demand accesses +system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.063415 # mshr miss rate for overall accesses +system.cpu.dcache.overall_mshr_miss_rate::total 0.063415 # mshr miss rate for overall accesses +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 56821.127451 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 56821.127451 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 57750 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 57750 # average WriteReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58576.958042 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 58576.958042 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57087.447552 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 57087.447552 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57087.447552 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 57087.447552 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 42 # number of replacements -system.cpu.icache.tags.tagsinuse 136.043653 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 3477 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 136.057531 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 3467 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 11.786441 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 11.752542 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 136.043653 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.265710 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.265710 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 136.057531 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.265737 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.265737 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 253 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 162 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 91 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.494141 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 7977 # Number of tag accesses -system.cpu.icache.tags.data_accesses 7977 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 3477 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 3477 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 3477 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 3477 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 3477 # number of overall hits -system.cpu.icache.overall_hits::total 3477 # number of overall hits -system.cpu.icache.ReadReq_misses::cpu.inst 364 # number of ReadReq misses -system.cpu.icache.ReadReq_misses::total 364 # number of ReadReq misses -system.cpu.icache.demand_misses::cpu.inst 364 # number of demand (read+write) misses -system.cpu.icache.demand_misses::total 364 # number of demand (read+write) misses -system.cpu.icache.overall_misses::cpu.inst 364 # number of overall misses -system.cpu.icache.overall_misses::total 364 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 22425741 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 22425741 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 22425741 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 22425741 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 22425741 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 22425741 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 3841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 3841 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 3841 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 3841 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 3841 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 3841 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094767 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.094767 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.094767 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.094767 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.094767 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.094767 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61609.178571 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 61609.178571 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 61609.178571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 61609.178571 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 61609.178571 # average overall miss latency -system.cpu.icache.blocked_cycles::no_mshrs 8359 # number of cycles access was blocked +system.cpu.icache.tags.tag_accesses 7955 # Number of tag accesses +system.cpu.icache.tags.data_accesses 7955 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 3467 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 3467 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 3467 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 3467 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 3467 # number of overall hits +system.cpu.icache.overall_hits::total 3467 # number of overall hits +system.cpu.icache.ReadReq_misses::cpu.inst 363 # number of ReadReq misses +system.cpu.icache.ReadReq_misses::total 363 # number of ReadReq misses +system.cpu.icache.demand_misses::cpu.inst 363 # number of demand (read+write) misses +system.cpu.icache.demand_misses::total 363 # number of demand (read+write) misses +system.cpu.icache.overall_misses::cpu.inst 363 # number of overall misses +system.cpu.icache.overall_misses::total 363 # number of overall misses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 21749991 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 21749991 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 21749991 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 21749991 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 21749991 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 21749991 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 3830 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 3830 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 3830 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 3830 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 3830 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 3830 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.094778 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.094778 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.094778 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.094778 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.094778 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.094778 # miss rate for overall accesses +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 59917.330579 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 59917.330579 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 59917.330579 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 59917.330579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 59917.330579 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 59917.330579 # average overall miss latency +system.cpu.icache.blocked_cycles::no_mshrs 8313 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 33 # number of cycles access was blocked -system.cpu.icache.blocked::no_mshrs 92 # number of cycles access was blocked +system.cpu.icache.blocked::no_mshrs 90 # number of cycles access was blocked system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked -system.cpu.icache.avg_blocked_cycles::no_mshrs 90.858696 # average number of cycles each access was blocked +system.cpu.icache.avg_blocked_cycles::no_mshrs 92.366667 # average number of cycles each access was blocked system.cpu.icache.avg_blocked_cycles::no_targets 33 # average number of cycles each access was blocked system.cpu.icache.fast_writes 0 # number of fast writes performed system.cpu.icache.cache_copies 0 # number of cache copies performed -system.cpu.icache.ReadReq_mshr_hits::cpu.inst 68 # number of ReadReq MSHR hits -system.cpu.icache.ReadReq_mshr_hits::total 68 # number of ReadReq MSHR hits -system.cpu.icache.demand_mshr_hits::cpu.inst 68 # number of demand (read+write) MSHR hits -system.cpu.icache.demand_mshr_hits::total 68 # number of demand (read+write) MSHR hits -system.cpu.icache.overall_mshr_hits::cpu.inst 68 # number of overall MSHR hits -system.cpu.icache.overall_mshr_hits::total 68 # number of overall MSHR hits +system.cpu.icache.ReadReq_mshr_hits::cpu.inst 67 # number of ReadReq MSHR hits +system.cpu.icache.ReadReq_mshr_hits::total 67 # number of ReadReq MSHR hits +system.cpu.icache.demand_mshr_hits::cpu.inst 67 # number of demand (read+write) MSHR hits +system.cpu.icache.demand_mshr_hits::total 67 # number of demand (read+write) MSHR hits +system.cpu.icache.overall_mshr_hits::cpu.inst 67 # number of overall MSHR hits +system.cpu.icache.overall_mshr_hits::total 67 # number of overall MSHR hits system.cpu.icache.ReadReq_mshr_misses::cpu.inst 296 # number of ReadReq MSHR misses system.cpu.icache.ReadReq_mshr_misses::total 296 # number of ReadReq MSHR misses system.cpu.icache.demand_mshr_misses::cpu.inst 296 # number of demand (read+write) MSHR misses system.cpu.icache.demand_mshr_misses::total 296 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 296 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 296 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18519493 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 18519493 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18519493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 18519493 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18519493 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 18519493 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077063 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.077063 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077063 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.077063 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62565.854730 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62565.854730 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62565.854730 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 62565.854730 # average overall mshr miss latency +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18653743 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 18653743 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18653743 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 18653743 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18653743 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 18653743 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.077285 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.077285 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.077285 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.077285 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 63019.402027 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 63019.402027 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 63019.402027 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 63019.402027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 63019.402027 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 63019.402027 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.prefetcher.num_hwpf_issued 112 # number of hwpf issued system.cpu.l2cache.prefetcher.pfIdentified 112 # number of prefetch candidates identified @@ -899,18 +899,18 @@ system.cpu.l2cache.prefetcher.pfInCache 0 # nu system.cpu.l2cache.prefetcher.pfRemovedFull 0 # number of prefetches dropped due to prefetch queue size system.cpu.l2cache.prefetcher.pfSpanPage 0 # number of prefetches not generated due to page crossing system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 192.519523 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 192.560599 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 42 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 364 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.115385 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.367812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 44.986812 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.164899 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008445 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.002746 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_blocks::cpu.inst 138.350778 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 45.044062 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher 9.165759 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.008444 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.002749 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher 0.000559 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::total 0.011750 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::total 0.011753 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1022 16 # Occupied blocks per task id system.cpu.l2cache.tags.occ_task_id_blocks::1024 348 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1022::0 8 # Occupied blocks per task id @@ -943,17 +943,17 @@ system.cpu.l2cache.demand_misses::total 386 # nu system.cpu.l2cache.overall_misses::cpu.inst 273 # number of overall misses system.cpu.l2cache.overall_misses::cpu.data 113 # number of overall misses system.cpu.l2cache.overall_misses::total 386 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18219750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5781750 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::total 24001500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 18354000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5568750 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::total 23922750 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2253750 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 2253750 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 18219750 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 8035500 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::total 26255250 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 18219750 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 8035500 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::total 26255250 # number of overall miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 18354000 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 7822500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::total 26176500 # number of demand (read+write) miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 18354000 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 7822500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::total 26176500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 296 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 102 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::total 398 # number of ReadReq accesses(hits+misses) @@ -976,17 +976,17 @@ system.cpu.l2cache.demand_miss_rate::total 0.879271 # system.cpu.l2cache.overall_miss_rate::cpu.inst 0.922297 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::cpu.data 0.790210 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.879271 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 66739.010989 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 69659.638554 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::total 67419.943820 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 67230.769231 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 67093.373494 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::total 67198.735955 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75125 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75125 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::total 68018.782383 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 66739.010989 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71110.619469 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::total 68018.782383 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 67230.769231 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69225.663717 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::total 67814.766839 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 67230.769231 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69225.663717 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::total 67814.766839 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -1018,20 +1018,20 @@ system.cpu.l2cache.overall_mshr_misses::cpu.inst 272 system.cpu.l2cache.overall_mshr_misses::cpu.data 108 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher 48 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 428 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15861750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4830750 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20692500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 15994000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4617750 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::total 20611750 # number of ReadReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.HardPFReq_mshr_miss_latency::total 1641917 # number of HardPFReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2002750 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2002750 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15861750 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6833500 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::total 22695250 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15861750 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6833500 # number of overall MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 15994000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6620500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::total 22614500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 15994000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6620500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher 1641917 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::total 24337167 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::total 24256417 # number of overall MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.918919 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.764706 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.879397 # mshr miss rate for ReadReq accesses @@ -1046,20 +1046,20 @@ system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.918919 system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.755245 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher inf # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.974943 # mshr miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58315.257353 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61932.692308 # average ReadReq mshr miss latency -system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59121.428571 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58801.470588 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 59201.923077 # average ReadReq mshr miss latency +system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58890.714286 # average ReadReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average HardPFReq mshr miss latency system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34206.604167 # average HardPFReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 66758.333333 # average ReadExReq mshr miss latency system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 66758.333333 # average ReadExReq mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency -system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59724.342105 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58315.257353 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63273.148148 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58801.470588 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61300.925926 # average overall mshr miss latency +system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59511.842105 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58801.470588 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61300.925926 # average overall mshr miss latency system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34206.604167 # average overall mshr miss latency -system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56862.539720 # average overall mshr miss latency +system.cpu.l2cache.overall_avg_mshr_miss_latency::total 56673.871495 # average overall mshr miss latency system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.toL2Bus.trans_dist::ReadReq 398 # Transaction distribution system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution @@ -1088,7 +1088,7 @@ system.cpu.toL2Bus.snoop_fanout::max_value 4 # system.cpu.toL2Bus.snoop_fanout::total 503 # Request fanout histogram system.cpu.toL2Bus.reqLayer0.occupancy 219500 # Layer occupancy (ticks) system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) -system.cpu.toL2Bus.respLayer0.occupancy 496749 # Layer occupancy (ticks) +system.cpu.toL2Bus.respLayer0.occupancy 496999 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer0.utilization 2.8 # Layer utilization (%) system.cpu.toL2Bus.respLayer1.occupancy 228995 # Layer occupancy (ticks) system.cpu.toL2Bus.respLayer1.utilization 1.3 # Layer utilization (%) @@ -1111,9 +1111,9 @@ system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Re system.membus.snoop_fanout::min_value 0 # Request fanout histogram system.membus.snoop_fanout::max_value 0 # Request fanout histogram system.membus.snoop_fanout::total 407 # Request fanout histogram -system.membus.reqLayer0.occupancy 509443 # Layer occupancy (ticks) -system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) -system.membus.respLayer1.occupancy 2140258 # Layer occupancy (ticks) -system.membus.respLayer1.utilization 11.9 # Layer utilization (%) +system.membus.reqLayer0.occupancy 508443 # Layer occupancy (ticks) +system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) +system.membus.respLayer1.occupancy 2142008 # Layer occupancy (ticks) +system.membus.respLayer1.utilization 12.0 # Layer utilization (%) ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt index cdd01be72..5334b6829 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2694500 # Number of ticks simulated -final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2695000 # Number of ticks simulated +final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 771856 # Simulator instruction rate (inst/s) -host_op_rate 901727 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 450886881 # Simulator tick rate (ticks/s) -host_mem_usage 297796 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4591 # Number of instructions simulated -sim_ops 5377 # Number of ops (including micro ops) simulated +host_inst_rate 88081 # Simulator instruction rate (inst/s) +host_op_rate 103121 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 51657705 # Simulator tick rate (ticks/s) +host_mem_usage 292672 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +sim_insts 4592 # Number of instructions simulated +sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory -system.physmem.bytes_read::total 22907 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 22911 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.checker.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -272,11 +272,11 @@ system.cpu.itb.inst_accesses 0 # IT system.cpu.itb.hits 0 # DTB hits system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses -system.cpu.numCycles 5390 # number of cpu cycles simulated +system.cpu.numCycles 5391 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4591 # Number of instructions committed -system.cpu.committedOps 5377 # Number of ops (including micro ops) committed +system.cpu.committedInsts 4592 # Number of instructions committed +system.cpu.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured @@ -287,18 +287,18 @@ system.cpu.num_int_register_reads 7607 # nu system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read +system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles +system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1007 # Number of branches fetched +system.cpu.Branches 1008 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction +system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction @@ -323,40 +323,40 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5390 # Class of executed instruction -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.trans_dist::ReadReq 5597 # Transaction distribution +system.membus.trans_dist::ReadResp 5608 # Transaction distribution system.membus.trans_dist::WriteReq 913 # Transaction distribution system.membus.trans_dist::WriteResp 913 # Transaction distribution system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution system.membus.trans_dist::StoreCondReq 11 # Transaction distribution system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::samples 6532 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram +system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram +system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt index bd1ca933f..cc40f6f8e 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000003 # Number of seconds simulated -sim_ticks 2694500 # Number of ticks simulated -final_tick 2694500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 2695000 # Number of ticks simulated +final_tick 2695000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 801222 # Simulator instruction rate (inst/s) -host_op_rate 936270 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 468120222 # Simulator tick rate (ticks/s) -host_mem_usage 297024 # Number of bytes of host memory used -host_seconds 0.01 # Real time elapsed on the host -sim_insts 4591 # Number of instructions simulated -sim_ops 5377 # Number of ops (including micro ops) simulated +host_inst_rate 99386 # Simulator instruction rate (inst/s) +host_op_rate 116351 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 58281162 # Simulator tick rate (ticks/s) +host_mem_usage 291652 # Number of bytes of host memory used +host_seconds 0.05 # Real time elapsed on the host +sim_insts 4592 # Number of instructions simulated +sim_ops 5378 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 18416 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 18420 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 4491 # Number of bytes read from this memory -system.physmem.bytes_read::total 22907 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 18416 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 18416 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 22911 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 18420 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 18420 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 3648 # Number of bytes written to this memory system.physmem.bytes_written::total 3648 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 4604 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 4605 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 1003 # Number of read requests responded to by this memory -system.physmem.num_reads::total 5607 # Number of read requests responded to by this memory +system.physmem.num_reads::total 5608 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 924 # Number of write requests responded to by this memory system.physmem.num_writes::total 924 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6834663203 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1666728521 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8501391724 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6834663203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6834663203 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1353868992 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1353868992 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6834663203 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3020597513 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9855260716 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6834879406 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1666419295 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8501298701 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6834879406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6834879406 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1353617811 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1353617811 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6834879406 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3020037106 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9854916512 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 5390 # number of cpu cycles simulated +system.cpu.numCycles 5391 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4591 # Number of instructions committed -system.cpu.committedOps 5377 # Number of ops (including micro ops) committed +system.cpu.committedInsts 4592 # Number of instructions committed +system.cpu.committedOps 5378 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured @@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 7607 # nu system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 16172 # number of times the CC registers were read +system.cpu.num_cc_register_reads 16175 # number of times the CC registers were read system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 5389.998000 # Number of busy cycles +system.cpu.num_busy_cycles 5390.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1007 # Number of branches fetched +system.cpu.Branches 1008 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction +system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction @@ -204,40 +204,40 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5390 # Class of executed instruction -system.membus.trans_dist::ReadReq 5596 # Transaction distribution -system.membus.trans_dist::ReadResp 5607 # Transaction distribution +system.cpu.op_class::total 5391 # Class of executed instruction +system.membus.trans_dist::ReadReq 5597 # Transaction distribution +system.membus.trans_dist::ReadResp 5608 # Transaction distribution system.membus.trans_dist::WriteReq 913 # Transaction distribution system.membus.trans_dist::WriteResp 913 # Transaction distribution system.membus.trans_dist::LoadLockedReq 11 # Transaction distribution system.membus.trans_dist::StoreCondReq 11 # Transaction distribution system.membus.trans_dist::StoreCondResp 11 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9208 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 9210 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 3854 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 13062 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18416 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 13064 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 18420 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 8139 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 26555 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 26559 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 6531 # Request fanout histogram -system.membus.snoop_fanout::mean 2.704946 # Request fanout histogram -system.membus.snoop_fanout::stdev 0.456102 # Request fanout histogram +system.membus.snoop_fanout::samples 6532 # Request fanout histogram +system.membus.snoop_fanout::mean 2.704991 # Request fanout histogram +system.membus.snoop_fanout::stdev 0.456082 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram -system.membus.snoop_fanout::2 1927 29.51% 29.51% # Request fanout histogram -system.membus.snoop_fanout::3 4604 70.49% 100.00% # Request fanout histogram +system.membus.snoop_fanout::2 1927 29.50% 29.50% # Request fanout histogram +system.membus.snoop_fanout::3 4605 70.50% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 6531 # Request fanout histogram +system.membus.snoop_fanout::total 6532 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt index 8573f117d..578791a49 100644 --- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.000026 # Number of seconds simulated -sim_ticks 25815500 # Number of ticks simulated -final_tick 25815500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 25816500 # Number of ticks simulated +final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 263675 # Simulator instruction rate (inst/s) -host_op_rate 307555 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1488783160 # Simulator tick rate (ticks/s) -host_mem_usage 306760 # Number of bytes of host memory used -host_seconds 0.02 # Real time elapsed on the host -sim_insts 4565 # Number of instructions simulated -sim_ops 5329 # Number of ops (including micro ops) simulated +host_inst_rate 77759 # Simulator instruction rate (inst/s) +host_op_rate 90742 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 439383785 # Simulator tick rate (ticks/s) +host_mem_usage 301384 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +sim_insts 4566 # Number of instructions simulated +sim_ops 5330 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory @@ -21,14 +21,14 @@ system.physmem.bytes_inst_read::total 14400 # Nu system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory system.physmem.num_reads::total 350 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 557804420 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 309891344 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 867695764 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 557804420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 557804420 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 557804420 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 309891344 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 867695764 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -147,11 +147,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 13 # Number of system calls -system.cpu.numCycles 51631 # number of cpu cycles simulated +system.cpu.numCycles 51633 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 4565 # Number of instructions committed -system.cpu.committedOps 5329 # Number of ops (including micro ops) committed +system.cpu.committedInsts 4566 # Number of instructions committed +system.cpu.committedOps 5330 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses system.cpu.num_func_calls 203 # number of times a function call or return occured @@ -162,18 +162,18 @@ system.cpu.num_int_register_reads 7573 # nu system.cpu.num_int_register_writes 2728 # number of times the integer registers were written system.cpu.num_fp_register_reads 16 # number of times the floating registers were read system.cpu.num_fp_register_writes 0 # number of times the floating registers were written -system.cpu.num_cc_register_reads 19184 # number of times the CC registers were read +system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written system.cpu.num_mem_refs 1965 # number of memory refs system.cpu.num_load_insts 1027 # Number of load instructions system.cpu.num_store_insts 938 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 51630.998000 # Number of busy cycles +system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 1007 # Number of branches fetched +system.cpu.Branches 1008 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 3418 63.41% 63.41% # Class of executed instruction +system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction @@ -198,22 +198,22 @@ system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Cl system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction -system.cpu.op_class::SimdFloatMisc 3 0.06% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMult 0 0.00% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.54% # Class of executed instruction -system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.54% # Class of executed instruction +system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction +system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 5390 # Class of executed instruction +system.cpu.op_class::total 5391 # Class of executed instruction system.cpu.dcache.tags.replacements 0 # number of replacements -system.cpu.dcache.tags.tagsinuse 82.895840 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 82.895840 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id @@ -320,26 +320,26 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1 # number of replacements -system.cpu.icache.tags.tagsinuse 114.421612 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 4364 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 18.107884 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 114.421612 # Average occupied blocks per requestor -system.cpu.icache.tags.occ_percent::cpu.inst 0.055870 # Average percentage of cache occupancy -system.cpu.icache.tags.occ_percent::total 0.055870 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy +system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 9451 # Number of tag accesses -system.cpu.icache.tags.data_accesses 9451 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 4364 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 4364 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 4364 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 4364 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 4364 # number of overall hits -system.cpu.icache.overall_hits::total 4364 # number of overall hits +system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses +system.cpu.icache.tags.data_accesses 9453 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits +system.cpu.icache.overall_hits::total 4365 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses @@ -352,18 +352,18 @@ system.cpu.icache.demand_miss_latency::cpu.inst 12588500 system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 4605 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 4605 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 4605 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 4605 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 4605 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 4605 # number of overall (read+write) accesses -system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052334 # miss rate for ReadReq accesses -system.cpu.icache.ReadReq_miss_rate::total 0.052334 # miss rate for ReadReq accesses -system.cpu.icache.demand_miss_rate::cpu.inst 0.052334 # miss rate for demand accesses -system.cpu.icache.demand_miss_rate::total 0.052334 # miss rate for demand accesses -system.cpu.icache.overall_miss_rate::cpu.inst 0.052334 # miss rate for overall accesses -system.cpu.icache.overall_miss_rate::total 0.052334 # miss rate for overall accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses +system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses +system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses +system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses +system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses +system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency @@ -390,12 +390,12 @@ system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for ReadReq accesses -system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052334 # mshr miss rate for ReadReq accesses -system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for demand accesses -system.cpu.icache.demand_mshr_miss_rate::total 0.052334 # mshr miss rate for demand accesses -system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052334 # mshr miss rate for overall accesses -system.cpu.icache.overall_mshr_miss_rate::total 0.052334 # mshr miss rate for overall accesses +system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses +system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses +system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses +system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses +system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses +system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency @@ -404,13 +404,13 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 153.835531 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.708552 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 48.126979 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt index b143a6790..cffe156e4 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.054141 # Number of seconds simulated -sim_ticks 54141000000 # Number of ticks simulated -final_tick 54141000000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 54141000500 # Number of ticks simulated +final_tick 54141000500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1893120 # Simulator instruction rate (inst/s) -host_op_rate 1902548 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1131265211 # Simulator tick rate (ticks/s) -host_mem_usage 433636 # Number of bytes of host memory used -host_seconds 47.86 # Real time elapsed on the host -sim_insts 90602407 # Number of instructions simulated -sim_ops 91053638 # Number of ops (including micro ops) simulated +host_inst_rate 1362402 # Simulator instruction rate (inst/s) +host_op_rate 1369187 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 814125846 # Simulator tick rate (ticks/s) +host_mem_usage 428768 # Number of bytes of host memory used +host_seconds 66.50 # Real time elapsed on the host +sim_insts 90602408 # Number of instructions simulated +sim_ops 91053639 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 431323080 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 431323084 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 90016598 # Number of bytes read from this memory -system.physmem.bytes_read::total 521339678 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 431323080 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 431323080 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 521339682 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 431323084 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 431323084 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 18908138 # Number of bytes written to this memory system.physmem.bytes_written::total 18908138 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 107830770 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 107830771 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 22461532 # Number of read requests responded to by this memory -system.physmem.num_reads::total 130292302 # Number of read requests responded to by this memory +system.physmem.num_reads::total 130292303 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 4738868 # Number of write requests responded to by this memory system.physmem.num_writes::total 4738868 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7966662603 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1662632718 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 9629295321 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7966662603 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7966662603 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 349238802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 349238802 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7966662603 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 2011871521 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9978534124 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7966662604 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1662632703 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 9629295306 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7966662604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7966662604 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 349238799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 349238799 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7966662604 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 2011871502 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9978534106 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 108282001 # number of cpu cycles simulated +system.cpu.numCycles 108282002 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90602407 # Number of instructions committed -system.cpu.committedOps 91053638 # Number of ops (including micro ops) committed +system.cpu.committedInsts 90602408 # Number of instructions committed +system.cpu.committedOps 91053639 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured @@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 124257699 # nu system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 271814240 # number of times the CC registers were read +system.cpu.num_cc_register_reads 271814243 # number of times the CC registers were read system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written system.cpu.num_mem_refs 27220755 # number of memory refs system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 108282000.998000 # Number of busy cycles +system.cpu.num_busy_cycles 108282001.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732304 # Number of branches fetched +system.cpu.Branches 18732305 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction @@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Cl system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054080 # Class of executed instruction -system.membus.trans_dist::ReadReq 130287905 # Transaction distribution -system.membus.trans_dist::ReadResp 130291792 # Transaction distribution +system.cpu.op_class::total 91054081 # Class of executed instruction +system.membus.trans_dist::ReadReq 130287906 # Transaction distribution +system.membus.trans_dist::ReadResp 130291793 # Transaction distribution system.membus.trans_dist::WriteReq 4734981 # Transaction distribution system.membus.trans_dist::WriteResp 4734981 # Transaction distribution system.membus.trans_dist::SoftPFReq 510 # Transaction distribution @@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 510 # Tr system.membus.trans_dist::LoadLockedReq 3887 # Transaction distribution system.membus.trans_dist::StoreCondReq 3887 # Transaction distribution system.membus.trans_dist::StoreCondResp 3887 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661540 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 215661542 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 54400800 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 270062340 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323080 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 270062342 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 431323084 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 108924736 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 540247816 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 540247820 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 135031170 # Request fanout histogram +system.membus.snoop_fanout::samples 135031171 # Request fanout histogram system.membus.snoop_fanout::mean 2.798562 # Request fanout histogram system.membus.snoop_fanout::stdev 0.401074 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::2 27200400 20.14% 20.14% # Request fanout histogram -system.membus.snoop_fanout::3 107830770 79.86% 100.00% # Request fanout histogram +system.membus.snoop_fanout::3 107830771 79.86% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 135031170 # Request fanout histogram +system.membus.snoop_fanout::total 135031171 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt index 7176a8af9..c88ed3ac4 100644 --- a/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/10.mcf/ref/arm/linux/simple-timing/stats.txt @@ -1,33 +1,33 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.147041 # Number of seconds simulated -sim_ticks 147041218500 # Number of ticks simulated -final_tick 147041218500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 147041219500 # Number of ticks simulated +final_tick 147041219500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 937429 # Simulator instruction rate (inst/s) -host_op_rate 942087 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1521808702 # Simulator tick rate (ticks/s) -host_mem_usage 442868 # Number of bytes of host memory used -host_seconds 96.62 # Real time elapsed on the host -sim_insts 90576861 # Number of instructions simulated -sim_ops 91026990 # Number of ops (including micro ops) simulated +host_inst_rate 770569 # Simulator instruction rate (inst/s) +host_op_rate 774399 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1250931150 # Simulator tick rate (ticks/s) +host_mem_usage 437476 # Number of bytes of host memory used +host_seconds 117.55 # Real time elapsed on the host +sim_insts 90576862 # Number of instructions simulated +sim_ops 91026991 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 36992 # Number of bytes read from this memory -system.physmem.bytes_read::cpu.data 944768 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 36928 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.data 944832 # Number of bytes read from this memory system.physmem.bytes_read::total 981760 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 36992 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 36992 # Number of instructions bytes read from this memory -system.physmem.num_reads::cpu.inst 578 # Number of read requests responded to by this memory -system.physmem.num_reads::cpu.data 14762 # Number of read requests responded to by this memory +system.physmem.bytes_inst_read::cpu.inst 36928 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 36928 # Number of instructions bytes read from this memory +system.physmem.num_reads::cpu.inst 577 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.data 14763 # Number of read requests responded to by this memory system.physmem.num_reads::total 15340 # Number of read requests responded to by this memory -system.physmem.bw_read::cpu.inst 251576 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 6425192 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 251140 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 6425627 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_read::total 6676767 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 251576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 251576 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 251576 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 6425192 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 251140 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 251140 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 251140 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 6425627 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::total 6676767 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested @@ -147,11 +147,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 442 # Number of system calls -system.cpu.numCycles 294082437 # number of cpu cycles simulated +system.cpu.numCycles 294082439 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 90576861 # Number of instructions committed -system.cpu.committedOps 91026990 # Number of ops (including micro ops) committed +system.cpu.committedInsts 90576862 # Number of instructions committed +system.cpu.committedOps 91026991 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 72326352 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 48 # Number of float alu accesses system.cpu.num_func_calls 112245 # number of times a function call or return occured @@ -162,18 +162,18 @@ system.cpu.num_int_register_reads 124237033 # nu system.cpu.num_int_register_writes 52782988 # number of times the integer registers were written system.cpu.num_fp_register_reads 54 # number of times the floating registers were read system.cpu.num_fp_register_writes 30 # number of times the floating registers were written -system.cpu.num_cc_register_reads 339191618 # number of times the CC registers were read +system.cpu.num_cc_register_reads 339191621 # number of times the CC registers were read system.cpu.num_cc_register_writes 53956115 # number of times the CC registers were written system.cpu.num_mem_refs 27220755 # number of memory refs system.cpu.num_load_insts 22475911 # Number of load instructions system.cpu.num_store_insts 4744844 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 294082436.998000 # Number of busy cycles +system.cpu.num_busy_cycles 294082438.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 18732304 # Number of branches fetched +system.cpu.Branches 18732305 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 63822828 70.09% 70.09% # Class of executed instruction +system.cpu.op_class::IntAlu 63822829 70.09% 70.09% # Class of executed instruction system.cpu.op_class::IntMult 10474 0.01% 70.10% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 70.10% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 70.10% # Class of executed instruction @@ -206,14 +206,14 @@ system.cpu.op_class::MemRead 22475911 24.68% 94.79% # Cl system.cpu.op_class::MemWrite 4744844 5.21% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 91054080 # Class of executed instruction +system.cpu.op_class::total 91054081 # Class of executed instruction system.cpu.dcache.tags.replacements 942702 # number of replacements -system.cpu.dcache.tags.tagsinuse 3565.593939 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 3565.593917 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 26253601 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 946798 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 27.728830 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 54410414000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593939 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 54410415000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 3565.593917 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.870506 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -248,14 +248,14 @@ system.cpu.dcache.demand_misses::cpu.data 946796 # n system.cpu.dcache.demand_misses::total 946796 # number of demand (read+write) misses system.cpu.dcache.overall_misses::cpu.data 946799 # number of overall misses system.cpu.dcache.overall_misses::total 946799 # number of overall misses -system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711364000 # number of ReadReq miss cycles -system.cpu.dcache.ReadReq_miss_latency::total 11711364000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::cpu.data 11711406000 # number of ReadReq miss cycles +system.cpu.dcache.ReadReq_miss_latency::total 11711406000 # number of ReadReq miss cycles system.cpu.dcache.WriteReq_miss_latency::cpu.data 1217183500 # number of WriteReq miss cycles system.cpu.dcache.WriteReq_miss_latency::total 1217183500 # number of WriteReq miss cycles -system.cpu.dcache.demand_miss_latency::cpu.data 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.demand_miss_latency::total 12928547500 # number of demand (read+write) miss cycles -system.cpu.dcache.overall_miss_latency::cpu.data 12928547500 # number of overall miss cycles -system.cpu.dcache.overall_miss_latency::total 12928547500 # number of overall miss cycles +system.cpu.dcache.demand_miss_latency::cpu.data 12928589500 # number of demand (read+write) miss cycles +system.cpu.dcache.demand_miss_latency::total 12928589500 # number of demand (read+write) miss cycles +system.cpu.dcache.overall_miss_latency::cpu.data 12928589500 # number of overall miss cycles +system.cpu.dcache.overall_miss_latency::total 12928589500 # number of overall miss cycles system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.ReadReq_accesses::total 22457135 # number of ReadReq accesses(hits+misses) system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 # number of WriteReq accesses(hits+misses) @@ -280,14 +280,14 @@ system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_miss_rate::total 0.034819 # miss rate for demand accesses system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 # miss rate for overall accesses system.cpu.dcache.overall_miss_rate::total 0.034818 # miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.923494 # average ReadReq miss latency -system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.923494 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13009.970151 # average ReadReq miss latency +system.cpu.dcache.ReadReq_avg_miss_latency::total 13009.970151 # average ReadReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 26114.773971 # average WriteReq miss latency system.cpu.dcache.WriteReq_avg_miss_latency::total 26114.773971 # average WriteReq miss latency -system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.050824 # average overall miss latency -system.cpu.dcache.demand_avg_miss_latency::total 13655.050824 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.007557 # average overall miss latency -system.cpu.dcache.overall_avg_miss_latency::total 13655.007557 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::cpu.data 13655.095184 # average overall miss latency +system.cpu.dcache.demand_avg_miss_latency::total 13655.095184 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::cpu.data 13655.051917 # average overall miss latency +system.cpu.dcache.overall_avg_miss_latency::total 13655.051917 # average overall miss latency system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -314,16 +314,16 @@ system.cpu.dcache.demand_mshr_misses::cpu.data 946795 system.cpu.dcache.demand_mshr_misses::total 946795 # number of demand (read+write) MSHR misses system.cpu.dcache.overall_mshr_misses::cpu.data 946798 # number of overall MSHR misses system.cpu.dcache.overall_mshr_misses::total 946798 # number of overall MSHR misses -system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361045000 # number of ReadReq MSHR miss cycles -system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361045000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10361087000 # number of ReadReq MSHR miss cycles +system.cpu.dcache.ReadReq_mshr_miss_latency::total 10361087000 # number of ReadReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1147270000 # number of WriteReq MSHR miss cycles system.cpu.dcache.WriteReq_mshr_miss_latency::total 1147270000 # number of WriteReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 118500 # number of SoftPFReq MSHR miss cycles system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 118500 # number of SoftPFReq MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508315000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.demand_mshr_miss_latency::total 11508315000 # number of demand (read+write) MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508433500 # number of overall MSHR miss cycles -system.cpu.dcache.overall_mshr_miss_latency::total 11508433500 # number of overall MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11508357000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.demand_mshr_miss_latency::total 11508357000 # number of demand (read+write) MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11508475500 # number of overall MSHR miss cycles +system.cpu.dcache.overall_mshr_miss_latency::total 11508475500 # number of overall MSHR miss cycles system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 # mshr miss rate for ReadReq accesses system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 # mshr miss rate for WriteReq accesses @@ -334,24 +334,24 @@ system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 # mshr miss rate for demand accesses system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 # mshr miss rate for overall accesses system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 # mshr miss rate for overall accesses -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.893511 # average ReadReq mshr miss latency -system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.893511 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 11509.940168 # average ReadReq mshr miss latency +system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 11509.940168 # average ReadReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 24614.773971 # average WriteReq mshr miss latency system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 24614.773971 # average WriteReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 39500 # average SoftPFReq mshr miss latency system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 39500 # average SoftPFReq mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.022999 # average overall mshr miss latency -system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.022999 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.109643 # average overall mshr miss latency -system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.109643 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12155.067359 # average overall mshr miss latency +system.cpu.dcache.demand_avg_mshr_miss_latency::total 12155.067359 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12155.154003 # average overall mshr miss latency +system.cpu.dcache.overall_avg_mshr_miss_latency::total 12155.154003 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 2 # number of replacements -system.cpu.icache.tags.tagsinuse 510.120572 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 107830172 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 510.120567 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 107830173 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 599 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 180016.981636 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 180016.983306 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 510.120572 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 510.120567 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.249082 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 597 # Occupied blocks per task id @@ -360,44 +360,44 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 6 system.cpu.icache.tags.age_task_id_blocks_1024::3 4 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 552 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 215662141 # Number of tag accesses -system.cpu.icache.tags.data_accesses 215662141 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 107830172 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 107830172 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 107830172 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 107830172 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 107830172 # number of overall hits -system.cpu.icache.overall_hits::total 107830172 # number of overall hits +system.cpu.icache.tags.tag_accesses 215662143 # Number of tag accesses +system.cpu.icache.tags.data_accesses 215662143 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 107830173 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 107830173 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 107830173 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 107830173 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 107830173 # number of overall hits +system.cpu.icache.overall_hits::total 107830173 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 599 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 599 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 599 # number of demand (read+write) misses system.cpu.icache.demand_misses::total 599 # number of demand (read+write) misses system.cpu.icache.overall_misses::cpu.inst 599 # number of overall misses system.cpu.icache.overall_misses::total 599 # number of overall misses -system.cpu.icache.ReadReq_miss_latency::cpu.inst 32074000 # number of ReadReq miss cycles -system.cpu.icache.ReadReq_miss_latency::total 32074000 # number of ReadReq miss cycles -system.cpu.icache.demand_miss_latency::cpu.inst 32074000 # number of demand (read+write) miss cycles -system.cpu.icache.demand_miss_latency::total 32074000 # number of demand (read+write) miss cycles -system.cpu.icache.overall_miss_latency::cpu.inst 32074000 # number of overall miss cycles -system.cpu.icache.overall_miss_latency::total 32074000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 107830771 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 107830771 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 107830771 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 107830771 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 107830771 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 107830771 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_miss_latency::cpu.inst 32032000 # number of ReadReq miss cycles +system.cpu.icache.ReadReq_miss_latency::total 32032000 # number of ReadReq miss cycles +system.cpu.icache.demand_miss_latency::cpu.inst 32032000 # number of demand (read+write) miss cycles +system.cpu.icache.demand_miss_latency::total 32032000 # number of demand (read+write) miss cycles +system.cpu.icache.overall_miss_latency::cpu.inst 32032000 # number of overall miss cycles +system.cpu.icache.overall_miss_latency::total 32032000 # number of overall miss cycles +system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 107830772 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 107830772 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 107830772 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 107830772 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 107830772 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000006 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 # miss rate for demand accesses system.cpu.icache.demand_miss_rate::total 0.000006 # miss rate for demand accesses system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 # miss rate for overall accesses system.cpu.icache.overall_miss_rate::total 0.000006 # miss rate for overall accesses -system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53545.909850 # average ReadReq miss latency -system.cpu.icache.ReadReq_avg_miss_latency::total 53545.909850 # average ReadReq miss latency -system.cpu.icache.demand_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency -system.cpu.icache.demand_avg_miss_latency::total 53545.909850 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::cpu.inst 53545.909850 # average overall miss latency -system.cpu.icache.overall_avg_miss_latency::total 53545.909850 # average overall miss latency +system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 53475.792988 # average ReadReq miss latency +system.cpu.icache.ReadReq_avg_miss_latency::total 53475.792988 # average ReadReq miss latency +system.cpu.icache.demand_avg_miss_latency::cpu.inst 53475.792988 # average overall miss latency +system.cpu.icache.demand_avg_miss_latency::total 53475.792988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::cpu.inst 53475.792988 # average overall miss latency +system.cpu.icache.overall_avg_miss_latency::total 53475.792988 # average overall miss latency system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked @@ -412,37 +412,37 @@ system.cpu.icache.demand_mshr_misses::cpu.inst 599 system.cpu.icache.demand_mshr_misses::total 599 # number of demand (read+write) MSHR misses system.cpu.icache.overall_mshr_misses::cpu.inst 599 # number of overall MSHR misses system.cpu.icache.overall_mshr_misses::total 599 # number of overall MSHR misses -system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31175500 # number of ReadReq MSHR miss cycles -system.cpu.icache.ReadReq_mshr_miss_latency::total 31175500 # number of ReadReq MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31175500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.demand_mshr_miss_latency::total 31175500 # number of demand (read+write) MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31175500 # number of overall MSHR miss cycles -system.cpu.icache.overall_mshr_miss_latency::total 31175500 # number of overall MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 31133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.ReadReq_mshr_miss_latency::total 31133500 # number of ReadReq MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::cpu.inst 31133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.demand_mshr_miss_latency::total 31133500 # number of demand (read+write) MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::cpu.inst 31133500 # number of overall MSHR miss cycles +system.cpu.icache.overall_mshr_miss_latency::total 31133500 # number of overall MSHR miss cycles system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 # mshr miss rate for ReadReq accesses system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for demand accesses system.cpu.icache.demand_mshr_miss_rate::total 0.000006 # mshr miss rate for demand accesses system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 # mshr miss rate for overall accesses system.cpu.icache.overall_mshr_miss_rate::total 0.000006 # mshr miss rate for overall accesses -system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52045.909850 # average ReadReq mshr miss latency -system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52045.909850 # average ReadReq mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency -system.cpu.icache.demand_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52045.909850 # average overall mshr miss latency -system.cpu.icache.overall_avg_mshr_miss_latency::total 52045.909850 # average overall mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 51975.792988 # average ReadReq mshr miss latency +system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 51975.792988 # average ReadReq mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 51975.792988 # average overall mshr miss latency +system.cpu.icache.demand_avg_mshr_miss_latency::total 51975.792988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 51975.792988 # average overall mshr miss latency +system.cpu.icache.overall_avg_mshr_miss_latency::total 51975.792988 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 9567.852421 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 9567.852356 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1827177 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 15323 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 119.244078 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446344 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 495.172977 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 193.233100 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 8879.446284 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.172984 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 194.233089 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.270979 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015111 # Average percentage of cache occupancy -system.cpu.l2cache.tags.occ_percent::cpu.data 0.005897 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 # Average percentage of cache occupancy +system.cpu.l2cache.tags.occ_percent::cpu.data 0.005928 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::total 0.291988 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_task_id_blocks::1024 15323 # Occupied blocks per task id system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id @@ -453,40 +453,40 @@ system.cpu.l2cache.tags.age_task_id_blocks_1024::4 13704 system.cpu.l2cache.tags.occ_task_id_percent::1024 0.467621 # Percentage of cache occupancy per task id system.cpu.l2cache.tags.tag_accesses 15179780 # Number of tag accesses system.cpu.l2cache.tags.data_accesses 15179780 # Number of data accesses -system.cpu.l2cache.ReadReq_hits::cpu.inst 21 # number of ReadReq hits -system.cpu.l2cache.ReadReq_hits::cpu.data 899975 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.inst 22 # number of ReadReq hits +system.cpu.l2cache.ReadReq_hits::cpu.data 899974 # number of ReadReq hits system.cpu.l2cache.ReadReq_hits::total 899996 # number of ReadReq hits system.cpu.l2cache.Writeback_hits::writebacks 942334 # number of Writeback hits system.cpu.l2cache.Writeback_hits::total 942334 # number of Writeback hits system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 # number of ReadExReq hits system.cpu.l2cache.ReadExReq_hits::total 32061 # number of ReadExReq hits -system.cpu.l2cache.demand_hits::cpu.inst 21 # number of demand (read+write) hits -system.cpu.l2cache.demand_hits::cpu.data 932036 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.inst 22 # number of demand (read+write) hits +system.cpu.l2cache.demand_hits::cpu.data 932035 # number of demand (read+write) hits system.cpu.l2cache.demand_hits::total 932057 # number of demand (read+write) hits -system.cpu.l2cache.overall_hits::cpu.inst 21 # number of overall hits -system.cpu.l2cache.overall_hits::cpu.data 932036 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.inst 22 # number of overall hits +system.cpu.l2cache.overall_hits::cpu.data 932035 # number of overall hits system.cpu.l2cache.overall_hits::total 932057 # number of overall hits -system.cpu.l2cache.ReadReq_misses::cpu.inst 578 # number of ReadReq misses -system.cpu.l2cache.ReadReq_misses::cpu.data 214 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.inst 577 # number of ReadReq misses +system.cpu.l2cache.ReadReq_misses::cpu.data 215 # number of ReadReq misses system.cpu.l2cache.ReadReq_misses::total 792 # number of ReadReq misses system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 # number of ReadExReq misses system.cpu.l2cache.ReadExReq_misses::total 14548 # number of ReadExReq misses -system.cpu.l2cache.demand_misses::cpu.inst 578 # number of demand (read+write) misses -system.cpu.l2cache.demand_misses::cpu.data 14762 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.inst 577 # number of demand (read+write) misses +system.cpu.l2cache.demand_misses::cpu.data 14763 # number of demand (read+write) misses system.cpu.l2cache.demand_misses::total 15340 # number of demand (read+write) misses -system.cpu.l2cache.overall_misses::cpu.inst 578 # number of overall misses -system.cpu.l2cache.overall_misses::cpu.data 14762 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.inst 577 # number of overall misses +system.cpu.l2cache.overall_misses::cpu.data 14763 # number of overall misses system.cpu.l2cache.overall_misses::total 15340 # number of overall misses -system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30356000 # number of ReadReq miss cycles -system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11237000 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 30303500 # number of ReadReq miss cycles +system.cpu.l2cache.ReadReq_miss_latency::cpu.data 11289500 # number of ReadReq miss cycles system.cpu.l2cache.ReadReq_miss_latency::total 41593000 # number of ReadReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 764020500 # number of ReadExReq miss cycles system.cpu.l2cache.ReadExReq_miss_latency::total 764020500 # number of ReadExReq miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.inst 30356000 # number of demand (read+write) miss cycles -system.cpu.l2cache.demand_miss_latency::cpu.data 775257500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.inst 30303500 # number of demand (read+write) miss cycles +system.cpu.l2cache.demand_miss_latency::cpu.data 775310000 # number of demand (read+write) miss cycles system.cpu.l2cache.demand_miss_latency::total 805613500 # number of demand (read+write) miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.inst 30356000 # number of overall miss cycles -system.cpu.l2cache.overall_miss_latency::cpu.data 775257500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.inst 30303500 # number of overall miss cycles +system.cpu.l2cache.overall_miss_latency::cpu.data 775310000 # number of overall miss cycles system.cpu.l2cache.overall_miss_latency::total 805613500 # number of overall miss cycles system.cpu.l2cache.ReadReq_accesses::cpu.inst 599 # number of ReadReq accesses(hits+misses) system.cpu.l2cache.ReadReq_accesses::cpu.data 900189 # number of ReadReq accesses(hits+misses) @@ -501,27 +501,27 @@ system.cpu.l2cache.demand_accesses::total 947397 # n system.cpu.l2cache.overall_accesses::cpu.inst 599 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::cpu.data 946798 # number of overall (read+write) accesses system.cpu.l2cache.overall_accesses::total 947397 # number of overall (read+write) accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.964942 # miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000238 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.963272 # miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.000239 # miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_miss_rate::total 0.000879 # miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 # miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 # miss rate for ReadExReq accesses -system.cpu.l2cache.demand_miss_rate::cpu.inst 0.964942 # miss rate for demand accesses -system.cpu.l2cache.demand_miss_rate::cpu.data 0.015591 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 # miss rate for demand accesses +system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 # miss rate for demand accesses system.cpu.l2cache.demand_miss_rate::total 0.016192 # miss rate for demand accesses -system.cpu.l2cache.overall_miss_rate::cpu.inst 0.964942 # miss rate for overall accesses -system.cpu.l2cache.overall_miss_rate::cpu.data 0.015591 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 # miss rate for overall accesses +system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 # miss rate for overall accesses system.cpu.l2cache.overall_miss_rate::total 0.016192 # miss rate for overall accesses -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.031142 # average ReadReq miss latency -system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.345794 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52519.064125 # average ReadReq miss latency +system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52509.302326 # average ReadReq miss latency system.cpu.l2cache.ReadReq_avg_miss_latency::total 52516.414141 # average ReadReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52517.218862 # average ReadExReq miss latency system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52517.218862 # average ReadExReq miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency -system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52519.064125 # average overall miss latency +system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52517.103570 # average overall miss latency system.cpu.l2cache.demand_avg_miss_latency::total 52517.177314 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.031142 # average overall miss latency -system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.104728 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52519.064125 # average overall miss latency +system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52517.103570 # average overall miss latency system.cpu.l2cache.overall_avg_miss_latency::total 52517.177314 # average overall miss latency system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked @@ -531,38 +531,38 @@ system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked system.cpu.l2cache.fast_writes 0 # number of fast writes performed system.cpu.l2cache.cache_copies 0 # number of cache copies performed -system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 578 # number of ReadReq MSHR misses -system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 214 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 577 # number of ReadReq MSHR misses +system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 215 # number of ReadReq MSHR misses system.cpu.l2cache.ReadReq_mshr_misses::total 792 # number of ReadReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 # number of ReadExReq MSHR misses system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 # number of ReadExReq MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.inst 578 # number of demand (read+write) MSHR misses -system.cpu.l2cache.demand_mshr_misses::cpu.data 14762 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 # number of demand (read+write) MSHR misses +system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 # number of demand (read+write) MSHR misses system.cpu.l2cache.demand_mshr_misses::total 15340 # number of demand (read+write) MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.inst 578 # number of overall MSHR misses -system.cpu.l2cache.overall_mshr_misses::cpu.data 14762 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 # number of overall MSHR misses +system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 # number of overall MSHR misses system.cpu.l2cache.overall_mshr_misses::total 15340 # number of overall MSHR misses -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23409000 # number of ReadReq MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8667000 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 23368500 # number of ReadReq MSHR miss cycles +system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 8707500 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadReq_mshr_miss_latency::total 32076000 # number of ReadReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 589194000 # number of ReadExReq MSHR miss cycles system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 589194000 # number of ReadExReq MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23409000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597861000 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 23368500 # number of demand (read+write) MSHR miss cycles +system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 597901500 # number of demand (read+write) MSHR miss cycles system.cpu.l2cache.demand_mshr_miss_latency::total 621270000 # number of demand (read+write) MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23409000 # number of overall MSHR miss cycles -system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597861000 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 23368500 # number of overall MSHR miss cycles +system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 597901500 # number of overall MSHR miss cycles system.cpu.l2cache.overall_mshr_miss_latency::total 621270000 # number of overall MSHR miss cycles -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for ReadReq accesses -system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000238 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for ReadReq accesses +system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.000239 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.000879 # mshr miss rate for ReadReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 # mshr miss rate for ReadExReq accesses system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 # mshr miss rate for ReadExReq accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for demand accesses -system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for demand accesses +system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for demand accesses system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 # mshr miss rate for demand accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.964942 # mshr miss rate for overall accesses -system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015591 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 # mshr miss rate for overall accesses +system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 # mshr miss rate for overall accesses system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 # mshr miss rate for overall accesses system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt index 93e5e3e06..313b6d716 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.048960 # Number of seconds simulated -sim_ticks 48960011000 # Number of ticks simulated -final_tick 48960011000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 48960011500 # Number of ticks simulated +final_tick 48960011500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1566427 # Simulator instruction rate (inst/s) -host_op_rate 2003243 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1081494789 # Simulator tick rate (ticks/s) -host_mem_usage 308080 # Number of bytes of host memory used -host_seconds 45.27 # Real time elapsed on the host -sim_insts 70913181 # Number of instructions simulated -sim_ops 90688136 # Number of ops (including micro ops) simulated +host_inst_rate 1111911 # Simulator instruction rate (inst/s) +host_op_rate 1421979 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 767686935 # Simulator tick rate (ticks/s) +host_mem_usage 303468 # Number of bytes of host memory used +host_seconds 63.78 # Real time elapsed on the host +sim_insts 70913182 # Number of instructions simulated +sim_ops 90688137 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 312580272 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 312580276 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 106573345 # Number of bytes read from this memory -system.physmem.bytes_read::total 419153617 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 312580272 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 312580272 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 419153621 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 312580276 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 312580276 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 78660211 # Number of bytes written to this memory system.physmem.bytes_written::total 78660211 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 78145068 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 78145069 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 22919730 # Number of read requests responded to by this memory -system.physmem.num_reads::total 101064798 # Number of read requests responded to by this memory +system.physmem.num_reads::total 101064799 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 19865820 # Number of write requests responded to by this memory system.physmem.num_writes::total 19865820 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 6384399546 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 2176742669 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8561142215 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 6384399546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 6384399546 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 1606621596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 1606621596 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 6384399546 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 3783364264 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 10167763810 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 6384399562 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 2176742646 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8561142209 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 6384399562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 6384399562 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 1606621579 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 1606621579 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 6384399562 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 3783364226 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 10167763788 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 97920023 # number of cpu cycles simulated +system.cpu.numCycles 97920024 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70913181 # Number of instructions committed -system.cpu.committedOps 90688136 # Number of ops (including micro ops) committed +system.cpu.committedInsts 70913182 # Number of instructions committed +system.cpu.committedOps 90688137 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured @@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 141479310 # nu system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 266608028 # number of times the CC registers were read +system.cpu.num_cc_register_reads 266608031 # number of times the CC registers were read system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written system.cpu.num_mem_refs 43422001 # number of memory refs system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 97920022.998000 # Number of busy cycles +system.cpu.num_busy_cycles 97920023.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741485 # Number of branches fetched +system.cpu.Branches 13741486 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction @@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690083 # Class of executed instruction -system.membus.trans_dist::ReadReq 100925135 # Transaction distribution -system.membus.trans_dist::ReadResp 100941054 # Transaction distribution +system.cpu.op_class::total 90690084 # Class of executed instruction +system.membus.trans_dist::ReadReq 100925136 # Transaction distribution +system.membus.trans_dist::ReadResp 100941055 # Transaction distribution system.membus.trans_dist::WriteReq 19849901 # Transaction distribution system.membus.trans_dist::WriteResp 19849901 # Transaction distribution system.membus.trans_dist::SoftPFReq 123744 # Transaction distribution @@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 123744 # Tr system.membus.trans_dist::LoadLockedReq 15919 # Transaction distribution system.membus.trans_dist::StoreCondReq 15919 # Transaction distribution system.membus.trans_dist::StoreCondResp 15919 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290136 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 156290138 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 85571100 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 241861236 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580272 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 241861238 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 312580276 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 185233556 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 497813828 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 497813832 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 120930618 # Request fanout histogram +system.membus.snoop_fanout::samples 120930619 # Request fanout histogram system.membus.snoop_fanout::mean 2.646198 # Request fanout histogram system.membus.snoop_fanout::stdev 0.478149 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::2 42785550 35.38% 35.38% # Request fanout histogram -system.membus.snoop_fanout::3 78145068 64.62% 100.00% # Request fanout histogram +system.membus.snoop_fanout::3 78145069 64.62% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 120930618 # Request fanout histogram +system.membus.snoop_fanout::total 120930619 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt index 6d597c67f..91d42cd77 100644 --- a/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/50.vortex/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.127293 # Number of seconds simulated -sim_ticks 127293405500 # Number of ticks simulated -final_tick 127293405500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 127293406500 # Number of ticks simulated +final_tick 127293406500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 802256 # Simulator instruction rate (inst/s) -host_op_rate 1024256 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1451138855 # Simulator tick rate (ticks/s) -host_mem_usage 317568 # Number of bytes of host memory used -host_seconds 87.72 # Real time elapsed on the host -sim_insts 70373628 # Number of instructions simulated -sim_ops 89847362 # Number of ops (including micro ops) simulated +host_inst_rate 627920 # Simulator instruction rate (inst/s) +host_op_rate 801678 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1135795886 # Simulator tick rate (ticks/s) +host_mem_usage 312172 # Number of bytes of host memory used +host_seconds 112.07 # Real time elapsed on the host +sim_insts 70373629 # Number of instructions simulated +sim_ops 89847363 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 255488 # Number of bytes read from this memory @@ -26,16 +26,16 @@ system.physmem.num_reads::total 127812 # Nu system.physmem.num_writes::writebacks 83909 # Number of write requests responded to by this memory system.physmem.num_writes::total 83909 # Number of write requests responded to by this memory system.physmem.bw_read::cpu.inst 2007080 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 62253657 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 64260737 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 62253656 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 64260736 # Total read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::cpu.inst 2007080 # Instruction read bandwidth from this memory (bytes/s) system.physmem.bw_inst_read::total 2007080 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::writebacks 42187386 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 42187386 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::writebacks 42187386 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_write::writebacks 42187385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 42187385 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::writebacks 42187385 # Total bandwidth to/from this memory (bytes/s) system.physmem.bw_total::cpu.inst 2007080 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 62253657 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 106448122 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 62253656 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 106448121 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -154,11 +154,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 1946 # Number of system calls -system.cpu.numCycles 254586811 # number of cpu cycles simulated +system.cpu.numCycles 254586813 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 70373628 # Number of instructions committed -system.cpu.committedOps 89847362 # Number of ops (including micro ops) committed +system.cpu.committedInsts 70373629 # Number of instructions committed +system.cpu.committedOps 89847363 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 81528488 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 56 # Number of float alu accesses system.cpu.num_func_calls 3311620 # number of times a function call or return occured @@ -169,18 +169,18 @@ system.cpu.num_int_register_reads 141328474 # nu system.cpu.num_int_register_writes 53916283 # number of times the integer registers were written system.cpu.num_fp_register_reads 36 # number of times the floating registers were read system.cpu.num_fp_register_writes 20 # number of times the floating registers were written -system.cpu.num_cc_register_reads 334802003 # number of times the CC registers were read +system.cpu.num_cc_register_reads 334802006 # number of times the CC registers were read system.cpu.num_cc_register_writes 36877020 # number of times the CC registers were written system.cpu.num_mem_refs 43422001 # number of memory refs system.cpu.num_load_insts 22866262 # Number of load instructions system.cpu.num_store_insts 20555739 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 254586810.998000 # Number of busy cycles +system.cpu.num_busy_cycles 254586812.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 13741485 # Number of branches fetched +system.cpu.Branches 13741486 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 47187956 52.03% 52.03% # Class of executed instruction +system.cpu.op_class::IntAlu 47187957 52.03% 52.03% # Class of executed instruction system.cpu.op_class::IntMult 80119 0.09% 52.12% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 52.12% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 52.12% # Class of executed instruction @@ -213,14 +213,14 @@ system.cpu.op_class::MemRead 22866262 25.21% 77.33% # Cl system.cpu.op_class::MemWrite 20555739 22.67% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 90690083 # Class of executed instruction +system.cpu.op_class::total 90690084 # Class of executed instruction system.cpu.dcache.tags.replacements 155902 # number of replacements -system.cpu.dcache.tags.tagsinuse 4076.389361 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 4076.389329 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 42608169 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 159998 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 266.304385 # Average number of references to valid blocks. -system.cpu.dcache.tags.warmup_cycle 1061070000 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389361 # Average occupied blocks per requestor +system.cpu.dcache.tags.warmup_cycle 1061071000 # Cycle when the warmup percentage was hit. +system.cpu.dcache.tags.occ_blocks::cpu.data 4076.389329 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.995212 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id @@ -352,12 +352,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 44030.809760 system.cpu.dcache.overall_avg_mshr_miss_latency::total 44030.809760 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 16890 # number of replacements -system.cpu.icache.tags.tagsinuse 1733.672975 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 78126161 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1733.672960 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 78126162 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 18908 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 4131.910355 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 4131.910408 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672975 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1733.672960 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.846520 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 2018 # Occupied blocks per task id @@ -366,14 +366,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::1 15 system.cpu.icache.tags.age_task_id_blocks_1024::3 294 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 1645 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.985352 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 156309046 # Number of tag accesses -system.cpu.icache.tags.data_accesses 156309046 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 78126161 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 78126161 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 78126161 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 78126161 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 78126161 # number of overall hits -system.cpu.icache.overall_hits::total 78126161 # number of overall hits +system.cpu.icache.tags.tag_accesses 156309048 # Number of tag accesses +system.cpu.icache.tags.data_accesses 156309048 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 78126162 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 78126162 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 78126162 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 78126162 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 78126162 # number of overall hits +system.cpu.icache.overall_hits::total 78126162 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 18908 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 18908 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 18908 # number of demand (read+write) misses @@ -386,12 +386,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 413935000 system.cpu.icache.demand_miss_latency::total 413935000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 413935000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 413935000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 78145069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 78145069 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 78145069 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 78145069 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 78145069 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 78145069 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 78145070 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 78145070 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 78145070 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 78145070 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 78145070 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 78145070 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000242 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000242 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000242 # miss rate for demand accesses @@ -438,14 +438,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 20392.056272 system.cpu.icache.overall_avg_mshr_miss_latency::total 20392.056272 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 94693 # number of replacements -system.cpu.l2cache.tags.tagsinuse 30351.006010 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 30351.005772 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 74295 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 125788 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.590637 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.l2cache.tags.occ_blocks::writebacks 27796.868072 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768401 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369537 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::writebacks 27796.867853 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1151.768393 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 1402.369526 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.848293 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035149 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.042797 # Average percentage of cache occupancy diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt index e6a9622eb..772df96ed 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-atomic/stats.txt @@ -1,40 +1,40 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.099596 # Number of seconds simulated -sim_ticks 99596491000 # Number of ticks simulated -final_tick 99596491000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 99596491500 # Number of ticks simulated +final_tick 99596491500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1940320 # Simulator instruction rate (inst/s) -host_op_rate 2045410 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1121471108 # Simulator tick rate (ticks/s) -host_mem_usage 304628 # Number of bytes of host memory used -host_seconds 88.81 # Real time elapsed on the host -sim_insts 172317409 # Number of instructions simulated -sim_ops 181650341 # Number of ops (including micro ops) simulated +host_inst_rate 1304038 # Simulator instruction rate (inst/s) +host_op_rate 1374666 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 753711187 # Simulator tick rate (ticks/s) +host_mem_usage 298984 # Number of bytes of host memory used +host_seconds 132.14 # Real time elapsed on the host +sim_insts 172317410 # Number of instructions simulated +sim_ops 181650342 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks -system.physmem.bytes_read::cpu.inst 759440204 # Number of bytes read from this memory +system.physmem.bytes_read::cpu.inst 759440208 # Number of bytes read from this memory system.physmem.bytes_read::cpu.data 110533661 # Number of bytes read from this memory -system.physmem.bytes_read::total 869973865 # Number of bytes read from this memory -system.physmem.bytes_inst_read::cpu.inst 759440204 # Number of instructions bytes read from this memory -system.physmem.bytes_inst_read::total 759440204 # Number of instructions bytes read from this memory +system.physmem.bytes_read::total 869973869 # Number of bytes read from this memory +system.physmem.bytes_inst_read::cpu.inst 759440208 # Number of instructions bytes read from this memory +system.physmem.bytes_inst_read::total 759440208 # Number of instructions bytes read from this memory system.physmem.bytes_written::cpu.data 45252940 # Number of bytes written to this memory system.physmem.bytes_written::total 45252940 # Number of bytes written to this memory -system.physmem.num_reads::cpu.inst 189860051 # Number of read requests responded to by this memory +system.physmem.num_reads::cpu.inst 189860052 # Number of read requests responded to by this memory system.physmem.num_reads::cpu.data 27777721 # Number of read requests responded to by this memory -system.physmem.num_reads::total 217637772 # Number of read requests responded to by this memory +system.physmem.num_reads::total 217637773 # Number of read requests responded to by this memory system.physmem.num_writes::cpu.data 12386694 # Number of write requests responded to by this memory system.physmem.num_writes::total 12386694 # Number of write requests responded to by this memory -system.physmem.bw_read::cpu.inst 7625170288 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::cpu.data 1109814813 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_read::total 8734985101 # Total read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::cpu.inst 7625170288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_inst_read::total 7625170288 # Instruction read bandwidth from this memory (bytes/s) -system.physmem.bw_write::cpu.data 454362795 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_write::total 454362795 # Write bandwidth from this memory (bytes/s) -system.physmem.bw_total::cpu.inst 7625170288 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::cpu.data 1564177607 # Total bandwidth to/from this memory (bytes/s) -system.physmem.bw_total::total 9189347896 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_read::cpu.inst 7625170290 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::cpu.data 1109814807 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_read::total 8734985097 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::cpu.inst 7625170290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read::total 7625170290 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write::cpu.data 454362792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_write::total 454362792 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total::cpu.inst 7625170290 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::cpu.data 1564177600 # Total bandwidth to/from this memory (bytes/s) +system.physmem.bw_total::total 9189347890 # Total bandwidth to/from this memory (bytes/s) system.cpu_clk_domain.clock 500 # Clock period in ticks system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst @@ -153,11 +153,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 199192983 # number of cpu cycles simulated +system.cpu.numCycles 199192984 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 172317409 # Number of instructions committed -system.cpu.committedOps 181650341 # Number of ops (including micro ops) committed +system.cpu.committedInsts 172317410 # Number of instructions committed +system.cpu.committedOps 181650342 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3545028 # number of times a function call or return occured @@ -168,18 +168,18 @@ system.cpu.num_int_register_reads 241970171 # nu system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_cc_register_reads 543309967 # number of times the CC registers were read +system.cpu.num_cc_register_reads 543309970 # number of times the CC registers were read system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written system.cpu.num_mem_refs 40540779 # number of memory refs system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 199192982.998000 # Number of busy cycles +system.cpu.num_busy_cycles 199192983.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 40300311 # Number of branches fetched +system.cpu.Branches 40300312 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction @@ -212,9 +212,9 @@ system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Cl system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 181650742 # Class of executed instruction -system.membus.trans_dist::ReadReq 217614902 # Transaction distribution -system.membus.trans_dist::ReadResp 217637309 # Transaction distribution +system.cpu.op_class::total 181650743 # Class of executed instruction +system.membus.trans_dist::ReadReq 217614903 # Transaction distribution +system.membus.trans_dist::ReadResp 217637310 # Transaction distribution system.membus.trans_dist::WriteReq 12364287 # Transaction distribution system.membus.trans_dist::WriteResp 12364287 # Transaction distribution system.membus.trans_dist::SoftPFReq 463 # Transaction distribution @@ -222,24 +222,24 @@ system.membus.trans_dist::SoftPFResp 463 # Tr system.membus.trans_dist::LoadLockedReq 22407 # Transaction distribution system.membus.trans_dist::StoreCondReq 22407 # Transaction distribution system.membus.trans_dist::StoreCondResp 22407 # Transaction distribution -system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720102 # Packet count per connected master and slave (bytes) +system.membus.pkt_count_system.cpu.icache_port::system.physmem.port 379720104 # Packet count per connected master and slave (bytes) system.membus.pkt_count_system.cpu.dcache_port::system.physmem.port 80328830 # Packet count per connected master and slave (bytes) -system.membus.pkt_count::total 460048932 # Packet count per connected master and slave (bytes) -system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440204 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_count::total 460048934 # Packet count per connected master and slave (bytes) +system.membus.pkt_size_system.cpu.icache_port::system.physmem.port 759440208 # Cumulative packet size per connected master and slave (bytes) system.membus.pkt_size_system.cpu.dcache_port::system.physmem.port 155786601 # Cumulative packet size per connected master and slave (bytes) -system.membus.pkt_size::total 915226805 # Cumulative packet size per connected master and slave (bytes) +system.membus.pkt_size::total 915226809 # Cumulative packet size per connected master and slave (bytes) system.membus.snoops 0 # Total snoops (count) -system.membus.snoop_fanout::samples 230024466 # Request fanout histogram +system.membus.snoop_fanout::samples 230024467 # Request fanout histogram system.membus.snoop_fanout::mean 2.825391 # Request fanout histogram system.membus.snoop_fanout::stdev 0.379633 # Request fanout histogram system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram system.membus.snoop_fanout::2 40164415 17.46% 17.46% # Request fanout histogram -system.membus.snoop_fanout::3 189860051 82.54% 100.00% # Request fanout histogram +system.membus.snoop_fanout::3 189860052 82.54% 100.00% # Request fanout histogram system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram system.membus.snoop_fanout::min_value 2 # Request fanout histogram system.membus.snoop_fanout::max_value 3 # Request fanout histogram -system.membus.snoop_fanout::total 230024466 # Request fanout histogram +system.membus.snoop_fanout::total 230024467 # Request fanout histogram ---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt index 6ce1a7f0e..e97c269ba 100644 --- a/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt +++ b/tests/quick/se/70.twolf/ref/arm/linux/simple-timing/stats.txt @@ -1,16 +1,16 @@ ---------- Begin Simulation Statistics ---------- sim_seconds 0.230173 # Number of seconds simulated -sim_ticks 230173357500 # Number of ticks simulated -final_tick 230173357500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_ticks 230173358500 # Number of ticks simulated +final_tick 230173358500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) sim_freq 1000000000000 # Frequency of simulated ticks -host_inst_rate 1098511 # Simulator instruction rate (inst/s) -host_op_rate 1158108 # Simulator op (including micro ops) rate (op/s) -host_tick_rate 1471393960 # Simulator tick rate (ticks/s) -host_mem_usage 313104 # Number of bytes of host memory used -host_seconds 156.43 # Real time elapsed on the host -sim_insts 171842483 # Number of instructions simulated -sim_ops 181165370 # Number of ops (including micro ops) simulated +host_inst_rate 794003 # Simulator instruction rate (inst/s) +host_op_rate 837080 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 1063522318 # Simulator tick rate (ticks/s) +host_mem_usage 308720 # Number of bytes of host memory used +host_seconds 216.43 # Real time elapsed on the host +sim_insts 171842484 # Number of instructions simulated +sim_ops 181165371 # Number of ops (including micro ops) simulated system.voltage_domain.voltage 1 # Voltage in Volts system.clk_domain.clock 1000 # Clock period in ticks system.physmem.bytes_read::cpu.inst 110656 # Number of bytes read from this memory @@ -147,11 +147,11 @@ system.cpu.itb.hits 0 # DT system.cpu.itb.misses 0 # DTB misses system.cpu.itb.accesses 0 # DTB accesses system.cpu.workload.num_syscalls 400 # Number of system calls -system.cpu.numCycles 460346715 # number of cpu cycles simulated +system.cpu.numCycles 460346717 # number of cpu cycles simulated system.cpu.numWorkItemsStarted 0 # number of work items this cpu started system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed -system.cpu.committedInsts 171842483 # Number of instructions committed -system.cpu.committedOps 181165370 # Number of ops (including micro ops) committed +system.cpu.committedInsts 171842484 # Number of instructions committed +system.cpu.committedOps 181165371 # Number of ops (including micro ops) committed system.cpu.num_int_alu_accesses 143085668 # Number of integer alu accesses system.cpu.num_fp_alu_accesses 1752310 # Number of float alu accesses system.cpu.num_func_calls 3545028 # number of times a function call or return occured @@ -162,18 +162,18 @@ system.cpu.num_int_register_reads 242291225 # nu system.cpu.num_int_register_writes 98192342 # number of times the integer registers were written system.cpu.num_fp_register_reads 2822225 # number of times the floating registers were read system.cpu.num_fp_register_writes 2378039 # number of times the floating registers were written -system.cpu.num_cc_register_reads 626384527 # number of times the CC registers were read +system.cpu.num_cc_register_reads 626384530 # number of times the CC registers were read system.cpu.num_cc_register_writes 190815535 # number of times the CC registers were written system.cpu.num_mem_refs 40540779 # number of memory refs system.cpu.num_load_insts 27896144 # Number of load instructions system.cpu.num_store_insts 12644635 # Number of store instructions system.cpu.num_idle_cycles 0.002000 # Number of idle cycles -system.cpu.num_busy_cycles 460346714.998000 # Number of busy cycles +system.cpu.num_busy_cycles 460346716.998000 # Number of busy cycles system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles system.cpu.idle_fraction 0.000000 # Percentage of idle cycles -system.cpu.Branches 40300311 # Number of branches fetched +system.cpu.Branches 40300312 # Number of branches fetched system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction -system.cpu.op_class::IntAlu 138988212 76.51% 76.51% # Class of executed instruction +system.cpu.op_class::IntAlu 138988213 76.51% 76.51% # Class of executed instruction system.cpu.op_class::IntMult 908940 0.50% 77.01% # Class of executed instruction system.cpu.op_class::IntDiv 0 0.00% 77.01% # Class of executed instruction system.cpu.op_class::FloatAdd 0 0.00% 77.01% # Class of executed instruction @@ -206,14 +206,14 @@ system.cpu.op_class::MemRead 27896144 15.36% 93.04% # Cl system.cpu.op_class::MemWrite 12644635 6.96% 100.00% # Class of executed instruction system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction -system.cpu.op_class::total 181650742 # Class of executed instruction +system.cpu.op_class::total 181650743 # Class of executed instruction system.cpu.dcache.tags.replacements 40 # number of replacements -system.cpu.dcache.tags.tagsinuse 1363.619277 # Cycle average of tags in use +system.cpu.dcache.tags.tagsinuse 1363.619271 # Cycle average of tags in use system.cpu.dcache.tags.total_refs 40162626 # Total number of references to valid blocks. system.cpu.dcache.tags.sampled_refs 1789 # Sample count of references to valid blocks. system.cpu.dcache.tags.avg_refs 22449.762996 # Average number of references to valid blocks. system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619277 # Average occupied blocks per requestor +system.cpu.dcache.tags.occ_blocks::cpu.data 1363.619271 # Average occupied blocks per requestor system.cpu.dcache.tags.occ_percent::cpu.data 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_percent::total 0.332915 # Average percentage of cache occupancy system.cpu.dcache.tags.occ_task_id_blocks::1024 1749 # Occupied blocks per task id @@ -341,12 +341,12 @@ system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 52003.912800 system.cpu.dcache.overall_avg_mshr_miss_latency::total 52003.912800 # average overall mshr miss latency system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.icache.tags.replacements 1506 # number of replacements -system.cpu.icache.tags.tagsinuse 1147.992598 # Cycle average of tags in use -system.cpu.icache.tags.total_refs 189857001 # Total number of references to valid blocks. +system.cpu.icache.tags.tagsinuse 1147.992594 # Cycle average of tags in use +system.cpu.icache.tags.total_refs 189857002 # Total number of references to valid blocks. system.cpu.icache.tags.sampled_refs 3051 # Sample count of references to valid blocks. -system.cpu.icache.tags.avg_refs 62227.794494 # Average number of references to valid blocks. +system.cpu.icache.tags.avg_refs 62227.794821 # Average number of references to valid blocks. system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992598 # Average occupied blocks per requestor +system.cpu.icache.tags.occ_blocks::cpu.inst 1147.992594 # Average occupied blocks per requestor system.cpu.icache.tags.occ_percent::cpu.inst 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_percent::total 0.560543 # Average percentage of cache occupancy system.cpu.icache.tags.occ_task_id_blocks::1024 1545 # Occupied blocks per task id @@ -356,14 +356,14 @@ system.cpu.icache.tags.age_task_id_blocks_1024::2 288 system.cpu.icache.tags.age_task_id_blocks_1024::3 270 # Occupied blocks per task id system.cpu.icache.tags.age_task_id_blocks_1024::4 942 # Occupied blocks per task id system.cpu.icache.tags.occ_task_id_percent::1024 0.754395 # Percentage of cache occupancy per task id -system.cpu.icache.tags.tag_accesses 379723155 # Number of tag accesses -system.cpu.icache.tags.data_accesses 379723155 # Number of data accesses -system.cpu.icache.ReadReq_hits::cpu.inst 189857001 # number of ReadReq hits -system.cpu.icache.ReadReq_hits::total 189857001 # number of ReadReq hits -system.cpu.icache.demand_hits::cpu.inst 189857001 # number of demand (read+write) hits -system.cpu.icache.demand_hits::total 189857001 # number of demand (read+write) hits -system.cpu.icache.overall_hits::cpu.inst 189857001 # number of overall hits -system.cpu.icache.overall_hits::total 189857001 # number of overall hits +system.cpu.icache.tags.tag_accesses 379723157 # Number of tag accesses +system.cpu.icache.tags.data_accesses 379723157 # Number of data accesses +system.cpu.icache.ReadReq_hits::cpu.inst 189857002 # number of ReadReq hits +system.cpu.icache.ReadReq_hits::total 189857002 # number of ReadReq hits +system.cpu.icache.demand_hits::cpu.inst 189857002 # number of demand (read+write) hits +system.cpu.icache.demand_hits::total 189857002 # number of demand (read+write) hits +system.cpu.icache.overall_hits::cpu.inst 189857002 # number of overall hits +system.cpu.icache.overall_hits::total 189857002 # number of overall hits system.cpu.icache.ReadReq_misses::cpu.inst 3051 # number of ReadReq misses system.cpu.icache.ReadReq_misses::total 3051 # number of ReadReq misses system.cpu.icache.demand_misses::cpu.inst 3051 # number of demand (read+write) misses @@ -376,12 +376,12 @@ system.cpu.icache.demand_miss_latency::cpu.inst 112371000 system.cpu.icache.demand_miss_latency::total 112371000 # number of demand (read+write) miss cycles system.cpu.icache.overall_miss_latency::cpu.inst 112371000 # number of overall miss cycles system.cpu.icache.overall_miss_latency::total 112371000 # number of overall miss cycles -system.cpu.icache.ReadReq_accesses::cpu.inst 189860052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.ReadReq_accesses::total 189860052 # number of ReadReq accesses(hits+misses) -system.cpu.icache.demand_accesses::cpu.inst 189860052 # number of demand (read+write) accesses -system.cpu.icache.demand_accesses::total 189860052 # number of demand (read+write) accesses -system.cpu.icache.overall_accesses::cpu.inst 189860052 # number of overall (read+write) accesses -system.cpu.icache.overall_accesses::total 189860052 # number of overall (read+write) accesses +system.cpu.icache.ReadReq_accesses::cpu.inst 189860053 # number of ReadReq accesses(hits+misses) +system.cpu.icache.ReadReq_accesses::total 189860053 # number of ReadReq accesses(hits+misses) +system.cpu.icache.demand_accesses::cpu.inst 189860053 # number of demand (read+write) accesses +system.cpu.icache.demand_accesses::total 189860053 # number of demand (read+write) accesses +system.cpu.icache.overall_accesses::cpu.inst 189860053 # number of overall (read+write) accesses +system.cpu.icache.overall_accesses::total 189860053 # number of overall (read+write) accesses system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000016 # miss rate for ReadReq accesses system.cpu.icache.ReadReq_miss_rate::total 0.000016 # miss rate for ReadReq accesses system.cpu.icache.demand_miss_rate::cpu.inst 0.000016 # miss rate for demand accesses @@ -428,14 +428,14 @@ system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35330.875123 system.cpu.icache.overall_avg_mshr_miss_latency::total 35330.875123 # average overall mshr miss latency system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate system.cpu.l2cache.tags.replacements 0 # number of replacements -system.cpu.l2cache.tags.tagsinuse 1675.663349 # Cycle average of tags in use +system.cpu.l2cache.tags.tagsinuse 1675.663342 # Cycle average of tags in use system.cpu.l2cache.tags.total_refs 1380 # Total number of references to valid blocks. system.cpu.l2cache.tags.sampled_refs 2369 # Sample count of references to valid blocks. system.cpu.l2cache.tags.avg_refs 0.582524 # Average number of references to valid blocks. system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. system.cpu.l2cache.tags.occ_blocks::writebacks 3.037779 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036753 # Average occupied blocks per requestor -system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588818 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.inst 1169.036747 # Average occupied blocks per requestor +system.cpu.l2cache.tags.occ_blocks::cpu.data 503.588816 # Average occupied blocks per requestor system.cpu.l2cache.tags.occ_percent::writebacks 0.000093 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.inst 0.035676 # Average percentage of cache occupancy system.cpu.l2cache.tags.occ_percent::cpu.data 0.015368 # Average percentage of cache occupancy |