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-rw-r--r--tests/simple-timing.py21
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/simple-timing.py b/tests/simple-timing.py
new file mode 100644
index 000000000..128cace3c
--- /dev/null
+++ b/tests/simple-timing.py
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+import m5
+from m5.objects import *
+m5.AddToPath('../configs/common')
+from SEConfig import *
+
+class MyCache(BaseCache):
+ assoc = 2
+ block_size = 64
+ latency = 1
+ mshrs = 10
+ tgts_per_mshr = 5
+
+cpu = TimingSimpleCPU()
+cpu.icache = MyCache(size = '128kB')
+cpu.dcache = MyCache(size = '256kB')
+cpu.l2cache = MyCache(size = '2MB')
+
+cpu.icache_port = cpu.icache.cpu_side
+cpu.dcache_port = cpu.dcache.cpu_side
+
+root = makeSESystem(cpu)