summaryrefslogtreecommitdiff
path: root/tests/simple-timing.py
diff options
context:
space:
mode:
Diffstat (limited to 'tests/simple-timing.py')
-rw-r--r--tests/simple-timing.py14
1 files changed, 8 insertions, 6 deletions
diff --git a/tests/simple-timing.py b/tests/simple-timing.py
index 128cace3c..b3d11e069 100644
--- a/tests/simple-timing.py
+++ b/tests/simple-timing.py
@@ -11,11 +11,13 @@ class MyCache(BaseCache):
tgts_per_mshr = 5
cpu = TimingSimpleCPU()
-cpu.icache = MyCache(size = '128kB')
-cpu.dcache = MyCache(size = '256kB')
-cpu.l2cache = MyCache(size = '2MB')
+cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'),
+ MyCache(size = '2MB'))
-cpu.icache_port = cpu.icache.cpu_side
-cpu.dcache_port = cpu.dcache.cpu_side
+system = System(cpu = cpu,
+ physmem = PhysicalMemory(),
+ membus = Bus())
+system.physmem.port = system.membus.port
+cpu.connectMemPorts(system.membus)
-root = makeSESystem(cpu)
+root = Root(system = system)