diff options
Diffstat (limited to 'tests/test-progs/asmtest/src/riscv/isa/rv64mi')
10 files changed, 630 insertions, 0 deletions
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/Makefrag b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/Makefrag new file mode 100644 index 000000000..b0ddefee6 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/Makefrag @@ -0,0 +1,19 @@ +#======================================================================= +# Makefrag for rv64mi tests +#----------------------------------------------------------------------- + +rv64mi_sc_tests = \ + access \ + breakpoint \ + csr \ + mcsr \ + illegal \ + ma_fetch \ + ma_addr \ + scall \ + sbreak \ + +rv32ud_p_tests = $(addprefix rv32ud-p-, $(rv32ud_sc_tests)) +#rv32ud_ps_tests = $(addprefix rv32ud-ps-, $(rv32ud_sc_tests)) + +spike_tests += $(rv64mi_p_tests) diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/access.S b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/access.S new file mode 100644 index 000000000..202a36412 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/access.S @@ -0,0 +1,70 @@ +# See LICENSE for license details. + +#***************************************************************************** +# access.S +#----------------------------------------------------------------------------- +# +# Test access-exception behavior. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + .align 2 + + # Flipping just the MSB should result in an illegal address for RV64. + la t2, fail + li t0, 1 << (__riscv_xlen - 1) + xor t0, t0, t2 + + # jalr to an illegal address should commit (hence should write rd). + # after the pc is set to rs1, an access exception should be raised. + li TESTNUM, 2 + li t1, CAUSE_FETCH_ACCESS + la t3, 1f + li t2, 0 + jalr t2, t0 +1: + + # A load to an illegal address should not commit. + li TESTNUM, 3 + li t1, CAUSE_LOAD_ACCESS + la t3, 1f + mv t2, t3 + lb t2, (t0) + j fail +1: + + j pass + + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + li a0, 2 + beq TESTNUM, a0, 2f + li a0, 3 + beq TESTNUM, a0, 2f + j fail + +2: + bne t2, t3, fail + + csrr t2, mcause + bne t2, t1, fail + + csrw mepc, t3 + mret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/breakpoint.S b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/breakpoint.S new file mode 100644 index 000000000..647430b8d --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/breakpoint.S @@ -0,0 +1,144 @@ +# See LICENSE for license details. + +#***************************************************************************** +# breakpoint.S +#----------------------------------------------------------------------------- +# +# Test breakpoints, if they are implemented. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # Set up breakpoint to trap on M-mode fetches. + li TESTNUM, 2 + + # Skip tselect if hard-wired. + csrw tselect, x0 + csrr a1, tselect + bne x0, a1, pass + + # Make sure there's a breakpoint there. + csrr a0, tdata1 + srli a0, a0, __riscv_xlen - 4 + li a1, 2 + bne a0, a1, pass + + la a2, 1f + csrw tdata2, a2 + li a0, MCONTROL_M | MCONTROL_EXECUTE + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + andi a1, a1, 0x7ff + bne a0, a1, 2f + .align 2 +1: + # Trap handler should skip this instruction. + beqz x0, fail + + # Make sure reads don't trap. + li TESTNUM, 3 + lw a0, (a2) + +2: + # Set up breakpoint to trap on M-mode reads. + li TESTNUM, 4 + li a0, MCONTROL_M | MCONTROL_LOAD + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + andi a1, a1, 0x7ff + bne a0, a1, 2f + la a2, data1 + csrw tdata2, a2 + + # Trap handler should skip this instruction. + lw a2, (a2) + beqz a2, fail + + # Make sure writes don't trap. + li TESTNUM, 5 + sw x0, (a2) + +2: + # Set up breakpoint to trap on M-mode stores. + li TESTNUM, 6 + li a0, MCONTROL_M | MCONTROL_STORE + csrw tdata1, a0 + # Skip if breakpoint type is unsupported. + csrr a1, tdata1 + andi a1, a1, 0x7ff + bne a0, a1, 2f + + # Trap handler should skip this instruction. + sw a2, (a2) + + # Make sure store didn't succeed. + li TESTNUM, 7 + lw a2, (a2) + bnez a2, fail + + # Try to set up a second breakpoint. + li a0, 1 + csrw tselect, a0 + csrr a1, tselect + bne a0, a1, pass + + # Make sure there's a breakpoint there. + csrr a0, tdata1 + srli a0, a0, __riscv_xlen - 4 + li a1, 2 + bne a0, a1, pass + + li a0, MCONTROL_M | MCONTROL_LOAD + csrw tdata1, a0 + la a3, data2 + csrw tdata2, a3 + + # Make sure the second breakpoint triggers. + li TESTNUM, 8 + lw a3, (a3) + beqz a3, fail + + # Make sure the first breakpoint still triggers. + li TESTNUM, 10 + la a2, data1 + sw a2, (a2) + li TESTNUM, 11 + lw a2, (a2) + bnez a2, fail + +2: + TEST_PASSFAIL + + .align 2 + .global mtvec_handler +mtvec_handler: + # Only even-numbered tests should trap. + andi t0, TESTNUM, 1 + bnez t0, fail + + li t0, CAUSE_BREAKPOINT + csrr t1, mcause + bne t0, t1, fail + + csrr t0, mepc + addi t0, t0, 4 + csrw mepc, t0 + mret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +data1: .word 0 +data2: .word 0 + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/csr.S b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/csr.S new file mode 100644 index 000000000..77e7619ec --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/csr.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/csr.S" diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S new file mode 100644 index 000000000..d825c4492 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/illegal.S @@ -0,0 +1,194 @@ +# See LICENSE for license details. + +#***************************************************************************** +# illegal.S +#----------------------------------------------------------------------------- +# +# Test illegal instruction trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + .align 2 + .option norvc + + li TESTNUM, 2 +bad2: + .word 0 + j fail + + # Skip the rest of the test if S-mode is not present. + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 + csrr t2, mstatus + and t2, t2, t0 + bne t1, t2, pass + + # Test vectored interrupts if they are supported. +test_vectored_interrupts: + csrwi mip, MIP_SSIP + csrwi mie, MIP_SSIP + la t0, mtvec_handler + 1 + csrrw s0, mtvec, t0 + csrr t0, mtvec + andi t0, t0, 1 + beqz t0, msip + csrsi mstatus, MSTATUS_MIE +1: + j 1b +msip: + csrw mtvec, s0 + + # Delegate supervisor software interrupts so WFI won't stall. + csrwi mideleg, MIP_SSIP + # Enter supervisor mode. + la t0, 1f + csrw mepc, t0 + li t0, MSTATUS_MPP + csrc mstatus, t0 + li t1, (MSTATUS_MPP & -MSTATUS_MPP) * PRV_S + csrs mstatus, t1 + mret + +1: + # Make sure WFI doesn't trap when TW=0. + wfi +bad3: + .word 0 + j fail + +bad4: + # Make sure WFI does trap when TW=1. + wfi + j fail + + # Make sure SFENCE.VMA and sptbr don't trap when TVM=0. + sfence.vma + csrr t0, sptbr +bad5: + .word 0 + j fail + +bad6: + # Make sure SFENCE.VMA and sptbr do trap when TVM=1. + sfence.vma + j fail +bad7: + csrr t0, sptbr + j fail + + # Make sure SRET doesn't trap when TSR=0. + la t0, bad8 + csrw sepc, t0 + li t0, SSTATUS_SPP + csrs sstatus, t0 + li t0, SSTATUS_SPIE + csrc sstatus, t0 + sret +bad8: + .word 0 + j fail + + # Make sure SRET does trap when TSR=1. + la t0, 1f + csrw sepc, t0 +bad9: + sret +1: + j fail + + TEST_PASSFAIL + + .align 8 + .global mtvec_handler +mtvec_handler: + j synchronous_exception + j msip + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + j fail + +synchronous_exception: + li t1, CAUSE_ILLEGAL_INSTRUCTION + csrr t0, mcause + bne t0, t1, fail + csrr t0, mepc + + # Make sure mtval contains either 0 or the instruction word. + csrr t2, mbadaddr + beqz t2, 1f + lhu t3, 0(t0) + lhu t4, 2(t0) + slli t4, t4, 16 + or t3, t3, t4 + bne t2, t3, fail +1: + + la t1, bad2 + beq t0, t1, 2f + la t1, bad3 + beq t0, t1, 3f + la t1, bad4 + beq t0, t1, 4f + la t1, bad5 + beq t0, t1, 5f + la t1, bad6 + beq t0, t1, 6f + la t1, bad7 + beq t0, t1, 7f + la t1, bad8 + beq t0, t1, 8f + la t1, bad9 + beq t0, t1, 9f + j fail +2: +4: +6: +7: + addi t0, t0, 8 + csrw mepc, t0 + mret + +3: + li t1, MSTATUS_TW + csrs mstatus, t1 + j 2b + +5: + li t1, MSTATUS_TVM + csrs mstatus, t1 + j 2b + +8: + li t1, MSTATUS_TSR + csrs mstatus, t1 + j 2b + +9: + j 2b + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ma_addr.S b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ma_addr.S new file mode 100644 index 000000000..721ac6afc --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ma_addr.S @@ -0,0 +1,126 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ma_addr.S +#----------------------------------------------------------------------------- +# +# Test misaligned ld/st trap. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + .align 2 + .option norvc + + la s0, data + + # indicate it's a load test + li s1, CAUSE_MISALIGNED_LOAD + +#define SEXT(x, n) ((-((x) >> ((n)-1)) << (n)) | ((x) & ((1 << (n))-1))) + +/* Check that a misaligned load either writes the correct value, or + takes an exception and performs no writeback. */ +#define MISALIGNED_LOAD_TEST(testnum, insn, base, offset, res) \ + li TESTNUM, testnum; \ + la t2, 1f; \ + addi t1, base, offset; \ + insn t1, offset(base); \ + li t2, res; \ + bne t1, t2, fail; \ +1: + + MISALIGNED_LOAD_TEST(2, lh, s0, 1, SEXT(0xbbcc, 16)) + MISALIGNED_LOAD_TEST(3, lhu, s0, 1, 0xbbcc) + MISALIGNED_LOAD_TEST(4, lw, s0, 1, SEXT(0x99aabbcc, 32)) + MISALIGNED_LOAD_TEST(5, lw, s0, 2, SEXT(0x8899aabb, 32)) + MISALIGNED_LOAD_TEST(6, lw, s0, 3, SEXT(0x778899aa, 32)) + +#if __riscv_xlen == 64 + MISALIGNED_LOAD_TEST(7, lwu, s0, 1, 0x99aabbcc) + MISALIGNED_LOAD_TEST(8, lwu, s0, 2, 0x8899aabb) + MISALIGNED_LOAD_TEST(9, lwu, s0, 3, 0x778899aa) + + MISALIGNED_LOAD_TEST(10, ld, s0, 1, 0x5566778899aabbcc) + MISALIGNED_LOAD_TEST(11, ld, s0, 2, 0x445566778899aabb) + MISALIGNED_LOAD_TEST(12, ld, s0, 3, 0x33445566778899aa) + MISALIGNED_LOAD_TEST(13, ld, s0, 4, 0x2233445566778899) + MISALIGNED_LOAD_TEST(14, ld, s0, 5, 0x1122334455667788) + MISALIGNED_LOAD_TEST(15, ld, s0, 6, 0xee11223344556677) + MISALIGNED_LOAD_TEST(16, ld, s0, 7, 0xffee112233445566) +#endif + + # indicate it's a store test + li s1, CAUSE_MISALIGNED_STORE + +/* Check that a misaligned store has some effect and takes no exception, + or takes no effect and generates an exception. This is not very + thorough. */ +#define MISALIGNED_STORE_TEST(testnum, insn, base, offset, size) \ + li TESTNUM, testnum; \ + la t2, 1f; \ + addi t1, base, offset; \ + insn x0, offset(base); \ + lb t1, (offset - 1)(base); \ + beqz t1, fail; \ + lb t1, (offset + size)(base); \ + beqz t1, fail; \ + lb t1, (offset + 0)(base); \ + bnez t1, fail; \ + lb t1, (offset + size - 1)(base); \ + bnez t1, fail; \ +1: + + MISALIGNED_STORE_TEST(22, sh, s0, 1, 2) + MISALIGNED_STORE_TEST(23, sw, s0, 5, 4) + MISALIGNED_STORE_TEST(24, sw, s0, 10, 4) + MISALIGNED_STORE_TEST(25, sw, s0, 15, 4) + +#if __riscv_xlen == 64 + MISALIGNED_STORE_TEST(26, sd, s0, 25, 8) + MISALIGNED_STORE_TEST(27, sd, s0, 34, 8) + MISALIGNED_STORE_TEST(28, sd, s0, 43, 8) + MISALIGNED_STORE_TEST(29, sd, s0, 52, 8) + MISALIGNED_STORE_TEST(30, sd, s0, 61, 8) + MISALIGNED_STORE_TEST(31, sd, s0, 70, 8) + MISALIGNED_STORE_TEST(32, sd, s0, 79, 8) +#endif + + TEST_PASSFAIL + + .align 3 + .global mtvec_handler +mtvec_handler: + csrr t0, mcause + bne t0, s1, fail + + csrr t0, mbadaddr + bne t0, t1, fail + + lb t0, (t0) + beqz t0, fail + + csrw mepc, t2 + mret + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +data: + .align 3 +.word 0xaabbccdd +.word 0x66778899 +.word 0x22334455 +.word 0xeeffee11 +.fill 0xff, 1, 80 + + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ma_fetch.S b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ma_fetch.S new file mode 100644 index 000000000..cfcb90c96 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ma_fetch.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/ma_fetch.S" diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/mcsr.S b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/mcsr.S new file mode 100644 index 000000000..e0256e7ef --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/mcsr.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# mcsr.S +#----------------------------------------------------------------------------- +# +# Test various M-mode CSRs. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64M +RVTEST_CODE_BEGIN + + # Check that mcpuid reports the correct XLEN +#if __riscv_xlen == 64 + TEST_CASE(2, a0, 0x2, csrr a0, misa; srl a0, a0, 62) +#else + TEST_CASE(2, a0, 0x1, csrr a0, misa; srl a0, a0, 30) +#endif + + # Check that mhartid reports 0 + TEST_CASE(3, a0, 0x0, csrr a0, mhartid) + + # Check that reading the following CSRs doesn't cause an exception + csrr a0, mimpid + csrr a0, marchid + csrr a0, mvendorid + + # Check that writing hte following CSRs doesn't cause an exception + li t0, 0 + csrs mtvec, t0 + csrs mepc, t0 + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/sbreak.S b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/sbreak.S new file mode 100644 index 000000000..f36a9f83d --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/sbreak.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/sbreak.S" diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64mi/scall.S b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/scall.S new file mode 100644 index 000000000..22e9eb55d --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64mi/scall.S @@ -0,0 +1,8 @@ +# See LICENSE for license details. + +#include "riscv_test.h" +#undef RVTEST_RV64S +#define RVTEST_RV64S RVTEST_RV64M +#define __MACHINE_MODE + +#include "../rv64si/scall.S" |