diff options
Diffstat (limited to 'tests/test-progs/asmtest/src/riscv/isa/rv64ud')
13 files changed, 803 insertions, 0 deletions
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/Makefrag b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/Makefrag new file mode 100644 index 000000000..782848110 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv64ud tests +#----------------------------------------------------------------------- + +rv64ud_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst move structural recoding \ + +rv64ud_p_tests = $(addprefix rv64ud-p-, $(rv64ud_sc_tests)) +rv64ud_v_tests = $(addprefix rv64ud-v-, $(rv64ud_sc_tests)) +rv64ud_ps_tests = $(addprefix rv64ud-ps-, $(rv64ud_sc_tests)) + +spike_tests += $(rv64ud_p_tests) $(rv64ud_v_tests) diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fadd.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fadd.S new file mode 100644 index 000000000..51ca82db7 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fadd.S @@ -0,0 +1,50 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fadd.S +#----------------------------------------------------------------------------- +# +# Test f{add|sub|mul}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_OP2_D + #define TEST_FP_OP2_D TEST_FP_OP2_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fadd.d, 0, 3.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 3, fadd.d, 1, -1234, -1235.1, 1.1 ); + TEST_FP_OP2_D( 4, fadd.d, 1, 3.14159266, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_D( 5, fsub.d, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 6, fsub.d, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_D( 7, fsub.d, 1, 3.1415926400000001, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_D( 8, fmul.d, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_D( 9, fmul.d, 1, 1358.61, -1235.1, -1.1 ); + TEST_FP_OP2_D(10, fmul.d, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); + + # Is the canonical NaN generated for Inf - Inf? + TEST_FP_OP2_D(11, fsub.d, 0x10, qNaN, Inf, Inf); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fclass.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fclass.S new file mode 100644 index 000000000..04a894735 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fclass.S @@ -0,0 +1,46 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fclass.S +#----------------------------------------------------------------------------- +# +# Test fclass.d instruction. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FCLASS_D + #define TEST_FCLASS_D TEST_FCLASS_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FCLASS_D( 2, 1 << 0, 0xfff0000000000000 ) + TEST_FCLASS_D( 3, 1 << 1, 0xbff0000000000000 ) + TEST_FCLASS_D( 4, 1 << 2, 0x800fffffffffffff ) + TEST_FCLASS_D( 5, 1 << 3, 0x8000000000000000 ) + TEST_FCLASS_D( 6, 1 << 4, 0x0000000000000000 ) + TEST_FCLASS_D( 7, 1 << 5, 0x000fffffffffffff ) + TEST_FCLASS_D( 8, 1 << 6, 0x3ff0000000000000 ) + TEST_FCLASS_D( 9, 1 << 7, 0x7ff0000000000000 ) + TEST_FCLASS_D(10, 1 << 8, 0x7ff0000000000001 ) + TEST_FCLASS_D(11, 1 << 9, 0x7ff8000000000000 ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fcmp.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fcmp.S new file mode 100644 index 000000000..7727a2871 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fcmp.S @@ -0,0 +1,56 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcmp.S +#----------------------------------------------------------------------------- +# +# Test f{eq|lt|le}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_CMP_OP_D + #define TEST_FP_CMP_OP_D TEST_FP_CMP_OP_D32 +#endif + + TEST_FP_CMP_OP_D( 2, feq.d, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_D( 3, fle.d, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_D( 4, flt.d, 0x00, 0, -1.36, -1.36) + + TEST_FP_CMP_OP_D( 5, feq.d, 0x00, 0, -1.37, -1.36) + TEST_FP_CMP_OP_D( 6, fle.d, 0x00, 1, -1.37, -1.36) + TEST_FP_CMP_OP_D( 7, flt.d, 0x00, 1, -1.37, -1.36) + + # Only sNaN should signal invalid for feq. + TEST_FP_CMP_OP_D( 8, feq.d, 0x00, 0, NaN, 0) + TEST_FP_CMP_OP_D( 9, feq.d, 0x00, 0, NaN, NaN) + TEST_FP_CMP_OP_D(10, feq.d, 0x10, 0, sNaN, 0) + + # qNaN should signal invalid for fle/flt. + TEST_FP_CMP_OP_D(11, flt.d, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_D(12, flt.d, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_D(13, flt.d, 0x10, 0, sNaN, 0) + TEST_FP_CMP_OP_D(14, fle.d, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_D(15, fle.d, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_D(16, fle.d, 0x10, 0, sNaN, 0) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fcvt.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fcvt.S new file mode 100644 index 000000000..98916b17d --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fcvt.S @@ -0,0 +1,79 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt.S +#----------------------------------------------------------------------------- +# +# Test fcvt.d.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_INT_FP_OP_D + #define TEST_INT_FP_OP_D TEST_INT_FP_OP_D32 + + #undef TEST_FCVT_S_D + #define TEST_FCVT_S_D TEST_FCVT_S_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_INT_FP_OP_D(2, fcvt.d.w, 2.0, 2); + TEST_INT_FP_OP_D(3, fcvt.d.w, -2.0, -2); + + TEST_INT_FP_OP_D(4, fcvt.d.wu, 2.0, 2); + TEST_INT_FP_OP_D(5, fcvt.d.wu, 4294967294, -2); + +#if __riscv_xlen >= 64 + TEST_INT_FP_OP_D(6, fcvt.d.l, 2.0, 2); + TEST_INT_FP_OP_D(7, fcvt.d.l, -2.0, -2); + + TEST_INT_FP_OP_D(8, fcvt.d.lu, 2.0, 2); + TEST_INT_FP_OP_D(9, fcvt.d.lu, 1.8446744073709552e19, -2); +#endif + + TEST_FCVT_S_D(10, -1.5, -1.5) + TEST_FCVT_D_S(11, -1.5, -1.5) + +#if __riscv_xlen >= 64 + TEST_CASE(12, a0, 0x7ff8000000000000, + la a1, test_data_22; + ld a2, 0(a1); + fmv.d.x f2, a2; + fcvt.s.d f2, f2; + fcvt.d.s f2, f2; + fmv.x.d a0, f2; + ) +#else + TEST_CASE_D32(12, a0, a1, 0x7ff8000000000000, + la a1, test_data_22; + fld f2, 0(a1); + fcvt.s.d f2, f2; + fcvt.d.s f2, f2; + fsd f2, 0(a1); + lw a0, 0(a1); + lw a1, 4(a1) + ) +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +test_data_22: + .dword 0x7ffcffffffff8004 + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fcvt_w.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fcvt_w.S new file mode 100644 index 000000000..56cc29d79 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fcvt_w.S @@ -0,0 +1,114 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt_w.S +#----------------------------------------------------------------------------- +# +# Test fcvt{wu|w|lu|l}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_INT_OP_D( 2, fcvt.w.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D( 3, fcvt.w.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D( 4, fcvt.w.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D( 5, fcvt.w.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D( 6, fcvt.w.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D( 7, fcvt.w.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D( 8, fcvt.w.d, 0x10, -1<<31, -3e9, rtz); + TEST_FP_INT_OP_D( 9, fcvt.w.d, 0x10, (1<<31)-1, 3e9, rtz); + + TEST_FP_INT_OP_D(12, fcvt.wu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(13, fcvt.wu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(14, fcvt.wu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(15, fcvt.wu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(16, fcvt.wu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(17, fcvt.wu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(18, fcvt.wu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(19, fcvt.wu.d, 0x00, 0xffffffffb2d05e00, 3e9, rtz); + +#if __riscv_xlen >= 64 + TEST_FP_INT_OP_D(22, fcvt.l.d, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_D(23, fcvt.l.d, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_D(24, fcvt.l.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(25, fcvt.l.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(26, fcvt.l.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(27, fcvt.l.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(28, fcvt.l.d, 0x00,-3000000000, -3e9, rtz); + TEST_FP_INT_OP_D(29, fcvt.l.d, 0x00, 3000000000, 3e9, rtz); + TEST_FP_INT_OP_D(20, fcvt.l.d, 0x10, -1<<63,-3e19, rtz); + TEST_FP_INT_OP_D(21, fcvt.l.d, 0x10, (1<<63)-1, 3e19, rtz); + + TEST_FP_INT_OP_D(32, fcvt.lu.d, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_D(33, fcvt.lu.d, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_D(34, fcvt.lu.d, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_D(35, fcvt.lu.d, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_D(36, fcvt.lu.d, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_D(37, fcvt.lu.d, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_D(38, fcvt.lu.d, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_D(39, fcvt.lu.d, 0x00, 3000000000, 3e9, rtz); +#endif + + # test negative NaN, negative infinity conversion + TEST_CASE(42, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(43, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.l.d x1, f1) +#endif + TEST_CASE(44, x1, 0xffffffff80000000, la x1, tdat_d; fld f1, 16(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(45, x1, 0x8000000000000000, la x1, tdat_d; fld f1, 16(x1); fcvt.l.d x1, f1) +#endif + + # test positive NaN, positive infinity conversion + TEST_CASE(52, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(53, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.l.d x1, f1) +#endif + TEST_CASE(54, x1, 0x000000007fffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.w.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(55, x1, 0x7fffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.l.d x1, f1) +#endif + + # test NaN, infinity conversions to unsigned integer + TEST_CASE(62, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.wu.d x1, f1) + TEST_CASE(63, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.wu.d x1, f1) + TEST_CASE(64, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.wu.d x1, f1) + TEST_CASE(65, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.wu.d x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE(66, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 0(x1); fcvt.lu.d x1, f1) + TEST_CASE(67, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 8(x1); fcvt.lu.d x1, f1) + TEST_CASE(68, x1, 0, la x1, tdat_d; fld f1, 16(x1); fcvt.lu.d x1, f1) + TEST_CASE(69, x1, 0xffffffffffffffff, la x1, tdat_d; fld f1, 24(x1); fcvt.lu.d x1, f1) +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +# -NaN, NaN, -inf, +inf +tdat: +.word 0xffffffff +.word 0x7fffffff +.word 0xff800000 +.word 0x7f800000 + +tdat_d: +.dword 0xffffffffffffffff +.dword 0x7fffffffffffffff +.dword 0xfff0000000000000 +.dword 0x7ff0000000000000 + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fdiv.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fdiv.S new file mode 100644 index 000000000..f985fa1db --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fdiv.S @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fdiv.S +#----------------------------------------------------------------------------- +# +# Test f{div|sqrt}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the functions with the 32-bit variants defined in test_macros.h + #undef TEST_FP_OP2_D + #define TEST_FP_OP2_D TEST_FP_OP2_D32 + + #undef TEST_FP_OP1_D + #define TEST_FP_OP1_D TEST_FP_OP1_D32 + + #undef TEST_FP_OP1_D_DWORD_RESULT + #define TEST_FP_OP1_D_DWORD_RESULT TEST_FP_OP1_D32_DWORD_RESULT +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fdiv.d, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_D( 3, fdiv.d, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_D( 4, fdiv.d, 0, 3.14159265, 3.14159265, 1.0 ); + + TEST_FP_OP1_D( 5, fsqrt.d, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_D( 6, fsqrt.d, 0, 100, 10000 ); + + TEST_FP_OP1_D_DWORD_RESULT(16, fsqrt.d, 0x10, 0x7FF8000000000000, -1.0 ); + + TEST_FP_OP1_D( 7, fsqrt.d, 1, 13.076696830622021, 171.0); + + TEST_FP_OP1_D( 8, fsqrt.d, 1,0.00040099251863345283320230749702, 1.60795e-7); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fmadd.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fmadd.S new file mode 100644 index 000000000..1e3ba669e --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fmadd.S @@ -0,0 +1,51 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd.S +#----------------------------------------------------------------------------- +# +# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_OP3_D + #define TEST_FP_OP3_D TEST_FP_OP3_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP3_D( 2, fmadd.d, 0, 3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 3, fmadd.d, 1, 1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 4, fmadd.d, 0, -12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 5, fnmadd.d, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 6, fnmadd.d, 1, -1236.1999999999999, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D( 7, fnmadd.d, 0, 12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D( 8, fmsub.d, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D( 9, fmsub.d, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(10, fmsub.d, 0, -8.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_D(11, fnmsub.d, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_D(12, fnmsub.d, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_D(13, fnmsub.d, 0, 8.0, 2.0, -5.0, -2.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fmin.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fmin.S new file mode 100644 index 000000000..10ff8e6a3 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/fmin.S @@ -0,0 +1,60 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin.S +#----------------------------------------------------------------------------- +# +# Test f{min|max}.d instructinos. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#if __riscv_xlen == 32 + # Replace the function with the 32-bit variant defined in test_macros.h + #undef TEST_FP_OP2_D + #define TEST_FP_OP2_D TEST_FP_OP2_D32 +#endif + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_D( 2, fmin.d, 0, 1.0, 2.5, 1.0 ); + TEST_FP_OP2_D( 3, fmin.d, 0, -1235.1, -1235.1, 1.1 ); + TEST_FP_OP2_D( 4, fmin.d, 0, -1235.1, 1.1, -1235.1 ); + TEST_FP_OP2_D( 5, fmin.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D( 6, fmin.d, 0, 0.00000001, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D( 7, fmin.d, 0, -2.0, -1.0, -2.0 ); + + TEST_FP_OP2_D(12, fmax.d, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_D(13, fmax.d, 0, 1.1, -1235.1, 1.1 ); + TEST_FP_OP2_D(14, fmax.d, 0, 1.1, 1.1, -1235.1 ); + TEST_FP_OP2_D(15, fmax.d, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_D(16, fmax.d, 0, 3.14159265, 3.14159265, 0.00000001 ); + TEST_FP_OP2_D(17, fmax.d, 0, -1.0, -1.0, -2.0 ); + + # FMIN(sNaN, x) = x + TEST_FP_OP2_D(20, fmax.d, 0x10, 1.0, sNaN, 1.0); + # FMIN(qNaN, qNaN) = canonical NaN + TEST_FP_OP2_D(21, fmax.d, 0x00, qNaN, NaN, NaN); + + # -0.0 < +0.0 + TEST_FP_OP2_D(30, fmin.d, 0, -0.0, -0.0, 0.0 ); + TEST_FP_OP2_D(31, fmin.d, 0, -0.0, 0.0, -0.0 ); + TEST_FP_OP2_D(32, fmax.d, 0, 0.0, -0.0, 0.0 ); + TEST_FP_OP2_D(33, fmax.d, 0, 0.0, 0.0, -0.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/ldst.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/ldst.S new file mode 100644 index 000000000..962934130 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/ldst.S @@ -0,0 +1,42 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + la s0, tdat + TEST_CASE(2, a0, 0x40000000bf800000, fld f2, 0(s0); fsd f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(3, a0, 0x40000000bf800000, fld f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(4, a0, 0x40000000bf800000, flw f2, 0(s0); fsw f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(5, a0, 0xc080000040400000, fld f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) + TEST_CASE(6, a0, 0xffffffff40400000, flw f2, 8(s0); fsd f2, 16(s0); ld a0, 16(s0)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/move.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/move.S new file mode 100644 index 000000000..8911d9522 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/move.S @@ -0,0 +1,113 @@ +# See LICENSE for license details. + +#***************************************************************************** +# move.S +#----------------------------------------------------------------------------- +# +# This test verifies that fmv.d.x, fmv.x.d, and fsgnj[x|n].d work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +#TODO: make 32-bit compatible version +#define TEST_FSGNJD(n, insn, new_sign, rs1_sign, rs2_sign) \ + TEST_CASE(n, a0, 0x123456789abcdef0 | (-(new_sign) << 63), \ + li a1, ((rs1_sign) << 63) | 0x123456789abcdef0; \ + li a2, -(rs2_sign); \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + insn f0, f1, f2; \ + fmv.x.d a0, f0) + + TEST_FSGNJD(10, fsgnj.d, 0, 0, 0) + TEST_FSGNJD(11, fsgnj.d, 1, 0, 1) + TEST_FSGNJD(12, fsgnj.d, 0, 1, 0) + TEST_FSGNJD(13, fsgnj.d, 1, 1, 1) + + TEST_FSGNJD(20, fsgnjn.d, 1, 0, 0) + TEST_FSGNJD(21, fsgnjn.d, 0, 0, 1) + TEST_FSGNJD(22, fsgnjn.d, 1, 1, 0) + TEST_FSGNJD(23, fsgnjn.d, 0, 1, 1) + + TEST_FSGNJD(30, fsgnjx.d, 0, 0, 0) + TEST_FSGNJD(31, fsgnjx.d, 1, 0, 1) + TEST_FSGNJD(32, fsgnjx.d, 1, 1, 0) + TEST_FSGNJD(33, fsgnjx.d, 0, 1, 1) + +// Test fsgnj.s in conjunction with double-precision moves +#define TEST_FSGNJS(n, rd, rs1, rs2) \ + TEST_CASE(n, a0, (rd) | (-((rd) >> 31) << 32), \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.s f0, f1, f2; \ + fmv.x.s a0, f0); \ + TEST_CASE(1##n, a0, (rd) | 0xffffffff00000000, \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.s f0, f1, f2; \ + fmv.x.d a0, f0) + + TEST_FSGNJS(40, 0x7fc00000, 0x7ffffffe12345678, 0) + TEST_FSGNJS(41, 0x7fc00000, 0xfffffffe12345678, 0) + TEST_FSGNJS(42, 0x7fc00000, 0x7fffffff12345678, 0) + TEST_FSGNJS(43, 0x12345678, 0xffffffff12345678, 0) + + TEST_FSGNJS(50, 0x7fc00000, 0x7ffffffe12345678, 0x80000000) + TEST_FSGNJS(51, 0x7fc00000, 0xfffffffe12345678, 0x80000000) + TEST_FSGNJS(52, 0x7fc00000, 0x7fffffff12345678, 0x80000000) + TEST_FSGNJS(53, 0x12345678, 0xffffffff12345678, 0x80000000) + + TEST_FSGNJS(60, 0xffc00000, 0x7ffffffe12345678, 0xffffffff80000000) + TEST_FSGNJS(61, 0xffc00000, 0xfffffffe12345678, 0xffffffff80000000) + TEST_FSGNJS(62, 0x92345678, 0xffffffff12345678, 0xffffffff80000000) + TEST_FSGNJS(63, 0x12345678, 0xffffffff12345678, 0x7fffffff80000000) + +// Test fsgnj.d in conjunction with single-precision moves +#define TEST_FSGNJD_SP(n, isnan, rd, rs1, rs2) \ + TEST_CASE(n, a0, ((rd) & 0xffffffff) | (-(((rd) >> 31) & 1) << 32), \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.d f0, f1, f2; \ + feq.s a0, f0, f0; \ + addi a0, a0, -!(isnan); \ + bnez a0, 1f; \ + fmv.x.s a0, f0; \ + 1:); \ + TEST_CASE(1##n, a0, rd, \ + li a1, rs1; \ + li a2, rs2; \ + fmv.d.x f1, a1; \ + fmv.d.x f2, a2; \ + fsgnj.d f0, f1, f2; \ + fmv.x.d a0, f0; \ + 1:) + + TEST_FSGNJD_SP(70, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff11111111) + TEST_FSGNJD_SP(71, 1, 0x7fffffff11111111, 0xffffffff11111111, 0x7fffffff11111111) + TEST_FSGNJD_SP(72, 0, 0xffffffff11111111, 0xffffffff11111111, 0xffffffff91111111) + TEST_FSGNJD_SP(73, 0, 0xffffffff11111111, 0xffffffff11111111, 0x8000000000000000) + TEST_FSGNJD_SP(74, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff11111111) + TEST_FSGNJD_SP(75, 1, 0x7fffffff11111111, 0x7fffffff11111111, 0x7fffffff11111111) + TEST_FSGNJD_SP(76, 0, 0xffffffff11111111, 0x7fffffff11111111, 0xffffffff91111111) + TEST_FSGNJD_SP(77, 0, 0xffffffff11111111, 0x7fffffff11111111, 0x8000000000000000) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/recoding.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/recoding.S new file mode 100644 index 000000000..69ad665a8 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/recoding.S @@ -0,0 +1,67 @@ +# See LICENSE for license details. + +#***************************************************************************** +# recoding.S +#----------------------------------------------------------------------------- +# +# Test corner cases of John Hauser's microarchitectural recoding scheme. +# There are twice as many recoded values as IEEE-754 values; some of these +# extras are redundant (e.g. Inf) and others are illegal (subnormals with +# too many bits set). +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + # Make sure infinities with different mantissas compare as equal. + fld f0, minf, a0 + fld f1, three, a0 + fmul.d f1, f1, f0 + TEST_CASE( 2, a0, 1, feq.d a0, f0, f1) + TEST_CASE( 3, a0, 1, fle.d a0, f0, f1) + TEST_CASE( 4, a0, 0, flt.d a0, f0, f1) + + # Likewise, but for zeroes. + fcvt.d.w f0, x0 + li a0, 1 + fcvt.d.w f1, a0 + fmul.d f1, f1, f0 + TEST_CASE(5, a0, 1, feq.d a0, f0, f1) + TEST_CASE(6, a0, 1, fle.d a0, f0, f1) + TEST_CASE(7, a0, 0, flt.d a0, f0, f1) + + # When converting small doubles to single-precision subnormals, + # ensure that the extra precision is discarded. + flw f0, big, a0 + fld f1, tiny, a0 + fcvt.s.d f1, f1 + fmul.s f0, f0, f1 + fmv.x.s a0, f0 + lw a1, small + TEST_CASE(10, a0, 0, sub a0, a0, a1) + + # Make sure FSD+FLD correctly saves and restores a single-precision value. + flw f0, three, a0 + fadd.s f1, f0, f0 + fadd.s f0, f0, f0 + fsd f0, tiny, a0 + fld f0, tiny, a0 + TEST_CASE(20, a0, 1, feq.s a0, f0, f1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +minf: .double -Inf +three: .double 3.0 +big: .float 1221 +small: .float 2.9133121e-37 +tiny: .double 2.3860049081905093e-40 + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64ud/structural.S b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/structural.S new file mode 100644 index 000000000..5ecbb96d6 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64ud/structural.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# structural.S +#----------------------------------------------------------------------------- +# +# This test verifies that the FPU correctly obviates structural hazards on its +# writeback port (e.g. fadd followed by fsgnj) +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + +li x25, 1 + +li x2, 0x3FF0000000000000 +li x1, 0x3F800000 + +#define TEST(nops, errcode) \ + fmv.d.x f4, x0 ;\ + fmv.s.x f3, x0 ;\ + fmv.d.x f2, x2 ;\ + fmv.s.x f1, x1 ;\ + j 1f ;\ + .align 5 ;\ +1:fmul.d f4, f2, f2 ;\ + nops ;\ + fsgnj.s f3, f1, f1 ;\ + fmv.x.d x4, f4 ;\ + fmv.x.s x5, f3 ;\ + beq x1, x5, 2f ;\ + RVTEST_FAIL ;\ +2:beq x2, x4, 2f ;\ + RVTEST_FAIL; \ +2:fmv.d.x f2, zero ;\ + fmv.s.x f1, zero ;\ + +TEST(;,2) +TEST(nop,4) +TEST(nop;nop,6) +TEST(nop;nop;nop,8) +TEST(nop;nop;nop;nop,10) +TEST(nop;nop;nop;nop;nop,12) +TEST(nop;nop;nop;nop;nop;nop,14) + +RVTEST_PASS + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END |