diff options
Diffstat (limited to 'tests/test-progs/asmtest/src/riscv/isa/rv64uf')
12 files changed, 576 insertions, 0 deletions
diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/Makefrag b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/Makefrag new file mode 100644 index 000000000..26c63af58 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/Makefrag @@ -0,0 +1,13 @@ +#======================================================================= +# Makefrag for rv64uf tests +#----------------------------------------------------------------------- + +rv64uf_sc_tests = \ + fadd fdiv fclass fcmp fcvt fcvt_w fmadd fmin \ + ldst move recoding \ + +rv64uf_p_tests = $(addprefix rv64uf-p-, $(rv64uf_sc_tests)) +rv64uf_v_tests = $(addprefix rv64uf-v-, $(rv64uf_sc_tests)) +rv64uf_ps_tests = $(addprefix rv64uf-ps-, $(rv64uf_sc_tests)) + +spike_tests += $(rv64uf_p_tests) $(rv64uf_v_tests) diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fadd.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fadd.S new file mode 100644 index 000000000..b6259df64 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fadd.S @@ -0,0 +1,44 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fadd.S +#----------------------------------------------------------------------------- +# +# Test f{add|sub|mul}.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_S( 2, fadd.s, 0, 3.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 3, fadd.s, 1, -1234, -1235.1, 1.1 ); + TEST_FP_OP2_S( 4, fadd.s, 1, 3.14159265, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_S( 5, fsub.s, 0, 1.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 6, fsub.s, 1, -1234, -1235.1, -1.1 ); + TEST_FP_OP2_S( 7, fsub.s, 1, 3.14159265, 3.14159265, 0.00000001 ); + + TEST_FP_OP2_S( 8, fmul.s, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_S( 9, fmul.s, 1, 1358.61, -1235.1, -1.1 ); + TEST_FP_OP2_S(10, fmul.s, 1, 3.14159265e-8, 3.14159265, 0.00000001 ); + + # Is the canonical NaN generated for Inf - Inf? + TEST_FP_OP2_S(11, fsub.s, 0x10, qNaNf, Inf, Inf); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fclass.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fclass.S new file mode 100644 index 000000000..9bb86b17b --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fclass.S @@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fclass.S +#----------------------------------------------------------------------------- +# +# Test fclass.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FCLASS_S( 2, 1 << 0, 0xff800000 ) + TEST_FCLASS_S( 3, 1 << 1, 0xbf800000 ) + TEST_FCLASS_S( 4, 1 << 2, 0x807fffff ) + TEST_FCLASS_S( 5, 1 << 3, 0x80000000 ) + TEST_FCLASS_S( 6, 1 << 4, 0x00000000 ) + TEST_FCLASS_S( 7, 1 << 5, 0x007fffff ) + TEST_FCLASS_S( 8, 1 << 6, 0x3f800000 ) + TEST_FCLASS_S( 9, 1 << 7, 0x7f800000 ) + TEST_FCLASS_S(10, 1 << 8, 0x7f800001 ) + TEST_FCLASS_S(11, 1 << 9, 0x7fc00000 ) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fcmp.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fcmp.S new file mode 100644 index 000000000..2d7fcc243 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fcmp.S @@ -0,0 +1,50 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcmp.S +#----------------------------------------------------------------------------- +# +# Test f{eq|lt|le}.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_CMP_OP_S( 2, feq.s, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_S( 3, fle.s, 0x00, 1, -1.36, -1.36) + TEST_FP_CMP_OP_S( 4, flt.s, 0x00, 0, -1.36, -1.36) + + TEST_FP_CMP_OP_S( 5, feq.s, 0x00, 0, -1.37, -1.36) + TEST_FP_CMP_OP_S( 6, fle.s, 0x00, 1, -1.37, -1.36) + TEST_FP_CMP_OP_S( 7, flt.s, 0x00, 1, -1.37, -1.36) + + # Only sNaN should signal invalid for feq. + TEST_FP_CMP_OP_S( 8, feq.s, 0x00, 0, NaN, 0) + TEST_FP_CMP_OP_S( 9, feq.s, 0x00, 0, NaN, NaN) + TEST_FP_CMP_OP_S(10, feq.s, 0x10, 0, sNaNf, 0) + + # qNaN should signal invalid for fle/flt. + TEST_FP_CMP_OP_S(11, flt.s, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_S(12, flt.s, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_S(13, flt.s, 0x10, 0, sNaNf, 0) + TEST_FP_CMP_OP_S(14, fle.s, 0x10, 0, NaN, 0) + TEST_FP_CMP_OP_S(15, fle.s, 0x10, 0, NaN, NaN) + TEST_FP_CMP_OP_S(16, fle.s, 0x10, 0, sNaNf, 0) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fcvt.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fcvt.S new file mode 100644 index 000000000..a41686e99 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fcvt.S @@ -0,0 +1,43 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt.S +#----------------------------------------------------------------------------- +# +# Test fcvt.s.{wu|w|lu|l}, fcvt.s.d, and fcvt.d.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_INT_FP_OP_S( 2, fcvt.s.w, 2.0, 2); + TEST_INT_FP_OP_S( 3, fcvt.s.w, -2.0, -2); + + TEST_INT_FP_OP_S( 4, fcvt.s.wu, 2.0, 2); + TEST_INT_FP_OP_S( 5, fcvt.s.wu, 4.2949673e9, -2); + +#if __riscv_xlen >= 64 + TEST_INT_FP_OP_S( 6, fcvt.s.l, 2.0, 2); + TEST_INT_FP_OP_S( 7, fcvt.s.l, -2.0, -2); + + TEST_INT_FP_OP_S( 8, fcvt.s.lu, 2.0, 2); + TEST_INT_FP_OP_S( 9, fcvt.s.lu, 1.8446744e19, -2); +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fcvt_w.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fcvt_w.S new file mode 100644 index 000000000..cad5cbae1 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fcvt_w.S @@ -0,0 +1,105 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fcvt_w.S +#----------------------------------------------------------------------------- +# +# Test fcvt{wu|w|lu|l}.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_INT_OP_S( 2, fcvt.w.s, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_S( 3, fcvt.w.s, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_S( 4, fcvt.w.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S( 5, fcvt.w.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S( 6, fcvt.w.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S( 7, fcvt.w.s, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_S( 8, fcvt.w.s, 0x10, -1<<31, -3e9, rtz); + TEST_FP_INT_OP_S( 9, fcvt.w.s, 0x10, (1<<31)-1, 3e9, rtz); + + TEST_FP_INT_OP_S(12, fcvt.wu.s, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_S(13, fcvt.wu.s, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_S(14, fcvt.wu.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S(15, fcvt.wu.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S(16, fcvt.wu.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S(17, fcvt.wu.s, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_S(18, fcvt.wu.s, 0x10, 0, -3e9, rtz); + TEST_FP_INT_OP_S(19, fcvt.wu.s, 0x00, 3000000000, 3e9, rtz); + +#if __riscv_xlen >= 64 + TEST_FP_INT_OP_S(22, fcvt.l.s, 0x01, -1, -1.1, rtz); + TEST_FP_INT_OP_S(23, fcvt.l.s, 0x00, -1, -1.0, rtz); + TEST_FP_INT_OP_S(24, fcvt.l.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S(25, fcvt.l.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S(26, fcvt.l.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S(27, fcvt.l.s, 0x01, 1, 1.1, rtz); + + TEST_FP_INT_OP_S(32, fcvt.lu.s, 0x10, 0, -3.0, rtz); + TEST_FP_INT_OP_S(33, fcvt.lu.s, 0x10, 0, -1.0, rtz); + TEST_FP_INT_OP_S(34, fcvt.lu.s, 0x01, 0, -0.9, rtz); + TEST_FP_INT_OP_S(35, fcvt.lu.s, 0x01, 0, 0.9, rtz); + TEST_FP_INT_OP_S(36, fcvt.lu.s, 0x00, 1, 1.0, rtz); + TEST_FP_INT_OP_S(37, fcvt.lu.s, 0x01, 1, 1.1, rtz); + TEST_FP_INT_OP_S(38, fcvt.lu.s, 0x10, 0, -3e9, rtz); +#endif + + # test negative NaN, negative infinity conversion + TEST_CASE( 42, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 0(x1); fcvt.w.s x1, f1) + TEST_CASE( 44, x1, 0xffffffff80000000, la x1, tdat ; flw f1, 8(x1); fcvt.w.s x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 43, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.l.s x1, f1) + TEST_CASE( 45, x1, 0x8000000000000000, la x1, tdat ; flw f1, 8(x1); fcvt.l.s x1, f1) +#endif + + # test positive NaN, positive infinity conversion + TEST_CASE( 52, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 4(x1); fcvt.w.s x1, f1) + TEST_CASE( 54, x1, 0x000000007fffffff, la x1, tdat ; flw f1, 12(x1); fcvt.w.s x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 53, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.l.s x1, f1) + TEST_CASE( 55, x1, 0x7fffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.l.s x1, f1) +#endif + + # test NaN, infinity conversions to unsigned integer + TEST_CASE( 62, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.wu.s x1, f1) + TEST_CASE( 63, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.wu.s x1, f1) + TEST_CASE( 64, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.wu.s x1, f1) + TEST_CASE( 65, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.wu.s x1, f1) +#if __riscv_xlen >= 64 + TEST_CASE( 66, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 0(x1); fcvt.lu.s x1, f1) + TEST_CASE( 67, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 4(x1); fcvt.lu.s x1, f1) + TEST_CASE( 68, x1, 0, la x1, tdat ; flw f1, 8(x1); fcvt.lu.s x1, f1) + TEST_CASE( 69, x1, 0xffffffffffffffff, la x1, tdat ; flw f1, 12(x1); fcvt.lu.s x1, f1) +#endif + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +# -NaN, NaN, -inf, +inf +tdat: +.word 0xffffffff +.word 0x7fffffff +.word 0xff800000 +.word 0x7f800000 + +tdat_d: +.dword 0xffffffffffffffff +.dword 0x7fffffffffffffff +.dword 0xfff0000000000000 +.dword 0x7ff0000000000000 + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fdiv.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fdiv.S new file mode 100644 index 000000000..a75a23d96 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fdiv.S @@ -0,0 +1,40 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fdiv.S +#----------------------------------------------------------------------------- +# +# Test f{div|sqrt}.s instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_S(2, fdiv.s, 1, 1.1557273520668288, 3.14159265, 2.71828182 ); + TEST_FP_OP2_S(3, fdiv.s, 1,-0.9991093838555584, -1234, 1235.1 ); + TEST_FP_OP2_S(4, fdiv.s, 0, 3.14159265, 3.14159265, 1.0 ); + + TEST_FP_OP1_S(5, fsqrt.s, 1, 1.7724538498928541, 3.14159265 ); + TEST_FP_OP1_S(6, fsqrt.s, 0, 100, 10000 ); + + TEST_FP_OP1_S_DWORD_RESULT(7, fsqrt.s, 0x10, 0x7FC00000, -1.0 ); + + TEST_FP_OP1_S(8, fsqrt.s, 1, 13.076696, 171.0); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fmadd.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fmadd.S new file mode 100644 index 000000000..241bead63 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fmadd.S @@ -0,0 +1,45 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmadd.S +#----------------------------------------------------------------------------- +# +# Test f[n]m{add|sub}.s and f[n]m{add|sub}.d instructions. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP3_S( 2, fmadd.s, 0, 3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 3, fmadd.s, 1, 1236.2, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S( 4, fmadd.s, 0, -12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_S( 5, fnmadd.s, 0, -3.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 6, fnmadd.s, 1, -1236.2, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S( 7, fnmadd.s, 0, 12.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_S( 8, fmsub.s, 0, 1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S( 9, fmsub.s, 1, 1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(10, fmsub.s, 0, -8.0, 2.0, -5.0, -2.0 ); + + TEST_FP_OP3_S(11, fnmsub.s, 0, -1.5, 1.0, 2.5, 1.0 ); + TEST_FP_OP3_S(12, fnmsub.s, 1, -1234, -1.0, -1235.1, 1.1 ); + TEST_FP_OP3_S(13, fnmsub.s, 0, 8.0, 2.0, -5.0, -2.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fmin.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fmin.S new file mode 100644 index 000000000..8c721aac2 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/fmin.S @@ -0,0 +1,54 @@ +# See LICENSE for license details. + +#***************************************************************************** +# fmin.S +#----------------------------------------------------------------------------- +# +# Test f{min|max}.s instructinos. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + #------------------------------------------------------------- + # Arithmetic tests + #------------------------------------------------------------- + + TEST_FP_OP2_S( 2, fmin.s, 0, 1.0, 2.5, 1.0 ); + TEST_FP_OP2_S( 3, fmin.s, 0, -1235.1, -1235.1, 1.1 ); + TEST_FP_OP2_S( 4, fmin.s, 0, -1235.1, 1.1, -1235.1 ); + TEST_FP_OP2_S( 5, fmin.s, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_S( 6, fmin.s, 0, 0.00000001, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S( 7, fmin.s, 0, -2.0, -1.0, -2.0 ); + + TEST_FP_OP2_S(12, fmax.s, 0, 2.5, 2.5, 1.0 ); + TEST_FP_OP2_S(13, fmax.s, 0, 1.1, -1235.1, 1.1 ); + TEST_FP_OP2_S(14, fmax.s, 0, 1.1, 1.1, -1235.1 ); + TEST_FP_OP2_S(15, fmax.s, 0, -1235.1, NaN, -1235.1 ); + TEST_FP_OP2_S(16, fmax.s, 0, 3.14159265, 3.14159265, 0.00000001 ); + TEST_FP_OP2_S(17, fmax.s, 0, -1.0, -1.0, -2.0 ); + + # FMIN(sNaN, x) = x + TEST_FP_OP2_S(20, fmax.s, 0x10, 1.0, sNaNf, 1.0); + # FMIN(qNaN, qNaN) = canonical NaN + TEST_FP_OP2_S(21, fmax.s, 0x00, qNaNf, NaN, NaN); + + # -0.0 < +0.0 + TEST_FP_OP2_S(30, fmin.s, 0, -0.0, -0.0, 0.0 ); + TEST_FP_OP2_S(31, fmin.s, 0, -0.0, 0.0, -0.0 ); + TEST_FP_OP2_S(32, fmax.s, 0, 0.0, -0.0, 0.0 ); + TEST_FP_OP2_S(33, fmax.s, 0, 0.0, 0.0, -0.0 ); + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/ldst.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/ldst.S new file mode 100644 index 000000000..c35dd8d61 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/ldst.S @@ -0,0 +1,38 @@ +# See LICENSE for license details. + +#***************************************************************************** +# ldst.S +#----------------------------------------------------------------------------- +# +# This test verifies that flw, fld, fsw, and fsd work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a0, 0x40000000deadbeef, la a1, tdat; flw f1, 4(a1); fsw f1, 20(a1); ld a0, 16(a1)) + TEST_CASE(3, a0, 0x1337d00dbf800000, la a1, tdat; flw f1, 0(a1); fsw f1, 24(a1); ld a0, 24(a1)) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +tdat: +.word 0xbf800000 +.word 0x40000000 +.word 0x40400000 +.word 0xc0800000 +.word 0xdeadbeef +.word 0xcafebabe +.word 0xabad1dea +.word 0x1337d00d + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/move.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/move.S new file mode 100644 index 000000000..60f7cf376 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/move.S @@ -0,0 +1,58 @@ +# See LICENSE for license details. + +#***************************************************************************** +# move.S +#----------------------------------------------------------------------------- +# +# This test verifies that the fmv.s.x, fmv.x.s, and fsgnj[x|n].d instructions +# and the fcsr work properly. +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + TEST_CASE(2, a1, 1, csrwi fcsr, 1; li a0, 0x1234; fssr a1, a0) + TEST_CASE(3, a0, 0x34, frsr a0) + TEST_CASE(4, a0, 0x14, frflags a0) + TEST_CASE(5, a0, 0x01, csrrwi a0, frm, 2) + TEST_CASE(6, a0, 0x54, frsr a0) + TEST_CASE(7, a0, 0x14, csrrci a0, fflags, 4) + TEST_CASE(8, a0, 0x50, frsr a0) + +#define TEST_FSGNJS(n, insn, new_sign, rs1_sign, rs2_sign) \ + TEST_CASE(n, a0, 0x12345678 | (-(new_sign) << 31), \ + li a1, ((rs1_sign) << 31) | 0x12345678; \ + li a2, -(rs2_sign); \ + fmv.s.x f1, a1; \ + fmv.s.x f2, a2; \ + insn f0, f1, f2; \ + fmv.x.s a0, f0) + + TEST_FSGNJS(10, fsgnj.s, 0, 0, 0) + TEST_FSGNJS(11, fsgnj.s, 1, 0, 1) + TEST_FSGNJS(12, fsgnj.s, 0, 1, 0) + TEST_FSGNJS(13, fsgnj.s, 1, 1, 1) + + TEST_FSGNJS(20, fsgnjn.s, 1, 0, 0) + TEST_FSGNJS(21, fsgnjn.s, 0, 0, 1) + TEST_FSGNJS(22, fsgnjn.s, 1, 1, 0) + TEST_FSGNJS(23, fsgnjn.s, 0, 1, 1) + + TEST_FSGNJS(30, fsgnjx.s, 0, 0, 0) + TEST_FSGNJS(31, fsgnjx.s, 1, 0, 1) + TEST_FSGNJS(32, fsgnjx.s, 1, 1, 0) + TEST_FSGNJS(33, fsgnjx.s, 0, 1, 1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + + TEST_DATA + +RVTEST_DATA_END diff --git a/tests/test-progs/asmtest/src/riscv/isa/rv64uf/recoding.S b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/recoding.S new file mode 100644 index 000000000..802be6627 --- /dev/null +++ b/tests/test-progs/asmtest/src/riscv/isa/rv64uf/recoding.S @@ -0,0 +1,46 @@ +# See LICENSE for license details. + +#***************************************************************************** +# recoding.S +#----------------------------------------------------------------------------- +# +# Test corner cases of John Hauser's microarchitectural recoding scheme. +# There are twice as many recoded values as IEEE-754 values; some of these +# extras are redundant (e.g. Inf) and others are illegal (subnormals with +# too many bits set). +# + +#include "riscv_test.h" +#include "test_macros.h" + +RVTEST_RV64UF +RVTEST_CODE_BEGIN + + # Make sure infinities with different mantissas compare as equal. + flw f0, minf, a0 + flw f1, three, a0 + fmul.s f1, f1, f0 + TEST_CASE( 2, a0, 1, feq.s a0, f0, f1) + TEST_CASE( 3, a0, 1, fle.s a0, f0, f1) + TEST_CASE( 4, a0, 0, flt.s a0, f0, f1) + + # Likewise, but for zeroes. + fcvt.s.w f0, x0 + li a0, 1 + fcvt.s.w f1, a0 + fmul.s f1, f1, f0 + TEST_CASE(5, a0, 1, feq.s a0, f0, f1) + TEST_CASE(6, a0, 1, fle.s a0, f0, f1) + TEST_CASE(7, a0, 0, flt.s a0, f0, f1) + + TEST_PASSFAIL + +RVTEST_CODE_END + + .data +RVTEST_DATA_BEGIN + +minf: .float -Inf +three: .float 3.0 + +RVTEST_DATA_END |