diff options
Diffstat (limited to 'tests/test1/ref/alpha/detailed/config.ini')
| -rw-r--r-- | tests/test1/ref/alpha/detailed/config.ini | 95 |
1 files changed, 41 insertions, 54 deletions
diff --git a/tests/test1/ref/alpha/detailed/config.ini b/tests/test1/ref/alpha/detailed/config.ini index 192833c8b..a442ec572 100644 --- a/tests/test1/ref/alpha/detailed/config.ini +++ b/tests/test1/ref/alpha/detailed/config.ini @@ -48,13 +48,13 @@ text_file=m5stats.txt [system] type=System -children=cpu0 physmem workload +children=cpu physmem workload mem_mode=atomic physmem=system.physmem -[system.cpu0] +[system.cpu] type=DerivO3CPU -children=checker fuPool mem +children=fuPool mem BTBEntries=4096 BTBTagSize=16 LFSTSize=1024 @@ -64,7 +64,6 @@ SQEntries=32 SSITSize=1024 activity=0 backComSize=5 -checker=system.cpu0.checker choiceCtrBits=2 choicePredictorSize=8192 clock=1 @@ -79,9 +78,10 @@ decodeWidth=8 defer_registration=false dispatchWidth=8 fetchToDecodeDelay=1 +fetchTrapLatency=1 fetchWidth=8 forwardComSize=5 -fuPool=system.cpu0.fuPool +fuPool=system.cpu.fuPool function_trace=false function_trace_start=0 globalCtrBits=2 @@ -102,11 +102,12 @@ max_insts_all_threads=0 max_insts_any_thread=500000 max_loads_all_threads=0 max_loads_any_thread=0 -mem=system.cpu0.mem +mem=system.cpu.mem numIQEntries=64 numPhysFloatRegs=256 numPhysIntRegs=256 numROBEntries=192 +numRobs=1 numThreads=1 predType=tournament renameToDecodeDelay=1 @@ -116,163 +117,149 @@ renameToROBDelay=1 renameWidth=8 squashWidth=8 system=system +trapLatency=13 wbDepth=1 wbWidth=8 workload=system.workload -[system.cpu0.checker] -type=O3Checker -clock=1 -defer_registration=false -exitOnError=true -function_trace=false -function_trace_start=0 -max_insts_all_threads=0 -max_insts_any_thread=0 -max_loads_all_threads=0 -max_loads_any_thread=0 -system=system -warnOnlyOnLoadError=false -workload=system.workload - -[system.cpu0.fuPool] +[system.cpu.fuPool] type=FUPool children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 -FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 +FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 -[system.cpu0.fuPool.FUList0] +[system.cpu.fuPool.FUList0] type=FUDesc children=opList0 count=6 -opList=system.cpu0.fuPool.FUList0.opList0 +opList=system.cpu.fuPool.FUList0.opList0 -[system.cpu0.fuPool.FUList0.opList0] +[system.cpu.fuPool.FUList0.opList0] type=OpDesc issueLat=1 opClass=IntAlu opLat=1 -[system.cpu0.fuPool.FUList1] +[system.cpu.fuPool.FUList1] type=FUDesc children=opList0 opList1 count=2 -opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 +opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 -[system.cpu0.fuPool.FUList1.opList0] +[system.cpu.fuPool.FUList1.opList0] type=OpDesc issueLat=1 opClass=IntMult opLat=3 -[system.cpu0.fuPool.FUList1.opList1] +[system.cpu.fuPool.FUList1.opList1] type=OpDesc issueLat=19 opClass=IntDiv opLat=20 -[system.cpu0.fuPool.FUList2] +[system.cpu.fuPool.FUList2] type=FUDesc children=opList0 opList1 opList2 count=4 -opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 +opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 -[system.cpu0.fuPool.FUList2.opList0] +[system.cpu.fuPool.FUList2.opList0] type=OpDesc issueLat=1 opClass=FloatAdd opLat=2 -[system.cpu0.fuPool.FUList2.opList1] +[system.cpu.fuPool.FUList2.opList1] type=OpDesc issueLat=1 opClass=FloatCmp opLat=2 -[system.cpu0.fuPool.FUList2.opList2] +[system.cpu.fuPool.FUList2.opList2] type=OpDesc issueLat=1 opClass=FloatCvt opLat=2 -[system.cpu0.fuPool.FUList3] +[system.cpu.fuPool.FUList3] type=FUDesc children=opList0 opList1 opList2 count=2 -opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 +opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 -[system.cpu0.fuPool.FUList3.opList0] +[system.cpu.fuPool.FUList3.opList0] type=OpDesc issueLat=1 opClass=FloatMult opLat=4 -[system.cpu0.fuPool.FUList3.opList1] +[system.cpu.fuPool.FUList3.opList1] type=OpDesc issueLat=12 opClass=FloatDiv opLat=12 -[system.cpu0.fuPool.FUList3.opList2] +[system.cpu.fuPool.FUList3.opList2] type=OpDesc issueLat=24 opClass=FloatSqrt opLat=24 -[system.cpu0.fuPool.FUList4] +[system.cpu.fuPool.FUList4] type=FUDesc children=opList0 count=0 -opList=system.cpu0.fuPool.FUList4.opList0 +opList=system.cpu.fuPool.FUList4.opList0 -[system.cpu0.fuPool.FUList4.opList0] +[system.cpu.fuPool.FUList4.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu0.fuPool.FUList5] +[system.cpu.fuPool.FUList5] type=FUDesc children=opList0 count=0 -opList=system.cpu0.fuPool.FUList5.opList0 +opList=system.cpu.fuPool.FUList5.opList0 -[system.cpu0.fuPool.FUList5.opList0] +[system.cpu.fuPool.FUList5.opList0] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu0.fuPool.FUList6] +[system.cpu.fuPool.FUList6] type=FUDesc children=opList0 opList1 count=4 -opList=system.cpu0.fuPool.FUList6.opList0 system.cpu0.fuPool.FUList6.opList1 +opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 -[system.cpu0.fuPool.FUList6.opList0] +[system.cpu.fuPool.FUList6.opList0] type=OpDesc issueLat=1 opClass=MemRead opLat=1 -[system.cpu0.fuPool.FUList6.opList1] +[system.cpu.fuPool.FUList6.opList1] type=OpDesc issueLat=1 opClass=MemWrite opLat=1 -[system.cpu0.fuPool.FUList7] +[system.cpu.fuPool.FUList7] type=FUDesc children=opList0 count=1 -opList=system.cpu0.fuPool.FUList7.opList0 +opList=system.cpu.fuPool.FUList7.opList0 -[system.cpu0.fuPool.FUList7.opList0] +[system.cpu.fuPool.FUList7.opList0] type=OpDesc issueLat=3 opClass=IprAccess opLat=3 -[system.cpu0.mem] +[system.cpu.mem] type=Bus bus_id=0 |