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-rw-r--r--tests/SConscript2
-rw-r--r--tests/configs/memtest-filter.py87
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini610
-rwxr-xr-xtests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr74
-rwxr-xr-xtests/quick/se/50.memtest/ref/null/none/memtest-filter/simout10
-rw-r--r--tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt1747
6 files changed, 2529 insertions, 1 deletions
diff --git a/tests/SConscript b/tests/SConscript
index 64f0067c7..ec2b4b121 100644
--- a/tests/SConscript
+++ b/tests/SConscript
@@ -344,7 +344,7 @@ configs += ['simple-atomic', 'simple-atomic-mp',
'inorder-timing',
'minor-timing', 'minor-timing-mp',
'o3-timing', 'o3-timing-mp',
- 'rubytest', 'memtest',
+ 'rubytest', 'memtest', 'memtest-filter',
'tgen-simple-mem', 'tgen-dram-ctrl']
if env['PROTOCOL'] != 'None':
diff --git a/tests/configs/memtest-filter.py b/tests/configs/memtest-filter.py
new file mode 100644
index 000000000..4de009d76
--- /dev/null
+++ b/tests/configs/memtest-filter.py
@@ -0,0 +1,87 @@
+# Copyright (c) 2006-2007 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Ron Dreslinski
+
+import m5
+from m5.objects import *
+m5.util.addToPath('../configs/common')
+from Caches import *
+
+#MAX CORES IS 8 with the fals sharing method
+nb_cores = 8
+cpus = [ MemTest() for i in xrange(nb_cores) ]
+
+# system simulated
+system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
+ funcbus = NoncoherentBus(),
+ physmem = SimpleMemory(),
+ membus = CoherentBus(width=16, snoop_filter = SnoopFilter()))
+# Dummy voltage domain for all our clock domains
+system.voltage_domain = VoltageDomain()
+system.clk_domain = SrcClockDomain(clock = '1GHz',
+ voltage_domain = system.voltage_domain)
+
+# Create a seperate clock domain for components that should run at
+# CPUs frequency
+system.cpu_clk_domain = SrcClockDomain(clock = '2GHz',
+ voltage_domain = system.voltage_domain)
+
+system.toL2Bus = CoherentBus(clk_domain = system.cpu_clk_domain, width=16,
+ snoop_filter = SnoopFilter())
+system.l2c = L2Cache(clk_domain = system.cpu_clk_domain, size='64kB', assoc=8)
+system.l2c.cpu_side = system.toL2Bus.master
+
+# connect l2c to membus
+system.l2c.mem_side = system.membus.slave
+
+# add L1 caches
+for cpu in cpus:
+ # All cpus are associated with cpu_clk_domain
+ cpu.clk_domain = system.cpu_clk_domain
+ cpu.l1c = L1Cache(size = '32kB', assoc = 4)
+ cpu.l1c.cpu_side = cpu.test
+ cpu.l1c.mem_side = system.toL2Bus.slave
+ system.funcbus.slave = cpu.functional
+
+system.system_port = system.membus.slave
+
+# connect reference memory to funcbus
+system.funcmem.port = system.funcbus.master
+
+# connect memory to membus
+system.physmem.port = system.membus.master
+
+
+# -----------------------
+# run simulation
+# -----------------------
+
+root = Root( full_system = False, system = system )
+root.system.mem_mode = 'timing'
+#root.trace.flags="Cache CachePort MemoryAccess"
+#root.trace.cycle=1
+
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
new file mode 100644
index 000000000..b9c14dc5f
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/config.ini
@@ -0,0 +1,610 @@
+[root]
+type=Root
+children=system
+eventq_index=0
+full_system=false
+sim_quantum=0
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+eventq_index=0
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+load_offset=0
+mem_mode=timing
+mem_ranges=
+memories=system.physmem system.funcmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.cpu0]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[0]
+test=system.cpu0.l1c.cpu_side
+
+[system.cpu0.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu0.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu0.test
+mem_side=system.toL2Bus.slave[0]
+
+[system.cpu0.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu1]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[1]
+test=system.cpu1.l1c.cpu_side
+
+[system.cpu1.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu1.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu1.test
+mem_side=system.toL2Bus.slave[1]
+
+[system.cpu1.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu2]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[2]
+test=system.cpu2.l1c.cpu_side
+
+[system.cpu2.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu2.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu2.test
+mem_side=system.toL2Bus.slave[2]
+
+[system.cpu2.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu3]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[3]
+test=system.cpu3.l1c.cpu_side
+
+[system.cpu3.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu3.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu3.test
+mem_side=system.toL2Bus.slave[3]
+
+[system.cpu3.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu4]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[4]
+test=system.cpu4.l1c.cpu_side
+
+[system.cpu4.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu4.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu4.test
+mem_side=system.toL2Bus.slave[4]
+
+[system.cpu4.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu5]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[5]
+test=system.cpu5.l1c.cpu_side
+
+[system.cpu5.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu5.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu5.test
+mem_side=system.toL2Bus.slave[5]
+
+[system.cpu5.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu6]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[6]
+test=system.cpu6.l1c.cpu_side
+
+[system.cpu6.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu6.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu6.test
+mem_side=system.toL2Bus.slave[6]
+
+[system.cpu6.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu7]
+type=MemTest
+children=l1c
+atomic=false
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+issue_dmas=false
+max_loads=100000
+memory_size=65536
+percent_dest_unaligned=50
+percent_functional=50
+percent_reads=65
+percent_source_unaligned=50
+percent_uncacheable=10
+progress_interval=10000
+suppress_func_warnings=false
+sys=system
+trace_addr=0
+functional=system.funcbus.slave[7]
+test=system.cpu7.l1c.cpu_side
+
+[system.cpu7.l1c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=4
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=2
+is_top_level=true
+max_miss_count=0
+mshrs=4
+prefetch_on_access=false
+prefetcher=Null
+response_latency=2
+sequential_access=false
+size=32768
+system=system
+tags=system.cpu7.l1c.tags
+tgts_per_mshr=20
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu7.test
+mem_side=system.toL2Bus.slave[7]
+
+[system.cpu7.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=2
+sequential_access=false
+size=32768
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+eventq_index=0
+voltage_domain=system.voltage_domain
+
+[system.funcbus]
+type=NoncoherentBus
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+use_default_range=false
+width=8
+master=system.funcmem.port
+slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional
+
+[system.funcmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=false
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.funcbus.master[0]
+
+[system.l2c]
+type=BaseCache
+children=tags
+addr_ranges=0:18446744073709551615
+assoc=8
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+forward_snoops=true
+hit_latency=20
+is_top_level=false
+max_miss_count=0
+mshrs=20
+prefetch_on_access=false
+prefetcher=Null
+response_latency=20
+sequential_access=false
+size=65536
+system=system
+tags=system.l2c.tags
+tgts_per_mshr=12
+two_queue=false
+write_buffers=8
+cpu_side=system.toL2Bus.master[0]
+mem_side=system.membus.slave[0]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+hit_latency=20
+sequential_access=false
+size=65536
+
+[system.membus]
+type=CoherentBus
+children=snoop_filter
+clk_domain=system.clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=system.membus.snoop_filter
+system=system
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.l2c.mem_side system.system_port
+
+[system.membus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=3
+system=system
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+eventq_index=0
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
+[system.toL2Bus]
+type=CoherentBus
+children=snoop_filter
+clk_domain=system.cpu_clk_domain
+eventq_index=0
+header_cycles=1
+snoop_filter=system.toL2Bus.snoop_filter
+system=system
+use_default_range=false
+width=16
+master=system.l2c.cpu_side
+slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
+
+[system.toL2Bus.snoop_filter]
+type=SnoopFilter
+eventq_index=0
+lookup_latency=3
+system=system
+
+[system.voltage_domain]
+type=VoltageDomain
+eventq_index=0
+voltage=1.000000
+
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
new file mode 100755
index 000000000..70113e2a8
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simerr
@@ -0,0 +1,74 @@
+warn: failed to generate dot output from build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter/config.dot
+system.cpu6: completed 10000 read, 5415 write accesses @145109000
+system.cpu2: completed 10000 read, 5349 write accesses @145417500
+system.cpu1: completed 10000 read, 5329 write accesses @146140000
+system.cpu0: completed 10000 read, 5371 write accesses @146497000
+system.cpu4: completed 10000 read, 5466 write accesses @147507000
+system.cpu3: completed 10000 read, 5586 write accesses @147982000
+system.cpu5: completed 10000 read, 5427 write accesses @148047500
+system.cpu7: completed 10000 read, 5356 write accesses @148467500
+system.cpu6: completed 20000 read, 10673 write accesses @289538000
+system.cpu2: completed 20000 read, 10526 write accesses @290832000
+system.cpu1: completed 20000 read, 10766 write accesses @292890999
+system.cpu5: completed 20000 read, 10736 write accesses @293627000
+system.cpu7: completed 20000 read, 10730 write accesses @293693000
+system.cpu0: completed 20000 read, 10671 write accesses @294206500
+system.cpu4: completed 20000 read, 10944 write accesses @296769500
+system.cpu3: completed 20000 read, 10962 write accesses @297951000
+system.cpu2: completed 30000 read, 15840 write accesses @436954000
+system.cpu1: completed 30000 read, 16134 write accesses @439432500
+system.cpu6: completed 30000 read, 16128 write accesses @439710500
+system.cpu7: completed 30000 read, 16048 write accesses @440819000
+system.cpu5: completed 30000 read, 16126 write accesses @441698000
+system.cpu3: completed 30000 read, 16409 write accesses @444974000
+system.cpu4: completed 30000 read, 16439 write accesses @445869500
+system.cpu0: completed 30000 read, 16254 write accesses @446194000
+system.cpu2: completed 40000 read, 21231 write accesses @582932500
+system.cpu6: completed 40000 read, 21466 write accesses @586141500
+system.cpu1: completed 40000 read, 21414 write accesses @588066500
+system.cpu3: completed 40000 read, 21735 write accesses @588220000
+system.cpu5: completed 40000 read, 21572 write accesses @588767000
+system.cpu7: completed 40000 read, 21513 write accesses @590091000
+system.cpu0: completed 40000 read, 21682 write accesses @592843000
+system.cpu4: completed 40000 read, 21885 write accesses @593488000
+system.cpu2: completed 50000 read, 26639 write accesses @730512000
+system.cpu3: completed 50000 read, 26953 write accesses @733051500
+system.cpu6: completed 50000 read, 26889 write accesses @736295000
+system.cpu1: completed 50000 read, 26860 write accesses @736946500
+system.cpu4: completed 50000 read, 27157 write accesses @739104500
+system.cpu5: completed 50000 read, 27043 write accesses @739175000
+system.cpu7: completed 50000 read, 27030 write accesses @739274500
+system.cpu0: completed 50000 read, 27007 write accesses @740081999
+system.cpu2: completed 60000 read, 31935 write accesses @875520000
+system.cpu3: completed 60000 read, 32327 write accesses @878608000
+system.cpu1: completed 60000 read, 32037 write accesses @880758000
+system.cpu5: completed 60000 read, 32374 write accesses @883996500
+system.cpu4: completed 60000 read, 32578 write accesses @885209000
+system.cpu6: completed 60000 read, 32302 write accesses @886481999
+system.cpu0: completed 60000 read, 32356 write accesses @886645000
+system.cpu7: completed 60000 read, 32534 write accesses @888148500
+system.cpu3: completed 70000 read, 37577 write accesses @1026143000
+system.cpu2: completed 70000 read, 37542 write accesses @1027029999
+system.cpu1: completed 70000 read, 37457 write accesses @1029024000
+system.cpu5: completed 70000 read, 37722 write accesses @1029495500
+system.cpu6: completed 70000 read, 37640 write accesses @1032918500
+system.cpu0: completed 70000 read, 37692 write accesses @1034293500
+system.cpu7: completed 70000 read, 37955 write accesses @1034390500
+system.cpu4: completed 70000 read, 38136 write accesses @1036569000
+system.cpu3: completed 80000 read, 42898 write accesses @1173212500
+system.cpu2: completed 80000 read, 42932 write accesses @1173575000
+system.cpu1: completed 80000 read, 42886 write accesses @1177639500
+system.cpu5: completed 80000 read, 43232 write accesses @1178175000
+system.cpu0: completed 80000 read, 42958 write accesses @1178771500
+system.cpu6: completed 80000 read, 42919 write accesses @1180797000
+system.cpu7: completed 80000 read, 43430 write accesses @1183823000
+system.cpu4: completed 80000 read, 43550 write accesses @1185935999
+system.cpu2: completed 90000 read, 48239 write accesses @1319473000
+system.cpu3: completed 90000 read, 48329 write accesses @1322081500
+system.cpu1: completed 90000 read, 48223 write accesses @1323240500
+system.cpu5: completed 90000 read, 48632 write accesses @1326787000
+system.cpu0: completed 90000 read, 48351 write accesses @1327807500
+system.cpu6: completed 90000 read, 48287 write accesses @1329208000
+system.cpu7: completed 90000 read, 48796 write accesses @1329462500
+system.cpu4: completed 90000 read, 48969 write accesses @1334198500
+system.cpu2: completed 100000 read, 53603 write accesses @1466014000
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout
new file mode 100755
index 000000000..c563af536
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/simout
@@ -0,0 +1,10 @@
+gem5 Simulator System. http://gem5.org
+gem5 is copyrighted software; use the --copyright option for details.
+
+gem5 compiled Feb 28 2014 18:29:12
+gem5 started Feb 28 2014 18:30:27
+gem5 executing on cz310588hp
+command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter -re tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest-filter
+Global frequency set at 1000000000000 ticks per second
+info: Entering event queue @ 0. Starting simulation...
+Exiting @ tick 1466014000 because maximum number of loads reached
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
new file mode 100644
index 000000000..03cf254c4
--- /dev/null
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest-filter/stats.txt
@@ -0,0 +1,1747 @@
+
+---------- Begin Simulation Statistics ----------
+sim_seconds 0.001466 # Number of seconds simulated
+sim_ticks 1466014000 # Number of ticks simulated
+final_tick 1466014000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_freq 1000000000000 # Frequency of simulated ticks
+host_tick_rate 362824283 # Simulator tick rate (ticks/s)
+host_mem_usage 344492 # Number of bytes of host memory used
+host_seconds 4.04 # Real time elapsed on the host
+system.voltage_domain.voltage 1 # Voltage in Volts
+system.clk_domain.clock 1000 # Clock period in ticks
+system.physmem.bytes_read::cpu0 81024 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1 82440 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu2 87271 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu3 81468 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu4 83154 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu5 83511 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu6 83243 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu7 81362 # Number of bytes read from this memory
+system.physmem.bytes_read::total 663473 # Number of bytes read from this memory
+system.physmem.bytes_written::writebacks 418112 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0 5482 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1 5323 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu2 5338 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu3 5333 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu4 5428 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu5 5332 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu6 5280 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu7 5327 # Number of bytes written to this memory
+system.physmem.bytes_written::total 460955 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0 11094 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1 11124 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu2 11230 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu3 10971 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu4 11082 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu5 11061 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu6 11171 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu7 11117 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 88850 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 6533 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0 5482 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1 5323 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu2 5338 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu3 5333 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu4 5428 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu5 5332 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu6 5280 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu7 5327 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 49376 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0 55268231 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1 56234115 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu2 59529445 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu3 55571093 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu4 56721150 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu5 56964667 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu6 56781859 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu7 55498788 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 452569348 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 285203279 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0 3739391 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1 3630934 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu2 3641166 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu3 3637755 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu4 3702557 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu5 3637073 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu6 3601603 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu7 3633662 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 314427420 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 285203279 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0 59007622 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1 59865049 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu2 63170611 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu3 59208848 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu4 60423707 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu5 60601741 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu6 60383462 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu7 59132450 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 766996768 # Total bandwidth to/from this memory (bytes/s)
+system.membus.snoop_filter.tot_requests 121068 # Total number of requests made to the snoop filter.
+system.membus.snoop_filter.hit_single_requests 119020 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.membus.throughput 766995404 # Throughput (bytes/s)
+system.membus.trans_dist::ReadReq 85646 # Transaction distribution
+system.membus.trans_dist::ReadResp 85644 # Transaction distribution
+system.membus.trans_dist::WriteReq 42843 # Transaction distribution
+system.membus.trans_dist::WriteResp 42842 # Transaction distribution
+system.membus.trans_dist::Writeback 6533 # Transaction distribution
+system.membus.trans_dist::UpgradeReq 57248 # Transaction distribution
+system.membus.trans_dist::UpgradeResp 46699 # Transaction distribution
+system.membus.trans_dist::ReadExReq 48957 # Transaction distribution
+system.membus.trans_dist::ReadExResp 3204 # Transaction distribution
+system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 419616 # Packet count per connected master and slave (bytes)
+system.membus.pkt_count::total 419616 # Packet count per connected master and slave (bytes)
+system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 1124426 # Cumulative packet size per connected master and slave (bytes)
+system.membus.tot_pkt_size::total 1124426 # Cumulative packet size per connected master and slave (bytes)
+system.membus.data_through_bus 1124426 # Total data (bytes)
+system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
+system.membus.snoops_through_bus 56301 # Total snoops (count)
+system.membus.snoop_fanout::samples 121068 # Request fanout histogram
+system.membus.snoop_fanout::mean 0 # Request fanout histogram
+system.membus.snoop_fanout::stdev 0 # Request fanout histogram
+system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.membus.snoop_fanout::0 121068 100.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.membus.snoop_fanout::min_value 0 # Request fanout histogram
+system.membus.snoop_fanout::max_value 0 # Request fanout histogram
+system.membus.snoop_fanout::total 121068 # Request fanout histogram
+system.membus.reqLayer0.occupancy 476149500 # Layer occupancy (ticks)
+system.membus.reqLayer0.utilization 32.5 # Layer utilization (%)
+system.membus.respLayer0.occupancy 322630500 # Layer occupancy (ticks)
+system.membus.respLayer0.utilization 22.0 # Layer utilization (%)
+system.cpu_clk_domain.clock 500 # Clock period in ticks
+system.l2c.tags.replacements 13552 # number of replacements
+system.l2c.tags.tagsinuse 786.290427 # Cycle average of tags in use
+system.l2c.tags.total_refs 149902 # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs 14350 # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs 10.446132 # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks 730.775276 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0 6.840177 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1 7.161871 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2 6.892698 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3 6.763865 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu4 6.714219 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu5 6.973391 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu6 7.262671 # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu7 6.906259 # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks 0.713648 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0 0.006680 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1 0.006994 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2 0.006731 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3 0.006605 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu4 0.006557 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu5 0.006810 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu6 0.007092 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu7 0.006744 # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total 0.767862 # Average percentage of cache occupancy
+system.l2c.tags.occ_task_id_blocks::1024 798 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::0 368 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::1 428 # Occupied blocks per task id
+system.l2c.tags.age_task_id_blocks_1024::2 2 # Occupied blocks per task id
+system.l2c.tags.occ_task_id_percent::1024 0.779297 # Percentage of cache occupancy per task id
+system.l2c.tags.tag_accesses 1950254 # Number of tag accesses
+system.l2c.tags.data_accesses 1950254 # Number of data accesses
+system.l2c.ReadReq_hits::cpu0 10780 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1 10796 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2 10830 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3 10794 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu4 10743 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu5 10804 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu6 10680 # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu7 10909 # number of ReadReq hits
+system.l2c.ReadReq_hits::total 86336 # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks 74514 # number of Writeback hits
+system.l2c.Writeback_hits::total 74514 # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0 330 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu1 332 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu2 379 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu3 363 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu4 357 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu5 362 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu6 317 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::cpu7 363 # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total 2803 # number of UpgradeReq hits
+system.l2c.ReadExReq_hits::cpu0 1848 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu1 1871 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu2 1840 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu3 1858 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu4 1858 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu5 1893 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu6 1894 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::cpu7 1826 # number of ReadExReq hits
+system.l2c.ReadExReq_hits::total 14888 # number of ReadExReq hits
+system.l2c.demand_hits::cpu0 12628 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1 12667 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2 12670 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3 12652 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu4 12601 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu5 12697 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu6 12574 # number of demand (read+write) hits
+system.l2c.demand_hits::cpu7 12735 # number of demand (read+write) hits
+system.l2c.demand_hits::total 101224 # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0 12628 # number of overall hits
+system.l2c.overall_hits::cpu1 12667 # number of overall hits
+system.l2c.overall_hits::cpu2 12670 # number of overall hits
+system.l2c.overall_hits::cpu3 12652 # number of overall hits
+system.l2c.overall_hits::cpu4 12601 # number of overall hits
+system.l2c.overall_hits::cpu5 12697 # number of overall hits
+system.l2c.overall_hits::cpu6 12574 # number of overall hits
+system.l2c.overall_hits::cpu7 12735 # number of overall hits
+system.l2c.overall_hits::total 101224 # number of overall hits
+system.l2c.ReadReq_misses::cpu0 745 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1 743 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2 781 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3 728 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu4 729 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu5 753 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu6 747 # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu7 720 # number of ReadReq misses
+system.l2c.ReadReq_misses::total 5946 # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0 1905 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1 1885 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2 1879 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3 1905 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu4 1913 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu5 1875 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu6 1933 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu7 1894 # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total 15189 # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0 4304 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1 4329 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2 4371 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3 4347 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu4 4382 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu5 4378 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu6 4299 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu7 4310 # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total 34720 # number of ReadExReq misses
+system.l2c.demand_misses::cpu0 5049 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1 5072 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2 5152 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3 5075 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu4 5111 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu5 5131 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu6 5046 # number of demand (read+write) misses
+system.l2c.demand_misses::cpu7 5030 # number of demand (read+write) misses
+system.l2c.demand_misses::total 40666 # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0 5049 # number of overall misses
+system.l2c.overall_misses::cpu1 5072 # number of overall misses
+system.l2c.overall_misses::cpu2 5152 # number of overall misses
+system.l2c.overall_misses::cpu3 5075 # number of overall misses
+system.l2c.overall_misses::cpu4 5111 # number of overall misses
+system.l2c.overall_misses::cpu5 5131 # number of overall misses
+system.l2c.overall_misses::cpu6 5046 # number of overall misses
+system.l2c.overall_misses::cpu7 5030 # number of overall misses
+system.l2c.overall_misses::total 40666 # number of overall misses
+system.l2c.ReadReq_miss_latency::cpu0 43593500 # number of ReadReq miss cycles
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+system.l2c.UpgradeReq_mshr_miss_rate::cpu0 0.852349 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu1 0.849346 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu2 0.832152 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu3 0.839506 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu4 0.842731 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu5 0.838176 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu6 0.859111 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::cpu7 0.839167 # mshr miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_mshr_miss_rate::total 0.844042 # mshr miss rate for UpgradeReq accesses
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+system.l2c.overall_mshr_miss_rate::cpu0 0.285286 # mshr miss rate for overall accesses
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+system.l2c.overall_mshr_miss_rate::total 0.286384 # mshr miss rate for overall accesses
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu2 46537.275064 # average ReadReq mshr miss latency
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+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0 40699.475066 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1 40772.172066 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2 40678.818520 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3 40777.310924 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu4 40670.151594 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu5 40691.733333 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu6 40768.753233 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu7 40722.016895 # average UpgradeReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0 41295.396419 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1 41272.002772 # average ReadExReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3 41276.972625 # average ReadExReq mshr miss latency
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+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu5 41386.249429 # average ReadExReq mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu0 42047.987309 # average overall mshr miss latency
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+system.l2c.overall_avg_mshr_miss_latency::cpu3 42111.571062 # average overall mshr miss latency
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+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu4 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu5 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu6 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
+system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu3 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu4 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu5 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu6 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
+system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
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+system.l2c.overall_avg_mshr_uncacheable_latency::cpu2 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu3 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu4 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu5 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
+system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
+system.funcbus.throughput 0 # Throughput (bytes/s)
+system.funcbus.data_through_bus 0 # Total data (bytes)
+system.toL2Bus.snoop_filter.tot_requests 548567 # Total number of requests made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_requests 252509 # Number of requests hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_requests 294010 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
+system.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
+system.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
+system.toL2Bus.throughput 22759385654 # Throughput (bytes/s)
+system.toL2Bus.trans_dist::ReadReq 368934 # Transaction distribution
+system.toL2Bus.trans_dist::ReadResp 368931 # Transaction distribution
+system.toL2Bus.trans_dist::WriteReq 42843 # Transaction distribution
+system.toL2Bus.trans_dist::WriteResp 42841 # Transaction distribution
+system.toL2Bus.trans_dist::Writeback 74514 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeReq 28540 # Transaction distribution
+system.toL2Bus.trans_dist::UpgradeResp 28540 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExReq 155707 # Transaction distribution
+system.toL2Bus.trans_dist::ReadExResp 155704 # Transaction distribution
+system.toL2Bus.pkt_count_system.cpu0.l1c.mem_side::system.l2c.cpu_side 118962 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu1.l1c.mem_side::system.l2c.cpu_side 119173 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu2.l1c.mem_side::system.l2c.cpu_side 119464 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu3.l1c.mem_side::system.l2c.cpu_side 119154 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu4.l1c.mem_side::system.l2c.cpu_side 118978 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu5.l1c.mem_side::system.l2c.cpu_side 119360 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu6.l1c.mem_side::system.l2c.cpu_side 119013 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count_system.cpu7.l1c.mem_side::system.l2c.cpu_side 118881 # Packet count per connected master and slave (bytes)
+system.toL2Bus.pkt_count::total 952985 # Packet count per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu0.l1c.mem_side::system.l2c.cpu_side 1734762 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu1.l1c.mem_side::system.l2c.cpu_side 1749843 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu2.l1c.mem_side::system.l2c.cpu_side 1754305 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu3.l1c.mem_side::system.l2c.cpu_side 1751569 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu4.l1c.mem_side::system.l2c.cpu_side 1739334 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu5.l1c.mem_side::system.l2c.cpu_side 1759819 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu6.l1c.mem_side::system.l2c.cpu_side 1742411 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size_system.cpu7.l1c.mem_side::system.l2c.cpu_side 1740191 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.tot_pkt_size::total 13972234 # Cumulative packet size per connected master and slave (bytes)
+system.toL2Bus.data_through_bus 13972234 # Total data (bytes)
+system.toL2Bus.snoop_data_through_bus 19393344 # Total snoop data (bytes)
+system.toL2Bus.snoops_through_bus 313569 # Total snoops (count)
+system.toL2Bus.snoop_fanout::samples 548567 # Request fanout histogram
+system.toL2Bus.snoop_fanout::mean 1.700997 # Request fanout histogram
+system.toL2Bus.snoop_fanout::stdev 1.184770 # Request fanout histogram
+system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::0 51420 9.37% 9.37% # Request fanout histogram
+system.toL2Bus.snoop_fanout::1 243442 44.38% 53.75% # Request fanout histogram
+system.toL2Bus.snoop_fanout::2 138727 25.29% 79.04% # Request fanout histogram
+system.toL2Bus.snoop_fanout::3 68606 12.51% 91.55% # Request fanout histogram
+system.toL2Bus.snoop_fanout::4 30441 5.55% 97.10% # Request fanout histogram
+system.toL2Bus.snoop_fanout::5 11622 2.12% 99.21% # Request fanout histogram
+system.toL2Bus.snoop_fanout::6 3640 0.66% 99.88% # Request fanout histogram
+system.toL2Bus.snoop_fanout::7 669 0.12% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
+system.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
+system.toL2Bus.snoop_fanout::max_value 7 # Request fanout histogram
+system.toL2Bus.snoop_fanout::total 548567 # Request fanout histogram
+system.toL2Bus.reqLayer0.occupancy 1466016000 # Layer occupancy (ticks)
+system.toL2Bus.reqLayer0.utilization 100.0 # Layer utilization (%)
+system.toL2Bus.respLayer0.occupancy 156116317 # Layer occupancy (ticks)
+system.toL2Bus.respLayer0.utilization 10.6 # Layer utilization (%)
+system.toL2Bus.respLayer1.occupancy 156768205 # Layer occupancy (ticks)
+system.toL2Bus.respLayer1.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer2.occupancy 156913339 # Layer occupancy (ticks)
+system.toL2Bus.respLayer2.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer3.occupancy 156965244 # Layer occupancy (ticks)
+system.toL2Bus.respLayer3.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer4.occupancy 156103724 # Layer occupancy (ticks)
+system.toL2Bus.respLayer4.utilization 10.6 # Layer utilization (%)
+system.toL2Bus.respLayer5.occupancy 156986709 # Layer occupancy (ticks)
+system.toL2Bus.respLayer5.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer6.occupancy 156696078 # Layer occupancy (ticks)
+system.toL2Bus.respLayer6.utilization 10.7 # Layer utilization (%)
+system.toL2Bus.respLayer7.occupancy 156271715 # Layer occupancy (ticks)
+system.toL2Bus.respLayer7.utilization 10.7 # Layer utilization (%)
+system.cpu0.num_reads 99418 # number of read accesses completed
+system.cpu0.num_writes 53245 # number of write accesses completed
+system.cpu0.num_copies 0 # number of copy accesses completed
+system.cpu0.l1c.tags.replacements 22099 # number of replacements
+system.cpu0.l1c.tags.tagsinuse 397.065512 # Cycle average of tags in use
+system.cpu0.l1c.tags.total_refs 13209 # Total number of references to valid blocks.
+system.cpu0.l1c.tags.sampled_refs 22488 # Sample count of references to valid blocks.
+system.cpu0.l1c.tags.avg_refs 0.587380 # Average number of references to valid blocks.
+system.cpu0.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
+system.cpu0.l1c.tags.occ_blocks::cpu0 397.065512 # Average occupied blocks per requestor
+system.cpu0.l1c.tags.occ_percent::cpu0 0.775519 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_percent::total 0.775519 # Average percentage of cache occupancy
+system.cpu0.l1c.tags.occ_task_id_blocks::1024 389 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::0 259 # Occupied blocks per task id
+system.cpu0.l1c.tags.age_task_id_blocks_1024::1 130 # Occupied blocks per task id
+system.cpu0.l1c.tags.occ_task_id_percent::1024 0.759766 # Percentage of cache occupancy per task id
+system.cpu0.l1c.tags.tag_accesses 330123 # Number of tag accesses
+system.cpu0.l1c.tags.data_accesses 330123 # Number of data accesses
+system.cpu0.l1c.ReadReq_hits::cpu0 8700 # number of ReadReq hits
+system.cpu0.l1c.ReadReq_hits::total 8700 # number of ReadReq hits
+system.cpu0.l1c.WriteReq_hits::cpu0 1042 # number of WriteReq hits
+system.cpu0.l1c.WriteReq_hits::total 1042 # number of WriteReq hits
+system.cpu0.l1c.demand_hits::cpu0 9742 # number of demand (read+write) hits
+system.cpu0.l1c.demand_hits::total 9742 # number of demand (read+write) hits
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+system.cpu0.l1c.overall_hits::total 9742 # number of overall hits
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+system.cpu0.l1c.ReadReq_misses::total 35979 # number of ReadReq misses
+system.cpu0.l1c.WriteReq_misses::cpu0 22956 # number of WriteReq misses
+system.cpu0.l1c.WriteReq_misses::total 22956 # number of WriteReq misses
+system.cpu0.l1c.demand_misses::cpu0 58935 # number of demand (read+write) misses
+system.cpu0.l1c.demand_misses::total 58935 # number of demand (read+write) misses
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+system.cpu0.l1c.overall_misses::total 58935 # number of overall misses
+system.cpu0.l1c.ReadReq_miss_latency::cpu0 2431275055 # number of ReadReq miss cycles
+system.cpu0.l1c.ReadReq_miss_latency::total 2431275055 # number of ReadReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::cpu0 1798190271 # number of WriteReq miss cycles
+system.cpu0.l1c.WriteReq_miss_latency::total 1798190271 # number of WriteReq miss cycles
+system.cpu0.l1c.demand_miss_latency::cpu0 4229465326 # number of demand (read+write) miss cycles
+system.cpu0.l1c.demand_miss_latency::total 4229465326 # number of demand (read+write) miss cycles
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+system.cpu0.l1c.overall_miss_latency::total 4229465326 # number of overall miss cycles
+system.cpu0.l1c.ReadReq_accesses::cpu0 44679 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.ReadReq_accesses::total 44679 # number of ReadReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::cpu0 23998 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.WriteReq_accesses::total 23998 # number of WriteReq accesses(hits+misses)
+system.cpu0.l1c.demand_accesses::cpu0 68677 # number of demand (read+write) accesses
+system.cpu0.l1c.demand_accesses::total 68677 # number of demand (read+write) accesses
+system.cpu0.l1c.overall_accesses::cpu0 68677 # number of overall (read+write) accesses
+system.cpu0.l1c.overall_accesses::total 68677 # number of overall (read+write) accesses
+system.cpu0.l1c.ReadReq_miss_rate::cpu0 0.805278 # miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_miss_rate::total 0.805278 # miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::cpu0 0.956580 # miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_miss_rate::total 0.956580 # miss rate for WriteReq accesses
+system.cpu0.l1c.demand_miss_rate::cpu0 0.858148 # miss rate for demand accesses
+system.cpu0.l1c.demand_miss_rate::total 0.858148 # miss rate for demand accesses
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+system.cpu0.l1c.overall_miss_rate::total 0.858148 # miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_miss_latency::cpu0 67574.836849 # average ReadReq miss latency
+system.cpu0.l1c.ReadReq_avg_miss_latency::total 67574.836849 # average ReadReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::cpu0 78332.038291 # average WriteReq miss latency
+system.cpu0.l1c.WriteReq_avg_miss_latency::total 78332.038291 # average WriteReq miss latency
+system.cpu0.l1c.demand_avg_miss_latency::cpu0 71764.916026 # average overall miss latency
+system.cpu0.l1c.demand_avg_miss_latency::total 71764.916026 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::cpu0 71764.916026 # average overall miss latency
+system.cpu0.l1c.overall_avg_miss_latency::total 71764.916026 # average overall miss latency
+system.cpu0.l1c.blocked_cycles::no_mshrs 2152877 # number of cycles access was blocked
+system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_mshrs 58943 # number of cycles access was blocked
+system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_mshrs 36.524727 # average number of cycles each access was blocked
+system.cpu0.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu0.l1c.fast_writes 0 # number of fast writes performed
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+system.cpu0.l1c.writebacks::writebacks 9551 # number of writebacks
+system.cpu0.l1c.writebacks::total 9551 # number of writebacks
+system.cpu0.l1c.ReadReq_mshr_misses::cpu0 35979 # number of ReadReq MSHR misses
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+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::cpu0 1091154570 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_uncacheable_latency::total 1091154570 # number of ReadReq MSHR uncacheable cycles
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+system.cpu0.l1c.overall_mshr_uncacheable_latency::cpu0 5132684213 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.overall_mshr_uncacheable_latency::total 5132684213 # number of overall MSHR uncacheable cycles
+system.cpu0.l1c.ReadReq_mshr_miss_rate::cpu0 0.805278 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.ReadReq_mshr_miss_rate::total 0.805278 # mshr miss rate for ReadReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::cpu0 0.956580 # mshr miss rate for WriteReq accesses
+system.cpu0.l1c.WriteReq_mshr_miss_rate::total 0.956580 # mshr miss rate for WriteReq accesses
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+system.cpu0.l1c.demand_mshr_miss_rate::total 0.858148 # mshr miss rate for demand accesses
+system.cpu0.l1c.overall_mshr_miss_rate::cpu0 0.858148 # mshr miss rate for overall accesses
+system.cpu0.l1c.overall_mshr_miss_rate::total 0.858148 # mshr miss rate for overall accesses
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::cpu0 65466.173240 # average ReadReq mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_miss_latency::total 65466.173240 # average ReadReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::cpu0 76238.715848 # average WriteReq mshr miss latency
+system.cpu0.l1c.WriteReq_avg_mshr_miss_latency::total 76238.715848 # average WriteReq mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency
+system.cpu0.l1c.demand_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::cpu0 69662.228014 # average overall mshr miss latency
+system.cpu0.l1c.overall_avg_mshr_miss_latency::total 69662.228014 # average overall mshr miss latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu0 inf # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu0 inf # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::cpu0 inf # average overall mshr uncacheable latency
+system.cpu0.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
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+system.cpu1.num_writes 53422 # number of write accesses completed
+system.cpu1.num_copies 0 # number of copy accesses completed
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+system.cpu1.l1c.tags.tagsinuse 398.933743 # Cycle average of tags in use
+system.cpu1.l1c.tags.total_refs 13300 # Total number of references to valid blocks.
+system.cpu1.l1c.tags.sampled_refs 22873 # Sample count of references to valid blocks.
+system.cpu1.l1c.tags.avg_refs 0.581472 # Average number of references to valid blocks.
+system.cpu1.l1c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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+system.cpu1.l1c.tags.occ_percent::cpu1 0.779167 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_percent::total 0.779167 # Average percentage of cache occupancy
+system.cpu1.l1c.tags.occ_task_id_blocks::1024 392 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::0 265 # Occupied blocks per task id
+system.cpu1.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
+system.cpu1.l1c.tags.occ_task_id_percent::1024 0.765625 # Percentage of cache occupancy per task id
+system.cpu1.l1c.tags.tag_accesses 331866 # Number of tag accesses
+system.cpu1.l1c.tags.data_accesses 331866 # Number of data accesses
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+system.cpu1.l1c.ReadReq_hits::total 8705 # number of ReadReq hits
+system.cpu1.l1c.WriteReq_hits::cpu1 1116 # number of WriteReq hits
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+system.cpu1.l1c.ReadReq_misses::total 36262 # number of ReadReq misses
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+system.cpu1.l1c.WriteReq_misses::total 22965 # number of WriteReq misses
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+system.cpu1.l1c.ReadReq_miss_latency::total 2445520804 # number of ReadReq miss cycles
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+system.cpu1.l1c.overall_miss_latency::total 4245633844 # number of overall miss cycles
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+system.cpu1.l1c.ReadReq_accesses::total 44967 # number of ReadReq accesses(hits+misses)
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+system.cpu1.l1c.WriteReq_accesses::total 24081 # number of WriteReq accesses(hits+misses)
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+system.cpu1.l1c.demand_accesses::total 69048 # number of demand (read+write) accesses
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+system.cpu1.l1c.overall_accesses::total 69048 # number of overall (read+write) accesses
+system.cpu1.l1c.ReadReq_miss_rate::cpu1 0.806414 # miss rate for ReadReq accesses
+system.cpu1.l1c.ReadReq_miss_rate::total 0.806414 # miss rate for ReadReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::cpu1 0.953656 # miss rate for WriteReq accesses
+system.cpu1.l1c.WriteReq_miss_rate::total 0.953656 # miss rate for WriteReq accesses
+system.cpu1.l1c.demand_miss_rate::cpu1 0.857766 # miss rate for demand accesses
+system.cpu1.l1c.demand_miss_rate::total 0.857766 # miss rate for demand accesses
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+system.cpu1.l1c.overall_miss_rate::total 0.857766 # miss rate for overall accesses
+system.cpu1.l1c.ReadReq_avg_miss_latency::cpu1 67440.317798 # average ReadReq miss latency
+system.cpu1.l1c.ReadReq_avg_miss_latency::total 67440.317798 # average ReadReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::cpu1 78385.065970 # average WriteReq miss latency
+system.cpu1.l1c.WriteReq_avg_miss_latency::total 78385.065970 # average WriteReq miss latency
+system.cpu1.l1c.demand_avg_miss_latency::cpu1 71684.094146 # average overall miss latency
+system.cpu1.l1c.demand_avg_miss_latency::total 71684.094146 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::cpu1 71684.094146 # average overall miss latency
+system.cpu1.l1c.overall_avg_miss_latency::total 71684.094146 # average overall miss latency
+system.cpu1.l1c.blocked_cycles::no_mshrs 2169051 # number of cycles access was blocked
+system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_mshrs 59314 # number of cycles access was blocked
+system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_mshrs 36.568955 # average number of cycles each access was blocked
+system.cpu1.l1c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
+system.cpu1.l1c.fast_writes 0 # number of fast writes performed
+system.cpu1.l1c.cache_copies 0 # number of cache copies performed
+system.cpu1.l1c.writebacks::writebacks 9774 # number of writebacks
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+system.cpu3.l1c.ReadReq_miss_rate::total 0.806692 # miss rate for ReadReq accesses
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+system.cpu3.l1c.overall_avg_miss_latency::cpu3 71666.662934 # average overall miss latency
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+system.cpu4.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu5.l1c.tags.occ_task_id_percent::1024 0.794922 # Percentage of cache occupancy per task id
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+system.cpu5.l1c.tags.data_accesses 332464 # Number of data accesses
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+system.cpu5.l1c.ReadReq_miss_rate::total 0.806229 # miss rate for ReadReq accesses
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+system.cpu5.l1c.WriteReq_miss_rate::total 0.954907 # miss rate for WriteReq accesses
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+system.cpu5.l1c.ReadReq_avg_miss_latency::total 67443.699171 # average ReadReq miss latency
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+system.cpu5.l1c.overall_avg_miss_latency::cpu5 71728.946159 # average overall miss latency
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+system.cpu5.l1c.blocked::no_mshrs 59485 # number of cycles access was blocked
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+system.cpu5.l1c.writebacks::total 9794 # number of writebacks
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+system.cpu6.l1c.overall_avg_miss_latency::cpu6 71748.465757 # average overall miss latency
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+system.cpu6.l1c.overall_avg_mshr_miss_latency::cpu6 69642.316381 # average overall mshr miss latency
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+system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::cpu6 inf # average overall mshr uncacheable latency
+system.cpu6.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
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+system.cpu7.num_writes 53734 # number of write accesses completed
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+system.cpu7.l1c.tags.age_task_id_blocks_1024::1 127 # Occupied blocks per task id
+system.cpu7.l1c.tags.occ_task_id_percent::1024 0.757812 # Percentage of cache occupancy per task id
+system.cpu7.l1c.tags.tag_accesses 330932 # Number of tag accesses
+system.cpu7.l1c.tags.data_accesses 330932 # Number of data accesses
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+system.cpu7.l1c.ReadReq_hits::total 8693 # number of ReadReq hits
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+system.cpu7.l1c.ReadReq_miss_latency::total 2444006416 # number of ReadReq miss cycles
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+system.cpu7.l1c.ReadReq_miss_rate::total 0.805916 # miss rate for ReadReq accesses
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+system.cpu7.l1c.WriteReq_miss_rate::total 0.952068 # miss rate for WriteReq accesses
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+system.cpu7.l1c.overall_miss_rate::total 0.857012 # miss rate for overall accesses
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+system.cpu7.l1c.ReadReq_avg_miss_latency::total 67706.635344 # average ReadReq miss latency
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+system.cpu7.l1c.overall_avg_miss_latency::cpu7 71931.505668 # average overall miss latency
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+system.cpu7.l1c.writebacks::total 9569 # number of writebacks
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+system.cpu7.l1c.WriteReq_mshr_misses::total 22922 # number of WriteReq MSHR misses
+system.cpu7.l1c.demand_mshr_misses::cpu7 59019 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.demand_mshr_misses::total 59019 # number of demand (read+write) MSHR misses
+system.cpu7.l1c.overall_mshr_misses::cpu7 59019 # number of overall MSHR misses
+system.cpu7.l1c.overall_mshr_misses::total 59019 # number of overall MSHR misses
+system.cpu7.l1c.ReadReq_mshr_miss_latency::cpu7 2367752098 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_miss_latency::total 2367752098 # number of ReadReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::cpu7 1753332745 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.WriteReq_mshr_miss_latency::total 1753332745 # number of WriteReq MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::cpu7 4121084843 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.demand_mshr_miss_latency::total 4121084843 # number of demand (read+write) MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::cpu7 4121084843 # number of overall MSHR miss cycles
+system.cpu7.l1c.overall_mshr_miss_latency::total 4121084843 # number of overall MSHR miss cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::cpu7 1099641500 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_uncacheable_latency::total 1099641500 # number of ReadReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::cpu7 3936158285 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.WriteReq_mshr_uncacheable_latency::total 3936158285 # number of WriteReq MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::cpu7 5035799785 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.overall_mshr_uncacheable_latency::total 5035799785 # number of overall MSHR uncacheable cycles
+system.cpu7.l1c.ReadReq_mshr_miss_rate::cpu7 0.805916 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.ReadReq_mshr_miss_rate::total 0.805916 # mshr miss rate for ReadReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::cpu7 0.952068 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.WriteReq_mshr_miss_rate::total 0.952068 # mshr miss rate for WriteReq accesses
+system.cpu7.l1c.demand_mshr_miss_rate::cpu7 0.857012 # mshr miss rate for demand accesses
+system.cpu7.l1c.demand_mshr_miss_rate::total 0.857012 # mshr miss rate for demand accesses
+system.cpu7.l1c.overall_mshr_miss_rate::cpu7 0.857012 # mshr miss rate for overall accesses
+system.cpu7.l1c.overall_mshr_miss_rate::total 0.857012 # mshr miss rate for overall accesses
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::cpu7 65594.151813 # average ReadReq mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_miss_latency::total 65594.151813 # average ReadReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::cpu7 76491.263633 # average WriteReq mshr miss latency
+system.cpu7.l1c.WriteReq_avg_mshr_miss_latency::total 76491.263633 # average WriteReq mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::cpu7 69826.409173 # average overall mshr miss latency
+system.cpu7.l1c.demand_avg_mshr_miss_latency::total 69826.409173 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::cpu7 69826.409173 # average overall mshr miss latency
+system.cpu7.l1c.overall_avg_mshr_miss_latency::total 69826.409173 # average overall mshr miss latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::cpu7 inf # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::cpu7 inf # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::cpu7 inf # average overall mshr uncacheable latency
+system.cpu7.l1c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
+system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate
+
+---------- End Simulation Statistics ----------