diff options
Diffstat (limited to 'tests')
29 files changed, 38761 insertions, 9 deletions
diff --git a/tests/SConscript b/tests/SConscript index e9c9a6432..886b7fe59 100644 --- a/tests/SConscript +++ b/tests/SConscript @@ -348,20 +348,26 @@ if env['TARGET_ISA'] == 'arm': 'realview64-switcheroo-timing', 'realview64-switcheroo-o3', 'realview64-switcheroo-full'] -if env['TARGET_ISA'] == 'x86': +if env['TARGET_ISA'] == 'x86' and not env['BUILD_GPU']: configs += ['pc-simple-atomic', 'pc-simple-timing', 'pc-o3-timing', 'pc-switcheroo-full'] -configs += ['simple-atomic', 'simple-atomic-mp', - 'simple-timing', 'simple-timing-mp', - 'minor-timing', 'minor-timing-mp', - 'o3-timing', 'o3-timing-mt', 'o3-timing-mp', - 'rubytest', 'memtest', 'memtest-filter', - 'tgen-simple-mem', 'tgen-dram-ctrl'] - -configs += ['learning-gem5-p1-simple', 'learning-gem5-p1-two-level'] +if env['TARGET_ISA'] == 'x86' and env['BUILD_GPU'] and \ + env['TARGET_GPU_ISA'] == 'hsail': + configs += ['gpu'] + if env['PROTOCOL'] == 'GPU_RfO': + configs += ['gpu-randomtest'] +else: + configs += ['simple-atomic', 'simple-atomic-mp', + 'simple-timing', 'simple-timing-mp', + 'minor-timing', 'minor-timing-mp', + 'o3-timing', 'o3-timing-mt', 'o3-timing-mp', + 'rubytest', 'memtest', 'memtest-filter', + 'tgen-simple-mem', 'tgen-dram-ctrl'] + + configs += ['learning-gem5-p1-simple', 'learning-gem5-p1-two-level'] if env['PROTOCOL'] != 'None': if env['PROTOCOL'] == 'MI_example': diff --git a/tests/configs/gpu-randomtest-ruby.py b/tests/configs/gpu-randomtest-ruby.py new file mode 100644 index 000000000..92e300394 --- /dev/null +++ b/tests/configs/gpu-randomtest-ruby.py @@ -0,0 +1,151 @@ +# +# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. +# All rights reserved. +# +# For use for simulation and test purposes only +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors +# may be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# Author: Brad Beckmann +# + +import m5 +from m5.objects import * +from m5.defines import buildEnv +from m5.util import addToPath +import os, optparse, sys + +# Get paths we might need. It's expected this file is in m5/configs/example. +config_path = os.path.dirname(os.path.abspath(__file__)) +config_root = os.path.dirname(config_path) +m5_root = os.path.dirname(config_root) +addToPath(config_root+'/configs/common') +addToPath(config_root+'/configs/ruby') +addToPath(config_root+'/configs/topologies') + +import Ruby +import Options + +parser = optparse.OptionParser() +Options.addCommonOptions(parser) + +# add the gpu specific options expected by the the gpu and gpu_RfO +parser.add_option("-u", "--num-compute-units", type="int", default=8, + help="number of compute units in the GPU") +parser.add_option("--numCPs", type="int", default=0, + help="Number of GPU Command Processors (CP)") +parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \ + "per CU") +parser.add_option("--wf-size", type="int", default=64, + help="Wavefront size(in workitems)") +parser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " \ + "WF slots per SIMD") + +# Add the ruby specific and protocol specific options +Ruby.define_options(parser) + +(options, args) = parser.parse_args() + +# +# Set the default cache size and associativity to be very small to encourage +# races between requests and writebacks. +# +options.l1d_size="256B" +options.l1i_size="256B" +options.l2_size="512B" +options.l3_size="1kB" +options.l1d_assoc=2 +options.l1i_assoc=2 +options.l2_assoc=2 +options.l3_assoc=2 +options.num_compute_units=8 +options.num_sqc=2 + +# Check to for the GPU_RfO protocol. Other GPU protocols are non-SC and will +# not work with the Ruby random tester. +assert(buildEnv['PROTOCOL'] == 'GPU_RfO') + +# +# create the tester and system, including ruby +# +tester = RubyTester(check_flush = False, checks_to_complete = 100, + wakeup_frequency = 10, num_cpus = options.num_cpus) + +# We set the testers as cpu for ruby to find the correct clock domains +# for the L1 Objects. +system = System(cpu = tester) + +# Dummy voltage domain for all our clock domains +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) +system.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = system.voltage_domain) + +system.mem_ranges = AddrRange('256MB') + +Ruby.create_system(options, False, system) + +# Create a separate clock domain for Ruby +system.ruby.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = system.voltage_domain) + +tester.num_cpus = len(system.ruby._cpu_ports) + +# +# The tester is most effective when randomization is turned on and +# artifical delay is randomly inserted on messages +# +system.ruby.randomization = True + +for ruby_port in system.ruby._cpu_ports: + # + # Tie the ruby tester ports to the ruby cpu read and write ports + # + if ruby_port.support_data_reqs and ruby_port.support_inst_reqs: + tester.cpuInstDataPort = ruby_port.slave + elif ruby_port.support_data_reqs: + tester.cpuDataPort = ruby_port.slave + elif ruby_port.support_inst_reqs: + tester.cpuInstPort = ruby_port.slave + + # Do not automatically retry stalled Ruby requests + ruby_port.no_retry_on_stall = True + + # + # Tell the sequencer this is the ruby tester so that it + # copies the subblock back to the checker + # + ruby_port.using_ruby_tester = True + +# ----------------------- +# run simulation +# ----------------------- + +root = Root(full_system = False, system = system ) +root.system.mem_mode = 'timing' + +# Not much point in this being higher than the L1 latency +m5.ticks.setGlobalFrequency('1ns') diff --git a/tests/configs/gpu-ruby.py b/tests/configs/gpu-ruby.py new file mode 100644 index 000000000..632b4dec0 --- /dev/null +++ b/tests/configs/gpu-ruby.py @@ -0,0 +1,353 @@ +# +# Copyright (c) 2015 Advanced Micro Devices, Inc. +# All rights reserved. +# +# For use for simulation and test purposes only +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors +# may be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# Author: Brad Beckmann +# + +import m5 +from m5.objects import * +from m5.defines import buildEnv +from m5.util import addToPath +import os, optparse, sys, math, glob + +# Get paths we might need +config_path = os.path.dirname(os.path.abspath(__file__)) +config_root = os.path.dirname(config_path) +addToPath(config_root+'/configs/common') +addToPath(config_root+'/configs/ruby') +addToPath(config_root+'/configs/topologies') + +import Ruby +import Options +import GPUTLBOptions, GPUTLBConfig + +########################## Script Options ######################## +def setOption(parser, opt_str, value = 1): + # check to make sure the option actually exists + if not parser.has_option(opt_str): + raise Exception("cannot find %s in list of possible options" % opt_str) + + opt = parser.get_option(opt_str) + # set the value + exec("parser.values.%s = %s" % (opt.dest, value)) + +def getOption(parser, opt_str): + # check to make sure the option actually exists + if not parser.has_option(opt_str): + raise Exception("cannot find %s in list of possible options" % opt_str) + + opt = parser.get_option(opt_str) + # get the value + exec("return_value = parser.values.%s" % opt.dest) + return return_value + +def run_test(root): + """gpu test requires a specialized run_test implementation to set up the + mmio space.""" + + # instantiate configuration + m5.instantiate() + + # Now that the system has been constructed, setup the mmio space + root.system.cpu[0].workload[0].map(0x10000000, 0x200000000, 4096) + + # simulate until program terminates + exit_event = m5.simulate(maxtick) + print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() + +parser = optparse.OptionParser() +Options.addCommonOptions(parser) +Options.addSEOptions(parser) + +parser.add_option("-k", "--kernel-files", + help="file(s) containing GPU kernel code (colon separated)") +parser.add_option("-u", "--num-compute-units", type="int", default=2, + help="number of GPU compute units"), +parser.add_option("--numCPs", type="int", default=0, + help="Number of GPU Command Processors (CP)") +parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \ + "per CU") +parser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs" \ + "sharing an SQC (icache, and thus icache TLB)") +parser.add_option("--wf-size", type="int", default=64, + help="Wavefront size(in workitems)") +parser.add_option("--wfs-per-simd", type="int", default=8, help="Number of " \ + "WF slots per SIMD") +parser.add_option("--sp-bypass-path-length", type="int", default=4, \ + help="Number of stages of bypass path in vector ALU for Single "\ + "Precision ops") +parser.add_option("--dp-bypass-path-length", type="int", default=4, \ + help="Number of stages of bypass path in vector ALU for Double "\ + "Precision ops") +parser.add_option("--issue-period", type="int", default=4, \ + help="Number of cycles per vector instruction issue period") +parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \ + help="VGPR to Coalescer (Global Memory) data bus width in bytes") +parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \ + help="Coalescer to VGPR (Global Memory) data bus width in bytes") +parser.add_option("--shr-mem-pipes-per-cu", type="int", default=1, \ + help="Number of Shared Memory pipelines per CU") +parser.add_option("--glb-mem-pipes-per-cu", type="int", default=1, \ + help="Number of Global Memory pipelines per CU") +parser.add_option("--vreg-file-size", type="int", default=2048, + help="number of physical vector registers per SIMD") +parser.add_option("--bw-scalor", type="int", default=0, + help="bandwidth scalor for scalability analysis") +parser.add_option("--CPUClock", type="string", default="2GHz", + help="CPU clock") +parser.add_option("--GPUClock", type="string", default="1GHz", + help="GPU clock") +parser.add_option("--cpu-voltage", action="store", type="string", + default='1.0V', + help = """CPU voltage domain""") +parser.add_option("--gpu-voltage", action="store", type="string", + default='1.0V', + help = """CPU voltage domain""") +parser.add_option("--CUExecPolicy", type="string", default="OLDEST-FIRST", + help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)") +parser.add_option("--xact-cas-mode", action="store_true", + help="enable load_compare mode (transactional CAS)") +parser.add_option("--SegFaultDebug",action="store_true", + help="checks for GPU seg fault before TLB access") +parser.add_option("--LocalMemBarrier",action="store_true", + help="Barrier does not wait for writethroughs to complete") +parser.add_option("--countPages", action="store_true", + help="Count Page Accesses and output in per-CU output files") +parser.add_option("--TLB-prefetch", type="int", help = "prefetch depth for"\ + "TLBs") +parser.add_option("--pf-type", type="string", help="type of prefetch: "\ + "PF_CU, PF_WF, PF_PHASE, PF_STRIDE") +parser.add_option("--pf-stride", type="int", help="set prefetch stride") +parser.add_option("--numLdsBanks", type="int", default=32, + help="number of physical banks per LDS module") +parser.add_option("--ldsBankConflictPenalty", type="int", default=1, + help="number of cycles per LDS bank conflict") + +# Add the ruby specific and protocol specific options +Ruby.define_options(parser) + +GPUTLBOptions.tlb_options(parser) + +(options, args) = parser.parse_args() + +# The GPU cache coherence protocols only work with the backing store +setOption(parser, "--access-backing-store") + +# Currently, the sqc (I-Cache of GPU) is shared by +# multiple compute units(CUs). The protocol works just fine +# even if sqc is not shared. Overriding this option here +# so that the user need not explicitly set this (assuming +# sharing sqc is the common usage) +n_cu = options.num_compute_units +num_sqc = int(math.ceil(float(n_cu) / options.cu_per_sqc)) +options.num_sqc = num_sqc # pass this to Ruby + +########################## Creating the GPU system ######################## +# shader is the GPU +shader = Shader(n_wf = options.wfs_per_simd, + clk_domain = SrcClockDomain( + clock = options.GPUClock, + voltage_domain = VoltageDomain( + voltage = options.gpu_voltage)), + timing = True) + +# GPU_RfO(Read For Ownership) implements SC/TSO memory model. +# Other GPU protocols implement release consistency at GPU side. +# So, all GPU protocols other than GPU_RfO should make their writes +# visible to the global memory and should read from global memory +# during kernal boundary. The pipeline initiates(or do not initiate) +# the acquire/release operation depending on this impl_kern_boundary_sync +# flag. This flag=true means pipeline initiates a acquire/release operation +# at kernel boundary. +if buildEnv['PROTOCOL'] == 'GPU_RfO': + shader.impl_kern_boundary_sync = False +else: + shader.impl_kern_boundary_sync = True + +# Switching off per-lane TLB by default +per_lane = False +if options.TLB_config == "perLane": + per_lane = True + +# List of compute units; one GPU can have multiple compute units +compute_units = [] +for i in xrange(n_cu): + compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane, + num_SIMDs = options.simds_per_cu, + wfSize = options.wf_size, + spbypass_pipe_length = \ + options.sp_bypass_path_length, + dpbypass_pipe_length = \ + options.dp_bypass_path_length, + issue_period = options.issue_period, + coalescer_to_vrf_bus_width = \ + options.glbmem_rd_bus_width, + vrf_to_coalescer_bus_width = \ + options.glbmem_wr_bus_width, + num_global_mem_pipes = \ + options.glb_mem_pipes_per_cu, + num_shared_mem_pipes = \ + options.shr_mem_pipes_per_cu, + n_wf = options.wfs_per_simd, + execPolicy = options.CUExecPolicy, + xactCasMode = options.xact_cas_mode, + debugSegFault = options.SegFaultDebug, + functionalTLB = True, + localMemBarrier = options.LocalMemBarrier, + countPages = options.countPages, + localDataStore = \ + LdsState(banks = options.numLdsBanks, + bankConflictPenalty = \ + options.ldsBankConflictPenalty))) + wavefronts = [] + vrfs = [] + for j in xrange(options.simds_per_cu): + for k in xrange(shader.n_wf): + wavefronts.append(Wavefront(simdId = j, wf_slot_id = k)) + vrfs.append(VectorRegisterFile(simd_id=j, + num_regs_per_simd=options.vreg_file_size)) + compute_units[-1].wavefronts = wavefronts + compute_units[-1].vector_register_file = vrfs + if options.TLB_prefetch: + compute_units[-1].prefetch_depth = options.TLB_prefetch + compute_units[-1].prefetch_prev_type = options.pf_type + + # attach the LDS and the CU to the bus (actually a Bridge) + compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave + compute_units[-1].ldsBus.master = compute_units[-1].localDataStore.cuPort + +# Attach compute units to GPU +shader.CUs = compute_units + +# this is a uniprocessor only test, thus the shader is the second index in the +# list of "system.cpus" +options.num_cpus = 1 +shader_idx = 1 +cpu = TimingSimpleCPU(cpu_id=0) + +########################## Creating the GPU dispatcher ######################## +# Dispatcher dispatches work from host CPU to GPU +host_cpu = cpu +dispatcher = GpuDispatcher() + +# Currently does not test for command processors +cpu_list = [cpu] + [shader] + [dispatcher] + +system = System(cpu = cpu_list, + mem_ranges = [AddrRange(options.mem_size)], + mem_mode = 'timing') + +# Dummy voltage domain for all our clock domains +system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) +system.clk_domain = SrcClockDomain(clock = '1GHz', + voltage_domain = system.voltage_domain) + +# Create a seperate clock domain for components that should run at +# CPUs frequency +system.cpu[0].clk_domain = SrcClockDomain(clock = '2GHz', + voltage_domain = \ + system.voltage_domain) + +# configure the TLB hierarchy +GPUTLBConfig.config_tlb_hierarchy(options, system, shader_idx) + +# create Ruby system +system.piobus = IOXBar(width=32, response_latency=0, + frontend_latency=0, forward_latency=0) +Ruby.create_system(options, None, system) + +# Create a separate clock for Ruby +system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, + voltage_domain = system.voltage_domain) + +# create the interrupt controller +cpu.createInterruptController() + +# +# Tie the cpu cache ports to the ruby cpu ports and +# physmem, respectively +# +cpu.connectAllPorts(system.ruby._cpu_ports[0]) +system.ruby._cpu_ports[0].mem_master_port = system.piobus.slave + +# attach CU ports to Ruby +# Because of the peculiarities of the CP core, you may have 1 CPU but 2 +# sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be +# hooked up until after the CP. To make this script generic, figure out +# the index as below, but note that this assumes there is one sequencer +# per compute unit and one sequencer per SQC for the math to work out +# correctly. +gpu_port_idx = len(system.ruby._cpu_ports) \ + - options.num_compute_units - options.num_sqc +gpu_port_idx = gpu_port_idx - options.numCPs * 2 + +wavefront_size = options.wf_size +for i in xrange(n_cu): + # The pipeline issues wavefront_size number of uncoalesced requests + # in one GPU issue cycle. Hence wavefront_size mem ports. + for j in xrange(wavefront_size): + system.cpu[shader_idx].CUs[i].memory_port[j] = \ + system.ruby._cpu_ports[gpu_port_idx].slave[j] + gpu_port_idx += 1 + +for i in xrange(n_cu): + if i > 0 and not i % options.cu_per_sqc: + gpu_port_idx += 1 + system.cpu[shader_idx].CUs[i].sqc_port = \ + system.ruby._cpu_ports[gpu_port_idx].slave +gpu_port_idx = gpu_port_idx + 1 + +assert(options.numCPs == 0) + +# connect dispatcher to the system.piobus +dispatcher.pio = system.piobus.master +dispatcher.dma = system.piobus.slave + +################# Connect the CPU and GPU via GPU Dispatcher ################### +# CPU rings the GPU doorbell to notify a pending task +# using this interface. +# And GPU uses this interface to notify the CPU of task completion +# The communcation happens through emulated driver. + +# Note this implicit setting of the cpu_pointer, shader_pointer and tlb array +# parameters must be after the explicit setting of the System cpu list +shader.cpu_pointer = host_cpu +dispatcher.cpu = host_cpu +dispatcher.shader_pointer = shader + +# ----------------------- +# run simulation +# ----------------------- + +root = Root(full_system = False, system = system) +m5.ticks.setGlobalFrequency('1THz') +root.system.mem_mode = 'timing' diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini new file mode 100644 index 000000000..5486af826 --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/config.ini @@ -0,0 +1,4423 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cp_cntrl0 cpu0 cpu1 cpu2 dir_cntrl0 dispatcher_coalescer dispatcher_tlb dvfs_handler l1_coalescer0 l1_coalescer1 l1_tlb0 l1_tlb1 l2_coalescer l2_tlb l3_coalescer l3_tlb mem_ctrls piobus ruby sqc_cntrl0 sqc_coalescer sqc_tlb sys_port_proxy tcc_cntrl0 tccdir_cntrl0 tcp_cntrl0 tcp_cntrl1 voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrls system.ruby.phys_mem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cp_cntrl0] +type=CorePair_Controller +children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore +L1D0cache=system.cp_cntrl0.L1D0cache +L1D1cache=system.cp_cntrl0.L1D1cache +L1Icache=system.cp_cntrl0.L1Icache +L2cache=system.cp_cntrl0.L2cache +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +issue_latency=15 +l2_hit_latency=18 +mandatoryQueue=system.cp_cntrl0.mandatoryQueue +number_of_TBEs=256 +probeToCore=system.cp_cntrl0.probeToCore +recycle_latency=10 +requestFromCore=system.cp_cntrl0.requestFromCore +responseFromCore=system.cp_cntrl0.responseFromCore +responseToCore=system.cp_cntrl0.responseToCore +ruby_system=system.ruby +send_evictions=true +sequencer=system.cp_cntrl0.sequencer +sequencer1=system.cp_cntrl0.sequencer1 +system=system +transitions_per_cycle=32 +triggerQueue=system.cp_cntrl0.triggerQueue +unblockFromCore=system.cp_cntrl0.unblockFromCore +version=0 + +[system.cp_cntrl0.L1D0cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1D0cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=65536 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.cp_cntrl0.L1D0cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=65536 + +[system.cp_cntrl0.L1D1cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1D1cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=65536 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.cp_cntrl0.L1D1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=65536 + +[system.cp_cntrl0.L1Icache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1Icache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=32768 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.cp_cntrl0.L1Icache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=32768 + +[system.cp_cntrl0.L2cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L2cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=2097152 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.cp_cntrl0.L2cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=2097152 + +[system.cp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.cp_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[3] + +[system.cp_cntrl0.requestFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.cp_cntrl0.responseFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[3] + +[system.cp_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[4] + +[system.cp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=0 +dcache=system.cp_cntrl0.L1D0cache +dcache_hit_latency=2 +deadlock_threshold=500000 +eventq_index=0 +icache=system.cp_cntrl0.L1Icache +icache_hit_latency=2 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave +mem_master_port=system.piobus.slave[0] +slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master + +[system.cp_cntrl0.sequencer1] +type=RubySequencer +clk_domain=system.clk_domain +coreid=1 +dcache=system.cp_cntrl0.L1D1cache +dcache_hit_latency=2 +deadlock_threshold=500000 +eventq_index=0 +icache=system.cp_cntrl0.L1Icache +icache_hit_latency=2 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=1 + +[system.cp_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.cp_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.cpu0] +type=TimingSimpleCPU +children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu0.clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.cp_cntrl0.sequencer.slave[1] +icache_port=system.cp_cntrl0.sequencer.slave[0] + +[system.cpu0.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu0.clk_domain +eventq_index=0 + +[system.cpu0.clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +clk_domain=system.cpu0.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.cp_cntrl0.sequencer.slave[3] + +[system.cpu0.interrupts] +type=X86LocalApic +clk_domain=system.cpu0.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.cp_cntrl0.sequencer.slave[4] +int_slave=system.cp_cntrl0.sequencer.master[1] +pio=system.cp_cntrl0.sequencer.master[0] + +[system.cpu0.isa] +type=X86ISA +eventq_index=0 + +[system.cpu0.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +clk_domain=system.cpu0.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.cp_cntrl0.sequencer.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu0.workload] +type=LiveProcess +cmd=gpu-hello +cwd= +drivers=system.cpu2.cl_driver +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu1] +type=Shader +children=CUs0 CUs1 clk_domain +CUs=system.cpu1.CUs0 system.cpu1.CUs1 +clk_domain=system.cpu1.clk_domain +cpu_pointer=system.cpu0 +eventq_index=0 +globalmem=65536 +impl_kern_boundary_sync=false +n_wf=8 +separate_acquire_release=false +timing=true +translation=false + +[system.cpu1.CUs0] +type=ComputeUnit +children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31 +clk_domain=system.cpu1.clk_domain +coalescer_to_vrf_bus_width=32 +countPages=false +cu_id=0 +debugSegFault=false +dpbypass_pipe_length=4 +eventq_index=0 +execPolicy=OLDEST-FIRST +functionalTLB=true +global_mem_queue_size=256 +issue_period=4 +localDataStore=system.cpu1.CUs0.localDataStore +localMemBarrier=false +local_mem_queue_size=256 +mem_req_latency=9 +mem_resp_latency=9 +n_wf=8 +num_SIMDs=4 +num_global_mem_pipes=1 +num_shared_mem_pipes=1 +perLaneTLB=false +prefetch_depth=0 +prefetch_prev_type=PF_PHASE +prefetch_stride=1 +spbypass_pipe_length=4 +system=system +vector_register_file=system.cpu1.CUs0.vector_register_file0 system.cpu1.CUs0.vector_register_file1 system.cpu1.CUs0.vector_register_file2 system.cpu1.CUs0.vector_register_file3 +vrf_to_coalescer_bus_width=32 +wavefronts=system.cpu1.CUs0.wavefronts00 system.cpu1.CUs0.wavefronts01 system.cpu1.CUs0.wavefronts02 system.cpu1.CUs0.wavefronts03 system.cpu1.CUs0.wavefronts04 system.cpu1.CUs0.wavefronts05 system.cpu1.CUs0.wavefronts06 system.cpu1.CUs0.wavefronts07 system.cpu1.CUs0.wavefronts08 system.cpu1.CUs0.wavefronts09 system.cpu1.CUs0.wavefronts10 system.cpu1.CUs0.wavefronts11 system.cpu1.CUs0.wavefronts12 system.cpu1.CUs0.wavefronts13 system.cpu1.CUs0.wavefronts14 system.cpu1.CUs0.wavefronts15 system.cpu1.CUs0.wavefronts16 system.cpu1.CUs0.wavefronts17 system.cpu1.CUs0.wavefronts18 system.cpu1.CUs0.wavefronts19 system.cpu1.CUs0.wavefronts20 system.cpu1.CUs0.wavefronts21 system.cpu1.CUs0.wavefronts22 system.cpu1.CUs0.wavefronts23 system.cpu1.CUs0.wavefronts24 system.cpu1.CUs0.wavefronts25 system.cpu1.CUs0.wavefronts26 system.cpu1.CUs0.wavefronts27 system.cpu1.CUs0.wavefronts28 system.cpu1.CUs0.wavefronts29 system.cpu1.CUs0.wavefronts30 system.cpu1.CUs0.wavefronts31 +wfSize=64 +xactCasMode=false +ldsPort=system.cpu1.CUs0.ldsBus.slave +memory_port=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl0.coalescer.slave[1] system.tcp_cntrl0.coalescer.slave[2] system.tcp_cntrl0.coalescer.slave[3] system.tcp_cntrl0.coalescer.slave[4] system.tcp_cntrl0.coalescer.slave[5] system.tcp_cntrl0.coalescer.slave[6] system.tcp_cntrl0.coalescer.slave[7] system.tcp_cntrl0.coalescer.slave[8] system.tcp_cntrl0.coalescer.slave[9] system.tcp_cntrl0.coalescer.slave[10] system.tcp_cntrl0.coalescer.slave[11] system.tcp_cntrl0.coalescer.slave[12] system.tcp_cntrl0.coalescer.slave[13] system.tcp_cntrl0.coalescer.slave[14] system.tcp_cntrl0.coalescer.slave[15] system.tcp_cntrl0.coalescer.slave[16] system.tcp_cntrl0.coalescer.slave[17] system.tcp_cntrl0.coalescer.slave[18] system.tcp_cntrl0.coalescer.slave[19] system.tcp_cntrl0.coalescer.slave[20] system.tcp_cntrl0.coalescer.slave[21] system.tcp_cntrl0.coalescer.slave[22] system.tcp_cntrl0.coalescer.slave[23] system.tcp_cntrl0.coalescer.slave[24] system.tcp_cntrl0.coalescer.slave[25] system.tcp_cntrl0.coalescer.slave[26] system.tcp_cntrl0.coalescer.slave[27] system.tcp_cntrl0.coalescer.slave[28] system.tcp_cntrl0.coalescer.slave[29] system.tcp_cntrl0.coalescer.slave[30] system.tcp_cntrl0.coalescer.slave[31] system.tcp_cntrl0.coalescer.slave[32] system.tcp_cntrl0.coalescer.slave[33] system.tcp_cntrl0.coalescer.slave[34] system.tcp_cntrl0.coalescer.slave[35] system.tcp_cntrl0.coalescer.slave[36] system.tcp_cntrl0.coalescer.slave[37] system.tcp_cntrl0.coalescer.slave[38] system.tcp_cntrl0.coalescer.slave[39] system.tcp_cntrl0.coalescer.slave[40] system.tcp_cntrl0.coalescer.slave[41] system.tcp_cntrl0.coalescer.slave[42] system.tcp_cntrl0.coalescer.slave[43] system.tcp_cntrl0.coalescer.slave[44] system.tcp_cntrl0.coalescer.slave[45] system.tcp_cntrl0.coalescer.slave[46] system.tcp_cntrl0.coalescer.slave[47] system.tcp_cntrl0.coalescer.slave[48] system.tcp_cntrl0.coalescer.slave[49] system.tcp_cntrl0.coalescer.slave[50] system.tcp_cntrl0.coalescer.slave[51] system.tcp_cntrl0.coalescer.slave[52] system.tcp_cntrl0.coalescer.slave[53] system.tcp_cntrl0.coalescer.slave[54] system.tcp_cntrl0.coalescer.slave[55] system.tcp_cntrl0.coalescer.slave[56] system.tcp_cntrl0.coalescer.slave[57] system.tcp_cntrl0.coalescer.slave[58] system.tcp_cntrl0.coalescer.slave[59] system.tcp_cntrl0.coalescer.slave[60] system.tcp_cntrl0.coalescer.slave[61] system.tcp_cntrl0.coalescer.slave[62] system.tcp_cntrl0.coalescer.slave[63] +sqc_port=system.sqc_cntrl0.sequencer.slave[0] +sqc_tlb_port=system.sqc_coalescer.slave[0] +translation_port=system.l1_coalescer0.slave[0] + +[system.cpu1.CUs0.ldsBus] +type=Bridge +clk_domain=system.cpu1.clk_domain +delay=0 +eventq_index=0 +ranges=0:18446744073709551615 +req_size=16 +resp_size=16 +master=system.cpu1.CUs0.localDataStore.cuPort +slave=system.cpu1.CUs0.ldsPort + +[system.cpu1.CUs0.localDataStore] +type=LdsState +bankConflictPenalty=1 +banks=32 +clk_domain=system.cpu1.clk_domain +eventq_index=0 +range=0:65535 +size=65536 +cuPort=system.cpu1.CUs0.ldsBus.master + +[system.cpu1.CUs0.vector_register_file0] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=0 + +[system.cpu1.CUs0.vector_register_file1] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=1 + +[system.cpu1.CUs0.vector_register_file2] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=2 + +[system.cpu1.CUs0.vector_register_file3] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=3 + +[system.cpu1.CUs0.wavefronts00] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts01] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts02] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts03] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts04] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts05] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts06] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts07] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts08] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts09] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts10] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts11] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts12] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts13] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts14] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts15] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts16] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts17] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts18] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts19] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts20] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts21] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts22] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts23] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts24] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts25] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts26] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts27] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts28] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts29] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts30] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts31] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=7 + +[system.cpu1.CUs1] +type=ComputeUnit +children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31 +clk_domain=system.cpu1.clk_domain +coalescer_to_vrf_bus_width=32 +countPages=false +cu_id=1 +debugSegFault=false +dpbypass_pipe_length=4 +eventq_index=0 +execPolicy=OLDEST-FIRST +functionalTLB=true +global_mem_queue_size=256 +issue_period=4 +localDataStore=system.cpu1.CUs1.localDataStore +localMemBarrier=false +local_mem_queue_size=256 +mem_req_latency=9 +mem_resp_latency=9 +n_wf=8 +num_SIMDs=4 +num_global_mem_pipes=1 +num_shared_mem_pipes=1 +perLaneTLB=false +prefetch_depth=0 +prefetch_prev_type=PF_PHASE +prefetch_stride=1 +spbypass_pipe_length=4 +system=system +vector_register_file=system.cpu1.CUs1.vector_register_file0 system.cpu1.CUs1.vector_register_file1 system.cpu1.CUs1.vector_register_file2 system.cpu1.CUs1.vector_register_file3 +vrf_to_coalescer_bus_width=32 +wavefronts=system.cpu1.CUs1.wavefronts00 system.cpu1.CUs1.wavefronts01 system.cpu1.CUs1.wavefronts02 system.cpu1.CUs1.wavefronts03 system.cpu1.CUs1.wavefronts04 system.cpu1.CUs1.wavefronts05 system.cpu1.CUs1.wavefronts06 system.cpu1.CUs1.wavefronts07 system.cpu1.CUs1.wavefronts08 system.cpu1.CUs1.wavefronts09 system.cpu1.CUs1.wavefronts10 system.cpu1.CUs1.wavefronts11 system.cpu1.CUs1.wavefronts12 system.cpu1.CUs1.wavefronts13 system.cpu1.CUs1.wavefronts14 system.cpu1.CUs1.wavefronts15 system.cpu1.CUs1.wavefronts16 system.cpu1.CUs1.wavefronts17 system.cpu1.CUs1.wavefronts18 system.cpu1.CUs1.wavefronts19 system.cpu1.CUs1.wavefronts20 system.cpu1.CUs1.wavefronts21 system.cpu1.CUs1.wavefronts22 system.cpu1.CUs1.wavefronts23 system.cpu1.CUs1.wavefronts24 system.cpu1.CUs1.wavefronts25 system.cpu1.CUs1.wavefronts26 system.cpu1.CUs1.wavefronts27 system.cpu1.CUs1.wavefronts28 system.cpu1.CUs1.wavefronts29 system.cpu1.CUs1.wavefronts30 system.cpu1.CUs1.wavefronts31 +wfSize=64 +xactCasMode=false +ldsPort=system.cpu1.CUs1.ldsBus.slave +memory_port=system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[1] system.tcp_cntrl1.coalescer.slave[2] system.tcp_cntrl1.coalescer.slave[3] system.tcp_cntrl1.coalescer.slave[4] system.tcp_cntrl1.coalescer.slave[5] system.tcp_cntrl1.coalescer.slave[6] system.tcp_cntrl1.coalescer.slave[7] system.tcp_cntrl1.coalescer.slave[8] system.tcp_cntrl1.coalescer.slave[9] system.tcp_cntrl1.coalescer.slave[10] system.tcp_cntrl1.coalescer.slave[11] system.tcp_cntrl1.coalescer.slave[12] system.tcp_cntrl1.coalescer.slave[13] system.tcp_cntrl1.coalescer.slave[14] system.tcp_cntrl1.coalescer.slave[15] system.tcp_cntrl1.coalescer.slave[16] system.tcp_cntrl1.coalescer.slave[17] system.tcp_cntrl1.coalescer.slave[18] system.tcp_cntrl1.coalescer.slave[19] system.tcp_cntrl1.coalescer.slave[20] system.tcp_cntrl1.coalescer.slave[21] system.tcp_cntrl1.coalescer.slave[22] system.tcp_cntrl1.coalescer.slave[23] system.tcp_cntrl1.coalescer.slave[24] system.tcp_cntrl1.coalescer.slave[25] system.tcp_cntrl1.coalescer.slave[26] system.tcp_cntrl1.coalescer.slave[27] system.tcp_cntrl1.coalescer.slave[28] system.tcp_cntrl1.coalescer.slave[29] system.tcp_cntrl1.coalescer.slave[30] system.tcp_cntrl1.coalescer.slave[31] system.tcp_cntrl1.coalescer.slave[32] system.tcp_cntrl1.coalescer.slave[33] system.tcp_cntrl1.coalescer.slave[34] system.tcp_cntrl1.coalescer.slave[35] system.tcp_cntrl1.coalescer.slave[36] system.tcp_cntrl1.coalescer.slave[37] system.tcp_cntrl1.coalescer.slave[38] system.tcp_cntrl1.coalescer.slave[39] system.tcp_cntrl1.coalescer.slave[40] system.tcp_cntrl1.coalescer.slave[41] system.tcp_cntrl1.coalescer.slave[42] system.tcp_cntrl1.coalescer.slave[43] system.tcp_cntrl1.coalescer.slave[44] system.tcp_cntrl1.coalescer.slave[45] system.tcp_cntrl1.coalescer.slave[46] system.tcp_cntrl1.coalescer.slave[47] system.tcp_cntrl1.coalescer.slave[48] system.tcp_cntrl1.coalescer.slave[49] system.tcp_cntrl1.coalescer.slave[50] system.tcp_cntrl1.coalescer.slave[51] system.tcp_cntrl1.coalescer.slave[52] system.tcp_cntrl1.coalescer.slave[53] system.tcp_cntrl1.coalescer.slave[54] system.tcp_cntrl1.coalescer.slave[55] system.tcp_cntrl1.coalescer.slave[56] system.tcp_cntrl1.coalescer.slave[57] system.tcp_cntrl1.coalescer.slave[58] system.tcp_cntrl1.coalescer.slave[59] system.tcp_cntrl1.coalescer.slave[60] system.tcp_cntrl1.coalescer.slave[61] system.tcp_cntrl1.coalescer.slave[62] system.tcp_cntrl1.coalescer.slave[63] +sqc_port=system.sqc_cntrl0.sequencer.slave[1] +sqc_tlb_port=system.sqc_coalescer.slave[1] +translation_port=system.l1_coalescer1.slave[0] + +[system.cpu1.CUs1.ldsBus] +type=Bridge +clk_domain=system.cpu1.clk_domain +delay=0 +eventq_index=0 +ranges=0:18446744073709551615 +req_size=16 +resp_size=16 +master=system.cpu1.CUs1.localDataStore.cuPort +slave=system.cpu1.CUs1.ldsPort + +[system.cpu1.CUs1.localDataStore] +type=LdsState +bankConflictPenalty=1 +banks=32 +clk_domain=system.cpu1.clk_domain +eventq_index=0 +range=0:65535 +size=65536 +cuPort=system.cpu1.CUs1.ldsBus.master + +[system.cpu1.CUs1.vector_register_file0] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=0 + +[system.cpu1.CUs1.vector_register_file1] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=1 + +[system.cpu1.CUs1.vector_register_file2] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=2 + +[system.cpu1.CUs1.vector_register_file3] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=3 + +[system.cpu1.CUs1.wavefronts00] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts01] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts02] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts03] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts04] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts05] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts06] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts07] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts08] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts09] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts10] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts11] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts12] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts13] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts14] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts15] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts16] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts17] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts18] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts19] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts20] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts21] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts22] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts23] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts24] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts25] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts26] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts27] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts28] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts29] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts30] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts31] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=7 + +[system.cpu1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu1.clk_domain.voltage_domain + +[system.cpu1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu2] +type=GpuDispatcher +children=cl_driver +cl_driver=system.cpu2.cl_driver +clk_domain=system.clk_domain +cpu=system.cpu0 +eventq_index=0 +pio_addr=8589934592 +pio_latency=1000 +shader_pointer=system.cpu1 +system=system +dma=system.piobus.slave[1] +pio=system.piobus.master[0] +translation_port=system.dispatcher_coalescer.slave[0] + +[system.cpu2.cl_driver] +type=ClDriver +codefile=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +eventq_index=0 +filename=hsa + +[system.dir_cntrl0] +type=Directory_Controller +children=L3CacheMemory L3triggerQueue directory probeToCore requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores +CPUonly=false +L3CacheMemory=system.dir_cntrl0.L3CacheMemory +L3triggerQueue=system.dir_cntrl0.L3triggerQueue +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +directory=system.dir_cntrl0.directory +eventq_index=0 +l3_hit_latency=15 +noTCCdir=false +number_of_TBEs=5120 +probeToCore=system.dir_cntrl0.probeToCore +recycle_latency=10 +requestFromCores=system.dir_cntrl0.requestFromCores +responseFromCores=system.dir_cntrl0.responseFromCores +responseFromMemory=system.dir_cntrl0.responseFromMemory +responseToCore=system.dir_cntrl0.responseToCore +response_latency=30 +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=32 +triggerQueue=system.dir_cntrl0.triggerQueue +unblockFromCores=system.dir_cntrl0.unblockFromCores +useL3OnWT=false +version=0 +memory=system.mem_ctrls.port + +[system.dir_cntrl0.L3CacheMemory] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=20 +dataArrayBanks=256.0 +eventq_index=0 +is_icache=false +replacement_policy=system.dir_cntrl0.L3CacheMemory.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16777216 +start_index_bit=6 +tagAccessLatency=15 +tagArrayBanks=256.0 + +[system.dir_cntrl0.L3CacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16777216 + +[system.dir_cntrl0.L3triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=536870912 +version=0 + +[system.dir_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[0] + +[system.dir_cntrl0.requestFromCores] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.dir_cntrl0.responseFromCores] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[1] + +[system.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.dir_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[1] + +[system.dir_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.dir_cntrl0.unblockFromCores] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[2] + +[system.dispatcher_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.dispatcher_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.dispatcher_tlb.slave[0] +slave=system.cpu2.translation_port + +[system.dispatcher_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.dispatcher_coalescer.clk_domain.voltage_domain + +[system.dispatcher_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.dispatcher_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.dispatcher_tlb.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[1] +slave=system.dispatcher_coalescer.master[0] + +[system.dispatcher_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.dispatcher_tlb.clk_domain.voltage_domain + +[system.dispatcher_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l1_coalescer0] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l1_coalescer0.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l1_tlb0.slave[0] +slave=system.cpu1.CUs0.translation_port[0] + +[system.l1_coalescer0.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_coalescer0.clk_domain.voltage_domain + +[system.l1_coalescer0.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_coalescer1] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l1_coalescer1.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l1_tlb1.slave[0] +slave=system.cpu1.CUs1.translation_port[0] + +[system.l1_coalescer1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_coalescer1.clk_domain.voltage_domain + +[system.l1_coalescer1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_tlb0] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l1_tlb0.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[2] +slave=system.l1_coalescer0.master[0] + +[system.l1_tlb0.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_tlb0.clk_domain.voltage_domain + +[system.l1_tlb0.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_tlb1] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l1_tlb1.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[3] +slave=system.l1_coalescer1.master[0] + +[system.l1_tlb1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_tlb1.clk_domain.voltage_domain + +[system.l1_tlb1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l2_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l2_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l2_tlb.slave[0] +slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0] + +[system.l2_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l2_coalescer.clk_domain.voltage_domain + +[system.l2_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l2_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l2_tlb.clk_domain +eventq_index=0 +hitLatency=69 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=4096 +master=system.l3_coalescer.slave[0] +slave=system.l2_coalescer.master[0] + +[system.l2_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l2_tlb.clk_domain.voltage_domain + +[system.l2_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l3_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l3_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l3_tlb.slave[0] +slave=system.l2_tlb.master[0] + +[system.l3_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l3_coalescer.clk_domain.voltage_domain + +[system.l3_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l3_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l3_tlb.clk_domain +eventq_index=0 +hitLatency=150 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=8192 +slave=system.l3_coalescer.master[0] + +[system.l3_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l3_tlb.clk_domain.voltage_domain + +[system.l3_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.dir_cntrl0.memory + +[system.piobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=0 +response_latency=0 +use_default_range=false +width=32 +master=system.cpu2.pio +slave=system.cp_cntrl0.sequencer.mem_master_port system.cpu2.dma + +[system.ruby] +type=RubySystem +children=clk_domain network phys_mem +access_backing_store=true +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=5 +number_of_virtual_networks=10 +phys_mem=system.ruby.phys_mem +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 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+eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers14] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers15] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers16] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers17] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers18] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers19] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers20] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers21] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers22] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers23] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers24] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers25] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers26] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers27] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers28] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers29] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers30] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers31] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=512 +eventq_index=0 +latency=1 +link_id=0 +node_a=system.ruby.network.ext_links0.int_node +node_b=system.ruby.network.ext_links1.int_node +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=512 +eventq_index=0 +latency=1 +link_id=1 +node_a=system.ruby.network.ext_links0.int_node +node_b=system.ruby.network.ext_links2.int_node +weight=1 + +[system.ruby.phys_mem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.ruby.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=false +latency=30000 +latency_var=0 +null=false +range=0:536870911 + +[system.sqc_cntrl0] +type=SQC_Controller +children=L1cache mandatoryQueue probeToSQC requestFromSQC responseFromSQC responseToSQC sequencer unblockFromCore +L1cache=system.sqc_cntrl0.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +issue_latency=80 +l2_hit_latency=18 +mandatoryQueue=system.sqc_cntrl0.mandatoryQueue +number_of_TBEs=256 +probeToSQC=system.sqc_cntrl0.probeToSQC +recycle_latency=10 +requestFromSQC=system.sqc_cntrl0.requestFromSQC +responseFromSQC=system.sqc_cntrl0.responseFromSQC +responseToSQC=system.sqc_cntrl0.responseToSQC +ruby_system=system.ruby +sequencer=system.sqc_cntrl0.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.sqc_cntrl0.unblockFromCore +version=0 + +[system.sqc_cntrl0.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.sqc_cntrl0.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=32768 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=4 + +[system.sqc_cntrl0.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=32768 + +[system.sqc_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.sqc_cntrl0.probeToSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[9] + +[system.sqc_cntrl0.requestFromSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[11] + +[system.sqc_cntrl0.responseFromSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[12] + +[system.sqc_cntrl0.responseToSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[10] + +[system.sqc_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.sqc_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.sqc_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=false +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=6 +slave=system.cpu1.CUs0.sqc_port system.cpu1.CUs1.sqc_port + +[system.sqc_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[13] + +[system.sqc_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.sqc_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.sqc_tlb.slave[0] +slave=system.cpu1.CUs0.sqc_tlb_port system.cpu1.CUs1.sqc_tlb_port + +[system.sqc_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.sqc_coalescer.clk_domain.voltage_domain + +[system.sqc_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.sqc_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.sqc_tlb.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[0] +slave=system.sqc_coalescer.master[0] + +[system.sqc_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.sqc_tlb.clk_domain.voltage_domain + +[system.sqc_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.tcc_cntrl0] +type=TCC_Controller +children=L2cache responseFromTCC responseToTCC w_TCCUnblockToTCCDir w_probeToTCC w_reqToTCC w_reqToTCCDir w_respToTCC w_respToTCCDir +L2cache=system.tcc_cntrl0.L2cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +l2_request_latency=1 +l2_response_latency=16 +number_of_TBEs=2048 +recycle_latency=10 +responseFromTCC=system.tcc_cntrl0.responseFromTCC +responseToTCC=system.tcc_cntrl0.responseToTCC +ruby_system=system.ruby +system=system +transitions_per_cycle=32 +version=0 +w_TCCUnblockToTCCDir=system.tcc_cntrl0.w_TCCUnblockToTCCDir +w_probeToTCC=system.tcc_cntrl0.w_probeToTCC +w_reqToTCC=system.tcc_cntrl0.w_reqToTCC +w_reqToTCCDir=system.tcc_cntrl0.w_reqToTCCDir +w_respToTCC=system.tcc_cntrl0.w_respToTCC +w_respToTCCDir=system.tcc_cntrl0.w_respToTCCDir + +[system.tcc_cntrl0.L2cache] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=8 +dataArrayBanks=256 +eventq_index=0 +is_icache=false +replacement_policy=system.tcc_cntrl0.L2cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=262144.0 +start_index_bit=6 +tagAccessLatency=2 +tagArrayBanks=256 + +[system.tcc_cntrl0.L2cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=262144.0 + +[system.tcc_cntrl0.responseFromTCC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[14] + +[system.tcc_cntrl0.responseToTCC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[11] + +[system.tcc_cntrl0.w_TCCUnblockToTCCDir] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_probeToTCC] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_reqToTCC] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_reqToTCCDir] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_respToTCC] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_respToTCCDir] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tccdir_cntrl0] +type=TCCdir_Controller +children=directory probeFromNB probeToCore requestFromTCP requestToNB responseFromNB responseFromTCP responseToCore responseToNB triggerQueue unblockFromTCP unblockToNB +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +directory=system.tccdir_cntrl0.directory +directory_latency=6 +eventq_index=0 +issue_latency=120 +number_of_TBEs=1024 +probeFromNB=system.tccdir_cntrl0.probeFromNB +probeToCore=system.tccdir_cntrl0.probeToCore +recycle_latency=10 +requestFromTCP=system.tccdir_cntrl0.requestFromTCP +requestToNB=system.tccdir_cntrl0.requestToNB +responseFromNB=system.tccdir_cntrl0.responseFromNB +responseFromTCP=system.tccdir_cntrl0.responseFromTCP +responseToCore=system.tccdir_cntrl0.responseToCore +responseToNB=system.tccdir_cntrl0.responseToNB +response_latency=5 +ruby_system=system.ruby +system=system +transitions_per_cycle=32 +triggerQueue=system.tccdir_cntrl0.triggerQueue +unblockFromTCP=system.tccdir_cntrl0.unblockFromTCP +unblockToNB=system.tccdir_cntrl0.unblockToNB +version=0 +w_TCCUnblockToTCCDir=system.tcc_cntrl0.w_TCCUnblockToTCCDir +w_probeToTCC=system.tcc_cntrl0.w_probeToTCC +w_reqToTCC=system.tcc_cntrl0.w_reqToTCC +w_reqToTCCDir=system.tcc_cntrl0.w_reqToTCCDir +w_respToTCC=system.tcc_cntrl0.w_respToTCC +w_respToTCCDir=system.tcc_cntrl0.w_respToTCCDir + +[system.tccdir_cntrl0.directory] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.tccdir_cntrl0.directory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=393216 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.tccdir_cntrl0.directory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=393216 + +[system.tccdir_cntrl0.probeFromNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[15] + +[system.tccdir_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[15] + +[system.tccdir_cntrl0.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[12] + +[system.tccdir_cntrl0.requestToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[17] + +[system.tccdir_cntrl0.responseFromNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[16] + +[system.tccdir_cntrl0.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[13] + +[system.tccdir_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[16] + +[system.tccdir_cntrl0.responseToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[18] + +[system.tccdir_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.tccdir_cntrl0.unblockFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[14] + +[system.tccdir_cntrl0.unblockToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[19] + +[system.tcp_cntrl0] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl0.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl0.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl0.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl0.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl0.requestFromTCP +responseFromTCP=system.tcp_cntrl0.responseFromTCP +responseToTCP=system.tcp_cntrl0.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl0.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl0.unblockFromCore +use_seq_not_coal=false +version=0 + +[system.tcp_cntrl0.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl0.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl0.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl0.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2048 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=false +version=2 +slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63] + +[system.tcp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl0.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[5] + +[system.tcp_cntrl0.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[5] + +[system.tcp_cntrl0.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[6] + +[system.tcp_cntrl0.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[6] + +[system.tcp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=3 + +[system.tcp_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[7] + +[system.tcp_cntrl1] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl1.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl1.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl1.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl1.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl1.requestFromTCP +responseFromTCP=system.tcp_cntrl1.responseFromTCP +responseToTCP=system.tcp_cntrl1.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl1.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl1.unblockFromCore +use_seq_not_coal=false +version=1 + +[system.tcp_cntrl1.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl1.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl1.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl1.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2048 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=false +version=4 +slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63] + +[system.tcp_cntrl1.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl1.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[7] + +[system.tcp_cntrl1.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[8] + +[system.tcp_cntrl1.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[9] + +[system.tcp_cntrl1.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[8] + +[system.tcp_cntrl1.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=5 + +[system.tcp_cntrl1.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[10] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr new file mode 100755 index 000000000..1e2b8911e --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simerr @@ -0,0 +1,5 @@ +warn: system.ruby.network adopting orphan SimObject param 'int_links' +warn: system.ruby.network adopting orphan SimObject param 'ext_links' +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout new file mode 100755 index 000000000..98757d4d3 --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/simout @@ -0,0 +1,21 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 19 2016 13:28:55 +gem5 started Jan 19 2016 13:29:16 +gem5 executing on zizzer, pid 48854 +command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_RfO + +Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +Global frequency set at 1000000000000 ticks per second +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +info: Entering event queue @ 0. Starting simulation... +keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23 +the gpu says: +elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe +Exiting @ tick 663454500 because target called exit() diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt new file mode 100644 index 000000000..ac9e12c7a --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_RfO/stats.txt @@ -0,0 +1,3202 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000663 # Number of seconds simulated +sim_ticks 663454500 # Number of ticks simulated +final_tick 663454500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 63999 # Simulator instruction rate (inst/s) +host_op_rate 131608 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 634065338 # Simulator tick rate (ticks/s) +host_mem_usage 1301448 # Number of bytes of host memory used +host_seconds 1.05 # Real time elapsed on the host +sim_insts 66963 # Number of instructions simulated +sim_ops 137705 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrls.bytes_read::dir_cntrl0 99264 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 99264 # Number of bytes read from this memory +system.mem_ctrls.num_reads::dir_cntrl0 1551 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1551 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::dir_cntrl0 149616892 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 149616892 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::dir_cntrl0 149616892 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 149616892 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1551 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1551 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 99264 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 99264 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 174 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 222 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 663221000 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1551 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1542 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 485 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 204.008247 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 145.772769 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 192.306659 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 178 36.70% 36.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 156 32.16% 68.87% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 70 14.43% 83.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 40 8.25% 91.55% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 15 3.09% 94.64% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 10 2.06% 96.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 9 1.86% 98.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 2 0.41% 98.97% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 5 1.03% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 485 # Bytes accessed per row activation +system.mem_ctrls.totQLat 15500500 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 44581750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 7755000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 9993.87 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28743.87 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 149.62 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 149.62 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 1.17 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 1.17 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 1062 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 68.47 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.avgGap 427608.64 # Average gap between requests +system.mem_ctrls.pageHitRate 68.47 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1391040 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 759000 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 43227600 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 335485755 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 102969000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 489167595 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 738.822020 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 170399250 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 22100000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 470741750 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 2275560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1241625 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6723600 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 43227600 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 371983995 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 70953000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 496405380 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 749.753724 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 115859750 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 22100000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 524145250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.ruby.clk_domain.clock 500 # Clock period in ticks +system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory +system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory +system.ruby.phys_mem.bw_read::cpu0.inst 1050200127 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu0.data 180618264 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 4943821 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 4943821 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::total 1240706032 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu0.inst 1050200127 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 3014525 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 3014525 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::total 1056229176 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu0.data 109678961 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 385859 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::total 110450679 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.inst 1050200127 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.data 290297225 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 5329680 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::total 1351156711 # Total bandwidth to/from this memory (bytes/s) +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 114203 +system.ruby.outstanding_req_hist::mean 1.000035 +system.ruby.outstanding_req_hist::gmean 1.000024 +system.ruby.outstanding_req_hist::stdev 0.005918 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 114203 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 114203 +system.ruby.latency_hist::mean 4.784183 +system.ruby.latency_hist::gmean 2.131364 +system.ruby.latency_hist::stdev 23.846744 +system.ruby.latency_hist | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1506 1.32% 99.97% | 19 0.02% 99.99% | 10 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 114203 +system.ruby.hit_latency_hist::bucket_size 64 +system.ruby.hit_latency_hist::max_bucket 639 +system.ruby.hit_latency_hist::samples 1535 +system.ruby.hit_latency_hist::mean 208.449511 +system.ruby.hit_latency_hist::gmean 208.002927 +system.ruby.hit_latency_hist::stdev 15.847049 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 1535 +system.ruby.miss_latency_hist::bucket_size 4 +system.ruby.miss_latency_hist::max_bucket 39 +system.ruby.miss_latency_hist::samples 112668 +system.ruby.miss_latency_hist::mean 2.009426 +system.ruby.miss_latency_hist::gmean 2.002413 +system.ruby.miss_latency_hist::stdev 0.411800 +system.ruby.miss_latency_hist | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 112668 +system.ruby.L1Cache.incomplete_times 112609 +system.ruby.L2Cache.incomplete_times 59 +system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses +system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses +system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads +system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes +system.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads +system.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes +system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses +system.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses +system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses +system.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses +system.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads +system.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes +system.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads +system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes +system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses +system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses +system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads +system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes +system.cp_cntrl0.L2cache.num_tag_array_reads 12059 # number of tag array reads +system.cp_cntrl0.L2cache.num_tag_array_writes 1649 # number of tag array writes +system.cpu0.clk_domain.clock 500 # Clock period in ticks +system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu0.workload.num_syscalls 21 # Number of system calls +system.cpu0.numCycles 1326909 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 66963 # Number of instructions committed +system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses +system.cpu0.num_func_calls 3196 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136380 # number of integer instructions +system.cpu0.num_fp_insts 1279 # number of float instructions +system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written +system.cpu0.num_mem_refs 27198 # number of memory refs +system.cpu0.num_load_insts 16684 # Number of load instructions +system.cpu0.num_store_insts 10514 # Number of store instructions +system.cpu0.num_idle_cycles 5227.003992 # Number of idle cycles +system.cpu0.num_busy_cycles 1321681.996008 # Number of busy cycles +system.cpu0.not_idle_fraction 0.996061 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.003939 # Percentage of idle cycles +system.cpu0.Branches 16199 # Number of branches fetched +system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction +system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction +system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction +system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction +system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 137705 # Class of executed instruction +system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.cpu1.clk_domain.clock 1000 # Clock period in ticks +system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 297 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 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with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 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number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 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with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 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+system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 273 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 272 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 256 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 3230 # number of cycles the CU issues nothing +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 128 # number of cycles the CU issued at least one instruction +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 780 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 367 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 384 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 327 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 414 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 30 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::stdev 0.220406 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::0 3230 96.19% 96.19% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::1 116 3.45% 99.64% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::2 11 0.33% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 82 # number of CU transitions from active to idle +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 82 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 39.280488 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 158.161058 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 62 75.61% 75.61% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 9 10.98% 86.59% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.22% 87.80% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 0 0.00% 87.80% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.44% 90.24% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.22% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.46% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 8.54% 100.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1285 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 82 # duration of idle periods in cycles +system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF +system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests +system.cpu1.CUs0.tlb_cycles -452460956000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs0.avg_translation_latency -588375755.526658 # Avg. translation latency for data translations +system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses +system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count +system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count +system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity +system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed +system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::mean 86.382979 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::stdev 229.391669 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::4-5 51 36.17% 45.39% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::6-7 32 22.70% 68.09% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::8-9 2 1.42% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::10 2 1.42% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::overflows 41 29.08% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::max_value 1291 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst) +system.cpu1.CUs0.num_total_cycles 3358 # number of cycles the CU ran for +system.cpu1.CUs0.vpc 2.015783 # Vector Operations per cycle (this CU only) +system.cpu1.CUs0.ipc 0.041989 # Instructions per cycle (this CU only) +system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction +system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed +system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD +system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations +system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed +system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts +system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 381 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 356 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 339 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 3228 # number of cycles the CU issues nothing +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 130 # number of cycles the CU issued at least one instruction +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 778 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 472 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 447 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 411 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 417 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.spc::samples 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::mean 0.041989 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::stdev 0.217686 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::0 3228 96.13% 96.13% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::1 120 3.57% 99.70% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::2 9 0.27% 99.97% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::3 1 0.03% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::total 3358 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 81 # number of CU transitions from active to idle +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 81 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 38.617284 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 158.076213 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 60 74.07% 74.07% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 10 12.35% 86.42% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 86.42% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.47% 88.89% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 2 2.47% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 91.36% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 8.64% 100.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1293 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 81 # duration of idle periods in cycles +system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF +system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests +system.cpu1.CUs1.tlb_cycles -452466433000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs1.avg_translation_latency -588382877.763329 # Avg. translation latency for data translations +system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses +system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count +system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count +system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity +system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed +system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::mean 85.666667 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::stdev 230.212531 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::4-5 52 36.88% 46.10% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::6-7 33 23.40% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::8-9 4 2.84% 72.34% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 73.05% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::overflows 38 26.95% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::max_value 1299 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst) +system.cpu1.CUs1.num_total_cycles 3358 # number of cycles the CU ran for +system.cpu1.CUs1.vpc 2.013699 # Vector Operations per cycle (this CU only) +system.cpu1.CUs1.ipc 0.041989 # Instructions per cycle (this CU only) +system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction +system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed +system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD +system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations +system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed +system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts +system.cpu2.num_kernel_launched 1 # number of kernel launched +system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits +system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses +system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses +system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1551 # number of data array writes +system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1551 # number of tag array reads +system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1551 # number of tag array writes +system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses +system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses +system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue +system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts +system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses +system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits +system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses +system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate +system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses +system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits +system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses +system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate +system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level +system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched +system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs +system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses +system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses +system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue +system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts +system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses +system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses +system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue +system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts +system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses +system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits +system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses +system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate +system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses +system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits +system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses +system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate +system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level +system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table +system.l1_tlb0.unique_pages 4 # Number of unique pages touched +system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs +system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses +system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits +system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses +system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate +system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses +system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits +system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses +system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate +system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level +system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table +system.l1_tlb1.unique_pages 3 # Number of unique pages touched +system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs +system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses +system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses +system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue +system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs +system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts +system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses +system.l2_tlb.local_TLB_hits 3 # Number of TLB hits +system.l2_tlb.local_TLB_misses 5 # Number of TLB misses +system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate +system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses +system.l2_tlb.global_TLB_hits 3 # Number of TLB hits +system.l2_tlb.global_TLB_misses 12 # Number of TLB misses +system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate +system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level +system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.l2_tlb.unique_pages 5 # Number of unique pages touched +system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs +system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs +system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses +system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses +system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue +system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs +system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts +system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses +system.l3_tlb.local_TLB_hits 0 # Number of TLB hits +system.l3_tlb.local_TLB_misses 5 # Number of TLB misses +system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate +system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses +system.l3_tlb.global_TLB_hits 0 # Number of TLB hits +system.l3_tlb.global_TLB_misses 12 # Number of TLB misses +system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate +system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level +system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table +system.l3_tlb.unique_pages 5 # Number of unique pages touched +system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs +system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs +system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.piobus.trans_dist::WriteReq 94 # Transaction distribution +system.piobus.trans_dist::WriteResp 94 # Transaction distribution +system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) +system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) +system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) +system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) +system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) +system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.ruby.network.ext_links0.int_node.percent_links_utilized 0.007952 +system.ruby.network.ext_links0.int_node.msg_count.Control::0 1551 +system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1551 +system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1563 +system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1539 +system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1551 +system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12408 +system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12408 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 112536 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12312 +system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12408 +system.ruby.network.ext_links1.int_node.percent_links_utilized 0.009970 +system.ruby.network.ext_links1.int_node.msg_count.Control::0 16 +system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 +system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 +system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 14 +system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1535 +system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 128 +system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 +system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 +system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 112 +system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12280 +system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl0.L1cache.num_data_array_reads 10 # number of data array reads +system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes +system.tcp_cntrl0.L1cache.num_tag_array_reads 27 # number of tag array reads +system.tcp_cntrl0.L1cache.num_tag_array_writes 18 # number of tag array writes +system.tcp_cntrl0.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array +system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array +system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP +system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl0.coalescer.gpu_ld_misses 2 # loads that miss in the GPU +system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP +system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 1 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl0.coalescer.gpu_st_misses 4 # stores that miss in the GPU +system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.ruby.network.ext_links2.int_node.percent_links_utilized 0.000721 +system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 +system.ruby.network.ext_links2.int_node.msg_count.Control::1 14 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 16 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 19 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 26 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 33 +system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1525 +system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 16 +system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::5 19 +system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 +system.ruby.network.ext_links2.int_node.msg_bytes.Control::1 112 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 128 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 152 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 1872 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 2376 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12200 +system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 128 +system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::5 152 +system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl1.L1cache.num_data_array_reads 7 # number of data array reads +system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes +system.tcp_cntrl1.L1cache.num_tag_array_reads 25 # number of tag array reads +system.tcp_cntrl1.L1cache.num_tag_array_writes 18 # number of tag array writes +system.tcp_cntrl1.L1cache.num_tag_array_stalls 2 # number of stalls caused by tag array +system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array +system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 3 # loads that hit in the TCP +system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 2 # TCP to TCP load transfers +system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl1.coalescer.gpu_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 4 # stores that hit in the TCP +system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl1.coalescer.gpu_st_misses 5 # stores that miss in the GPU +system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads +system.sqc_cntrl0.L1cache.num_data_array_writes 5 # number of data array writes +system.sqc_cntrl0.L1cache.num_tag_array_reads 86 # number of tag array reads +system.sqc_cntrl0.L1cache.num_tag_array_writes 5 # number of tag array writes +system.sqc_cntrl0.L1cache.num_data_array_stalls 44 # number of stalls caused by data array +system.sqc_cntrl0.sequencer.load_waiting_on_load 120 # Number of times a load aliased with a pending load +system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses +system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses +system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits +system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses +system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses +system.tccdir_cntrl0.directory.num_tag_array_reads 1554 # number of tag array reads +system.tccdir_cntrl0.directory.num_tag_array_writes 27 # number of tag array writes +system.ruby.network.msg_count.Control 3116 +system.ruby.network.msg_count.Request_Control 3121 +system.ruby.network.msg_count.Response_Data 3159 +system.ruby.network.msg_count.Response_Control 3078 +system.ruby.network.msg_count.Unblock_Control 3121 +system.ruby.network.msg_byte.Control 24928 +system.ruby.network.msg_byte.Request_Control 24968 +system.ruby.network.msg_byte.Response_Data 227448 +system.ruby.network.msg_byte.Response_Control 24624 +system.ruby.network.msg_byte.Unblock_Control 24968 +system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses +system.sqc_coalescer.coalesced_accesses 63 # Number of coalesced TLB accesses +system.sqc_coalescer.queuing_cycles 100000 # Number of cycles spent in queue +system.sqc_coalescer.local_queuing_cycles 100000 # Number of cycles spent in queue for all incoming reqs +system.sqc_coalescer.local_latency 1162.790698 # Avg. latency over all incoming pkts +system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks +system.sqc_tlb.local_TLB_accesses 63 # Number of TLB accesses +system.sqc_tlb.local_TLB_hits 62 # Number of TLB hits +system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses +system.sqc_tlb.local_TLB_miss_rate 1.587302 # TLB miss rate +system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses +system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits +system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses +system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate +system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level +system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.sqc_tlb.unique_pages 1 # Number of unique pages touched +system.sqc_tlb.local_cycles 63001 # Number of cycles spent in queue for all incoming reqs +system.sqc_tlb.local_latency 1000.015873 # Avg. latency over incoming coalesced reqs +system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.005592 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1551 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 12 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1539 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1551 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12408 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 864 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12312 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12408 +system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.016287 +system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 16 +system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 +system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 128 +system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 +system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.001977 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 16 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 1152 +system.ruby.network.ext_links1.int_node.throttle0.link_utilization 0.016287 +system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 16 +system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 +system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 128 +system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 +system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.003653 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 14 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1535 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 112 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12280 +system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.000084 +system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::1 8 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+system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 1010 0.00% 0.00% +system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 1010 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 323 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 323 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.CPUPrbResp 176 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 176 0.00% 0.00% +system.ruby.Directory_Controller.B.CoreUnblock 1551 0.00% 0.00% +system.ruby.LD.latency_hist::bucket_size 32 +system.ruby.LD.latency_hist::max_bucket 319 +system.ruby.LD.latency_hist::samples 16335 +system.ruby.LD.latency_hist::mean 4.217447 +system.ruby.LD.latency_hist::gmean 2.103537 +system.ruby.LD.latency_hist::stdev 21.286370 +system.ruby.LD.latency_hist | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 166 1.02% 99.94% | 9 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 16335 +system.ruby.LD.hit_latency_hist::bucket_size 32 +system.ruby.LD.hit_latency_hist::max_bucket 319 +system.ruby.LD.hit_latency_hist::samples 175 +system.ruby.LD.hit_latency_hist::mean 208.468571 +system.ruby.LD.hit_latency_hist::gmean 208.231054 +system.ruby.LD.hit_latency_hist::stdev 10.632194 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 175 +system.ruby.LD.miss_latency_hist::bucket_size 4 +system.ruby.LD.miss_latency_hist::max_bucket 39 +system.ruby.LD.miss_latency_hist::samples 16160 +system.ruby.LD.miss_latency_hist::mean 2.005569 +system.ruby.LD.miss_latency_hist::gmean 2.001425 +system.ruby.LD.miss_latency_hist::stdev 0.316580 +system.ruby.LD.miss_latency_hist | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.miss_latency_hist::total 16160 +system.ruby.ST.latency_hist::bucket_size 64 +system.ruby.ST.latency_hist::max_bucket 639 +system.ruby.ST.latency_hist::samples 10412 +system.ruby.ST.latency_hist::mean 8.385709 +system.ruby.ST.latency_hist::gmean 2.308923 +system.ruby.ST.latency_hist::stdev 35.862445 +system.ruby.ST.latency_hist | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 316 3.03% 99.94% | 3 0.03% 99.97% | 3 0.03% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 10412 +system.ruby.ST.hit_latency_hist::bucket_size 64 +system.ruby.ST.hit_latency_hist::max_bucket 639 +system.ruby.ST.hit_latency_hist::samples 322 +system.ruby.ST.hit_latency_hist::mean 208.484472 +system.ruby.ST.hit_latency_hist::gmean 208.014366 +system.ruby.ST.hit_latency_hist::stdev 16.327683 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 322 +system.ruby.ST.miss_latency_hist::bucket_size 1 +system.ruby.ST.miss_latency_hist::max_bucket 9 +system.ruby.ST.miss_latency_hist::samples 10090 +system.ruby.ST.miss_latency_hist::mean 2 +system.ruby.ST.miss_latency_hist::gmean 2.000000 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 10090 +system.ruby.IFETCH.latency_hist::bucket_size 64 +system.ruby.IFETCH.latency_hist::max_bucket 639 +system.ruby.IFETCH.latency_hist::samples 87095 +system.ruby.IFETCH.latency_hist::mean 4.462093 +system.ruby.IFETCH.latency_hist::gmean 2.116390 +system.ruby.IFETCH.latency_hist::stdev 22.435279 +system.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1011 1.16% 99.97% | 16 0.02% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 87095 +system.ruby.IFETCH.hit_latency_hist::bucket_size 64 +system.ruby.IFETCH.hit_latency_hist::max_bucket 639 +system.ruby.IFETCH.hit_latency_hist::samples 1034 +system.ruby.IFETCH.hit_latency_hist::mean 208.444874 +system.ruby.IFETCH.hit_latency_hist::gmean 207.968565 +system.ruby.IFETCH.hit_latency_hist::stdev 16.462617 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 1034 +system.ruby.IFETCH.miss_latency_hist::bucket_size 4 +system.ruby.IFETCH.miss_latency_hist::max_bucket 39 +system.ruby.IFETCH.miss_latency_hist::samples 86061 +system.ruby.IFETCH.miss_latency_hist::mean 2.011294 +system.ruby.IFETCH.miss_latency_hist::gmean 2.002892 +system.ruby.IFETCH.miss_latency_hist::stdev 0.450747 +system.ruby.IFETCH.miss_latency_hist | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 86061 +system.ruby.RMW_Read.latency_hist::bucket_size 32 +system.ruby.RMW_Read.latency_hist::max_bucket 319 +system.ruby.RMW_Read.latency_hist::samples 341 +system.ruby.RMW_Read.latency_hist::mean 4.392962 +system.ruby.RMW_Read.latency_hist::gmean 2.111743 +system.ruby.RMW_Read.latency_hist::stdev 21.996747 +system.ruby.RMW_Read.latency_hist | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 4 1.17% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 341 +system.ruby.RMW_Read.hit_latency_hist::bucket_size 32 +system.ruby.RMW_Read.hit_latency_hist::max_bucket 319 +system.ruby.RMW_Read.hit_latency_hist::samples 4 +system.ruby.RMW_Read.hit_latency_hist::mean 206 +system.ruby.RMW_Read.hit_latency_hist::gmean 206.000000 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 4 +system.ruby.RMW_Read.miss_latency_hist::bucket_size 1 +system.ruby.RMW_Read.miss_latency_hist::max_bucket 9 +system.ruby.RMW_Read.miss_latency_hist::samples 337 +system.ruby.RMW_Read.miss_latency_hist::mean 2 +system.ruby.RMW_Read.miss_latency_hist::gmean 2.000000 +system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 337 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.latency_hist::samples 10 +system.ruby.Locked_RMW_Read.latency_hist::mean 2 +system.ruby.Locked_RMW_Read.latency_hist::gmean 2 +system.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 10 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 10 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 2 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 2 +system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 10 +system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.latency_hist::samples 10 +system.ruby.Locked_RMW_Write.latency_hist::mean 2 +system.ruby.Locked_RMW_Write.latency_hist::gmean 2 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 10 +system.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.miss_latency_hist::samples 10 +system.ruby.Locked_RMW_Write.miss_latency_hist::mean 2 +system.ruby.Locked_RMW_Write.miss_latency_hist::gmean 2 +system.ruby.Locked_RMW_Write.miss_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.miss_latency_hist::total 10 +system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 1 +system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 9 +system.ruby.L1Cache.miss_mach_latency_hist::samples 112609 +system.ruby.L1Cache.miss_mach_latency_hist::mean 2 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 2.000000 +system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 112609 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 112609 +system.ruby.L2Cache.miss_mach_latency_hist::bucket_size 4 +system.ruby.L2Cache.miss_mach_latency_hist::max_bucket 39 +system.ruby.L2Cache.miss_mach_latency_hist::samples 59 +system.ruby.L2Cache.miss_mach_latency_hist::mean 20 +system.ruby.L2Cache.miss_mach_latency_hist::gmean 20.000000 +system.ruby.L2Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L2Cache.miss_mach_latency_hist::total 59 +system.ruby.Directory.hit_mach_latency_hist::bucket_size 64 +system.ruby.Directory.hit_mach_latency_hist::max_bucket 639 +system.ruby.Directory.hit_mach_latency_hist::samples 1535 +system.ruby.Directory.hit_mach_latency_hist::mean 208.449511 +system.ruby.Directory.hit_mach_latency_hist::gmean 208.002927 +system.ruby.Directory.hit_mach_latency_hist::stdev 15.847049 +system.ruby.Directory.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1506 98.11% 98.11% | 19 1.24% 99.35% | 10 0.65% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.hit_mach_latency_hist::total 1535 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 16155 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 2 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 2.000000 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 16155 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size 4 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket 39 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0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 166 94.86% 94.86% | 9 5.14% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.hit_type_mach_latency_hist::total 175 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10090 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 2 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 2.000000 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10090 +system.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size 64 +system.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket 639 +system.ruby.ST.Directory.hit_type_mach_latency_hist::samples 322 +system.ruby.ST.Directory.hit_type_mach_latency_hist::mean 208.484472 +system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 208.014366 +system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 16.327683 +system.ruby.ST.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 316 98.14% 98.14% | 3 0.93% 99.07% | 3 0.93% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.hit_type_mach_latency_hist::total 322 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples 86007 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean 2 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean 2.000000 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total 86007 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size 4 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket 39 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples 54 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean 20 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean 20.000000 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total 54 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 64 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 639 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1034 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 208.444874 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 207.968565 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev 16.462617 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1011 97.78% 97.78% | 16 1.55% 99.32% | 7 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1034 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 337 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 2 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 2.000000 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total 337 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size 32 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket 319 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples 4 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean 206 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean 206.000000 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 4 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total 4 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 10 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 2 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 2 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total 10 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket 9 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+system.ruby.TCCdir_Controller.CPUPrbResp 14 0.00% 0.00% +system.ruby.TCCdir_Controller.ProbeAcksComplete 13 0.00% 0.00% +system.ruby.TCCdir_Controller.CoreUnblock 17 0.00% 0.00% +system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckS 7 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckM 9 0.00% 0.00% +system.ruby.TCCdir_Controller.PrbInvData 326 0.00% 0.00% +system.ruby.TCCdir_Controller.PrbShrData 1209 0.00% 0.00% +system.ruby.TCCdir_Controller.I.RdBlk 2 0.00% 0.00% +system.ruby.TCCdir_Controller.I.RdBlkM 9 0.00% 0.00% +system.ruby.TCCdir_Controller.I.RdBlkS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.I.PrbInvData 325 0.00% 0.00% +system.ruby.TCCdir_Controller.I.PrbShrData 1200 0.00% 0.00% +system.ruby.TCCdir_Controller.S.RdBlk 2 0.00% 0.00% +system.ruby.TCCdir_Controller.S.PrbInvData 1 0.00% 0.00% +system.ruby.TCCdir_Controller.M.RdBlkM 1 0.00% 0.00% +system.ruby.TCCdir_Controller.M.PrbShrData 9 0.00% 0.00% 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+system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 7 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlkM 4 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 9 0.00% 0.00% +system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00% +system.ruby.TCP_Controller.Load::total 10 +system.ruby.TCP_Controller.Store | 9 50.00% 50.00% | 9 50.00% 100.00% +system.ruby.TCP_Controller.Store::total 18 +system.ruby.TCP_Controller.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.TCC_AckS::total 4 +system.ruby.TCP_Controller.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% +system.ruby.TCP_Controller.TCC_AckM::total 10 +system.ruby.TCP_Controller.PrbInvData | 1 33.33% 33.33% | 2 66.67% 100.00% +system.ruby.TCP_Controller.PrbInvData::total 3 +system.ruby.TCP_Controller.PrbShrData | 7 63.64% 63.64% | 4 36.36% 100.00% +system.ruby.TCP_Controller.PrbShrData::total 11 +system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.I.Load::total 4 +system.ruby.TCP_Controller.I.Store | 5 50.00% 50.00% | 5 50.00% 100.00% +system.ruby.TCP_Controller.I.Store::total 10 +system.ruby.TCP_Controller.S.Load | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.TCP_Controller.S.Load::total 6 +system.ruby.TCP_Controller.S.PrbInvData | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.S.PrbInvData::total 2 +system.ruby.TCP_Controller.S.PrbShrData | 2 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.S.PrbShrData::total 2 +system.ruby.TCP_Controller.M.Store | 4 50.00% 50.00% | 4 50.00% 100.00% +system.ruby.TCP_Controller.M.Store::total 8 +system.ruby.TCP_Controller.M.PrbInvData | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.TCP_Controller.M.PrbInvData::total 1 +system.ruby.TCP_Controller.M.PrbShrData | 5 55.56% 55.56% | 4 44.44% 100.00% +system.ruby.TCP_Controller.M.PrbShrData::total 9 +system.ruby.TCP_Controller.I_M.TCC_AckM | 5 50.00% 50.00% | 5 50.00% 100.00% +system.ruby.TCP_Controller.I_M.TCC_AckM::total 10 +system.ruby.TCP_Controller.I_ES.TCC_AckS | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.I_ES.TCC_AckS::total 4 + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/config.ini new file mode 100644 index 000000000..33ae7164f --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/config.ini @@ -0,0 +1,4063 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cpu0 cpu1 cpu2 dispatcher_coalescer dispatcher_tlb dvfs_handler l1_coalescer0 l1_coalescer1 l1_tlb0 l1_tlb1 l2_coalescer l2_tlb l3_coalescer l3_tlb mem_ctrls piobus ruby sqc_coalescer sqc_tlb sys_port_proxy voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrls system.ruby.phys_mem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0] +type=TimingSimpleCPU +children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu0.clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.ruby.cp_cntrl0.sequencer.slave[1] +icache_port=system.ruby.cp_cntrl0.sequencer.slave[0] + +[system.cpu0.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu0.clk_domain +eventq_index=0 + +[system.cpu0.clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +clk_domain=system.cpu0.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.ruby.cp_cntrl0.sequencer.slave[3] + +[system.cpu0.interrupts] +type=X86LocalApic +clk_domain=system.cpu0.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.ruby.cp_cntrl0.sequencer.slave[4] +int_slave=system.ruby.cp_cntrl0.sequencer.master[1] +pio=system.ruby.cp_cntrl0.sequencer.master[0] + +[system.cpu0.isa] +type=X86ISA +eventq_index=0 + +[system.cpu0.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +clk_domain=system.cpu0.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.ruby.cp_cntrl0.sequencer.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu0.workload] +type=LiveProcess +cmd=gpu-hello +cwd= +drivers=system.cpu2.cl_driver +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu1] +type=Shader +children=CUs0 CUs1 clk_domain +CUs=system.cpu1.CUs0 system.cpu1.CUs1 +clk_domain=system.cpu1.clk_domain +cpu_pointer=system.cpu0 +eventq_index=0 +globalmem=65536 +impl_kern_boundary_sync=true +n_wf=8 +separate_acquire_release=false +timing=true +translation=false + +[system.cpu1.CUs0] +type=ComputeUnit +children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31 +clk_domain=system.cpu1.clk_domain +coalescer_to_vrf_bus_width=32 +countPages=false +cu_id=0 +debugSegFault=false +dpbypass_pipe_length=4 +eventq_index=0 +execPolicy=OLDEST-FIRST +functionalTLB=true +global_mem_queue_size=256 +issue_period=4 +localDataStore=system.cpu1.CUs0.localDataStore +localMemBarrier=false +local_mem_queue_size=256 +mem_req_latency=9 +mem_resp_latency=9 +n_wf=8 +num_SIMDs=4 +num_global_mem_pipes=1 +num_shared_mem_pipes=1 +perLaneTLB=false +prefetch_depth=0 +prefetch_prev_type=PF_PHASE +prefetch_stride=1 +spbypass_pipe_length=4 +system=system +vector_register_file=system.cpu1.CUs0.vector_register_file0 system.cpu1.CUs0.vector_register_file1 system.cpu1.CUs0.vector_register_file2 system.cpu1.CUs0.vector_register_file3 +vrf_to_coalescer_bus_width=32 +wavefronts=system.cpu1.CUs0.wavefronts00 system.cpu1.CUs0.wavefronts01 system.cpu1.CUs0.wavefronts02 system.cpu1.CUs0.wavefronts03 system.cpu1.CUs0.wavefronts04 system.cpu1.CUs0.wavefronts05 system.cpu1.CUs0.wavefronts06 system.cpu1.CUs0.wavefronts07 system.cpu1.CUs0.wavefronts08 system.cpu1.CUs0.wavefronts09 system.cpu1.CUs0.wavefronts10 system.cpu1.CUs0.wavefronts11 system.cpu1.CUs0.wavefronts12 system.cpu1.CUs0.wavefronts13 system.cpu1.CUs0.wavefronts14 system.cpu1.CUs0.wavefronts15 system.cpu1.CUs0.wavefronts16 system.cpu1.CUs0.wavefronts17 system.cpu1.CUs0.wavefronts18 system.cpu1.CUs0.wavefronts19 system.cpu1.CUs0.wavefronts20 system.cpu1.CUs0.wavefronts21 system.cpu1.CUs0.wavefronts22 system.cpu1.CUs0.wavefronts23 system.cpu1.CUs0.wavefronts24 system.cpu1.CUs0.wavefronts25 system.cpu1.CUs0.wavefronts26 system.cpu1.CUs0.wavefronts27 system.cpu1.CUs0.wavefronts28 system.cpu1.CUs0.wavefronts29 system.cpu1.CUs0.wavefronts30 system.cpu1.CUs0.wavefronts31 +wfSize=64 +xactCasMode=false +ldsPort=system.cpu1.CUs0.ldsBus.slave +memory_port=system.ruby.tcp_cntrl0.coalescer.slave[0] system.ruby.tcp_cntrl0.coalescer.slave[1] system.ruby.tcp_cntrl0.coalescer.slave[2] system.ruby.tcp_cntrl0.coalescer.slave[3] system.ruby.tcp_cntrl0.coalescer.slave[4] system.ruby.tcp_cntrl0.coalescer.slave[5] system.ruby.tcp_cntrl0.coalescer.slave[6] system.ruby.tcp_cntrl0.coalescer.slave[7] system.ruby.tcp_cntrl0.coalescer.slave[8] system.ruby.tcp_cntrl0.coalescer.slave[9] system.ruby.tcp_cntrl0.coalescer.slave[10] system.ruby.tcp_cntrl0.coalescer.slave[11] system.ruby.tcp_cntrl0.coalescer.slave[12] system.ruby.tcp_cntrl0.coalescer.slave[13] system.ruby.tcp_cntrl0.coalescer.slave[14] system.ruby.tcp_cntrl0.coalescer.slave[15] system.ruby.tcp_cntrl0.coalescer.slave[16] system.ruby.tcp_cntrl0.coalescer.slave[17] system.ruby.tcp_cntrl0.coalescer.slave[18] system.ruby.tcp_cntrl0.coalescer.slave[19] system.ruby.tcp_cntrl0.coalescer.slave[20] system.ruby.tcp_cntrl0.coalescer.slave[21] system.ruby.tcp_cntrl0.coalescer.slave[22] system.ruby.tcp_cntrl0.coalescer.slave[23] system.ruby.tcp_cntrl0.coalescer.slave[24] system.ruby.tcp_cntrl0.coalescer.slave[25] system.ruby.tcp_cntrl0.coalescer.slave[26] system.ruby.tcp_cntrl0.coalescer.slave[27] system.ruby.tcp_cntrl0.coalescer.slave[28] system.ruby.tcp_cntrl0.coalescer.slave[29] system.ruby.tcp_cntrl0.coalescer.slave[30] system.ruby.tcp_cntrl0.coalescer.slave[31] system.ruby.tcp_cntrl0.coalescer.slave[32] system.ruby.tcp_cntrl0.coalescer.slave[33] system.ruby.tcp_cntrl0.coalescer.slave[34] system.ruby.tcp_cntrl0.coalescer.slave[35] system.ruby.tcp_cntrl0.coalescer.slave[36] system.ruby.tcp_cntrl0.coalescer.slave[37] system.ruby.tcp_cntrl0.coalescer.slave[38] system.ruby.tcp_cntrl0.coalescer.slave[39] system.ruby.tcp_cntrl0.coalescer.slave[40] system.ruby.tcp_cntrl0.coalescer.slave[41] system.ruby.tcp_cntrl0.coalescer.slave[42] system.ruby.tcp_cntrl0.coalescer.slave[43] system.ruby.tcp_cntrl0.coalescer.slave[44] system.ruby.tcp_cntrl0.coalescer.slave[45] system.ruby.tcp_cntrl0.coalescer.slave[46] system.ruby.tcp_cntrl0.coalescer.slave[47] system.ruby.tcp_cntrl0.coalescer.slave[48] system.ruby.tcp_cntrl0.coalescer.slave[49] system.ruby.tcp_cntrl0.coalescer.slave[50] system.ruby.tcp_cntrl0.coalescer.slave[51] system.ruby.tcp_cntrl0.coalescer.slave[52] system.ruby.tcp_cntrl0.coalescer.slave[53] system.ruby.tcp_cntrl0.coalescer.slave[54] system.ruby.tcp_cntrl0.coalescer.slave[55] system.ruby.tcp_cntrl0.coalescer.slave[56] system.ruby.tcp_cntrl0.coalescer.slave[57] system.ruby.tcp_cntrl0.coalescer.slave[58] system.ruby.tcp_cntrl0.coalescer.slave[59] system.ruby.tcp_cntrl0.coalescer.slave[60] system.ruby.tcp_cntrl0.coalescer.slave[61] system.ruby.tcp_cntrl0.coalescer.slave[62] system.ruby.tcp_cntrl0.coalescer.slave[63] +sqc_port=system.ruby.sqc_cntrl0.sequencer.slave[0] +sqc_tlb_port=system.sqc_coalescer.slave[0] +translation_port=system.l1_coalescer0.slave[0] + +[system.cpu1.CUs0.ldsBus] +type=Bridge +clk_domain=system.cpu1.clk_domain +delay=0 +eventq_index=0 +ranges=0:18446744073709551615 +req_size=16 +resp_size=16 +master=system.cpu1.CUs0.localDataStore.cuPort +slave=system.cpu1.CUs0.ldsPort + +[system.cpu1.CUs0.localDataStore] +type=LdsState +bankConflictPenalty=1 +banks=32 +clk_domain=system.cpu1.clk_domain +eventq_index=0 +range=0:65535 +size=65536 +cuPort=system.cpu1.CUs0.ldsBus.master + +[system.cpu1.CUs0.vector_register_file0] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=0 + +[system.cpu1.CUs0.vector_register_file1] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=1 + +[system.cpu1.CUs0.vector_register_file2] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=2 + +[system.cpu1.CUs0.vector_register_file3] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=3 + +[system.cpu1.CUs0.wavefronts00] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts01] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts02] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts03] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts04] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts05] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts06] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts07] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts08] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts09] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts10] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts11] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts12] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts13] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts14] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts15] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts16] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts17] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts18] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts19] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts20] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts21] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts22] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts23] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts24] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts25] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts26] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts27] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts28] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts29] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts30] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts31] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=7 + +[system.cpu1.CUs1] +type=ComputeUnit +children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31 +clk_domain=system.cpu1.clk_domain +coalescer_to_vrf_bus_width=32 +countPages=false +cu_id=1 +debugSegFault=false +dpbypass_pipe_length=4 +eventq_index=0 +execPolicy=OLDEST-FIRST +functionalTLB=true +global_mem_queue_size=256 +issue_period=4 +localDataStore=system.cpu1.CUs1.localDataStore +localMemBarrier=false +local_mem_queue_size=256 +mem_req_latency=9 +mem_resp_latency=9 +n_wf=8 +num_SIMDs=4 +num_global_mem_pipes=1 +num_shared_mem_pipes=1 +perLaneTLB=false +prefetch_depth=0 +prefetch_prev_type=PF_PHASE +prefetch_stride=1 +spbypass_pipe_length=4 +system=system +vector_register_file=system.cpu1.CUs1.vector_register_file0 system.cpu1.CUs1.vector_register_file1 system.cpu1.CUs1.vector_register_file2 system.cpu1.CUs1.vector_register_file3 +vrf_to_coalescer_bus_width=32 +wavefronts=system.cpu1.CUs1.wavefronts00 system.cpu1.CUs1.wavefronts01 system.cpu1.CUs1.wavefronts02 system.cpu1.CUs1.wavefronts03 system.cpu1.CUs1.wavefronts04 system.cpu1.CUs1.wavefronts05 system.cpu1.CUs1.wavefronts06 system.cpu1.CUs1.wavefronts07 system.cpu1.CUs1.wavefronts08 system.cpu1.CUs1.wavefronts09 system.cpu1.CUs1.wavefronts10 system.cpu1.CUs1.wavefronts11 system.cpu1.CUs1.wavefronts12 system.cpu1.CUs1.wavefronts13 system.cpu1.CUs1.wavefronts14 system.cpu1.CUs1.wavefronts15 system.cpu1.CUs1.wavefronts16 system.cpu1.CUs1.wavefronts17 system.cpu1.CUs1.wavefronts18 system.cpu1.CUs1.wavefronts19 system.cpu1.CUs1.wavefronts20 system.cpu1.CUs1.wavefronts21 system.cpu1.CUs1.wavefronts22 system.cpu1.CUs1.wavefronts23 system.cpu1.CUs1.wavefronts24 system.cpu1.CUs1.wavefronts25 system.cpu1.CUs1.wavefronts26 system.cpu1.CUs1.wavefronts27 system.cpu1.CUs1.wavefronts28 system.cpu1.CUs1.wavefronts29 system.cpu1.CUs1.wavefronts30 system.cpu1.CUs1.wavefronts31 +wfSize=64 +xactCasMode=false +ldsPort=system.cpu1.CUs1.ldsBus.slave +memory_port=system.ruby.tcp_cntrl1.coalescer.slave[0] system.ruby.tcp_cntrl1.coalescer.slave[1] system.ruby.tcp_cntrl1.coalescer.slave[2] system.ruby.tcp_cntrl1.coalescer.slave[3] system.ruby.tcp_cntrl1.coalescer.slave[4] system.ruby.tcp_cntrl1.coalescer.slave[5] system.ruby.tcp_cntrl1.coalescer.slave[6] system.ruby.tcp_cntrl1.coalescer.slave[7] system.ruby.tcp_cntrl1.coalescer.slave[8] system.ruby.tcp_cntrl1.coalescer.slave[9] system.ruby.tcp_cntrl1.coalescer.slave[10] system.ruby.tcp_cntrl1.coalescer.slave[11] system.ruby.tcp_cntrl1.coalescer.slave[12] system.ruby.tcp_cntrl1.coalescer.slave[13] system.ruby.tcp_cntrl1.coalescer.slave[14] system.ruby.tcp_cntrl1.coalescer.slave[15] system.ruby.tcp_cntrl1.coalescer.slave[16] system.ruby.tcp_cntrl1.coalescer.slave[17] system.ruby.tcp_cntrl1.coalescer.slave[18] system.ruby.tcp_cntrl1.coalescer.slave[19] system.ruby.tcp_cntrl1.coalescer.slave[20] system.ruby.tcp_cntrl1.coalescer.slave[21] system.ruby.tcp_cntrl1.coalescer.slave[22] system.ruby.tcp_cntrl1.coalescer.slave[23] system.ruby.tcp_cntrl1.coalescer.slave[24] system.ruby.tcp_cntrl1.coalescer.slave[25] system.ruby.tcp_cntrl1.coalescer.slave[26] system.ruby.tcp_cntrl1.coalescer.slave[27] system.ruby.tcp_cntrl1.coalescer.slave[28] system.ruby.tcp_cntrl1.coalescer.slave[29] system.ruby.tcp_cntrl1.coalescer.slave[30] system.ruby.tcp_cntrl1.coalescer.slave[31] system.ruby.tcp_cntrl1.coalescer.slave[32] system.ruby.tcp_cntrl1.coalescer.slave[33] system.ruby.tcp_cntrl1.coalescer.slave[34] system.ruby.tcp_cntrl1.coalescer.slave[35] system.ruby.tcp_cntrl1.coalescer.slave[36] system.ruby.tcp_cntrl1.coalescer.slave[37] system.ruby.tcp_cntrl1.coalescer.slave[38] system.ruby.tcp_cntrl1.coalescer.slave[39] system.ruby.tcp_cntrl1.coalescer.slave[40] system.ruby.tcp_cntrl1.coalescer.slave[41] system.ruby.tcp_cntrl1.coalescer.slave[42] system.ruby.tcp_cntrl1.coalescer.slave[43] system.ruby.tcp_cntrl1.coalescer.slave[44] system.ruby.tcp_cntrl1.coalescer.slave[45] system.ruby.tcp_cntrl1.coalescer.slave[46] system.ruby.tcp_cntrl1.coalescer.slave[47] system.ruby.tcp_cntrl1.coalescer.slave[48] system.ruby.tcp_cntrl1.coalescer.slave[49] system.ruby.tcp_cntrl1.coalescer.slave[50] system.ruby.tcp_cntrl1.coalescer.slave[51] system.ruby.tcp_cntrl1.coalescer.slave[52] system.ruby.tcp_cntrl1.coalescer.slave[53] system.ruby.tcp_cntrl1.coalescer.slave[54] system.ruby.tcp_cntrl1.coalescer.slave[55] system.ruby.tcp_cntrl1.coalescer.slave[56] system.ruby.tcp_cntrl1.coalescer.slave[57] system.ruby.tcp_cntrl1.coalescer.slave[58] system.ruby.tcp_cntrl1.coalescer.slave[59] system.ruby.tcp_cntrl1.coalescer.slave[60] system.ruby.tcp_cntrl1.coalescer.slave[61] system.ruby.tcp_cntrl1.coalescer.slave[62] system.ruby.tcp_cntrl1.coalescer.slave[63] +sqc_port=system.ruby.sqc_cntrl0.sequencer.slave[1] +sqc_tlb_port=system.sqc_coalescer.slave[1] +translation_port=system.l1_coalescer1.slave[0] + +[system.cpu1.CUs1.ldsBus] +type=Bridge +clk_domain=system.cpu1.clk_domain +delay=0 +eventq_index=0 +ranges=0:18446744073709551615 +req_size=16 +resp_size=16 +master=system.cpu1.CUs1.localDataStore.cuPort +slave=system.cpu1.CUs1.ldsPort + +[system.cpu1.CUs1.localDataStore] +type=LdsState +bankConflictPenalty=1 +banks=32 +clk_domain=system.cpu1.clk_domain +eventq_index=0 +range=0:65535 +size=65536 +cuPort=system.cpu1.CUs1.ldsBus.master + +[system.cpu1.CUs1.vector_register_file0] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=0 + +[system.cpu1.CUs1.vector_register_file1] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=1 + +[system.cpu1.CUs1.vector_register_file2] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=2 + +[system.cpu1.CUs1.vector_register_file3] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=3 + +[system.cpu1.CUs1.wavefronts00] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts01] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts02] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts03] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts04] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts05] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts06] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts07] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts08] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts09] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts10] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts11] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts12] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts13] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts14] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts15] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts16] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts17] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts18] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts19] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts20] +type=Wavefront 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+eventq_index=0 +simdId=3 +wf_slot_id=7 + +[system.cpu1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu1.clk_domain.voltage_domain + +[system.cpu1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu2] +type=GpuDispatcher +children=cl_driver +cl_driver=system.cpu2.cl_driver +clk_domain=system.clk_domain +cpu=system.cpu0 +eventq_index=0 +pio_addr=8589934592 +pio_latency=1000 +shader_pointer=system.cpu1 +system=system +dma=system.piobus.slave[1] +pio=system.piobus.master[0] +translation_port=system.dispatcher_coalescer.slave[0] + +[system.cpu2.cl_driver] +type=ClDriver +codefile=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +eventq_index=0 +filename=hsa + +[system.dispatcher_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.dispatcher_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.dispatcher_tlb.slave[0] +slave=system.cpu2.translation_port + +[system.dispatcher_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.dispatcher_coalescer.clk_domain.voltage_domain + +[system.dispatcher_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.dispatcher_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.dispatcher_tlb.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[1] +slave=system.dispatcher_coalescer.master[0] + +[system.dispatcher_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.dispatcher_tlb.clk_domain.voltage_domain + +[system.dispatcher_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l1_coalescer0] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l1_coalescer0.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l1_tlb0.slave[0] +slave=system.cpu1.CUs0.translation_port[0] + +[system.l1_coalescer0.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_coalescer0.clk_domain.voltage_domain + +[system.l1_coalescer0.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_coalescer1] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l1_coalescer1.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l1_tlb1.slave[0] +slave=system.cpu1.CUs1.translation_port[0] + +[system.l1_coalescer1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_coalescer1.clk_domain.voltage_domain + +[system.l1_coalescer1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_tlb0] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l1_tlb0.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[2] +slave=system.l1_coalescer0.master[0] + +[system.l1_tlb0.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_tlb0.clk_domain.voltage_domain + +[system.l1_tlb0.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_tlb1] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l1_tlb1.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[3] +slave=system.l1_coalescer1.master[0] + +[system.l1_tlb1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_tlb1.clk_domain.voltage_domain + +[system.l1_tlb1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l2_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l2_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l2_tlb.slave[0] +slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0] + +[system.l2_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l2_coalescer.clk_domain.voltage_domain + +[system.l2_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l2_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l2_tlb.clk_domain +eventq_index=0 +hitLatency=69 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=4096 +master=system.l3_coalescer.slave[0] +slave=system.l2_coalescer.master[0] + +[system.l2_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l2_tlb.clk_domain.voltage_domain + +[system.l2_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l3_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l3_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l3_tlb.slave[0] +slave=system.l2_tlb.master[0] + +[system.l3_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l3_coalescer.clk_domain.voltage_domain + +[system.l3_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l3_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l3_tlb.clk_domain +eventq_index=0 +hitLatency=150 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=8192 +slave=system.l3_coalescer.master[0] + +[system.l3_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l3_tlb.clk_domain.voltage_domain + +[system.l3_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.ruby.dir_cntrl0.memory + +[system.piobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=0 +response_latency=0 +use_default_range=false +width=32 +master=system.cpu2.pio +slave=system.ruby.cp_cntrl0.sequencer.mem_master_port system.cpu2.dma + +[system.ruby] +type=RubySystem +children=clk_domain cp_cntrl0 dir_cntrl0 network phys_mem sqc_cntrl0 tcc_cntrl0 tcp_cntrl0 tcp_cntrl1 +access_backing_store=true +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=5 +number_of_virtual_networks=10 +phys_mem=system.ruby.phys_mem +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.cp_cntrl0] +type=CorePair_Controller +children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore +L1D0cache=system.ruby.cp_cntrl0.L1D0cache +L1D1cache=system.ruby.cp_cntrl0.L1D1cache +L1Icache=system.ruby.cp_cntrl0.L1Icache +L2cache=system.ruby.cp_cntrl0.L2cache +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +eventq_index=0 +issue_latency=120 +l2_hit_latency=18 +mandatoryQueue=system.ruby.cp_cntrl0.mandatoryQueue +number_of_TBEs=256 +probeToCore=system.ruby.cp_cntrl0.probeToCore +recycle_latency=10 +requestFromCore=system.ruby.cp_cntrl0.requestFromCore +responseFromCore=system.ruby.cp_cntrl0.responseFromCore +responseToCore=system.ruby.cp_cntrl0.responseToCore +ruby_system=system.ruby +send_evictions=true +sequencer=system.ruby.cp_cntrl0.sequencer +sequencer1=system.ruby.cp_cntrl0.sequencer1 +system=system +transitions_per_cycle=32 +triggerQueue=system.ruby.cp_cntrl0.triggerQueue +unblockFromCore=system.ruby.cp_cntrl0.unblockFromCore +version=0 + +[system.ruby.cp_cntrl0.L1D0cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=2 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.cp_cntrl0.L1D0cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=65536 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=2 + +[system.ruby.cp_cntrl0.L1D0cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=65536 + +[system.ruby.cp_cntrl0.L1D1cache] +type=RubyCache +children=replacement_policy +assoc=2 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+assoc=8 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.cp_cntrl0.L2cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=2097152 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=16 + +[system.ruby.cp_cntrl0.L2cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=2097152 + +[system.ruby.cp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.cp_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[3] + +[system.ruby.cp_cntrl0.requestFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.ruby.cp_cntrl0.responseFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[3] + +[system.ruby.cp_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[4] + +[system.ruby.cp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.ruby.clk_domain +coreid=0 +dcache=system.ruby.cp_cntrl0.L1D0cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.ruby.cp_cntrl0.L1Icache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave +mem_master_port=system.piobus.slave[0] +slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master + +[system.ruby.cp_cntrl0.sequencer1] +type=RubySequencer +clk_domain=system.ruby.clk_domain +coreid=1 +dcache=system.ruby.cp_cntrl0.L1D1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.ruby.cp_cntrl0.L1Icache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=1 + +[system.ruby.cp_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.cp_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.ruby.dir_cntrl0] +type=Directory_Controller +children=L3CacheMemory L3triggerQueue directory probeToCore requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue 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+node_a=system.ruby.network.ext_links0.int_node +node_b=system.ruby.network.ext_links2.int_node +weight=1 + +[system.ruby.phys_mem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.ruby.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=false +latency=30000 +latency_var=0 +null=false +range=0:536870911 + +[system.ruby.sqc_cntrl0] +type=SQC_Controller +children=L1cache mandatoryQueue probeToSQC requestFromSQC responseToSQC sequencer +L1cache=system.ruby.sqc_cntrl0.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +eventq_index=0 +issue_latency=80 +l2_hit_latency=18 +mandatoryQueue=system.ruby.sqc_cntrl0.mandatoryQueue +number_of_TBEs=256 +probeToSQC=system.ruby.sqc_cntrl0.probeToSQC +recycle_latency=10 +requestFromSQC=system.ruby.sqc_cntrl0.requestFromSQC +responseToSQC=system.ruby.sqc_cntrl0.responseToSQC +ruby_system=system.ruby +sequencer=system.ruby.sqc_cntrl0.sequencer +system=system +transitions_per_cycle=32 +version=0 + +[system.ruby.sqc_cntrl0.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=8 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.sqc_cntrl0.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=32768 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=8 + +[system.ruby.sqc_cntrl0.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=32768 + +[system.ruby.sqc_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.sqc_cntrl0.probeToSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[9] + +[system.ruby.sqc_cntrl0.requestFromSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[11] + +[system.ruby.sqc_cntrl0.responseToSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[10] + +[system.ruby.sqc_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.ruby.clk_domain +coreid=99 +dcache=system.ruby.sqc_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.ruby.sqc_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=false +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=6 +slave=system.cpu1.CUs0.sqc_port system.cpu1.CUs1.sqc_port + +[system.ruby.tcc_cntrl0] +type=TCC_Controller +children=L2cache probeFromNB requestFromTCP requestToNB responseFromNB responseToCore responseToNB triggerQueue unblockToNB +L2cache=system.ruby.tcc_cntrl0.L2cache +WB=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +eventq_index=0 +l2_request_latency=120 +l2_response_latency=16 +number_of_TBEs=5120 +probeFromNB=system.ruby.tcc_cntrl0.probeFromNB +recycle_latency=10 +requestFromTCP=system.ruby.tcc_cntrl0.requestFromTCP +requestToNB=system.ruby.tcc_cntrl0.requestToNB +responseFromNB=system.ruby.tcc_cntrl0.responseFromNB +responseToCore=system.ruby.tcc_cntrl0.responseToCore +responseToNB=system.ruby.tcc_cntrl0.responseToNB +ruby_system=system.ruby +system=system +transitions_per_cycle=32 +triggerQueue=system.ruby.tcc_cntrl0.triggerQueue +unblockToNB=system.ruby.tcc_cntrl0.unblockToNB +version=0 + +[system.ruby.tcc_cntrl0.L2cache] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=8 +dataArrayBanks=256 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.tcc_cntrl0.L2cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=262144 +start_index_bit=6 +tagAccessLatency=2 +tagArrayBanks=256 + +[system.ruby.tcc_cntrl0.L2cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=262144 + +[system.ruby.tcc_cntrl0.probeFromNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[12] + +[system.ruby.tcc_cntrl0.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[11] + +[system.ruby.tcc_cntrl0.requestToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[13] + +[system.ruby.tcc_cntrl0.responseFromNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[13] + +[system.ruby.tcc_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[12] + +[system.ruby.tcc_cntrl0.responseToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[14] + +[system.ruby.tcc_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.tcc_cntrl0.unblockToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[15] + +[system.ruby.tcp_cntrl0] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.ruby.tcp_cntrl0.L1cache +TCC_select_num_bits=0 +WB=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +coalescer=system.ruby.tcp_cntrl0.coalescer +disableL1=false +eventq_index=0 +issue_latency=1 +l2_hit_latency=18 +mandatoryQueue=system.ruby.tcp_cntrl0.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.ruby.tcp_cntrl0.probeToTCP +recycle_latency=10 +requestFromTCP=system.ruby.tcp_cntrl0.requestFromTCP +responseFromTCP=system.ruby.tcp_cntrl0.responseFromTCP +responseToTCP=system.ruby.tcp_cntrl0.responseToTCP +ruby_system=system.ruby +sequencer=system.ruby.tcp_cntrl0.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.ruby.tcp_cntrl0.unblockFromCore +use_seq_not_coal=false +version=0 + +[system.ruby.tcp_cntrl0.L1cache] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.tcp_cntrl0.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=16 + +[system.ruby.tcp_cntrl0.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=16384 + +[system.ruby.tcp_cntrl0.coalescer] +type=VIPERCoalescer +assume_rfo=false +clk_domain=system.ruby.clk_domain +coreid=99 +dcache=system.ruby.tcp_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.ruby.tcp_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_inv_per_cycle=32 +max_outstanding_requests=2560 +max_wb_per_cycle=32 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=false +version=2 +slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63] + +[system.ruby.tcp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.tcp_cntrl0.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[5] + +[system.ruby.tcp_cntrl0.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[5] + +[system.ruby.tcp_cntrl0.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[6] + +[system.ruby.tcp_cntrl0.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[6] + +[system.ruby.tcp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.ruby.clk_domain +coreid=99 +dcache=system.ruby.tcp_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.ruby.tcp_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=3 + +[system.ruby.tcp_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[7] + +[system.ruby.tcp_cntrl1] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.ruby.tcp_cntrl1.L1cache +TCC_select_num_bits=0 +WB=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +cluster_id=0 +coalescer=system.ruby.tcp_cntrl1.coalescer +disableL1=false +eventq_index=0 +issue_latency=1 +l2_hit_latency=18 +mandatoryQueue=system.ruby.tcp_cntrl1.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.ruby.tcp_cntrl1.probeToTCP +recycle_latency=10 +requestFromTCP=system.ruby.tcp_cntrl1.requestFromTCP +responseFromTCP=system.ruby.tcp_cntrl1.responseFromTCP +responseToTCP=system.ruby.tcp_cntrl1.responseToTCP +ruby_system=system.ruby +sequencer=system.ruby.tcp_cntrl1.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.ruby.tcp_cntrl1.unblockFromCore +use_seq_not_coal=false +version=1 + +[system.ruby.tcp_cntrl1.L1cache] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.ruby.tcp_cntrl1.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=16 + +[system.ruby.tcp_cntrl1.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=16384 + +[system.ruby.tcp_cntrl1.coalescer] +type=VIPERCoalescer +assume_rfo=false +clk_domain=system.ruby.clk_domain +coreid=99 +dcache=system.ruby.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.ruby.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_inv_per_cycle=32 +max_outstanding_requests=2560 +max_wb_per_cycle=32 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=false +version=4 +slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63] + +[system.ruby.tcp_cntrl1.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.ruby.tcp_cntrl1.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[7] + +[system.ruby.tcp_cntrl1.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[8] + +[system.ruby.tcp_cntrl1.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[9] + +[system.ruby.tcp_cntrl1.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[8] + +[system.ruby.tcp_cntrl1.sequencer] +type=RubySequencer +clk_domain=system.ruby.clk_domain +coreid=99 +dcache=system.ruby.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.ruby.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=5 + +[system.ruby.tcp_cntrl1.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[10] + +[system.sqc_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.sqc_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.sqc_tlb.slave[0] +slave=system.cpu1.CUs0.sqc_tlb_port system.cpu1.CUs1.sqc_tlb_port + +[system.sqc_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.sqc_coalescer.clk_domain.voltage_domain + +[system.sqc_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.sqc_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.sqc_tlb.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[0] +slave=system.sqc_coalescer.master[0] + +[system.sqc_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.sqc_tlb.clk_domain.voltage_domain + +[system.sqc_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simerr b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simerr new file mode 100755 index 000000000..1e2b8911e --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simerr @@ -0,0 +1,5 @@ +warn: system.ruby.network adopting orphan SimObject param 'int_links' +warn: system.ruby.network adopting orphan SimObject param 'ext_links' +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simout new file mode 100755 index 000000000..3b7ae46db --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/simout @@ -0,0 +1,21 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 19 2016 13:36:44 +gem5 started Jan 19 2016 13:37:09 +gem5 executing on zizzer, pid 49676 +command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER + +Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +Global frequency set at 1000000000000 ticks per second +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +info: Entering event queue @ 0. Starting simulation... +keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23 +the gpu says: +elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe +Exiting @ tick 314399500 because target called exit() diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/stats.txt new file mode 100644 index 000000000..7e23ea73c --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER/stats.txt @@ -0,0 +1,3201 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000314 # Number of seconds simulated +sim_ticks 314399500 # Number of ticks simulated +final_tick 314399500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 59851 # Simulator instruction rate (inst/s) +host_op_rate 123077 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 280996968 # Simulator tick rate (ticks/s) +host_mem_usage 1296852 # Number of bytes of host memory used +host_seconds 1.12 # Real time elapsed on the host +sim_insts 66963 # Number of instructions simulated +sim_ops 137705 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrls.bytes_read::ruby.dir_cntrl0 99840 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 99840 # Number of bytes read from this memory +system.mem_ctrls.num_reads::ruby.dir_cntrl0 1560 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1560 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::ruby.dir_cntrl0 317557757 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 317557757 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::ruby.dir_cntrl0 317557757 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 317557757 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1560 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1560 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 99840 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 99840 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 314257000 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1560 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1544 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 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req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 398 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 247.798995 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 164.777646 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 248.151006 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 138 34.67% 34.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 115 28.89% 63.57% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 55 13.82% 77.39% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 30 7.54% 84.92% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 19 4.77% 89.70% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 13 3.27% 92.96% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7 1.76% 94.72% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 7 1.76% 96.48% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 14 3.52% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 398 # Bytes accessed per row activation +system.mem_ctrls.totQLat 12586250 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 41836250 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 7800000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 8068.11 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 26818.11 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 317.56 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 317.56 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 2.48 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 2.48 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.04 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 1157 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 74.17 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.avgGap 201446.79 # Average gap between requests +system.mem_ctrls.pageHitRate 74.17 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1141560 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 622875 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 20342400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 179243055 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 29795250 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 236480340 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 758.654968 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 51073000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 10400000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 252847000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 1867320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1018875 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6684600 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 20342400 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 198048780 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 13299000 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 241260975 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 773.991771 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 20941500 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 10400000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 280382250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.ruby.clk_domain.clock 500 # Clock period in ticks +system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory +system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory +system.ruby.phys_mem.bw_read::cpu0.inst 2216161285 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu0.data 381145644 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 10432587 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 10432587 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::total 2618172103 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu0.inst 2216161285 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 6361333 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 6361333 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::total 2228883952 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu0.data 231447569 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 814251 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 814251 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::total 233076070 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.inst 2216161285 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.data 612593213 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 11246837 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 11246837 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::total 2851248173 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.clk_domain.clock 500 # Clock period in ticks +system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu0.workload.num_syscalls 21 # Number of system calls +system.cpu0.numCycles 628799 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 66963 # Number of instructions committed +system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses +system.cpu0.num_func_calls 3196 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136380 # number of integer instructions +system.cpu0.num_fp_insts 1279 # number of float instructions +system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written +system.cpu0.num_mem_refs 27198 # number of memory refs +system.cpu0.num_load_insts 16684 # Number of load instructions +system.cpu0.num_store_insts 10514 # Number of store instructions +system.cpu0.num_idle_cycles 8671.003972 # Number of idle cycles +system.cpu0.num_busy_cycles 620127.996028 # Number of busy cycles +system.cpu0.not_idle_fraction 0.986210 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.013790 # Percentage of idle cycles +system.cpu0.Branches 16199 # Number of branches fetched +system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction +system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction +system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction +system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction +system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 137705 # Class of executed instruction +system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.cpu1.clk_domain.clock 1000 # Clock period in ticks +system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 216 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 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source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 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+system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 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number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 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with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 195 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 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source register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 194 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 177 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 4663 # number of cycles the CU issues nothing +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 102 # number of cycles the CU issued at least one instruction +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1993 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 288 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 325 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 248 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 341 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 27 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.spc::samples 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::mean 0.029591 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::stdev 0.214321 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::0 4663 97.86% 97.86% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::1 65 1.36% 99.22% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::2 35 0.73% 99.96% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::3 2 0.04% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::total 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 66 # number of CU transitions from active to idle +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 66 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 61.575758 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 253.572448 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 45 68.18% 68.18% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 10 15.15% 83.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 83.33% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.52% 84.85% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 3.03% 87.88% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.52% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.39% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 10.61% 100.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1685 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 66 # duration of idle periods in cycles +system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF +system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests +system.cpu1.CUs0.tlb_cycles -212991640500 # total number of cycles for all uncoalesced requests +system.cpu1.CUs0.avg_translation_latency -276972224.317295 # Avg. translation latency for data translations +system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses +system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count +system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count +system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity +system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed +system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::mean 81.602837 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::stdev 244.924445 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::4-5 57 40.43% 49.65% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::6-7 28 19.86% 69.50% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::8-9 2 1.42% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::max_value 1686 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst) +system.cpu1.CUs0.num_total_cycles 4765 # number of cycles the CU ran for +system.cpu1.CUs0.vpc 1.420567 # Vector Operations per cycle (this CU only) +system.cpu1.CUs0.ipc 0.029591 # Instructions per cycle (this CU only) +system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction +system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed +system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD +system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations +system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed +system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts +system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 216 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 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with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 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number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 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with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 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+system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 195 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 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source register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 190 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 176 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies 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source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands 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number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands 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instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 4667 # number of cycles the CU issues nothing +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 98 # number of cycles the CU issued at least one instruction +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 2052 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 327 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 265 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 285 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 341 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 32 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.spc::samples 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::mean 0.029591 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::stdev 0.218204 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::0 4667 97.94% 97.94% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::1 57 1.20% 99.14% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::2 39 0.82% 99.96% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::3 2 0.04% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::total 4765 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 68 # number of CU transitions from active to idle +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 68 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 61 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 257.808908 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 49 72.06% 72.06% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 8 11.76% 83.82% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 83.82% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.94% 86.76% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 1 1.47% 88.24% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.47% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 10.29% 100.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1764 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 68 # duration of idle periods in cycles +system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF +system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests +system.cpu1.CUs1.tlb_cycles -212991830500 # total number of cycles for all uncoalesced requests +system.cpu1.CUs1.avg_translation_latency -276972471.391417 # Avg. translation latency for data translations +system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses +system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count +system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count +system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity +system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed +system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::mean 82.212766 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::stdev 248.914352 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::6-7 28 19.86% 66.67% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::8-9 5 3.55% 70.21% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::overflows 41 29.08% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::max_value 1765 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst) +system.cpu1.CUs1.num_total_cycles 4765 # number of cycles the CU ran for +system.cpu1.CUs1.vpc 1.419098 # Vector Operations per cycle (this CU only) +system.cpu1.CUs1.ipc 0.029591 # Instructions per cycle (this CU only) +system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction +system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed +system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD +system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations +system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed +system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts +system.cpu2.num_kernel_launched 1 # number of kernel launched +system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses +system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses +system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue +system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts +system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses +system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits +system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses +system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate +system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses +system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits +system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses +system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate +system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level +system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched +system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs +system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses +system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses +system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue +system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts +system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses +system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses +system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue +system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts +system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses +system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits +system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses +system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate +system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses +system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits +system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses +system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate +system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level +system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table +system.l1_tlb0.unique_pages 4 # Number of unique pages touched +system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs +system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses +system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits +system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses +system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate +system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses +system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits +system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses +system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate +system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level +system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table +system.l1_tlb1.unique_pages 3 # Number of unique pages touched +system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs +system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses +system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses +system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue +system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs +system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts +system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses +system.l2_tlb.local_TLB_hits 3 # Number of TLB hits +system.l2_tlb.local_TLB_misses 5 # Number of TLB misses +system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate +system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses +system.l2_tlb.global_TLB_hits 3 # Number of TLB hits +system.l2_tlb.global_TLB_misses 12 # Number of TLB misses +system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate +system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level +system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.l2_tlb.unique_pages 5 # Number of unique pages touched +system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs +system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs +system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses +system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses +system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue +system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs +system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts +system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses +system.l3_tlb.local_TLB_hits 0 # Number of TLB hits +system.l3_tlb.local_TLB_misses 5 # Number of TLB misses +system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate +system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses +system.l3_tlb.global_TLB_hits 0 # Number of TLB hits +system.l3_tlb.global_TLB_misses 12 # Number of TLB misses +system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate +system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level +system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table +system.l3_tlb.unique_pages 5 # Number of unique pages touched +system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs +system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs +system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.piobus.trans_dist::WriteReq 94 # Transaction distribution +system.piobus.trans_dist::WriteResp 94 # Transaction distribution +system.piobus.pkt_count_system.ruby.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) +system.piobus.pkt_size_system.ruby.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) +system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) +system.piobus.reqLayer0.occupancy 234500 # Layer occupancy (ticks) +system.piobus.reqLayer0.utilization 0.1 # Layer utilization (%) +system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) +system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 114203 +system.ruby.outstanding_req_hist::mean 1.000035 +system.ruby.outstanding_req_hist::gmean 1.000024 +system.ruby.outstanding_req_hist::stdev 0.005918 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 114203 +system.ruby.latency_hist::bucket_size 128 +system.ruby.latency_hist::max_bucket 1279 +system.ruby.latency_hist::samples 114203 +system.ruby.latency_hist::mean 4.423518 +system.ruby.latency_hist::gmean 1.078765 +system.ruby.latency_hist::stdev 30.010569 +system.ruby.latency_hist | 112668 98.66% 98.66% | 1136 0.99% 99.65% | 372 0.33% 99.98% | 3 0.00% 99.98% | 8 0.01% 99.99% | 14 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 114203 +system.ruby.hit_latency_hist::bucket_size 128 +system.ruby.hit_latency_hist::max_bucket 1279 +system.ruby.hit_latency_hist::samples 1535 +system.ruby.hit_latency_hist::mean 255.015635 +system.ruby.hit_latency_hist::gmean 251.519163 +system.ruby.hit_latency_hist::stdev 57.825523 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 1136 74.01% 74.01% | 372 24.23% 98.24% | 3 0.20% 98.44% | 8 0.52% 98.96% | 14 0.91% 99.87% | 2 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 1535 +system.ruby.miss_latency_hist::bucket_size 2 +system.ruby.miss_latency_hist::max_bucket 19 +system.ruby.miss_latency_hist::samples 112668 +system.ruby.miss_latency_hist::mean 1.009426 +system.ruby.miss_latency_hist::gmean 1.001543 +system.ruby.miss_latency_hist::stdev 0.411800 +system.ruby.miss_latency_hist | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% +system.ruby.miss_latency_hist::total 112668 +system.ruby.L1Cache.incomplete_times 112609 +system.ruby.L2Cache.incomplete_times 59 +system.ruby.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits +system.ruby.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses +system.ruby.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses +system.ruby.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads +system.ruby.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes +system.ruby.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads +system.ruby.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes +system.ruby.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits +system.ruby.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses +system.ruby.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses +system.ruby.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits +system.ruby.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses +system.ruby.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses +system.ruby.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads +system.ruby.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes +system.ruby.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads +system.ruby.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes +system.ruby.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.ruby.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses +system.ruby.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses +system.ruby.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads +system.ruby.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes +system.ruby.cp_cntrl0.L2cache.num_tag_array_reads 12068 # number of tag array reads +system.ruby.cp_cntrl0.L2cache.num_tag_array_writes 1658 # number of tag array writes +system.ruby.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits +system.ruby.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses +system.ruby.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses +system.ruby.dir_cntrl0.L3CacheMemory.num_data_array_writes 1560 # number of data array writes +system.ruby.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1560 # number of tag array reads +system.ruby.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1578 # number of tag array writes +system.ruby.network.ext_links0.int_node.percent_links_utilized 1.075754 +system.ruby.network.ext_links0.int_node.msg_count.Control::0 1560 +system.ruby.network.ext_links0.int_node.msg_count.Data::0 18 +system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1542 +system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1546 +system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 1558 +system.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1541 +system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 12480 +system.ruby.network.ext_links0.int_node.msg_bytes.Data::0 1296 +system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12336 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 111312 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 12464 +system.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12328 +system.ruby.network.ext_links1.int_node.percent_links_utilized 1.347807 +system.ruby.network.ext_links1.int_node.msg_count.Control::0 25 +system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 +system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 +system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 23 +system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1534 +system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 200 +system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 +system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 +system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 184 +system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12272 +system.ruby.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.ruby.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.ruby.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.ruby.tcp_cntrl0.L1cache.num_data_array_reads 6 # number of data array reads +system.ruby.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes +system.ruby.tcp_cntrl0.L1cache.num_tag_array_reads 1297 # number of tag array reads +system.ruby.tcp_cntrl0.L1cache.num_tag_array_writes 11 # number of tag array writes +system.ruby.tcp_cntrl0.L1cache.num_tag_array_stalls 5082 # number of stalls caused by tag array +system.ruby.tcp_cntrl0.L1cache.num_data_array_stalls 6 # number of stalls caused by data array +system.ruby.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.ruby.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers +system.ruby.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.ruby.tcp_cntrl0.coalescer.gpu_ld_misses 5 # loads that miss in the GPU +system.ruby.tcp_cntrl0.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP +system.ruby.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers +system.ruby.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.ruby.tcp_cntrl0.coalescer.gpu_st_misses 9 # stores that miss in the GPU +system.ruby.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.ruby.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.ruby.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.ruby.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.ruby.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.ruby.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.ruby.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.ruby.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.ruby.network.ext_links2.int_node.percent_links_utilized 0.115426 +system.ruby.network.ext_links2.int_node.msg_count.Control::0 1535 +system.ruby.network.ext_links2.int_node.msg_count.Data::0 18 +system.ruby.network.ext_links2.int_node.msg_count.Data::1 18 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 7 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 9 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 9 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 11 +system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1535 +system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::3 16 +system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 7 +system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 12280 +system.ruby.network.ext_links2.int_node.msg_bytes.Data::0 1296 +system.ruby.network.ext_links2.int_node.msg_bytes.Data::1 1296 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 56 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 72 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 648 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 792 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 12280 +system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::3 128 +system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 56 +system.ruby.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits +system.ruby.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses +system.ruby.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses +system.ruby.tcp_cntrl1.L1cache.num_data_array_reads 6 # number of data array reads +system.ruby.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes +system.ruby.tcp_cntrl1.L1cache.num_tag_array_reads 1297 # number of tag array reads +system.ruby.tcp_cntrl1.L1cache.num_tag_array_writes 11 # number of tag array writes +system.ruby.tcp_cntrl1.L1cache.num_tag_array_stalls 5082 # number of stalls caused by tag array +system.ruby.tcp_cntrl1.L1cache.num_data_array_stalls 6 # number of stalls caused by data array +system.ruby.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.ruby.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers +system.ruby.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.ruby.tcp_cntrl1.coalescer.gpu_ld_misses 5 # loads that miss in the GPU +system.ruby.tcp_cntrl1.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP +system.ruby.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers +system.ruby.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.ruby.tcp_cntrl1.coalescer.gpu_st_misses 9 # stores that miss in the GPU +system.ruby.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.ruby.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.ruby.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.ruby.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.ruby.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.ruby.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.ruby.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.ruby.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.ruby.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.ruby.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.ruby.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.ruby.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads +system.ruby.sqc_cntrl0.L1cache.num_tag_array_reads 91 # number of tag array reads +system.ruby.sqc_cntrl0.L1cache.num_tag_array_writes 10 # number of tag array writes +system.ruby.sqc_cntrl0.sequencer.load_waiting_on_load 97 # Number of times a load aliased with a pending load +system.ruby.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.ruby.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses +system.ruby.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses +system.ruby.tcc_cntrl0.L2cache.num_data_array_writes 9 # number of data array writes +system.ruby.tcc_cntrl0.L2cache.num_tag_array_reads 1569 # number of tag array reads +system.ruby.tcc_cntrl0.L2cache.num_tag_array_writes 1545 # number of tag array writes +system.ruby.tcc_cntrl0.L2cache.num_tag_array_stalls 1 # number of stalls caused by tag array +system.ruby.network.msg_count.Control 3120 +system.ruby.network.msg_count.Data 54 +system.ruby.network.msg_count.Request_Control 3093 +system.ruby.network.msg_count.Response_Data 3103 +system.ruby.network.msg_count.Response_Control 3116 +system.ruby.network.msg_count.Writeback_Control 48 +system.ruby.network.msg_count.Unblock_Control 3082 +system.ruby.network.msg_byte.Control 24960 +system.ruby.network.msg_byte.Data 3888 +system.ruby.network.msg_byte.Request_Control 24744 +system.ruby.network.msg_byte.Response_Data 223416 +system.ruby.network.msg_byte.Response_Control 24928 +system.ruby.network.msg_byte.Writeback_Control 384 +system.ruby.network.msg_byte.Unblock_Control 24656 +system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses +system.sqc_coalescer.coalesced_accesses 48 # Number of coalesced TLB accesses +system.sqc_coalescer.queuing_cycles 211000 # Number of cycles spent in queue +system.sqc_coalescer.local_queuing_cycles 211000 # Number of cycles spent in queue for all incoming reqs +system.sqc_coalescer.local_latency 2453.488372 # Avg. latency over all incoming pkts +system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks +system.sqc_tlb.local_TLB_accesses 48 # Number of TLB accesses +system.sqc_tlb.local_TLB_hits 47 # Number of TLB hits +system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses +system.sqc_tlb.local_TLB_miss_rate 2.083333 # TLB miss rate +system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses +system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits +system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses +system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate +system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level +system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.sqc_tlb.unique_pages 1 # Number of unique pages touched +system.sqc_tlb.local_cycles 48001 # Number of cycles spent in queue for all incoming reqs +system.sqc_tlb.local_latency 1000.020833 # Avg. latency over incoming coalesced reqs +system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.766700 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0 18 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1542 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 2 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 1558 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1541 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Data::0 1296 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 12336 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 144 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 12464 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12328 +system.ruby.network.ext_links0.int_node.throttle1.link_utilization 2.201021 +system.ruby.network.ext_links0.int_node.throttle1.msg_count.Control::0 25 +system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Data::2 1535 +system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Control::0 200 +system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Data::2 110520 +system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.259542 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Control::0 1535 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 9 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Control::0 12280 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 648 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links1.int_node.throttle0.link_utilization 2.201021 +system.ruby.network.ext_links1.int_node.throttle0.msg_count.Control::0 25 +system.ruby.network.ext_links1.int_node.throttle0.msg_count.Response_Data::2 1535 +system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Control::0 200 +system.ruby.network.ext_links1.int_node.throttle0.msg_bytes.Response_Data::2 110520 +system.ruby.network.ext_links1.int_node.throttle1.link_utilization 0.494594 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Request_Control::0 1535 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Data::2 2 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Response_Control::2 23 +system.ruby.network.ext_links1.int_node.throttle1.msg_count.Unblock_Control::4 1534 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Request_Control::0 12280 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Data::2 144 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Response_Control::2 184 +system.ruby.network.ext_links1.int_node.throttle1.msg_bytes.Unblock_Control::4 12272 +system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.005566 +system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 3 +system.ruby.network.ext_links2.int_node.throttle0.msg_count.Writeback_Control::3 8 +system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 216 +system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Writeback_Control::3 64 +system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.005566 +system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 3 +system.ruby.network.ext_links2.int_node.throttle1.msg_count.Writeback_Control::3 8 +system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 216 +system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Writeback_Control::3 64 +system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0.286737 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Control::0 1535 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Data::1 18 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::1 9 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2 9 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Control::0 12280 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Data::1 1296 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::1 72 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2 648 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.007156 +system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 5 +system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 360 +system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.272106 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Data::0 18 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Request_Control::0 7 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Control::2 1535 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Unblock_Control::4 7 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Data::0 1296 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Request_Control::0 56 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Control::2 12280 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Unblock_Control::4 56 +system.ruby.LD.latency_hist::bucket_size 128 +system.ruby.LD.latency_hist::max_bucket 1279 +system.ruby.LD.latency_hist::samples 16335 +system.ruby.LD.latency_hist::mean 3.784451 +system.ruby.LD.latency_hist::gmean 1.062267 +system.ruby.LD.latency_hist::stdev 27.056562 +system.ruby.LD.latency_hist | 16160 98.93% 98.93% | 90 0.55% 99.48% | 84 0.51% 99.99% | 0 0.00% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 16335 +system.ruby.LD.hit_latency_hist::bucket_size 128 +system.ruby.LD.hit_latency_hist::max_bucket 1279 +system.ruby.LD.hit_latency_hist::samples 175 +system.ruby.LD.hit_latency_hist::mean 260.394286 +system.ruby.LD.hit_latency_hist::gmean 258.339713 +system.ruby.LD.hit_latency_hist::stdev 42.039376 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 90 51.43% 51.43% | 84 48.00% 99.43% | 0 0.00% 99.43% | 0 0.00% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 175 +system.ruby.LD.miss_latency_hist::bucket_size 2 +system.ruby.LD.miss_latency_hist::max_bucket 19 +system.ruby.LD.miss_latency_hist::samples 16160 +system.ruby.LD.miss_latency_hist::mean 1.005569 +system.ruby.LD.miss_latency_hist::gmean 1.000911 +system.ruby.LD.miss_latency_hist::stdev 0.316580 +system.ruby.LD.miss_latency_hist | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% +system.ruby.LD.miss_latency_hist::total 16160 +system.ruby.ST.latency_hist::bucket_size 128 +system.ruby.ST.latency_hist::max_bucket 1279 +system.ruby.ST.latency_hist::samples 10412 +system.ruby.ST.latency_hist::mean 8.839992 +system.ruby.ST.latency_hist::gmean 1.186243 +system.ruby.ST.latency_hist::stdev 45.390081 +system.ruby.ST.latency_hist | 10090 96.91% 96.91% | 254 2.44% 99.35% | 62 0.60% 99.94% | 0 0.00% 99.94% | 1 0.01% 99.95% | 4 0.04% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 10412 +system.ruby.ST.hit_latency_hist::bucket_size 128 +system.ruby.ST.hit_latency_hist::max_bucket 1279 +system.ruby.ST.hit_latency_hist::samples 322 +system.ruby.ST.hit_latency_hist::mean 254.509317 +system.ruby.ST.hit_latency_hist::gmean 250.282441 +system.ruby.ST.hit_latency_hist::stdev 65.931487 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 254 78.88% 78.88% | 62 19.25% 98.14% | 0 0.00% 98.14% | 1 0.31% 98.45% | 4 1.24% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 322 +system.ruby.ST.miss_latency_hist::bucket_size 1 +system.ruby.ST.miss_latency_hist::max_bucket 9 +system.ruby.ST.miss_latency_hist::samples 10090 +system.ruby.ST.miss_latency_hist::mean 1 +system.ruby.ST.miss_latency_hist::gmean 1 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 10090 +system.ruby.IFETCH.latency_hist::bucket_size 128 +system.ruby.IFETCH.latency_hist::max_bucket 1279 +system.ruby.IFETCH.latency_hist::samples 87095 +system.ruby.IFETCH.latency_hist::mean 4.017395 +system.ruby.IFETCH.latency_hist::gmean 1.069735 +system.ruby.IFETCH.latency_hist::stdev 28.134930 +system.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 790 0.91% 99.72% | 224 0.26% 99.98% | 3 0.00% 99.98% | 7 0.01% 99.99% | 9 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 87095 +system.ruby.IFETCH.hit_latency_hist::bucket_size 128 +system.ruby.IFETCH.hit_latency_hist::max_bucket 1279 +system.ruby.IFETCH.hit_latency_hist::samples 1034 +system.ruby.IFETCH.hit_latency_hist::mean 254.218569 +system.ruby.IFETCH.hit_latency_hist::gmean 250.716467 +system.ruby.IFETCH.hit_latency_hist::stdev 57.514968 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 790 76.40% 76.40% | 224 21.66% 98.07% | 3 0.29% 98.36% | 7 0.68% 99.03% | 9 0.87% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 1034 +system.ruby.IFETCH.miss_latency_hist::bucket_size 2 +system.ruby.IFETCH.miss_latency_hist::max_bucket 19 +system.ruby.IFETCH.miss_latency_hist::samples 86061 +system.ruby.IFETCH.miss_latency_hist::mean 1.011294 +system.ruby.IFETCH.miss_latency_hist::gmean 1.001849 +system.ruby.IFETCH.miss_latency_hist::stdev 0.450747 +system.ruby.IFETCH.miss_latency_hist | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 86061 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0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 2 50.00% 50.00% | 0 0.00% 50.00% | 2 50.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 4 +system.ruby.RMW_Read.miss_latency_hist::bucket_size 1 +system.ruby.RMW_Read.miss_latency_hist::max_bucket 9 +system.ruby.RMW_Read.miss_latency_hist::samples 337 +system.ruby.RMW_Read.miss_latency_hist::mean 1 +system.ruby.RMW_Read.miss_latency_hist::gmean 1 +system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 337 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.latency_hist::samples 10 +system.ruby.Locked_RMW_Read.latency_hist::mean 1 +system.ruby.Locked_RMW_Read.latency_hist::gmean 1 +system.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 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0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 59 100.00% 100.00% +system.ruby.L2Cache.miss_mach_latency_hist::total 59 +system.ruby.Directory.hit_mach_latency_hist::bucket_size 128 +system.ruby.Directory.hit_mach_latency_hist::max_bucket 1279 +system.ruby.Directory.hit_mach_latency_hist::samples 1535 +system.ruby.Directory.hit_mach_latency_hist::mean 255.015635 +system.ruby.Directory.hit_mach_latency_hist::gmean 251.519163 +system.ruby.Directory.hit_mach_latency_hist::stdev 57.825523 +system.ruby.Directory.hit_mach_latency_hist | 0 0.00% 0.00% | 1136 74.01% 74.01% | 372 24.23% 98.24% | 3 0.20% 98.44% | 8 0.52% 98.96% | 14 0.91% 99.87% | 2 0.13% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.hit_mach_latency_hist::total 1535 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 16155 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1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.hit_type_mach_latency_hist::total 322 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples 86007 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total 86007 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size 2 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket 19 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples 54 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0.68% 99.03% | 9 0.87% 99.90% | 1 0.10% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1034 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 337 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total 337 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size 32 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket 319 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+system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% +system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% +system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% +system.ruby.CorePair_Controller.I.PrbInvData 17 0.00% 0.00% +system.ruby.CorePair_Controller.I.PrbShrData 5 0.00% 0.00% +system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% +system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% +system.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00% +system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% +system.ruby.CorePair_Controller.E0.C0_Load_L1hit 3356 0.00% 0.00% +system.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00% +system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% +system.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00% +system.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00% +system.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00% +system.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% +system.ruby.CorePair_Controller.I_E0S.NB_AckE 175 0.00% 0.00% +system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00% +system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% +system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% +system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% +system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkS 1034 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkM 326 0.00% 0.00% +system.ruby.Directory_Controller.RdBlk 182 0.00% 0.00% +system.ruby.Directory_Controller.WriteThrough 16 0.00% 0.00% +system.ruby.Directory_Controller.Atomic 3 0.00% 0.00% +system.ruby.Directory_Controller.CPUPrbResp 1560 0.00% 0.00% +system.ruby.Directory_Controller.ProbeAcksComplete 1560 0.00% 0.00% +system.ruby.Directory_Controller.MemData 1560 0.00% 0.00% +system.ruby.Directory_Controller.CoreUnblock 1541 0.00% 0.00% +system.ruby.Directory_Controller.UnblockWriteThrough 18 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkS 1034 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkM 326 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlk 182 0.00% 0.00% +system.ruby.Directory_Controller.U.WriteThrough 16 0.00% 0.00% +system.ruby.Directory_Controller.U.Atomic 2 0.00% 0.00% +system.ruby.Directory_Controller.BS_M.MemData 1034 0.00% 0.00% +system.ruby.Directory_Controller.BM_M.MemData 326 0.00% 0.00% +system.ruby.Directory_Controller.B_M.MemData 175 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.CPUPrbResp 1034 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 1034 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.Atomic 1 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.CPUPrbResp 326 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 326 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.MemData 18 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.CPUPrbResp 175 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 175 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.MemData 7 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 18 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 18 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.CPUPrbResp 7 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 7 0.00% 0.00% +system.ruby.Directory_Controller.B.CoreUnblock 1541 0.00% 0.00% +system.ruby.Directory_Controller.B.UnblockWriteThrough 18 0.00% 0.00% +system.ruby.SQC_Controller.Fetch 86 0.00% 0.00% +system.ruby.SQC_Controller.Data 5 0.00% 0.00% +system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% +system.ruby.SQC_Controller.I.Data 5 0.00% 0.00% +system.ruby.SQC_Controller.V.Fetch 81 0.00% 0.00% +system.ruby.TCC_Controller.RdBlk 9 0.00% 0.00% +system.ruby.TCC_Controller.WrVicBlk 16 0.00% 0.00% +system.ruby.TCC_Controller.Atomic 2 0.00% 0.00% +system.ruby.TCC_Controller.AtomicDone 1 0.00% 0.00% +system.ruby.TCC_Controller.Data 9 0.00% 0.00% +system.ruby.TCC_Controller.PrbInv 1535 0.00% 0.00% +system.ruby.TCC_Controller.WBAck 16 0.00% 0.00% +system.ruby.TCC_Controller.V.PrbInv 1 0.00% 0.00% +system.ruby.TCC_Controller.I.RdBlk 7 0.00% 0.00% +system.ruby.TCC_Controller.I.WrVicBlk 16 0.00% 0.00% +system.ruby.TCC_Controller.I.Atomic 1 0.00% 0.00% +system.ruby.TCC_Controller.I.PrbInv 1534 0.00% 0.00% +system.ruby.TCC_Controller.I.WBAck 16 0.00% 0.00% +system.ruby.TCC_Controller.IV.RdBlk 2 0.00% 0.00% +system.ruby.TCC_Controller.IV.Data 7 0.00% 0.00% +system.ruby.TCC_Controller.A.Atomic 1 0.00% 0.00% +system.ruby.TCC_Controller.A.AtomicDone 1 0.00% 0.00% +system.ruby.TCC_Controller.A.Data 2 0.00% 0.00% +system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00% +system.ruby.TCP_Controller.Load::total 10 +system.ruby.TCP_Controller.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.StoreThrough::total 16 +system.ruby.TCP_Controller.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.Atomic::total 2 +system.ruby.TCP_Controller.Flush | 768 50.00% 50.00% | 768 50.00% 100.00% +system.ruby.TCP_Controller.Flush::total 1536 +system.ruby.TCP_Controller.Evict | 512 50.00% 50.00% | 512 50.00% 100.00% +system.ruby.TCP_Controller.Evict::total 1024 +system.ruby.TCP_Controller.TCC_Ack | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.TCP_Controller.TCC_Ack::total 6 +system.ruby.TCP_Controller.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.TCC_AckWB::total 16 +system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.I.Load::total 4 +system.ruby.TCP_Controller.I.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.I.StoreThrough::total 16 +system.ruby.TCP_Controller.I.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.I.Atomic::total 2 +system.ruby.TCP_Controller.I.Flush | 766 50.00% 50.00% | 766 50.00% 100.00% +system.ruby.TCP_Controller.I.Flush::total 1532 +system.ruby.TCP_Controller.I.Evict | 510 50.00% 50.00% | 510 50.00% 100.00% +system.ruby.TCP_Controller.I.Evict::total 1020 +system.ruby.TCP_Controller.I.TCC_Ack | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.I.TCC_Ack::total 4 +system.ruby.TCP_Controller.I.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.I.TCC_AckWB::total 16 +system.ruby.TCP_Controller.V.Load | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.TCP_Controller.V.Load::total 6 +system.ruby.TCP_Controller.V.Flush | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.V.Flush::total 4 +system.ruby.TCP_Controller.V.Evict | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.V.Evict::total 4 +system.ruby.TCP_Controller.A.TCC_Ack | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.A.TCC_Ack::total 2 + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/config.ini new file mode 100644 index 000000000..b3fabf81b --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/config.ini @@ -0,0 +1,4089 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cp_cntrl0 cpu0 cpu1 cpu2 dir_cntrl0 dispatcher_coalescer dispatcher_tlb dvfs_handler l1_coalescer0 l1_coalescer1 l1_tlb0 l1_tlb1 l2_coalescer l2_tlb l3_coalescer l3_tlb mem_ctrls piobus ruby sqc_cntrl0 sqc_coalescer sqc_tlb sys_port_proxy tcc_cntrl0 tcp_cntrl0 tcp_cntrl1 voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrls system.ruby.phys_mem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cp_cntrl0] +type=CorePair_Controller +children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore +L1D0cache=system.cp_cntrl0.L1D0cache +L1D1cache=system.cp_cntrl0.L1D1cache +L1Icache=system.cp_cntrl0.L1Icache +L2cache=system.cp_cntrl0.L2cache +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +issue_latency=120 +l2_hit_latency=18 +mandatoryQueue=system.cp_cntrl0.mandatoryQueue +number_of_TBEs=256 +probeToCore=system.cp_cntrl0.probeToCore +recycle_latency=10 +requestFromCore=system.cp_cntrl0.requestFromCore +responseFromCore=system.cp_cntrl0.responseFromCore +responseToCore=system.cp_cntrl0.responseToCore +ruby_system=system.ruby +send_evictions=true +sequencer=system.cp_cntrl0.sequencer +sequencer1=system.cp_cntrl0.sequencer1 +system=system +transitions_per_cycle=32 +triggerQueue=system.cp_cntrl0.triggerQueue +unblockFromCore=system.cp_cntrl0.unblockFromCore +version=0 + +[system.cp_cntrl0.L1D0cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=2 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1D0cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=65536 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=2 + +[system.cp_cntrl0.L1D0cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=65536 + +[system.cp_cntrl0.L1D1cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=2 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1D1cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=65536 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=2 + +[system.cp_cntrl0.L1D1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=65536 + +[system.cp_cntrl0.L1Icache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=2 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1Icache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=32768 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=2 + +[system.cp_cntrl0.L1Icache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=32768 + +[system.cp_cntrl0.L2cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L2cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=2097152 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=16 + +[system.cp_cntrl0.L2cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=2097152 + +[system.cp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.cp_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[3] + +[system.cp_cntrl0.requestFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.cp_cntrl0.responseFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[3] + +[system.cp_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[4] + +[system.cp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=0 +dcache=system.cp_cntrl0.L1D0cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.cp_cntrl0.L1Icache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave +mem_master_port=system.piobus.slave[0] +slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master + +[system.cp_cntrl0.sequencer1] +type=RubySequencer +clk_domain=system.clk_domain +coreid=1 +dcache=system.cp_cntrl0.L1D1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.cp_cntrl0.L1Icache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=1 + +[system.cp_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.cp_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.cpu0] +type=TimingSimpleCPU +children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu0.clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.cp_cntrl0.sequencer.slave[1] +icache_port=system.cp_cntrl0.sequencer.slave[0] + +[system.cpu0.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu0.clk_domain +eventq_index=0 + +[system.cpu0.clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +clk_domain=system.cpu0.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.cp_cntrl0.sequencer.slave[3] + +[system.cpu0.interrupts] +type=X86LocalApic +clk_domain=system.cpu0.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.cp_cntrl0.sequencer.slave[4] +int_slave=system.cp_cntrl0.sequencer.master[1] +pio=system.cp_cntrl0.sequencer.master[0] + +[system.cpu0.isa] +type=X86ISA +eventq_index=0 + +[system.cpu0.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +clk_domain=system.cpu0.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.cp_cntrl0.sequencer.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu0.workload] +type=LiveProcess +cmd=gpu-hello +cwd= +drivers=system.cpu2.cl_driver +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu1] +type=Shader +children=CUs0 CUs1 clk_domain +CUs=system.cpu1.CUs0 system.cpu1.CUs1 +clk_domain=system.cpu1.clk_domain +cpu_pointer=system.cpu0 +eventq_index=0 +globalmem=65536 +impl_kern_boundary_sync=true +n_wf=8 +separate_acquire_release=false +timing=true +translation=false + +[system.cpu1.CUs0] +type=ComputeUnit +children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31 +clk_domain=system.cpu1.clk_domain +coalescer_to_vrf_bus_width=32 +countPages=false +cu_id=0 +debugSegFault=false +dpbypass_pipe_length=4 +eventq_index=0 +execPolicy=OLDEST-FIRST +functionalTLB=true +global_mem_queue_size=256 +issue_period=4 +localDataStore=system.cpu1.CUs0.localDataStore +localMemBarrier=false +local_mem_queue_size=256 +mem_req_latency=9 +mem_resp_latency=9 +n_wf=8 +num_SIMDs=4 +num_global_mem_pipes=1 +num_shared_mem_pipes=1 +perLaneTLB=false +prefetch_depth=0 +prefetch_prev_type=PF_PHASE +prefetch_stride=1 +spbypass_pipe_length=4 +system=system +vector_register_file=system.cpu1.CUs0.vector_register_file0 system.cpu1.CUs0.vector_register_file1 system.cpu1.CUs0.vector_register_file2 system.cpu1.CUs0.vector_register_file3 +vrf_to_coalescer_bus_width=32 +wavefronts=system.cpu1.CUs0.wavefronts00 system.cpu1.CUs0.wavefronts01 system.cpu1.CUs0.wavefronts02 system.cpu1.CUs0.wavefronts03 system.cpu1.CUs0.wavefronts04 system.cpu1.CUs0.wavefronts05 system.cpu1.CUs0.wavefronts06 system.cpu1.CUs0.wavefronts07 system.cpu1.CUs0.wavefronts08 system.cpu1.CUs0.wavefronts09 system.cpu1.CUs0.wavefronts10 system.cpu1.CUs0.wavefronts11 system.cpu1.CUs0.wavefronts12 system.cpu1.CUs0.wavefronts13 system.cpu1.CUs0.wavefronts14 system.cpu1.CUs0.wavefronts15 system.cpu1.CUs0.wavefronts16 system.cpu1.CUs0.wavefronts17 system.cpu1.CUs0.wavefronts18 system.cpu1.CUs0.wavefronts19 system.cpu1.CUs0.wavefronts20 system.cpu1.CUs0.wavefronts21 system.cpu1.CUs0.wavefronts22 system.cpu1.CUs0.wavefronts23 system.cpu1.CUs0.wavefronts24 system.cpu1.CUs0.wavefronts25 system.cpu1.CUs0.wavefronts26 system.cpu1.CUs0.wavefronts27 system.cpu1.CUs0.wavefronts28 system.cpu1.CUs0.wavefronts29 system.cpu1.CUs0.wavefronts30 system.cpu1.CUs0.wavefronts31 +wfSize=64 +xactCasMode=false +ldsPort=system.cpu1.CUs0.ldsBus.slave +memory_port=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl0.coalescer.slave[1] system.tcp_cntrl0.coalescer.slave[2] system.tcp_cntrl0.coalescer.slave[3] system.tcp_cntrl0.coalescer.slave[4] system.tcp_cntrl0.coalescer.slave[5] system.tcp_cntrl0.coalescer.slave[6] system.tcp_cntrl0.coalescer.slave[7] system.tcp_cntrl0.coalescer.slave[8] system.tcp_cntrl0.coalescer.slave[9] system.tcp_cntrl0.coalescer.slave[10] system.tcp_cntrl0.coalescer.slave[11] system.tcp_cntrl0.coalescer.slave[12] system.tcp_cntrl0.coalescer.slave[13] system.tcp_cntrl0.coalescer.slave[14] system.tcp_cntrl0.coalescer.slave[15] system.tcp_cntrl0.coalescer.slave[16] system.tcp_cntrl0.coalescer.slave[17] system.tcp_cntrl0.coalescer.slave[18] system.tcp_cntrl0.coalescer.slave[19] system.tcp_cntrl0.coalescer.slave[20] system.tcp_cntrl0.coalescer.slave[21] system.tcp_cntrl0.coalescer.slave[22] system.tcp_cntrl0.coalescer.slave[23] system.tcp_cntrl0.coalescer.slave[24] system.tcp_cntrl0.coalescer.slave[25] system.tcp_cntrl0.coalescer.slave[26] system.tcp_cntrl0.coalescer.slave[27] system.tcp_cntrl0.coalescer.slave[28] system.tcp_cntrl0.coalescer.slave[29] system.tcp_cntrl0.coalescer.slave[30] system.tcp_cntrl0.coalescer.slave[31] system.tcp_cntrl0.coalescer.slave[32] system.tcp_cntrl0.coalescer.slave[33] system.tcp_cntrl0.coalescer.slave[34] system.tcp_cntrl0.coalescer.slave[35] system.tcp_cntrl0.coalescer.slave[36] system.tcp_cntrl0.coalescer.slave[37] system.tcp_cntrl0.coalescer.slave[38] system.tcp_cntrl0.coalescer.slave[39] system.tcp_cntrl0.coalescer.slave[40] system.tcp_cntrl0.coalescer.slave[41] system.tcp_cntrl0.coalescer.slave[42] system.tcp_cntrl0.coalescer.slave[43] system.tcp_cntrl0.coalescer.slave[44] system.tcp_cntrl0.coalescer.slave[45] system.tcp_cntrl0.coalescer.slave[46] system.tcp_cntrl0.coalescer.slave[47] system.tcp_cntrl0.coalescer.slave[48] system.tcp_cntrl0.coalescer.slave[49] system.tcp_cntrl0.coalescer.slave[50] system.tcp_cntrl0.coalescer.slave[51] system.tcp_cntrl0.coalescer.slave[52] system.tcp_cntrl0.coalescer.slave[53] system.tcp_cntrl0.coalescer.slave[54] system.tcp_cntrl0.coalescer.slave[55] system.tcp_cntrl0.coalescer.slave[56] system.tcp_cntrl0.coalescer.slave[57] system.tcp_cntrl0.coalescer.slave[58] system.tcp_cntrl0.coalescer.slave[59] system.tcp_cntrl0.coalescer.slave[60] system.tcp_cntrl0.coalescer.slave[61] system.tcp_cntrl0.coalescer.slave[62] system.tcp_cntrl0.coalescer.slave[63] +sqc_port=system.sqc_cntrl0.sequencer.slave[0] +sqc_tlb_port=system.sqc_coalescer.slave[0] +translation_port=system.l1_coalescer0.slave[0] + +[system.cpu1.CUs0.ldsBus] +type=Bridge +clk_domain=system.cpu1.clk_domain +delay=0 +eventq_index=0 +ranges=0:18446744073709551615 +req_size=16 +resp_size=16 +master=system.cpu1.CUs0.localDataStore.cuPort +slave=system.cpu1.CUs0.ldsPort + +[system.cpu1.CUs0.localDataStore] +type=LdsState +bankConflictPenalty=1 +banks=32 +clk_domain=system.cpu1.clk_domain +eventq_index=0 +range=0:65535 +size=65536 +cuPort=system.cpu1.CUs0.ldsBus.master + +[system.cpu1.CUs0.vector_register_file0] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=0 + +[system.cpu1.CUs0.vector_register_file1] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=1 + +[system.cpu1.CUs0.vector_register_file2] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=2 + +[system.cpu1.CUs0.vector_register_file3] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=3 + +[system.cpu1.CUs0.wavefronts00] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts01] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts02] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts03] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts04] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts05] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts06] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts07] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts08] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts09] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts10] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts11] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts12] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts13] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts14] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts15] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts16] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts17] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts18] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts19] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts20] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts21] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts22] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts23] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts24] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts25] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts26] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts27] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts28] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts29] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts30] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts31] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=7 + +[system.cpu1.CUs1] +type=ComputeUnit +children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31 +clk_domain=system.cpu1.clk_domain +coalescer_to_vrf_bus_width=32 +countPages=false +cu_id=1 +debugSegFault=false +dpbypass_pipe_length=4 +eventq_index=0 +execPolicy=OLDEST-FIRST +functionalTLB=true +global_mem_queue_size=256 +issue_period=4 +localDataStore=system.cpu1.CUs1.localDataStore +localMemBarrier=false +local_mem_queue_size=256 +mem_req_latency=9 +mem_resp_latency=9 +n_wf=8 +num_SIMDs=4 +num_global_mem_pipes=1 +num_shared_mem_pipes=1 +perLaneTLB=false +prefetch_depth=0 +prefetch_prev_type=PF_PHASE +prefetch_stride=1 +spbypass_pipe_length=4 +system=system +vector_register_file=system.cpu1.CUs1.vector_register_file0 system.cpu1.CUs1.vector_register_file1 system.cpu1.CUs1.vector_register_file2 system.cpu1.CUs1.vector_register_file3 +vrf_to_coalescer_bus_width=32 +wavefronts=system.cpu1.CUs1.wavefronts00 system.cpu1.CUs1.wavefronts01 system.cpu1.CUs1.wavefronts02 system.cpu1.CUs1.wavefronts03 system.cpu1.CUs1.wavefronts04 system.cpu1.CUs1.wavefronts05 system.cpu1.CUs1.wavefronts06 system.cpu1.CUs1.wavefronts07 system.cpu1.CUs1.wavefronts08 system.cpu1.CUs1.wavefronts09 system.cpu1.CUs1.wavefronts10 system.cpu1.CUs1.wavefronts11 system.cpu1.CUs1.wavefronts12 system.cpu1.CUs1.wavefronts13 system.cpu1.CUs1.wavefronts14 system.cpu1.CUs1.wavefronts15 system.cpu1.CUs1.wavefronts16 system.cpu1.CUs1.wavefronts17 system.cpu1.CUs1.wavefronts18 system.cpu1.CUs1.wavefronts19 system.cpu1.CUs1.wavefronts20 system.cpu1.CUs1.wavefronts21 system.cpu1.CUs1.wavefronts22 system.cpu1.CUs1.wavefronts23 system.cpu1.CUs1.wavefronts24 system.cpu1.CUs1.wavefronts25 system.cpu1.CUs1.wavefronts26 system.cpu1.CUs1.wavefronts27 system.cpu1.CUs1.wavefronts28 system.cpu1.CUs1.wavefronts29 system.cpu1.CUs1.wavefronts30 system.cpu1.CUs1.wavefronts31 +wfSize=64 +xactCasMode=false +ldsPort=system.cpu1.CUs1.ldsBus.slave +memory_port=system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[1] system.tcp_cntrl1.coalescer.slave[2] system.tcp_cntrl1.coalescer.slave[3] system.tcp_cntrl1.coalescer.slave[4] system.tcp_cntrl1.coalescer.slave[5] system.tcp_cntrl1.coalescer.slave[6] system.tcp_cntrl1.coalescer.slave[7] system.tcp_cntrl1.coalescer.slave[8] system.tcp_cntrl1.coalescer.slave[9] system.tcp_cntrl1.coalescer.slave[10] system.tcp_cntrl1.coalescer.slave[11] system.tcp_cntrl1.coalescer.slave[12] system.tcp_cntrl1.coalescer.slave[13] system.tcp_cntrl1.coalescer.slave[14] system.tcp_cntrl1.coalescer.slave[15] system.tcp_cntrl1.coalescer.slave[16] system.tcp_cntrl1.coalescer.slave[17] system.tcp_cntrl1.coalescer.slave[18] system.tcp_cntrl1.coalescer.slave[19] system.tcp_cntrl1.coalescer.slave[20] system.tcp_cntrl1.coalescer.slave[21] system.tcp_cntrl1.coalescer.slave[22] system.tcp_cntrl1.coalescer.slave[23] system.tcp_cntrl1.coalescer.slave[24] system.tcp_cntrl1.coalescer.slave[25] system.tcp_cntrl1.coalescer.slave[26] system.tcp_cntrl1.coalescer.slave[27] system.tcp_cntrl1.coalescer.slave[28] system.tcp_cntrl1.coalescer.slave[29] system.tcp_cntrl1.coalescer.slave[30] system.tcp_cntrl1.coalescer.slave[31] system.tcp_cntrl1.coalescer.slave[32] system.tcp_cntrl1.coalescer.slave[33] system.tcp_cntrl1.coalescer.slave[34] system.tcp_cntrl1.coalescer.slave[35] system.tcp_cntrl1.coalescer.slave[36] system.tcp_cntrl1.coalescer.slave[37] system.tcp_cntrl1.coalescer.slave[38] system.tcp_cntrl1.coalescer.slave[39] system.tcp_cntrl1.coalescer.slave[40] system.tcp_cntrl1.coalescer.slave[41] system.tcp_cntrl1.coalescer.slave[42] system.tcp_cntrl1.coalescer.slave[43] system.tcp_cntrl1.coalescer.slave[44] system.tcp_cntrl1.coalescer.slave[45] system.tcp_cntrl1.coalescer.slave[46] system.tcp_cntrl1.coalescer.slave[47] system.tcp_cntrl1.coalescer.slave[48] system.tcp_cntrl1.coalescer.slave[49] system.tcp_cntrl1.coalescer.slave[50] system.tcp_cntrl1.coalescer.slave[51] system.tcp_cntrl1.coalescer.slave[52] system.tcp_cntrl1.coalescer.slave[53] system.tcp_cntrl1.coalescer.slave[54] system.tcp_cntrl1.coalescer.slave[55] system.tcp_cntrl1.coalescer.slave[56] system.tcp_cntrl1.coalescer.slave[57] system.tcp_cntrl1.coalescer.slave[58] system.tcp_cntrl1.coalescer.slave[59] system.tcp_cntrl1.coalescer.slave[60] system.tcp_cntrl1.coalescer.slave[61] system.tcp_cntrl1.coalescer.slave[62] system.tcp_cntrl1.coalescer.slave[63] +sqc_port=system.sqc_cntrl0.sequencer.slave[1] +sqc_tlb_port=system.sqc_coalescer.slave[1] +translation_port=system.l1_coalescer1.slave[0] + +[system.cpu1.CUs1.ldsBus] +type=Bridge +clk_domain=system.cpu1.clk_domain +delay=0 +eventq_index=0 +ranges=0:18446744073709551615 +req_size=16 +resp_size=16 +master=system.cpu1.CUs1.localDataStore.cuPort +slave=system.cpu1.CUs1.ldsPort + +[system.cpu1.CUs1.localDataStore] +type=LdsState +bankConflictPenalty=1 +banks=32 +clk_domain=system.cpu1.clk_domain +eventq_index=0 +range=0:65535 +size=65536 +cuPort=system.cpu1.CUs1.ldsBus.master + +[system.cpu1.CUs1.vector_register_file0] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=0 + +[system.cpu1.CUs1.vector_register_file1] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=1 + +[system.cpu1.CUs1.vector_register_file2] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=2 + +[system.cpu1.CUs1.vector_register_file3] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=3 + +[system.cpu1.CUs1.wavefronts00] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts01] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts02] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts03] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts04] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts05] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts06] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts07] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts08] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts09] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts10] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts11] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts12] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts13] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts14] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts15] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts16] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts17] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts18] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts19] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts20] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts21] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts22] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts23] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts24] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts25] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts26] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts27] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts28] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts29] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts30] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts31] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=7 + +[system.cpu1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu1.clk_domain.voltage_domain + +[system.cpu1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu2] +type=GpuDispatcher +children=cl_driver +cl_driver=system.cpu2.cl_driver +clk_domain=system.clk_domain +cpu=system.cpu0 +eventq_index=0 +pio_addr=8589934592 +pio_latency=1000 +shader_pointer=system.cpu1 +system=system +dma=system.piobus.slave[1] +pio=system.piobus.master[0] +translation_port=system.dispatcher_coalescer.slave[0] + +[system.cpu2.cl_driver] +type=ClDriver +codefile=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +eventq_index=0 +filename=hsa + +[system.dir_cntrl0] +type=Directory_Controller +children=L3CacheMemory L3triggerQueue ProbeFilterMemory directory probeToCore requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores +CAB_TCC=false +L3CacheMemory=system.dir_cntrl0.L3CacheMemory +L3triggerQueue=system.dir_cntrl0.L3triggerQueue +ProbeFilterMemory=system.dir_cntrl0.ProbeFilterMemory +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +directory=system.dir_cntrl0.directory +eventq_index=0 +inclusiveDir=true +l3_hit_latency=15 +noTCCdir=true +number_of_TBEs=2560 +probeToCore=system.dir_cntrl0.probeToCore +recycle_latency=10 +requestFromCores=system.dir_cntrl0.requestFromCores +responseFromCores=system.dir_cntrl0.responseFromCores +responseFromMemory=system.dir_cntrl0.responseFromMemory +responseToCore=system.dir_cntrl0.responseToCore +response_latency=30 +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=32 +triggerQueue=system.dir_cntrl0.triggerQueue +unblockFromCores=system.dir_cntrl0.unblockFromCores +useL3OnWT=false +version=0 +memory=system.mem_ctrls.port + +[system.dir_cntrl0.L3CacheMemory] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=20 +dataArrayBanks=16.0 +eventq_index=0 +is_icache=false +replacement_policy=system.dir_cntrl0.L3CacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=16777216 +start_index_bit=6 +tagAccessLatency=15 +tagArrayBanks=16.0 + +[system.dir_cntrl0.L3CacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=16777216 + +[system.dir_cntrl0.L3triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.dir_cntrl0.ProbeFilterMemory] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=64 +dataAccessLatency=1 +dataArrayBanks=256 +eventq_index=0 +is_icache=false +replacement_policy=system.dir_cntrl0.ProbeFilterMemory.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=1048576 +start_index_bit=6 +tagAccessLatency=8 +tagArrayBanks=8 + +[system.dir_cntrl0.ProbeFilterMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=1048576 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=536870912 +version=0 + +[system.dir_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[0] + +[system.dir_cntrl0.requestFromCores] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[0] + +[system.dir_cntrl0.responseFromCores] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[1] + +[system.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.dir_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[1] + +[system.dir_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.dir_cntrl0.unblockFromCores] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[2] + +[system.dispatcher_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.dispatcher_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.dispatcher_tlb.slave[0] +slave=system.cpu2.translation_port + +[system.dispatcher_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.dispatcher_coalescer.clk_domain.voltage_domain + +[system.dispatcher_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.dispatcher_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.dispatcher_tlb.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[1] +slave=system.dispatcher_coalescer.master[0] + +[system.dispatcher_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.dispatcher_tlb.clk_domain.voltage_domain + +[system.dispatcher_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l1_coalescer0] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l1_coalescer0.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l1_tlb0.slave[0] +slave=system.cpu1.CUs0.translation_port[0] + +[system.l1_coalescer0.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_coalescer0.clk_domain.voltage_domain + +[system.l1_coalescer0.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_coalescer1] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l1_coalescer1.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l1_tlb1.slave[0] +slave=system.cpu1.CUs1.translation_port[0] + +[system.l1_coalescer1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_coalescer1.clk_domain.voltage_domain + +[system.l1_coalescer1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_tlb0] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 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+voltage_domain=system.l1_tlb1.clk_domain.voltage_domain + +[system.l1_tlb1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l2_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l2_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l2_tlb.slave[0] +slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0] + +[system.l2_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l2_coalescer.clk_domain.voltage_domain + +[system.l2_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l2_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l2_tlb.clk_domain +eventq_index=0 +hitLatency=69 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=4096 +master=system.l3_coalescer.slave[0] +slave=system.l2_coalescer.master[0] + +[system.l2_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l2_tlb.clk_domain.voltage_domain + +[system.l2_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l3_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l3_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l3_tlb.slave[0] +slave=system.l2_tlb.master[0] + +[system.l3_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l3_coalescer.clk_domain.voltage_domain + +[system.l3_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l3_tlb] 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+frontend_latency=0 +response_latency=0 +use_default_range=false +width=32 +master=system.cpu2.pio +slave=system.cp_cntrl0.sequencer.mem_master_port system.cpu2.dma + +[system.ruby] +type=RubySystem +children=clk_domain network phys_mem +access_backing_store=true +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=5 +number_of_virtual_networks=10 +phys_mem=system.ruby.phys_mem +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 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system.tcp_cntrl0.probeToTCP.slave system.tcp_cntrl0.responseToTCP.slave system.tcp_cntrl1.probeToTCP.slave system.tcp_cntrl1.responseToTCP.slave system.sqc_cntrl0.probeToSQC.slave system.sqc_cntrl0.responseToSQC.slave system.tcc_cntrl0.requestFromTCP.slave system.tcc_cntrl0.probeFromNB.slave system.tcc_cntrl0.responseFromNB.slave +slave=system.dir_cntrl0.probeToCore.master system.dir_cntrl0.responseToCore.master system.cp_cntrl0.requestFromCore.master system.cp_cntrl0.responseFromCore.master system.cp_cntrl0.unblockFromCore.master system.tcp_cntrl0.requestFromTCP.master system.tcp_cntrl0.responseFromTCP.master system.tcp_cntrl0.unblockFromCore.master system.tcp_cntrl1.requestFromTCP.master system.tcp_cntrl1.responseFromTCP.master system.tcp_cntrl1.unblockFromCore.master system.sqc_cntrl0.requestFromSQC.master system.tcc_cntrl0.responseToCore.master system.tcc_cntrl0.requestToNB.master system.tcc_cntrl0.responseToNB.master system.tcc_cntrl0.unblockToNB.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +children=int_node +bandwidth_factor=32 +eventq_index=0 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.ext_links0.int_node +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.ext_links0.int_node] +type=Switch +children=port_buffers00 port_buffers01 port_buffers02 port_buffers03 port_buffers04 port_buffers05 port_buffers06 port_buffers07 port_buffers08 port_buffers09 port_buffers10 port_buffers11 port_buffers12 port_buffers13 port_buffers14 port_buffers15 port_buffers16 port_buffers17 port_buffers18 port_buffers19 port_buffers20 port_buffers21 port_buffers22 port_buffers23 port_buffers24 port_buffers25 port_buffers26 port_buffers27 port_buffers28 port_buffers29 port_buffers30 port_buffers31 port_buffers32 port_buffers33 port_buffers34 port_buffers35 port_buffers36 port_buffers37 port_buffers38 port_buffers39 port_buffers40 port_buffers41 port_buffers42 port_buffers43 port_buffers44 port_buffers45 port_buffers46 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+is_cpu_sequencer=false +max_inv_per_cycle=32 +max_outstanding_requests=2560 +max_wb_per_cycle=32 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=false +version=2 +slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63] + +[system.tcp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl0.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[5] + +[system.tcp_cntrl0.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[5] + +[system.tcp_cntrl0.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[6] + +[system.tcp_cntrl0.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[6] + +[system.tcp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=3 + +[system.tcp_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[7] + +[system.tcp_cntrl1] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl1.L1cache +TCC_select_num_bits=0 +WB=false +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl1.coalescer +disableL1=false +eventq_index=0 +issue_latency=1 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl1.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl1.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl1.requestFromTCP +responseFromTCP=system.tcp_cntrl1.responseFromTCP +responseToTCP=system.tcp_cntrl1.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl1.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl1.unblockFromCore +use_seq_not_coal=false +version=1 + +[system.tcp_cntrl1.L1cache] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl1.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=16 + +[system.tcp_cntrl1.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl1.coalescer] +type=VIPERCoalescer +assume_rfo=false +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_inv_per_cycle=32 +max_outstanding_requests=2560 +max_wb_per_cycle=32 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=false +version=4 +slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63] + +[system.tcp_cntrl1.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl1.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[7] + +[system.tcp_cntrl1.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[8] + +[system.tcp_cntrl1.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[9] + +[system.tcp_cntrl1.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[8] + +[system.tcp_cntrl1.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=5 + +[system.tcp_cntrl1.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[10] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simerr b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simerr new file mode 100755 index 000000000..1e2b8911e --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simerr @@ -0,0 +1,5 @@ +warn: system.ruby.network adopting orphan SimObject param 'int_links' +warn: system.ruby.network adopting orphan SimObject param 'ext_links' +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simout new file mode 100755 index 000000000..8e68d38e1 --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/simout @@ -0,0 +1,21 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 19 2016 13:39:50 +gem5 started Jan 19 2016 13:40:22 +gem5 executing on zizzer, pid 50252 +command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Baseline -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Baseline + +Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +Global frequency set at 1000000000000 ticks per second +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +info: Entering event queue @ 0. Starting simulation... +keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23 +the gpu says: +elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe +Exiting @ tick 548459500 because target called exit() diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/stats.txt new file mode 100644 index 000000000..281a367a9 --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Baseline/stats.txt @@ -0,0 +1,3200 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000548 # Number of seconds simulated +sim_ticks 548459500 # Number of ticks simulated +final_tick 548459500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 76623 # Simulator instruction rate (inst/s) +host_op_rate 157567 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 627550839 # Simulator tick rate (ticks/s) +host_mem_usage 1298164 # Number of bytes of host memory used +host_seconds 0.87 # Real time elapsed on the host +sim_insts 66963 # Number of instructions simulated +sim_ops 137705 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrls.bytes_read::dir_cntrl0 99840 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 99840 # Number of bytes read from this memory +system.mem_ctrls.num_reads::dir_cntrl0 1560 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1560 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::dir_cntrl0 182037142 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 182037142 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::dir_cntrl0 182037142 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 182037142 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1560 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1560 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 99840 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 99840 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 182 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 223 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 548231000 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1560 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1545 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 3 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 5 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 467 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 212.008565 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 148.026325 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 209.604491 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 171 36.62% 36.62% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 154 32.98% 69.59% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 64 13.70% 83.30% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 31 6.64% 89.94% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 16 3.43% 93.36% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 12 2.57% 95.93% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 7 1.50% 97.43% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 3 0.64% 98.07% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 9 1.93% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 467 # Bytes accessed per row activation +system.mem_ctrls.totQLat 15697750 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 44947750 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 7800000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 10062.66 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 28812.66 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 182.04 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 182.04 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 1.42 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 1.42 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.01 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 1088 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 69.74 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.avgGap 351430.13 # Average gap between requests +system.mem_ctrls.pageHitRate 69.74 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1323000 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 721875 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 35599200 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 300176820 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 63865500 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 407021595 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 746.421165 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 107390750 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 18200000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 422764250 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 2207520 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1204500 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6731400 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 35599200 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 328972365 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 38606250 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 413321235 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 757.973831 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 62414250 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 18200000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 464697000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.ruby.clk_domain.clock 500 # Clock period in ticks +system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory +system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory +system.ruby.phys_mem.bw_read::cpu0.inst 1270394623 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu0.data 218488330 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 5980387 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 5980387 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::total 1500843727 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu0.inst 1270394623 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 3646577 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 3646577 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::total 1277687778 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu0.data 132675248 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 466762 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 466762 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::total 133608771 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.inst 1270394623 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.data 351163577 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 6447149 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 6447149 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::total 1634452498 # Total bandwidth to/from this memory (bytes/s) +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 114203 +system.ruby.outstanding_req_hist::mean 1.000035 +system.ruby.outstanding_req_hist::gmean 1.000024 +system.ruby.outstanding_req_hist::stdev 0.005918 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 114203 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 114203 +system.ruby.latency_hist::mean 3.766924 +system.ruby.latency_hist::gmean 1.075767 +system.ruby.latency_hist::stdev 23.927354 +system.ruby.latency_hist | 112668 98.66% 98.66% | 0 0.00% 98.66% | 0 0.00% 98.66% | 1489 1.30% 99.96% | 10 0.01% 99.97% | 13 0.01% 99.98% | 16 0.01% 99.99% | 7 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 114203 +system.ruby.hit_latency_hist::bucket_size 64 +system.ruby.hit_latency_hist::max_bucket 639 +system.ruby.hit_latency_hist::samples 1535 +system.ruby.hit_latency_hist::mean 206.165472 +system.ruby.hit_latency_hist::gmean 204.491657 +system.ruby.hit_latency_hist::stdev 32.551053 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1489 97.00% 97.00% | 10 0.65% 97.65% | 13 0.85% 98.50% | 16 1.04% 99.54% | 7 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 1535 +system.ruby.miss_latency_hist::bucket_size 2 +system.ruby.miss_latency_hist::max_bucket 19 +system.ruby.miss_latency_hist::samples 112668 +system.ruby.miss_latency_hist::mean 1.009426 +system.ruby.miss_latency_hist::gmean 1.001543 +system.ruby.miss_latency_hist::stdev 0.411800 +system.ruby.miss_latency_hist | 112609 99.95% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 0 0.00% 99.95% | 59 0.05% 100.00% +system.ruby.miss_latency_hist::total 112668 +system.ruby.L1Cache.incomplete_times 112609 +system.ruby.L2Cache.incomplete_times 59 +system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1D0cache.demand_misses 506 # Number of cache demand misses +system.cp_cntrl0.L1D0cache.demand_accesses 506 # Number of cache demand accesses +system.cp_cntrl0.L1D0cache.num_data_array_reads 16155 # number of data array reads +system.cp_cntrl0.L1D0cache.num_data_array_writes 11985 # number of data array writes +system.cp_cntrl0.L1D0cache.num_tag_array_reads 27132 # number of tag array reads +system.cp_cntrl0.L1D0cache.num_tag_array_writes 1584 # number of tag array writes +system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses +system.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses +system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1Icache.demand_misses 1088 # Number of cache demand misses +system.cp_cntrl0.L1Icache.demand_accesses 1088 # Number of cache demand accesses +system.cp_cntrl0.L1Icache.num_data_array_reads 86007 # number of data array reads +system.cp_cntrl0.L1Icache.num_data_array_writes 54 # number of data array writes +system.cp_cntrl0.L1Icache.num_tag_array_reads 87684 # number of tag array reads +system.cp_cntrl0.L1Icache.num_tag_array_writes 54 # number of tag array writes +system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L2cache.demand_misses 1535 # Number of cache demand misses +system.cp_cntrl0.L2cache.demand_accesses 1535 # Number of cache demand accesses +system.cp_cntrl0.L2cache.num_data_array_reads 120 # number of data array reads +system.cp_cntrl0.L2cache.num_data_array_writes 11982 # number of data array writes +system.cp_cntrl0.L2cache.num_tag_array_reads 12046 # number of tag array reads +system.cp_cntrl0.L2cache.num_tag_array_writes 1641 # number of tag array writes +system.cpu0.clk_domain.clock 500 # Clock period in ticks +system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu0.workload.num_syscalls 21 # Number of system calls +system.cpu0.numCycles 1096919 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 66963 # Number of instructions committed +system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses +system.cpu0.num_func_calls 3196 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136380 # number of integer instructions +system.cpu0.num_fp_insts 1279 # number of float instructions +system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written +system.cpu0.num_mem_refs 27198 # number of memory refs +system.cpu0.num_load_insts 16684 # Number of load instructions +system.cpu0.num_store_insts 10514 # Number of store instructions +system.cpu0.num_idle_cycles 7577.003986 # Number of idle cycles +system.cpu0.num_busy_cycles 1089341.996014 # Number of busy cycles +system.cpu0.not_idle_fraction 0.993092 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.006908 # Percentage of idle cycles +system.cpu0.Branches 16199 # Number of branches fetched +system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction +system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction +system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction +system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction +system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 137705 # Class of executed instruction +system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.cpu1.clk_domain.clock 1000 # Clock period in ticks +system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 372 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 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source register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 353 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 344 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 329 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 4357 # number of cycles the CU issues nothing +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 133 # number of cycles the CU issued at least one instruction +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1547 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 483 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 439 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 403 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 436 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.spc::samples 4490 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::mean 0.031403 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::stdev 0.185563 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::0 4357 97.04% 97.04% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::1 126 2.81% 99.84% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::2 6 0.13% 99.98% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::3 1 0.02% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::total 4490 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 68 # number of CU transitions from active to idle +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 68 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 59.558824 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 213.072854 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 48 70.59% 70.59% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 8 11.76% 82.35% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.47% 83.82% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.47% 85.29% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.94% 88.24% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.47% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 10.29% 100.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1300 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 68 # duration of idle periods in cycles +system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF +system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests +system.cpu1.CUs0.tlb_cycles -373675448000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs0.avg_translation_latency -485923859.557867 # Avg. translation latency for data translations +system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses +system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count +system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count +system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity +system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed +system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::mean 94.900709 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::stdev 247.493154 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 68.79% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::max_value 1303 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst) +system.cpu1.CUs0.num_total_cycles 4490 # number of cycles the CU ran for +system.cpu1.CUs0.vpc 1.507572 # Vector Operations per cycle (this CU only) +system.cpu1.CUs0.ipc 0.031403 # Instructions per cycle (this CU only) +system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction +system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed +system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD +system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations +system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed +system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts +system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 377 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 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with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 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number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands 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with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 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+system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 355 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands 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source register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 352 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 337 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 4359 # number of cycles the CU issues nothing +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 131 # number of cycles the CU issued at least one instruction +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1552 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 447 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 464 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 464 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 426 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 33 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.spc::samples 4490 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::mean 0.031403 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::stdev 0.189130 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::0 4359 97.08% 97.08% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::1 123 2.74% 99.82% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::2 6 0.13% 99.96% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::3 2 0.04% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::total 4490 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 74 # number of CU transitions from active to idle +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 74 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 55.324324 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 207.911408 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 56 75.68% 75.68% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 7 9.46% 85.14% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 85.14% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.70% 87.84% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 1 1.35% 89.19% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.35% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 9.46% 100.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1304 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 74 # duration of idle periods in cycles +system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF +system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests +system.cpu1.CUs1.tlb_cycles -373672588000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs1.avg_translation_latency -485920140.442133 # Avg. translation latency for data translations +system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses +system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count +system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count +system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity +system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed +system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::mean 95.106383 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::stdev 249.293307 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::6-7 29 20.57% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::8-9 5 3.55% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::max_value 1307 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst) +system.cpu1.CUs1.num_total_cycles 4490 # number of cycles the CU ran for +system.cpu1.CUs1.vpc 1.506013 # Vector Operations per cycle (this CU only) +system.cpu1.CUs1.ipc 0.031403 # Instructions per cycle (this CU only) +system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction +system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed +system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD +system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations +system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed +system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts +system.cpu2.num_kernel_launched 1 # number of kernel launched +system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits +system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses +system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses +system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1560 # number of data array writes +system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1560 # number of tag array reads +system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1578 # number of tag array writes +system.dir_cntrl0.ProbeFilterMemory.demand_hits 0 # Number of cache demand hits +system.dir_cntrl0.ProbeFilterMemory.demand_misses 0 # Number of cache demand misses +system.dir_cntrl0.ProbeFilterMemory.demand_accesses 0 # Number of cache demand accesses +system.dir_cntrl0.ProbeFilterMemory.num_tag_array_reads 1560 # number of tag array reads +system.dir_cntrl0.ProbeFilterMemory.num_tag_array_writes 1560 # number of tag array writes +system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses +system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses +system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue +system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts +system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses +system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits +system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses +system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate +system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses +system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits +system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses +system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate +system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level +system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched +system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs +system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses +system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses +system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue +system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts +system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses +system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses +system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue +system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts +system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses +system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits +system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses +system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate +system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses +system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits +system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses +system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate +system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level +system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table +system.l1_tlb0.unique_pages 4 # Number of unique pages touched +system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs +system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses +system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits +system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses +system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate +system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses +system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits +system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses +system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate +system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level +system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table +system.l1_tlb1.unique_pages 3 # Number of unique pages touched +system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs +system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses +system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses +system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue +system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs +system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts +system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses +system.l2_tlb.local_TLB_hits 3 # Number of TLB hits +system.l2_tlb.local_TLB_misses 5 # Number of TLB misses +system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate +system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses +system.l2_tlb.global_TLB_hits 3 # Number of TLB hits +system.l2_tlb.global_TLB_misses 12 # Number of TLB misses +system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate +system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level +system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.l2_tlb.unique_pages 5 # Number of unique pages touched +system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs +system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs +system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses +system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses +system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue +system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs +system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts +system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses +system.l3_tlb.local_TLB_hits 0 # Number of TLB hits +system.l3_tlb.local_TLB_misses 5 # Number of TLB misses +system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate +system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses +system.l3_tlb.global_TLB_hits 0 # Number of TLB hits +system.l3_tlb.global_TLB_misses 12 # Number of TLB misses +system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate +system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level +system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table +system.l3_tlb.unique_pages 5 # Number of unique pages touched +system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs +system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs +system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.piobus.trans_dist::WriteReq 94 # Transaction distribution +system.piobus.trans_dist::WriteResp 94 # Transaction distribution +system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) +system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) +system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) +system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) +system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) +system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.ruby.network.ext_links0.int_node.percent_links_utilized 0.130525 +system.ruby.network.ext_links0.int_node.msg_count.Control::0 4 +system.ruby.network.ext_links0.int_node.msg_count.Data::0 18 +system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1542 +system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1546 +system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 2 +system.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1541 +system.ruby.network.ext_links0.int_node.msg_bytes.Control::0 32 +system.ruby.network.ext_links0.int_node.msg_bytes.Data::0 1296 +system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12336 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 111312 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 16 +system.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12328 +system.ruby.network.ext_links1.int_node.percent_links_utilized 0.192653 +system.ruby.network.ext_links1.int_node.msg_count.Control::0 3 +system.ruby.network.ext_links1.int_node.msg_count.Request_Control::0 1535 +system.ruby.network.ext_links1.int_node.msg_count.Response_Data::2 1537 +system.ruby.network.ext_links1.int_node.msg_count.Response_Control::2 1 +system.ruby.network.ext_links1.int_node.msg_count.Unblock_Control::4 1534 +system.ruby.network.ext_links1.int_node.msg_bytes.Control::0 24 +system.ruby.network.ext_links1.int_node.msg_bytes.Request_Control::0 12280 +system.ruby.network.ext_links1.int_node.msg_bytes.Response_Data::2 110664 +system.ruby.network.ext_links1.int_node.msg_bytes.Response_Control::2 8 +system.ruby.network.ext_links1.int_node.msg_bytes.Unblock_Control::4 12272 +system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl0.L1cache.num_data_array_reads 6 # number of data array reads +system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes +system.tcp_cntrl0.L1cache.num_tag_array_reads 1297 # number of tag array reads +system.tcp_cntrl0.L1cache.num_tag_array_writes 11 # number of tag array writes +system.tcp_cntrl0.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array +system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array +system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl0.coalescer.gpu_ld_misses 5 # loads that miss in the GPU +system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl0.coalescer.gpu_st_misses 9 # stores that miss in the GPU +system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.ruby.network.ext_links2.int_node.percent_links_utilized 0.002557 +system.ruby.network.ext_links2.int_node.msg_count.Control::0 1 +system.ruby.network.ext_links2.int_node.msg_count.Data::0 18 +system.ruby.network.ext_links2.int_node.msg_count.Data::1 18 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 7 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::1 9 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 9 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::3 11 +system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 1 +system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links2.int_node.msg_count.Writeback_Control::3 16 +system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 7 +system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 8 +system.ruby.network.ext_links2.int_node.msg_bytes.Data::0 1296 +system.ruby.network.ext_links2.int_node.msg_bytes.Data::1 1296 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 56 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::1 72 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 648 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::3 792 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 8 +system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links2.int_node.msg_bytes.Writeback_Control::3 128 +system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 56 +system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl1.L1cache.num_data_array_reads 6 # number of data array reads +system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes +system.tcp_cntrl1.L1cache.num_tag_array_reads 1297 # number of tag array reads +system.tcp_cntrl1.L1cache.num_tag_array_writes 11 # number of tag array writes +system.tcp_cntrl1.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array +system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array +system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl1.coalescer.gpu_ld_misses 5 # loads that miss in the GPU +system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl1.coalescer.gpu_st_misses 9 # stores that miss in the GPU +system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads +system.sqc_cntrl0.L1cache.num_tag_array_reads 91 # number of tag array reads +system.sqc_cntrl0.L1cache.num_tag_array_writes 10 # number of tag array writes +system.sqc_cntrl0.sequencer.load_waiting_on_load 98 # Number of times a load aliased with a pending load +system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses +system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses +system.tcc_cntrl0.L2cache.num_data_array_writes 9 # number of data array writes +system.tcc_cntrl0.L2cache.num_tag_array_reads 35 # number of tag array reads +system.tcc_cntrl0.L2cache.num_tag_array_writes 11 # number of tag array writes +system.ruby.network.msg_count.Control 8 +system.ruby.network.msg_count.Data 54 +system.ruby.network.msg_count.Request_Control 3093 +system.ruby.network.msg_count.Response_Data 3103 +system.ruby.network.msg_count.Response_Control 4 +system.ruby.network.msg_count.Writeback_Control 48 +system.ruby.network.msg_count.Unblock_Control 3082 +system.ruby.network.msg_byte.Control 64 +system.ruby.network.msg_byte.Data 3888 +system.ruby.network.msg_byte.Request_Control 24744 +system.ruby.network.msg_byte.Response_Data 223416 +system.ruby.network.msg_byte.Response_Control 32 +system.ruby.network.msg_byte.Writeback_Control 384 +system.ruby.network.msg_byte.Unblock_Control 24656 +system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses +system.sqc_coalescer.coalesced_accesses 66 # Number of coalesced TLB accesses +system.sqc_coalescer.queuing_cycles 288000 # Number of cycles spent in queue +system.sqc_coalescer.local_queuing_cycles 288000 # Number of cycles spent in queue for all incoming reqs +system.sqc_coalescer.local_latency 3348.837209 # Avg. latency over all incoming pkts +system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks +system.sqc_tlb.local_TLB_accesses 66 # Number of TLB accesses +system.sqc_tlb.local_TLB_hits 65 # Number of TLB hits +system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses +system.sqc_tlb.local_TLB_miss_rate 1.515152 # TLB miss rate +system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses +system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits +system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses +system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate +system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level +system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.sqc_tlb.unique_pages 1 # Number of unique pages touched +system.sqc_tlb.local_cycles 66001 # Number of cycles spent in queue for all incoming reqs +system.sqc_tlb.local_latency 1000.015152 # Avg. latency over incoming coalesced reqs +system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.074413 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0 18 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+system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::3 3 +system.ruby.network.ext_links2.int_node.throttle0.msg_count.Writeback_Control::3 8 +system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::3 216 +system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Writeback_Control::3 64 +system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.000798 +system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Data::3 3 +system.ruby.network.ext_links2.int_node.throttle1.msg_count.Writeback_Control::3 8 +system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Data::3 216 +system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Writeback_Control::3 64 +system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0.006131 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Control::0 1 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Data::1 18 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::1 9 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2 9 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Control::0 8 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Data::1 1296 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::1 72 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2 648 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links2.int_node.throttle3.link_utilization 0.001026 +system.ruby.network.ext_links2.int_node.throttle3.msg_count.Response_Data::3 5 +system.ruby.network.ext_links2.int_node.throttle3.msg_bytes.Response_Data::3 360 +system.ruby.network.ext_links2.int_node.throttle4.link_utilization 0.004034 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Data::0 18 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Request_Control::0 7 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Response_Control::2 1 +system.ruby.network.ext_links2.int_node.throttle4.msg_count.Unblock_Control::4 7 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Data::0 1296 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Request_Control::0 56 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Response_Control::2 8 +system.ruby.network.ext_links2.int_node.throttle4.msg_bytes.Unblock_Control::4 56 +system.ruby.CorePair_Controller.C0_Load_L1miss 180 0.00% 0.00% +system.ruby.CorePair_Controller.C0_Load_L1hit 16155 0.00% 0.00% +system.ruby.CorePair_Controller.Ifetch0_L1hit 86007 0.00% 0.00% +system.ruby.CorePair_Controller.Ifetch0_L1miss 1088 0.00% 0.00% +system.ruby.CorePair_Controller.C0_Store_L1miss 325 0.00% 0.00% +system.ruby.CorePair_Controller.C0_Store_L1hit 10448 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckS 1034 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckM 326 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckE 175 0.00% 0.00% +system.ruby.CorePair_Controller.L1I_Repl 589 0.00% 0.00% +system.ruby.CorePair_Controller.L1D0_Repl 24 0.00% 0.00% +system.ruby.CorePair_Controller.L2_to_L1D0 5 0.00% 0.00% +system.ruby.CorePair_Controller.L2_to_L1I 54 0.00% 0.00% +system.ruby.CorePair_Controller.PrbInvData 1 0.00% 0.00% +system.ruby.CorePair_Controller.PrbShrData 2 0.00% 0.00% +system.ruby.CorePair_Controller.I.C0_Load_L1miss 175 0.00% 0.00% +system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% +system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% +system.ruby.CorePair_Controller.S.Ifetch0_L1hit 86007 0.00% 0.00% +system.ruby.CorePair_Controller.S.Ifetch0_L1miss 54 0.00% 0.00% +system.ruby.CorePair_Controller.S.L1I_Repl 589 0.00% 0.00% +system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% +system.ruby.CorePair_Controller.E0.C0_Load_L1hit 3356 0.00% 0.00% +system.ruby.CorePair_Controller.E0.C0_Store_L1hit 46 0.00% 0.00% +system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% +system.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00% +system.ruby.CorePair_Controller.O.C0_Load_L1hit 3 0.00% 0.00% +system.ruby.CorePair_Controller.O.C0_Store_L1hit 1 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Load_L1miss 3 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Load_L1hit 12796 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Store_L1hit 10401 0.00% 0.00% +system.ruby.CorePair_Controller.M0.L1D0_Repl 8 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbInvData 1 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% +system.ruby.CorePair_Controller.I_E0S.NB_AckE 175 0.00% 0.00% +system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 54 0.00% 0.00% +system.ruby.CorePair_Controller.O_M0.NB_AckM 1 0.00% 0.00% +system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% +system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% +system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 3 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkS 1034 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkM 326 0.00% 0.00% +system.ruby.Directory_Controller.RdBlk 182 0.00% 0.00% +system.ruby.Directory_Controller.WriteThrough 16 0.00% 0.00% +system.ruby.Directory_Controller.Atomic 3 0.00% 0.00% +system.ruby.Directory_Controller.CPUPrbResp 4 0.00% 0.00% +system.ruby.Directory_Controller.ProbeAcksComplete 1560 0.00% 0.00% +system.ruby.Directory_Controller.MemData 1560 0.00% 0.00% +system.ruby.Directory_Controller.CoreUnblock 1541 0.00% 0.00% +system.ruby.Directory_Controller.UnblockWriteThrough 18 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkS 1034 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkM 326 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlk 182 0.00% 0.00% +system.ruby.Directory_Controller.U.WriteThrough 16 0.00% 0.00% +system.ruby.Directory_Controller.U.Atomic 2 0.00% 0.00% +system.ruby.Directory_Controller.BS_M.MemData 1034 0.00% 0.00% +system.ruby.Directory_Controller.BM_M.MemData 343 0.00% 0.00% +system.ruby.Directory_Controller.B_M.MemData 180 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 1034 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.Atomic 1 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.CPUPrbResp 1 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 343 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.MemData 1 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 180 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.MemData 2 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 1 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 1 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.CPUPrbResp 2 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 2 0.00% 0.00% +system.ruby.Directory_Controller.B.CoreUnblock 1541 0.00% 0.00% +system.ruby.Directory_Controller.B.UnblockWriteThrough 18 0.00% 0.00% +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 +system.ruby.LD.latency_hist::samples 16335 +system.ruby.LD.latency_hist::mean 3.253444 +system.ruby.LD.latency_hist::gmean 1.059859 +system.ruby.LD.latency_hist::stdev 21.887471 +system.ruby.LD.latency_hist | 16160 98.93% 98.93% | 0 0.00% 98.93% | 0 0.00% 98.93% | 170 1.04% 99.97% | 1 0.01% 99.98% | 1 0.01% 99.98% | 2 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 16335 +system.ruby.LD.hit_latency_hist::bucket_size 64 +system.ruby.LD.hit_latency_hist::max_bucket 639 +system.ruby.LD.hit_latency_hist::samples 175 +system.ruby.LD.hit_latency_hist::mean 210.828571 +system.ruby.LD.hit_latency_hist::gmean 209.031405 +system.ruby.LD.hit_latency_hist::stdev 34.022715 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 170 97.14% 97.14% | 1 0.57% 97.71% | 1 0.57% 98.29% | 2 1.14% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 175 +system.ruby.LD.miss_latency_hist::bucket_size 2 +system.ruby.LD.miss_latency_hist::max_bucket 19 +system.ruby.LD.miss_latency_hist::samples 16160 +system.ruby.LD.miss_latency_hist::mean 1.005569 +system.ruby.LD.miss_latency_hist::gmean 1.000911 +system.ruby.LD.miss_latency_hist::stdev 0.316580 +system.ruby.LD.miss_latency_hist | 16155 99.97% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 0 0.00% 99.97% | 5 0.03% 100.00% +system.ruby.LD.miss_latency_hist::total 16160 +system.ruby.ST.latency_hist::bucket_size 64 +system.ruby.ST.latency_hist::max_bucket 639 +system.ruby.ST.latency_hist::samples 10412 +system.ruby.ST.latency_hist::mean 7.384076 +system.ruby.ST.latency_hist::gmean 1.178989 +system.ruby.ST.latency_hist::stdev 36.341010 +system.ruby.ST.latency_hist | 10090 96.91% 96.91% | 0 0.00% 96.91% | 0 0.00% 96.91% | 309 2.97% 99.88% | 4 0.04% 99.91% | 2 0.02% 99.93% | 3 0.03% 99.96% | 4 0.04% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 10412 +system.ruby.ST.hit_latency_hist::bucket_size 64 +system.ruby.ST.hit_latency_hist::max_bucket 639 +system.ruby.ST.hit_latency_hist::samples 322 +system.ruby.ST.hit_latency_hist::mean 207.431677 +system.ruby.ST.hit_latency_hist::gmean 205.258691 +system.ruby.ST.hit_latency_hist::stdev 37.529677 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 309 95.96% 95.96% | 4 1.24% 97.20% | 2 0.62% 97.83% | 3 0.93% 98.76% | 4 1.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 322 +system.ruby.ST.miss_latency_hist::bucket_size 1 +system.ruby.ST.miss_latency_hist::max_bucket 9 +system.ruby.ST.miss_latency_hist::samples 10090 +system.ruby.ST.miss_latency_hist::mean 1 +system.ruby.ST.miss_latency_hist::gmean 1 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 10090 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 10090 +system.ruby.IFETCH.latency_hist::bucket_size 64 +system.ruby.IFETCH.latency_hist::max_bucket 639 +system.ruby.IFETCH.latency_hist::samples 87095 +system.ruby.IFETCH.latency_hist::mean 3.432677 +system.ruby.IFETCH.latency_hist::gmean 1.067087 +system.ruby.IFETCH.latency_hist::stdev 22.344689 +system.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 0 0.00% 98.81% | 0 0.00% 98.81% | 1006 1.16% 99.97% | 5 0.01% 99.97% | 10 0.01% 99.99% | 11 0.01% 100.00% | 2 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 87095 +system.ruby.IFETCH.hit_latency_hist::bucket_size 64 +system.ruby.IFETCH.hit_latency_hist::max_bucket 639 +system.ruby.IFETCH.hit_latency_hist::samples 1034 +system.ruby.IFETCH.hit_latency_hist::mean 204.967118 +system.ruby.IFETCH.hit_latency_hist::gmean 203.475698 +system.ruby.IFETCH.hit_latency_hist::stdev 30.573589 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1006 97.29% 97.29% | 5 0.48% 97.78% | 10 0.97% 98.74% | 11 1.06% 99.81% | 2 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 1034 +system.ruby.IFETCH.miss_latency_hist::bucket_size 2 +system.ruby.IFETCH.miss_latency_hist::max_bucket 19 +system.ruby.IFETCH.miss_latency_hist::samples 86061 +system.ruby.IFETCH.miss_latency_hist::mean 1.011294 +system.ruby.IFETCH.miss_latency_hist::gmean 1.001849 +system.ruby.IFETCH.miss_latency_hist::stdev 0.450747 +system.ruby.IFETCH.miss_latency_hist | 86007 99.94% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 0 0.00% 99.94% | 54 0.06% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 86061 +system.ruby.RMW_Read.latency_hist::bucket_size 32 +system.ruby.RMW_Read.latency_hist::max_bucket 319 +system.ruby.RMW_Read.latency_hist::samples 341 +system.ruby.RMW_Read.latency_hist::mean 3.451613 +system.ruby.RMW_Read.latency_hist::gmean 1.064718 +system.ruby.RMW_Read.latency_hist::stdev 22.561449 +system.ruby.RMW_Read.latency_hist | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 3 0.88% 99.71% | 1 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 341 +system.ruby.RMW_Read.hit_latency_hist::bucket_size 32 +system.ruby.RMW_Read.hit_latency_hist::max_bucket 319 +system.ruby.RMW_Read.hit_latency_hist::samples 4 +system.ruby.RMW_Read.hit_latency_hist::mean 210 +system.ruby.RMW_Read.hit_latency_hist::gmean 209.766277 +system.ruby.RMW_Read.hit_latency_hist::stdev 11.430952 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 4 +system.ruby.RMW_Read.miss_latency_hist::bucket_size 1 +system.ruby.RMW_Read.miss_latency_hist::max_bucket 9 +system.ruby.RMW_Read.miss_latency_hist::samples 337 +system.ruby.RMW_Read.miss_latency_hist::mean 1 +system.ruby.RMW_Read.miss_latency_hist::gmean 1 +system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 337 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.latency_hist::samples 10 +system.ruby.Locked_RMW_Read.latency_hist::mean 1 +system.ruby.Locked_RMW_Read.latency_hist::gmean 1 +system.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 10 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 10 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 1 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 1 +system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 10 +system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.latency_hist::samples 10 +system.ruby.Locked_RMW_Write.latency_hist::mean 1 +system.ruby.Locked_RMW_Write.latency_hist::gmean 1 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 10 +system.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.miss_latency_hist::samples 10 +system.ruby.Locked_RMW_Write.miss_latency_hist::mean 1 +system.ruby.Locked_RMW_Write.miss_latency_hist::gmean 1 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100.00% | 0 0.00% 100.00% +system.ruby.Directory.hit_mach_latency_hist::total 1535 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 16155 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 16155 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 16155 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size 2 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket 19 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::samples 5 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::mean 19 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::gmean 19.000000 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 5 100.00% 100.00% +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::total 5 +system.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket 639 +system.ruby.LD.Directory.hit_type_mach_latency_hist::samples 175 +system.ruby.LD.Directory.hit_type_mach_latency_hist::mean 210.828571 +system.ruby.LD.Directory.hit_type_mach_latency_hist::gmean 209.031405 +system.ruby.LD.Directory.hit_type_mach_latency_hist::stdev 34.022715 +system.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 170 97.14% 97.14% | 1 0.57% 97.71% | 1 0.57% 98.29% | 2 1.14% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 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+system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 205.258691 +system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 37.529677 +system.ruby.ST.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 309 95.96% 95.96% | 4 1.24% 97.20% | 2 0.62% 97.83% | 3 0.93% 98.76% | 4 1.24% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.hit_type_mach_latency_hist::total 322 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples 86007 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 86007 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total 86007 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size 2 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket 19 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples 54 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean 19 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean 19.000000 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 54 100.00% 100.00% +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total 54 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 64 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 639 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1034 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 204.967118 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 203.475698 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev 30.573589 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1006 97.29% 97.29% | 5 0.48% 97.78% | 10 0.97% 98.74% | 11 1.06% 99.81% | 2 0.19% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1034 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 337 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total 337 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size 32 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket 319 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples 4 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean 210 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean 209.766277 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::stdev 11.430952 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total 4 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 10 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total 10 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::samples 10 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::total 10 +system.ruby.SQC_Controller.Fetch 86 0.00% 0.00% +system.ruby.SQC_Controller.Data 5 0.00% 0.00% +system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% +system.ruby.SQC_Controller.I.Data 5 0.00% 0.00% +system.ruby.SQC_Controller.V.Fetch 81 0.00% 0.00% +system.ruby.TCC_Controller.RdBlk 9 0.00% 0.00% +system.ruby.TCC_Controller.WrVicBlk 16 0.00% 0.00% +system.ruby.TCC_Controller.Atomic 2 0.00% 0.00% +system.ruby.TCC_Controller.AtomicDone 1 0.00% 0.00% +system.ruby.TCC_Controller.Data 9 0.00% 0.00% +system.ruby.TCC_Controller.PrbInv 1 0.00% 0.00% +system.ruby.TCC_Controller.WBAck 16 0.00% 0.00% +system.ruby.TCC_Controller.V.PrbInv 1 0.00% 0.00% +system.ruby.TCC_Controller.I.RdBlk 7 0.00% 0.00% +system.ruby.TCC_Controller.I.WrVicBlk 16 0.00% 0.00% +system.ruby.TCC_Controller.I.Atomic 1 0.00% 0.00% +system.ruby.TCC_Controller.I.WBAck 16 0.00% 0.00% +system.ruby.TCC_Controller.IV.RdBlk 2 0.00% 0.00% +system.ruby.TCC_Controller.IV.Data 7 0.00% 0.00% +system.ruby.TCC_Controller.A.Atomic 1 0.00% 0.00% +system.ruby.TCC_Controller.A.AtomicDone 1 0.00% 0.00% +system.ruby.TCC_Controller.A.Data 2 0.00% 0.00% +system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00% +system.ruby.TCP_Controller.Load::total 10 +system.ruby.TCP_Controller.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.StoreThrough::total 16 +system.ruby.TCP_Controller.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.Atomic::total 2 +system.ruby.TCP_Controller.Flush | 768 50.00% 50.00% | 768 50.00% 100.00% +system.ruby.TCP_Controller.Flush::total 1536 +system.ruby.TCP_Controller.Evict | 512 50.00% 50.00% | 512 50.00% 100.00% +system.ruby.TCP_Controller.Evict::total 1024 +system.ruby.TCP_Controller.TCC_Ack | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.TCP_Controller.TCC_Ack::total 6 +system.ruby.TCP_Controller.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.TCC_AckWB::total 16 +system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.I.Load::total 4 +system.ruby.TCP_Controller.I.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.I.StoreThrough::total 16 +system.ruby.TCP_Controller.I.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.I.Atomic::total 2 +system.ruby.TCP_Controller.I.Flush | 766 50.00% 50.00% | 766 50.00% 100.00% +system.ruby.TCP_Controller.I.Flush::total 1532 +system.ruby.TCP_Controller.I.Evict | 510 50.00% 50.00% | 510 50.00% 100.00% +system.ruby.TCP_Controller.I.Evict::total 1020 +system.ruby.TCP_Controller.I.TCC_Ack | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.I.TCC_Ack::total 4 +system.ruby.TCP_Controller.I.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.I.TCC_AckWB::total 16 +system.ruby.TCP_Controller.V.Load | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.TCP_Controller.V.Load::total 6 +system.ruby.TCP_Controller.V.Flush | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.V.Flush::total 4 +system.ruby.TCP_Controller.V.Evict | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.V.Evict::total 4 +system.ruby.TCP_Controller.A.TCC_Ack | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.A.TCC_Ack::total 2 + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/config.ini b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/config.ini new file mode 100644 index 000000000..38646dce2 --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/config.ini @@ -0,0 +1,5094 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=clk_domain cp_cntrl0 cpu0 cpu1 cpu2 dir_cntrl0 dispatcher_coalescer dispatcher_tlb dvfs_handler l1_coalescer0 l1_coalescer1 l1_tlb0 l1_tlb1 l2_coalescer l2_tlb l3_coalescer l3_tlb mem_ctrls piobus rb_cntrl0 reg_cntrl0 ruby sqc_cntrl0 sqc_coalescer sqc_tlb sys_port_proxy tcc_cntrl0 tcc_rb_cntrl0 tcp_cntrl0 tcp_cntrl1 voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:536870911 +memories=system.mem_ctrls system.ruby.phys_mem +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cp_cntrl0] +type=CorePair_Controller +children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore +L1D0cache=system.cp_cntrl0.L1D0cache +L1D1cache=system.cp_cntrl0.L1D1cache +L1Icache=system.cp_cntrl0.L1Icache +L2cache=system.cp_cntrl0.L2cache +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +issue_latency=1 +l2_hit_latency=18 +mandatoryQueue=system.cp_cntrl0.mandatoryQueue +number_of_TBEs=256 +probeToCore=system.cp_cntrl0.probeToCore +recycle_latency=10 +regionBufferNum=0 +requestFromCore=system.cp_cntrl0.requestFromCore +responseFromCore=system.cp_cntrl0.responseFromCore +responseToCore=system.cp_cntrl0.responseToCore +ruby_system=system.ruby +send_evictions=true +sequencer=system.cp_cntrl0.sequencer +sequencer1=system.cp_cntrl0.sequencer1 +system=system +transitions_per_cycle=32 +triggerQueue=system.cp_cntrl0.triggerQueue +unblockFromCore=system.cp_cntrl0.unblockFromCore +version=0 + +[system.cp_cntrl0.L1D0cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=2 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1D0cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=65536 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=2 + +[system.cp_cntrl0.L1D0cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=65536 + +[system.cp_cntrl0.L1D1cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=2 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1D1cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=65536 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=2 + +[system.cp_cntrl0.L1D1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=65536 + +[system.cp_cntrl0.L1Icache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=2 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1Icache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=32768 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=2 + +[system.cp_cntrl0.L1Icache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=32768 + +[system.cp_cntrl0.L2cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L2cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=2097152 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=16 + +[system.cp_cntrl0.L2cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=2097152 + +[system.cp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.cp_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[0] + +[system.cp_cntrl0.requestFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[0] + +[system.cp_cntrl0.responseFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[1] + +[system.cp_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[1] + +[system.cp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=0 +dcache=system.cp_cntrl0.L1D0cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.cp_cntrl0.L1Icache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave +mem_master_port=system.piobus.slave[0] +slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master + +[system.cp_cntrl0.sequencer1] +type=RubySequencer +clk_domain=system.clk_domain +coreid=1 +dcache=system.cp_cntrl0.L1D1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.cp_cntrl0.L1Icache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=1 + +[system.cp_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.cp_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.cpu0] +type=TimingSimpleCPU +children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload +branchPred=Null +checker=Null +clk_domain=system.cpu0.clk_domain +cpu_id=0 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +eventq_index=0 +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +isa=system.cpu0.isa +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +profile=0 +progress_interval=0 +simpoint_start_insts= +socket_id=0 +switched_out=false +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.cp_cntrl0.sequencer.slave[1] +icache_port=system.cp_cntrl0.sequencer.slave[0] + +[system.cpu0.apic_clk_domain] +type=DerivedClockDomain +clk_divider=16 +clk_domain=system.cpu0.clk_domain +eventq_index=0 + +[system.cpu0.clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cpu0.dtb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +clk_domain=system.cpu0.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.cp_cntrl0.sequencer.slave[3] + +[system.cpu0.interrupts] +type=X86LocalApic +clk_domain=system.cpu0.apic_clk_domain +eventq_index=0 +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=100000 +system=system +int_master=system.cp_cntrl0.sequencer.slave[4] +int_slave=system.cp_cntrl0.sequencer.master[1] +pio=system.cp_cntrl0.sequencer.master[0] + +[system.cpu0.isa] +type=X86ISA +eventq_index=0 + +[system.cpu0.itb] +type=X86TLB +children=walker +eventq_index=0 +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +clk_domain=system.cpu0.clk_domain +eventq_index=0 +num_squash_per_cycle=4 +system=system +port=system.cp_cntrl0.sequencer.slave[2] + +[system.cpu0.tracer] +type=ExeTracer +eventq_index=0 + +[system.cpu0.workload] +type=LiveProcess +cmd=gpu-hello +cwd= +drivers=system.cpu2.cl_driver +egid=100 +env= +errout=cerr +euid=100 +eventq_index=0 +executable=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello +gid=100 +input=cin +kvmInSE=false +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 +useArchPT=false + +[system.cpu1] +type=Shader +children=CUs0 CUs1 clk_domain +CUs=system.cpu1.CUs0 system.cpu1.CUs1 +clk_domain=system.cpu1.clk_domain +cpu_pointer=system.cpu0 +eventq_index=0 +globalmem=65536 +impl_kern_boundary_sync=true +n_wf=8 +separate_acquire_release=false +timing=true +translation=false + +[system.cpu1.CUs0] +type=ComputeUnit +children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31 +clk_domain=system.cpu1.clk_domain +coalescer_to_vrf_bus_width=32 +countPages=false +cu_id=0 +debugSegFault=false +dpbypass_pipe_length=4 +eventq_index=0 +execPolicy=OLDEST-FIRST +functionalTLB=true +global_mem_queue_size=256 +issue_period=4 +localDataStore=system.cpu1.CUs0.localDataStore +localMemBarrier=false +local_mem_queue_size=256 +mem_req_latency=9 +mem_resp_latency=9 +n_wf=8 +num_SIMDs=4 +num_global_mem_pipes=1 +num_shared_mem_pipes=1 +perLaneTLB=false +prefetch_depth=0 +prefetch_prev_type=PF_PHASE +prefetch_stride=1 +spbypass_pipe_length=4 +system=system +vector_register_file=system.cpu1.CUs0.vector_register_file0 system.cpu1.CUs0.vector_register_file1 system.cpu1.CUs0.vector_register_file2 system.cpu1.CUs0.vector_register_file3 +vrf_to_coalescer_bus_width=32 +wavefronts=system.cpu1.CUs0.wavefronts00 system.cpu1.CUs0.wavefronts01 system.cpu1.CUs0.wavefronts02 system.cpu1.CUs0.wavefronts03 system.cpu1.CUs0.wavefronts04 system.cpu1.CUs0.wavefronts05 system.cpu1.CUs0.wavefronts06 system.cpu1.CUs0.wavefronts07 system.cpu1.CUs0.wavefronts08 system.cpu1.CUs0.wavefronts09 system.cpu1.CUs0.wavefronts10 system.cpu1.CUs0.wavefronts11 system.cpu1.CUs0.wavefronts12 system.cpu1.CUs0.wavefronts13 system.cpu1.CUs0.wavefronts14 system.cpu1.CUs0.wavefronts15 system.cpu1.CUs0.wavefronts16 system.cpu1.CUs0.wavefronts17 system.cpu1.CUs0.wavefronts18 system.cpu1.CUs0.wavefronts19 system.cpu1.CUs0.wavefronts20 system.cpu1.CUs0.wavefronts21 system.cpu1.CUs0.wavefronts22 system.cpu1.CUs0.wavefronts23 system.cpu1.CUs0.wavefronts24 system.cpu1.CUs0.wavefronts25 system.cpu1.CUs0.wavefronts26 system.cpu1.CUs0.wavefronts27 system.cpu1.CUs0.wavefronts28 system.cpu1.CUs0.wavefronts29 system.cpu1.CUs0.wavefronts30 system.cpu1.CUs0.wavefronts31 +wfSize=64 +xactCasMode=false +ldsPort=system.cpu1.CUs0.ldsBus.slave +memory_port=system.tcp_cntrl0.coalescer.slave[0] system.tcp_cntrl0.coalescer.slave[1] system.tcp_cntrl0.coalescer.slave[2] system.tcp_cntrl0.coalescer.slave[3] system.tcp_cntrl0.coalescer.slave[4] system.tcp_cntrl0.coalescer.slave[5] system.tcp_cntrl0.coalescer.slave[6] system.tcp_cntrl0.coalescer.slave[7] system.tcp_cntrl0.coalescer.slave[8] system.tcp_cntrl0.coalescer.slave[9] system.tcp_cntrl0.coalescer.slave[10] system.tcp_cntrl0.coalescer.slave[11] system.tcp_cntrl0.coalescer.slave[12] system.tcp_cntrl0.coalescer.slave[13] system.tcp_cntrl0.coalescer.slave[14] system.tcp_cntrl0.coalescer.slave[15] system.tcp_cntrl0.coalescer.slave[16] system.tcp_cntrl0.coalescer.slave[17] system.tcp_cntrl0.coalescer.slave[18] system.tcp_cntrl0.coalescer.slave[19] system.tcp_cntrl0.coalescer.slave[20] system.tcp_cntrl0.coalescer.slave[21] system.tcp_cntrl0.coalescer.slave[22] system.tcp_cntrl0.coalescer.slave[23] system.tcp_cntrl0.coalescer.slave[24] system.tcp_cntrl0.coalescer.slave[25] system.tcp_cntrl0.coalescer.slave[26] system.tcp_cntrl0.coalescer.slave[27] system.tcp_cntrl0.coalescer.slave[28] system.tcp_cntrl0.coalescer.slave[29] system.tcp_cntrl0.coalescer.slave[30] system.tcp_cntrl0.coalescer.slave[31] system.tcp_cntrl0.coalescer.slave[32] system.tcp_cntrl0.coalescer.slave[33] system.tcp_cntrl0.coalescer.slave[34] system.tcp_cntrl0.coalescer.slave[35] system.tcp_cntrl0.coalescer.slave[36] system.tcp_cntrl0.coalescer.slave[37] system.tcp_cntrl0.coalescer.slave[38] system.tcp_cntrl0.coalescer.slave[39] system.tcp_cntrl0.coalescer.slave[40] system.tcp_cntrl0.coalescer.slave[41] system.tcp_cntrl0.coalescer.slave[42] system.tcp_cntrl0.coalescer.slave[43] system.tcp_cntrl0.coalescer.slave[44] system.tcp_cntrl0.coalescer.slave[45] system.tcp_cntrl0.coalescer.slave[46] system.tcp_cntrl0.coalescer.slave[47] system.tcp_cntrl0.coalescer.slave[48] system.tcp_cntrl0.coalescer.slave[49] system.tcp_cntrl0.coalescer.slave[50] system.tcp_cntrl0.coalescer.slave[51] system.tcp_cntrl0.coalescer.slave[52] system.tcp_cntrl0.coalescer.slave[53] system.tcp_cntrl0.coalescer.slave[54] system.tcp_cntrl0.coalescer.slave[55] system.tcp_cntrl0.coalescer.slave[56] system.tcp_cntrl0.coalescer.slave[57] system.tcp_cntrl0.coalescer.slave[58] system.tcp_cntrl0.coalescer.slave[59] system.tcp_cntrl0.coalescer.slave[60] system.tcp_cntrl0.coalescer.slave[61] system.tcp_cntrl0.coalescer.slave[62] system.tcp_cntrl0.coalescer.slave[63] +sqc_port=system.sqc_cntrl0.sequencer.slave[0] +sqc_tlb_port=system.sqc_coalescer.slave[0] +translation_port=system.l1_coalescer0.slave[0] + +[system.cpu1.CUs0.ldsBus] +type=Bridge +clk_domain=system.cpu1.clk_domain +delay=0 +eventq_index=0 +ranges=0:18446744073709551615 +req_size=16 +resp_size=16 +master=system.cpu1.CUs0.localDataStore.cuPort +slave=system.cpu1.CUs0.ldsPort + +[system.cpu1.CUs0.localDataStore] +type=LdsState +bankConflictPenalty=1 +banks=32 +clk_domain=system.cpu1.clk_domain +eventq_index=0 +range=0:65535 +size=65536 +cuPort=system.cpu1.CUs0.ldsBus.master + +[system.cpu1.CUs0.vector_register_file0] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=0 + +[system.cpu1.CUs0.vector_register_file1] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=1 + +[system.cpu1.CUs0.vector_register_file2] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=2 + +[system.cpu1.CUs0.vector_register_file3] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=3 + +[system.cpu1.CUs0.wavefronts00] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts01] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts02] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts03] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts04] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts05] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts06] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts07] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts08] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts09] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts10] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts11] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts12] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts13] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts14] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts15] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts16] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts17] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts18] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts19] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts20] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts21] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts22] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts23] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=7 + +[system.cpu1.CUs0.wavefronts24] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=0 + +[system.cpu1.CUs0.wavefronts25] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=1 + +[system.cpu1.CUs0.wavefronts26] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=2 + +[system.cpu1.CUs0.wavefronts27] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=3 + +[system.cpu1.CUs0.wavefronts28] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=4 + +[system.cpu1.CUs0.wavefronts29] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=5 + +[system.cpu1.CUs0.wavefronts30] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=6 + +[system.cpu1.CUs0.wavefronts31] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=7 + +[system.cpu1.CUs1] +type=ComputeUnit +children=ldsBus localDataStore vector_register_file0 vector_register_file1 vector_register_file2 vector_register_file3 wavefronts00 wavefronts01 wavefronts02 wavefronts03 wavefronts04 wavefronts05 wavefronts06 wavefronts07 wavefronts08 wavefronts09 wavefronts10 wavefronts11 wavefronts12 wavefronts13 wavefronts14 wavefronts15 wavefronts16 wavefronts17 wavefronts18 wavefronts19 wavefronts20 wavefronts21 wavefronts22 wavefronts23 wavefronts24 wavefronts25 wavefronts26 wavefronts27 wavefronts28 wavefronts29 wavefronts30 wavefronts31 +clk_domain=system.cpu1.clk_domain +coalescer_to_vrf_bus_width=32 +countPages=false +cu_id=1 +debugSegFault=false +dpbypass_pipe_length=4 +eventq_index=0 +execPolicy=OLDEST-FIRST +functionalTLB=true +global_mem_queue_size=256 +issue_period=4 +localDataStore=system.cpu1.CUs1.localDataStore +localMemBarrier=false +local_mem_queue_size=256 +mem_req_latency=9 +mem_resp_latency=9 +n_wf=8 +num_SIMDs=4 +num_global_mem_pipes=1 +num_shared_mem_pipes=1 +perLaneTLB=false +prefetch_depth=0 +prefetch_prev_type=PF_PHASE +prefetch_stride=1 +spbypass_pipe_length=4 +system=system +vector_register_file=system.cpu1.CUs1.vector_register_file0 system.cpu1.CUs1.vector_register_file1 system.cpu1.CUs1.vector_register_file2 system.cpu1.CUs1.vector_register_file3 +vrf_to_coalescer_bus_width=32 +wavefronts=system.cpu1.CUs1.wavefronts00 system.cpu1.CUs1.wavefronts01 system.cpu1.CUs1.wavefronts02 system.cpu1.CUs1.wavefronts03 system.cpu1.CUs1.wavefronts04 system.cpu1.CUs1.wavefronts05 system.cpu1.CUs1.wavefronts06 system.cpu1.CUs1.wavefronts07 system.cpu1.CUs1.wavefronts08 system.cpu1.CUs1.wavefronts09 system.cpu1.CUs1.wavefronts10 system.cpu1.CUs1.wavefronts11 system.cpu1.CUs1.wavefronts12 system.cpu1.CUs1.wavefronts13 system.cpu1.CUs1.wavefronts14 system.cpu1.CUs1.wavefronts15 system.cpu1.CUs1.wavefronts16 system.cpu1.CUs1.wavefronts17 system.cpu1.CUs1.wavefronts18 system.cpu1.CUs1.wavefronts19 system.cpu1.CUs1.wavefronts20 system.cpu1.CUs1.wavefronts21 system.cpu1.CUs1.wavefronts22 system.cpu1.CUs1.wavefronts23 system.cpu1.CUs1.wavefronts24 system.cpu1.CUs1.wavefronts25 system.cpu1.CUs1.wavefronts26 system.cpu1.CUs1.wavefronts27 system.cpu1.CUs1.wavefronts28 system.cpu1.CUs1.wavefronts29 system.cpu1.CUs1.wavefronts30 system.cpu1.CUs1.wavefronts31 +wfSize=64 +xactCasMode=false +ldsPort=system.cpu1.CUs1.ldsBus.slave +memory_port=system.tcp_cntrl1.coalescer.slave[0] system.tcp_cntrl1.coalescer.slave[1] system.tcp_cntrl1.coalescer.slave[2] system.tcp_cntrl1.coalescer.slave[3] system.tcp_cntrl1.coalescer.slave[4] system.tcp_cntrl1.coalescer.slave[5] system.tcp_cntrl1.coalescer.slave[6] system.tcp_cntrl1.coalescer.slave[7] system.tcp_cntrl1.coalescer.slave[8] system.tcp_cntrl1.coalescer.slave[9] system.tcp_cntrl1.coalescer.slave[10] system.tcp_cntrl1.coalescer.slave[11] system.tcp_cntrl1.coalescer.slave[12] system.tcp_cntrl1.coalescer.slave[13] system.tcp_cntrl1.coalescer.slave[14] system.tcp_cntrl1.coalescer.slave[15] system.tcp_cntrl1.coalescer.slave[16] system.tcp_cntrl1.coalescer.slave[17] system.tcp_cntrl1.coalescer.slave[18] system.tcp_cntrl1.coalescer.slave[19] system.tcp_cntrl1.coalescer.slave[20] system.tcp_cntrl1.coalescer.slave[21] system.tcp_cntrl1.coalescer.slave[22] system.tcp_cntrl1.coalescer.slave[23] system.tcp_cntrl1.coalescer.slave[24] system.tcp_cntrl1.coalescer.slave[25] system.tcp_cntrl1.coalescer.slave[26] system.tcp_cntrl1.coalescer.slave[27] system.tcp_cntrl1.coalescer.slave[28] system.tcp_cntrl1.coalescer.slave[29] system.tcp_cntrl1.coalescer.slave[30] system.tcp_cntrl1.coalescer.slave[31] system.tcp_cntrl1.coalescer.slave[32] system.tcp_cntrl1.coalescer.slave[33] system.tcp_cntrl1.coalescer.slave[34] system.tcp_cntrl1.coalescer.slave[35] system.tcp_cntrl1.coalescer.slave[36] system.tcp_cntrl1.coalescer.slave[37] system.tcp_cntrl1.coalescer.slave[38] system.tcp_cntrl1.coalescer.slave[39] system.tcp_cntrl1.coalescer.slave[40] system.tcp_cntrl1.coalescer.slave[41] system.tcp_cntrl1.coalescer.slave[42] system.tcp_cntrl1.coalescer.slave[43] system.tcp_cntrl1.coalescer.slave[44] system.tcp_cntrl1.coalescer.slave[45] system.tcp_cntrl1.coalescer.slave[46] system.tcp_cntrl1.coalescer.slave[47] system.tcp_cntrl1.coalescer.slave[48] system.tcp_cntrl1.coalescer.slave[49] system.tcp_cntrl1.coalescer.slave[50] system.tcp_cntrl1.coalescer.slave[51] system.tcp_cntrl1.coalescer.slave[52] system.tcp_cntrl1.coalescer.slave[53] system.tcp_cntrl1.coalescer.slave[54] system.tcp_cntrl1.coalescer.slave[55] system.tcp_cntrl1.coalescer.slave[56] system.tcp_cntrl1.coalescer.slave[57] system.tcp_cntrl1.coalescer.slave[58] system.tcp_cntrl1.coalescer.slave[59] system.tcp_cntrl1.coalescer.slave[60] system.tcp_cntrl1.coalescer.slave[61] system.tcp_cntrl1.coalescer.slave[62] system.tcp_cntrl1.coalescer.slave[63] +sqc_port=system.sqc_cntrl0.sequencer.slave[1] +sqc_tlb_port=system.sqc_coalescer.slave[1] +translation_port=system.l1_coalescer1.slave[0] + +[system.cpu1.CUs1.ldsBus] +type=Bridge +clk_domain=system.cpu1.clk_domain +delay=0 +eventq_index=0 +ranges=0:18446744073709551615 +req_size=16 +resp_size=16 +master=system.cpu1.CUs1.localDataStore.cuPort +slave=system.cpu1.CUs1.ldsPort + +[system.cpu1.CUs1.localDataStore] +type=LdsState +bankConflictPenalty=1 +banks=32 +clk_domain=system.cpu1.clk_domain +eventq_index=0 +range=0:65535 +size=65536 +cuPort=system.cpu1.CUs1.ldsBus.master + +[system.cpu1.CUs1.vector_register_file0] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=0 + +[system.cpu1.CUs1.vector_register_file1] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=1 + +[system.cpu1.CUs1.vector_register_file2] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=2 + +[system.cpu1.CUs1.vector_register_file3] +type=VectorRegisterFile +eventq_index=0 +min_alloc=4 +num_regs_per_simd=2048 +simd_id=3 + +[system.cpu1.CUs1.wavefronts00] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts01] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts02] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts03] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts04] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts05] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts06] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts07] +type=Wavefront +eventq_index=0 +simdId=0 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts08] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts09] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts10] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts11] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts12] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts13] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts14] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts15] +type=Wavefront +eventq_index=0 +simdId=1 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts16] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts17] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts18] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts19] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts20] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts21] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts22] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts23] +type=Wavefront +eventq_index=0 +simdId=2 +wf_slot_id=7 + +[system.cpu1.CUs1.wavefronts24] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=0 + +[system.cpu1.CUs1.wavefronts25] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=1 + +[system.cpu1.CUs1.wavefronts26] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=2 + +[system.cpu1.CUs1.wavefronts27] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=3 + +[system.cpu1.CUs1.wavefronts28] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=4 + +[system.cpu1.CUs1.wavefronts29] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=5 + +[system.cpu1.CUs1.wavefronts30] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=6 + +[system.cpu1.CUs1.wavefronts31] +type=Wavefront +eventq_index=0 +simdId=3 +wf_slot_id=7 + +[system.cpu1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.cpu1.clk_domain.voltage_domain + +[system.cpu1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.cpu2] +type=GpuDispatcher +children=cl_driver +cl_driver=system.cpu2.cl_driver +clk_domain=system.clk_domain +cpu=system.cpu0 +eventq_index=0 +pio_addr=8589934592 +pio_latency=1000 +shader_pointer=system.cpu1 +system=system +dma=system.piobus.slave[1] +pio=system.piobus.master[0] +translation_port=system.dispatcher_coalescer.slave[0] + +[system.cpu2.cl_driver] +type=ClDriver +codefile=/dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +eventq_index=0 +filename=hsa + +[system.dir_cntrl0] +type=Directory_Controller +children=L3CacheMemory L3triggerQueue directory probeToCore reqFromRegBuf reqFromRegDir reqToRegDir requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores unblockToRegDir +L3CacheMemory=system.dir_cntrl0.L3CacheMemory +L3triggerQueue=system.dir_cntrl0.L3triggerQueue +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +directory=system.dir_cntrl0.directory +eventq_index=0 +l3_hit_latency=15 +number_of_TBEs=5120 +probeToCore=system.dir_cntrl0.probeToCore +recycle_latency=10 +reqFromRegBuf=system.dir_cntrl0.reqFromRegBuf +reqFromRegDir=system.dir_cntrl0.reqFromRegDir +reqToRegDir=system.dir_cntrl0.reqToRegDir +requestFromCores=system.dir_cntrl0.requestFromCores +responseFromCores=system.dir_cntrl0.responseFromCores +responseFromMemory=system.dir_cntrl0.responseFromMemory +responseToCore=system.dir_cntrl0.responseToCore +response_latency=25 +response_latency_regionDir=1 +ruby_system=system.ruby +system=system +to_memory_controller_latency=1 +transitions_per_cycle=32 +triggerQueue=system.dir_cntrl0.triggerQueue +unblockFromCores=system.dir_cntrl0.unblockFromCores +unblockToRegDir=system.dir_cntrl0.unblockToRegDir +useL3OnWT=false +version=0 +memory=system.mem_ctrls.port + +[system.dir_cntrl0.L3CacheMemory] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=20 +dataArrayBanks=16.0 +eventq_index=0 +is_icache=false +replacement_policy=system.dir_cntrl0.L3CacheMemory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=16777216 +start_index_bit=6 +tagAccessLatency=15 +tagArrayBanks=16.0 + +[system.dir_cntrl0.L3CacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=16777216 + +[system.dir_cntrl0.L3triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +eventq_index=0 +numa_high_bit=5 +size=536870912 +version=0 + +[system.dir_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[18] + +[system.dir_cntrl0.reqFromRegBuf] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[24] + +[system.dir_cntrl0.reqFromRegDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[25] + +[system.dir_cntrl0.reqToRegDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[20] + +[system.dir_cntrl0.requestFromCores] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[21] + +[system.dir_cntrl0.responseFromCores] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[22] + +[system.dir_cntrl0.responseFromMemory] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.dir_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[19] + +[system.dir_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.dir_cntrl0.unblockFromCores] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[23] + +[system.dir_cntrl0.unblockToRegDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[21] + +[system.dispatcher_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.dispatcher_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.dispatcher_tlb.slave[0] +slave=system.cpu2.translation_port + +[system.dispatcher_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.dispatcher_coalescer.clk_domain.voltage_domain + +[system.dispatcher_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.dispatcher_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.dispatcher_tlb.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[1] +slave=system.dispatcher_coalescer.master[0] + +[system.dispatcher_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.dispatcher_tlb.clk_domain.voltage_domain + +[system.dispatcher_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.dvfs_handler] +type=DVFSHandler +domains= +enable=false +eventq_index=0 +sys_clk_domain=system.clk_domain +transition_latency=100000000 + +[system.l1_coalescer0] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l1_coalescer0.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l1_tlb0.slave[0] +slave=system.cpu1.CUs0.translation_port[0] + +[system.l1_coalescer0.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_coalescer0.clk_domain.voltage_domain + +[system.l1_coalescer0.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_coalescer1] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l1_coalescer1.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l1_tlb1.slave[0] +slave=system.cpu1.CUs1.translation_port[0] + +[system.l1_coalescer1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_coalescer1.clk_domain.voltage_domain + +[system.l1_coalescer1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_tlb0] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l1_tlb0.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[2] +slave=system.l1_coalescer0.master[0] + +[system.l1_tlb0.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_tlb0.clk_domain.voltage_domain + +[system.l1_tlb0.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l1_tlb1] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l1_tlb1.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[3] +slave=system.l1_coalescer1.master[0] + +[system.l1_tlb1.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l1_tlb1.clk_domain.voltage_domain + +[system.l1_tlb1.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l2_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l2_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l2_tlb.slave[0] +slave=system.sqc_tlb.master[0] system.dispatcher_tlb.master[0] system.l1_tlb0.master[0] system.l1_tlb1.master[0] + +[system.l2_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l2_coalescer.clk_domain.voltage_domain + +[system.l2_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l2_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l2_tlb.clk_domain +eventq_index=0 +hitLatency=69 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=4096 +master=system.l3_coalescer.slave[0] +slave=system.l2_coalescer.master[0] + +[system.l2_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l2_tlb.clk_domain.voltage_domain + +[system.l2_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l3_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.l3_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.l3_tlb.slave[0] +slave=system.l2_tlb.master[0] + +[system.l3_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l3_coalescer.clk_domain.voltage_domain + +[system.l3_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.l3_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.l3_tlb.clk_domain +eventq_index=0 +hitLatency=150 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=8192 +slave=system.l3_coalescer.master[0] + +[system.l3_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.l3_tlb.clk_domain.voltage_domain + +[system.l3_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.mem_ctrls] +type=DRAMCtrl +IDD0=0.075000 +IDD02=0.000000 +IDD2N=0.050000 +IDD2N2=0.000000 +IDD2P0=0.000000 +IDD2P02=0.000000 +IDD2P1=0.000000 +IDD2P12=0.000000 +IDD3N=0.057000 +IDD3N2=0.000000 +IDD3P0=0.000000 +IDD3P02=0.000000 +IDD3P1=0.000000 +IDD3P12=0.000000 +IDD4R=0.187000 +IDD4R2=0.000000 +IDD4W=0.165000 +IDD4W2=0.000000 +IDD5=0.220000 +IDD52=0.000000 +IDD6=0.000000 +IDD62=0.000000 +VDD=1.500000 +VDD2=0.000000 +activation_limit=4 +addr_mapping=RoRaBaCoCh +bank_groups_per_rank=0 +banks_per_rank=8 +burst_length=8 +channels=1 +clk_domain=system.clk_domain +conf_table_reported=true +device_bus_width=8 +device_rowbuffer_size=1024 +device_size=536870912 +devices_per_rank=8 +dll=true +eventq_index=0 +in_addr_map=true +max_accesses_per_row=16 +mem_sched_policy=frfcfs +min_writes_per_switch=16 +null=false +page_policy=open_adaptive +range=0:536870911 +ranks_per_channel=2 +read_buffer_size=32 +static_backend_latency=10000 +static_frontend_latency=10000 +tBURST=5000 +tCCD_L=0 +tCK=1250 +tCL=13750 +tCS=2500 +tRAS=35000 +tRCD=13750 +tREFI=7800000 +tRFC=260000 +tRP=13750 +tRRD=6000 +tRRD_L=0 +tRTP=7500 +tRTW=2500 +tWR=15000 +tWTR=7500 +tXAW=30000 +tXP=0 +tXPDLL=0 +tXS=0 +tXSDLL=0 +write_buffer_size=64 +write_high_thresh_perc=85 +write_low_thresh_perc=50 +port=system.dir_cntrl0.memory + +[system.piobus] +type=NoncoherentXBar +clk_domain=system.clk_domain +eventq_index=0 +forward_latency=0 +frontend_latency=0 +response_latency=0 +use_default_range=false +width=32 +master=system.cpu2.pio +slave=system.cp_cntrl0.sequencer.mem_master_port system.cpu2.dma + +[system.rb_cntrl0] +type=RegionBuffer_Controller +children=cacheMemory notifyFromRegionDir probeFromRegionDir requestFromCore requestToNetwork responseFromCore responseToRegDir triggerQueue unblockFromDir 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+replacement_policy=system.rb_cntrl0.cacheMemory.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=1048576 +start_index_bit=10 +tagAccessLatency=1 +tagArrayBanks=64 + +[system.rb_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=4 +block_size=64 +eventq_index=0 +size=1048576 + +[system.rb_cntrl0.notifyFromRegionDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[4] + +[system.rb_cntrl0.probeFromRegionDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[5] + +[system.rb_cntrl0.requestFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[2] + +[system.rb_cntrl0.requestToNetwork] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[3] + +[system.rb_cntrl0.responseFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[3] + +[system.rb_cntrl0.responseToRegDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[4] + +[system.rb_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.rb_cntrl0.unblockFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[6] + +[system.reg_cntrl0] +type=RegionDir_Controller +children=cacheMemory notifyToRBuffer probeToRBuffer requestFromRegBuf requestToDir responseFromRBuffer triggerQueue +TCC_select_num_bits=0 +always_migrate=false +asym_migrate=false +blocksPerRegion=16 +buffer_size=0 +cacheMemory=system.reg_cntrl0.cacheMemory +clk_domain=system.clk_domain +cluster_id=0 +cpuRegionBufferNum=0 +eventq_index=0 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network phys_mem +access_backing_store=true +all_instructions=false +block_size_bytes=64 +clk_domain=system.ruby.clk_domain +eventq_index=0 +hot_lines=false +memory_size_bits=48 +num_of_sequencers=5 +number_of_virtual_networks=10 +phys_mem=system.ruby.phys_mem +randomization=false + +[system.ruby.clk_domain] +type=SrcClockDomain +clock=500 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.ruby.network] +type=SimpleNetwork +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_link_buffers00 int_link_buffers01 int_link_buffers02 int_link_buffers03 int_link_buffers04 int_link_buffers05 int_link_buffers06 int_link_buffers07 int_link_buffers08 int_link_buffers09 int_link_buffers10 int_link_buffers11 int_link_buffers12 int_link_buffers13 int_link_buffers14 int_link_buffers15 int_link_buffers16 int_link_buffers17 int_link_buffers18 int_link_buffers19 int_link_buffers20 int_link_buffers21 int_link_buffers22 int_link_buffers23 int_link_buffers24 int_link_buffers25 int_link_buffers26 int_link_buffers27 int_link_buffers28 int_link_buffers29 int_link_buffers30 int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links0 system.ruby.network.ext_links1 system.ruby.network.ext_links2 system.ruby.network.ext_links3 system.ruby.network.ext_links4 system.ruby.network.ext_links5 system.ruby.network.ext_links6 system.ruby.network.ext_links7 system.ruby.network.ext_links8 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 system.ruby.network.int_link_buffers05 system.ruby.network.int_link_buffers06 system.ruby.network.int_link_buffers07 system.ruby.network.int_link_buffers08 system.ruby.network.int_link_buffers09 system.ruby.network.int_link_buffers10 system.ruby.network.int_link_buffers11 system.ruby.network.int_link_buffers12 system.ruby.network.int_link_buffers13 system.ruby.network.int_link_buffers14 system.ruby.network.int_link_buffers15 system.ruby.network.int_link_buffers16 system.ruby.network.int_link_buffers17 system.ruby.network.int_link_buffers18 system.ruby.network.int_link_buffers19 system.ruby.network.int_link_buffers20 system.ruby.network.int_link_buffers21 system.ruby.network.int_link_buffers22 system.ruby.network.int_link_buffers23 system.ruby.network.int_link_buffers24 system.ruby.network.int_link_buffers25 system.ruby.network.int_link_buffers26 system.ruby.network.int_link_buffers27 system.ruby.network.int_link_buffers28 system.ruby.network.int_link_buffers29 system.ruby.network.int_link_buffers30 system.ruby.network.int_link_buffers31 system.ruby.network.int_link_buffers32 system.ruby.network.int_link_buffers33 system.ruby.network.int_link_buffers34 system.ruby.network.int_link_buffers35 system.ruby.network.int_link_buffers36 system.ruby.network.int_link_buffers37 system.ruby.network.int_link_buffers38 system.ruby.network.int_link_buffers39 +int_links=system.ruby.network.int_links0 system.ruby.network.int_links1 +netifs= +number_of_virtual_networks=10 +routers=system.ruby.network.ext_links0.int_node system.ruby.network.ext_links2.int_node system.ruby.network.ext_links4.int_node +ruby_system=system.ruby +topology=Crossbar +master=system.cp_cntrl0.probeToCore.slave system.cp_cntrl0.responseToCore.slave system.rb_cntrl0.requestFromCore.slave system.rb_cntrl0.responseFromCore.slave system.rb_cntrl0.notifyFromRegionDir.slave system.rb_cntrl0.probeFromRegionDir.slave system.rb_cntrl0.unblockFromDir.slave system.tcp_cntrl0.probeToTCP.slave system.tcp_cntrl0.responseToTCP.slave system.tcp_cntrl1.probeToTCP.slave system.tcp_cntrl1.responseToTCP.slave system.sqc_cntrl0.probeToSQC.slave system.sqc_cntrl0.responseToSQC.slave system.tcc_cntrl0.requestFromTCP.slave system.tcc_cntrl0.probeFromNB.slave system.tcc_cntrl0.responseFromNB.slave system.tcc_rb_cntrl0.requestFromCore.slave system.tcc_rb_cntrl0.responseFromCore.slave system.tcc_rb_cntrl0.notifyFromRegionDir.slave system.tcc_rb_cntrl0.probeFromRegionDir.slave system.tcc_rb_cntrl0.unblockFromDir.slave system.dir_cntrl0.requestFromCores.slave system.dir_cntrl0.responseFromCores.slave system.dir_cntrl0.unblockFromCores.slave system.dir_cntrl0.reqFromRegBuf.slave system.dir_cntrl0.reqFromRegDir.slave system.reg_cntrl0.responseFromRBuffer.slave system.reg_cntrl0.requestFromRegBuf.slave +slave=system.cp_cntrl0.requestFromCore.master system.cp_cntrl0.responseFromCore.master system.cp_cntrl0.unblockFromCore.master system.rb_cntrl0.requestToNetwork.master system.rb_cntrl0.responseToRegDir.master system.tcp_cntrl0.requestFromTCP.master system.tcp_cntrl0.responseFromTCP.master system.tcp_cntrl0.unblockFromCore.master system.tcp_cntrl1.requestFromTCP.master system.tcp_cntrl1.responseFromTCP.master system.tcp_cntrl1.unblockFromCore.master system.sqc_cntrl0.requestFromSQC.master system.tcc_cntrl0.responseToCore.master system.tcc_cntrl0.requestToNB.master system.tcc_cntrl0.responseToNB.master system.tcc_cntrl0.unblockToNB.master system.tcc_rb_cntrl0.requestToNetwork.master system.tcc_rb_cntrl0.responseToRegDir.master system.dir_cntrl0.probeToCore.master system.dir_cntrl0.responseToCore.master system.dir_cntrl0.reqToRegDir.master system.dir_cntrl0.unblockToRegDir.master system.reg_cntrl0.requestToDir.master system.reg_cntrl0.notifyToRBuffer.master system.reg_cntrl0.probeToRBuffer.master + +[system.ruby.network.ext_links0] +type=SimpleExtLink +children=int_node +bandwidth_factor=32 +eventq_index=0 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+[system.ruby.network.int_link_buffers32] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers33] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers34] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers35] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers36] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers37] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers38] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_link_buffers39] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.ruby.network.int_links0] +type=SimpleIntLink +bandwidth_factor=32 +eventq_index=0 +latency=1 +link_id=0 +node_a=system.ruby.network.ext_links0.int_node +node_b=system.ruby.network.ext_links2.int_node +weight=1 + +[system.ruby.network.int_links1] +type=SimpleIntLink +bandwidth_factor=32 +eventq_index=0 +latency=1 +link_id=1 +node_a=system.ruby.network.ext_links0.int_node +node_b=system.ruby.network.ext_links4.int_node +weight=1 + +[system.ruby.phys_mem] +type=SimpleMemory +bandwidth=73.000000 +clk_domain=system.ruby.clk_domain +conf_table_reported=true +eventq_index=0 +in_addr_map=false +latency=30000 +latency_var=0 +null=false +range=0:536870911 + +[system.sqc_cntrl0] +type=SQC_Controller +children=L1cache mandatoryQueue probeToSQC requestFromSQC responseToSQC sequencer +L1cache=system.sqc_cntrl0.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +issue_latency=80 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+[system.sqc_cntrl0.probeToSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[11] + +[system.sqc_cntrl0.requestFromSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[11] + +[system.sqc_cntrl0.responseToSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[12] + +[system.sqc_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.sqc_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.sqc_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=false +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=6 +slave=system.cpu1.CUs0.sqc_port system.cpu1.CUs1.sqc_port + +[system.sqc_coalescer] +type=TLBCoalescer +children=clk_domain +clk_domain=system.sqc_coalescer.clk_domain +coalescingWindow=1 +disableCoalescing=false +eventq_index=0 +probesPerCycle=2 +master=system.sqc_tlb.slave[0] +slave=system.cpu1.CUs0.sqc_tlb_port system.cpu1.CUs1.sqc_tlb_port + +[system.sqc_coalescer.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.sqc_coalescer.clk_domain.voltage_domain + +[system.sqc_coalescer.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.sqc_tlb] +type=X86GPUTLB +children=clk_domain +accessDistance=false +allocationPolicy=true +assoc=32 +clk_domain=system.sqc_tlb.clk_domain +eventq_index=0 +hitLatency=1 +maxOutstandingReqs=64 +missLatency1=5 +missLatency2=750 +size=32 +master=system.l2_coalescer.slave[0] +slave=system.sqc_coalescer.master[0] + +[system.sqc_tlb.clk_domain] +type=SrcClockDomain +children=voltage_domain +clock=1000 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.sqc_tlb.clk_domain.voltage_domain + +[system.sqc_tlb.clk_domain.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.tcc_cntrl0] +type=TCC_Controller +children=L2cache probeFromNB requestFromTCP requestToNB responseFromNB responseToCore responseToNB triggerQueue unblockToNB +L2cache=system.tcc_cntrl0.L2cache +WB=false +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +l2_request_latency=1 +l2_response_latency=16 +number_of_TBEs=5120 +probeFromNB=system.tcc_cntrl0.probeFromNB +recycle_latency=10 +regionBufferNum=1 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+randomization=false +slave=system.ruby.network.master[14] + +[system.tcc_cntrl0.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[13] + +[system.tcc_cntrl0.requestToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[13] + +[system.tcc_cntrl0.responseFromNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[15] + +[system.tcc_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[12] + +[system.tcc_cntrl0.responseToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[14] + +[system.tcc_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.tcc_cntrl0.unblockToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[15] + +[system.tcc_rb_cntrl0] +type=RegionBuffer_Controller +children=cacheMemory notifyFromRegionDir probeFromRegionDir requestFromCore requestToNetwork responseFromCore responseToRegDir triggerQueue unblockFromDir +TCC_select_num_bits=0 +blocksPerRegion=16 +buffer_size=0 +cacheMemory=system.tcc_rb_cntrl0.cacheMemory +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +isOnCPU=false +nextEvictLatency=1 +noTCCdir=true +notifyFromRegionDir=system.tcc_rb_cntrl0.notifyFromRegionDir +number_of_TBEs=5120 +probeFromRegionDir=system.tcc_rb_cntrl0.probeFromRegionDir +recycle_latency=10 +requestFromCore=system.tcc_rb_cntrl0.requestFromCore +requestToNetwork=system.tcc_rb_cntrl0.requestToNetwork +responseFromCore=system.tcc_rb_cntrl0.responseFromCore +responseToRegDir=system.tcc_rb_cntrl0.responseToRegDir +ruby_system=system.ruby +system=system +toDirLatency=60 +toRegionDirLatency=120 +transitions_per_cycle=32 +triggerQueue=system.tcc_rb_cntrl0.triggerQueue +unblockFromDir=system.tcc_rb_cntrl0.unblockFromDir +version=1 + +[system.tcc_rb_cntrl0.cacheMemory] +type=RubyCache +children=replacement_policy +assoc=4 +block_size=1024 +dataAccessLatency=1 +dataArrayBanks=64 +eventq_index=0 +is_icache=false +replacement_policy=system.tcc_rb_cntrl0.cacheMemory.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=1048576 +start_index_bit=10 +tagAccessLatency=1 +tagArrayBanks=64 + +[system.tcc_rb_cntrl0.cacheMemory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=4 +block_size=64 +eventq_index=0 +size=1048576 + +[system.tcc_rb_cntrl0.notifyFromRegionDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[18] + +[system.tcc_rb_cntrl0.probeFromRegionDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[19] + +[system.tcc_rb_cntrl0.requestFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[16] + +[system.tcc_rb_cntrl0.requestToNetwork] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[16] + +[system.tcc_rb_cntrl0.responseFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[17] + +[system.tcc_rb_cntrl0.responseToRegDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[17] + +[system.tcc_rb_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.tcc_rb_cntrl0.unblockFromDir] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[20] + +[system.tcp_cntrl0] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl0.L1cache +TCC_select_num_bits=0 +WB=false +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl0.coalescer +disableL1=false +eventq_index=0 +issue_latency=1 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl0.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl0.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl0.requestFromTCP +responseFromTCP=system.tcp_cntrl0.responseFromTCP +responseToTCP=system.tcp_cntrl0.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl0.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl0.unblockFromCore +use_seq_not_coal=false +version=0 + +[system.tcp_cntrl0.L1cache] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl0.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=16 + +[system.tcp_cntrl0.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl0.coalescer] +type=VIPERCoalescer +assume_rfo=false +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_inv_per_cycle=32 +max_outstanding_requests=2560 +max_wb_per_cycle=32 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=false +version=2 +slave=system.cpu1.CUs0.memory_port[0] system.cpu1.CUs0.memory_port[1] system.cpu1.CUs0.memory_port[2] system.cpu1.CUs0.memory_port[3] system.cpu1.CUs0.memory_port[4] system.cpu1.CUs0.memory_port[5] system.cpu1.CUs0.memory_port[6] system.cpu1.CUs0.memory_port[7] system.cpu1.CUs0.memory_port[8] system.cpu1.CUs0.memory_port[9] system.cpu1.CUs0.memory_port[10] system.cpu1.CUs0.memory_port[11] system.cpu1.CUs0.memory_port[12] system.cpu1.CUs0.memory_port[13] system.cpu1.CUs0.memory_port[14] system.cpu1.CUs0.memory_port[15] system.cpu1.CUs0.memory_port[16] system.cpu1.CUs0.memory_port[17] system.cpu1.CUs0.memory_port[18] system.cpu1.CUs0.memory_port[19] system.cpu1.CUs0.memory_port[20] system.cpu1.CUs0.memory_port[21] system.cpu1.CUs0.memory_port[22] system.cpu1.CUs0.memory_port[23] system.cpu1.CUs0.memory_port[24] system.cpu1.CUs0.memory_port[25] system.cpu1.CUs0.memory_port[26] system.cpu1.CUs0.memory_port[27] system.cpu1.CUs0.memory_port[28] system.cpu1.CUs0.memory_port[29] system.cpu1.CUs0.memory_port[30] system.cpu1.CUs0.memory_port[31] system.cpu1.CUs0.memory_port[32] system.cpu1.CUs0.memory_port[33] system.cpu1.CUs0.memory_port[34] system.cpu1.CUs0.memory_port[35] system.cpu1.CUs0.memory_port[36] system.cpu1.CUs0.memory_port[37] system.cpu1.CUs0.memory_port[38] system.cpu1.CUs0.memory_port[39] system.cpu1.CUs0.memory_port[40] system.cpu1.CUs0.memory_port[41] system.cpu1.CUs0.memory_port[42] system.cpu1.CUs0.memory_port[43] system.cpu1.CUs0.memory_port[44] system.cpu1.CUs0.memory_port[45] system.cpu1.CUs0.memory_port[46] system.cpu1.CUs0.memory_port[47] system.cpu1.CUs0.memory_port[48] system.cpu1.CUs0.memory_port[49] system.cpu1.CUs0.memory_port[50] system.cpu1.CUs0.memory_port[51] system.cpu1.CUs0.memory_port[52] system.cpu1.CUs0.memory_port[53] system.cpu1.CUs0.memory_port[54] system.cpu1.CUs0.memory_port[55] system.cpu1.CUs0.memory_port[56] system.cpu1.CUs0.memory_port[57] system.cpu1.CUs0.memory_port[58] system.cpu1.CUs0.memory_port[59] system.cpu1.CUs0.memory_port[60] system.cpu1.CUs0.memory_port[61] system.cpu1.CUs0.memory_port[62] system.cpu1.CUs0.memory_port[63] + +[system.tcp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl0.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[7] + +[system.tcp_cntrl0.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[5] + +[system.tcp_cntrl0.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[6] + +[system.tcp_cntrl0.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[8] + +[system.tcp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=3 + +[system.tcp_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[7] + +[system.tcp_cntrl1] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl1.L1cache +TCC_select_num_bits=0 +WB=false +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl1.coalescer +disableL1=false +eventq_index=0 +issue_latency=1 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl1.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl1.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl1.requestFromTCP +responseFromTCP=system.tcp_cntrl1.responseFromTCP +responseToTCP=system.tcp_cntrl1.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl1.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl1.unblockFromCore +use_seq_not_coal=false +version=1 + +[system.tcp_cntrl1.L1cache] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl1.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=16 + +[system.tcp_cntrl1.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl1.coalescer] +type=VIPERCoalescer +assume_rfo=false +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_inv_per_cycle=32 +max_outstanding_requests=2560 +max_wb_per_cycle=32 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=false +version=4 +slave=system.cpu1.CUs1.memory_port[0] system.cpu1.CUs1.memory_port[1] system.cpu1.CUs1.memory_port[2] system.cpu1.CUs1.memory_port[3] system.cpu1.CUs1.memory_port[4] system.cpu1.CUs1.memory_port[5] system.cpu1.CUs1.memory_port[6] system.cpu1.CUs1.memory_port[7] system.cpu1.CUs1.memory_port[8] system.cpu1.CUs1.memory_port[9] system.cpu1.CUs1.memory_port[10] system.cpu1.CUs1.memory_port[11] system.cpu1.CUs1.memory_port[12] system.cpu1.CUs1.memory_port[13] system.cpu1.CUs1.memory_port[14] system.cpu1.CUs1.memory_port[15] system.cpu1.CUs1.memory_port[16] system.cpu1.CUs1.memory_port[17] system.cpu1.CUs1.memory_port[18] system.cpu1.CUs1.memory_port[19] system.cpu1.CUs1.memory_port[20] system.cpu1.CUs1.memory_port[21] system.cpu1.CUs1.memory_port[22] system.cpu1.CUs1.memory_port[23] system.cpu1.CUs1.memory_port[24] system.cpu1.CUs1.memory_port[25] system.cpu1.CUs1.memory_port[26] system.cpu1.CUs1.memory_port[27] system.cpu1.CUs1.memory_port[28] system.cpu1.CUs1.memory_port[29] system.cpu1.CUs1.memory_port[30] system.cpu1.CUs1.memory_port[31] system.cpu1.CUs1.memory_port[32] system.cpu1.CUs1.memory_port[33] system.cpu1.CUs1.memory_port[34] system.cpu1.CUs1.memory_port[35] system.cpu1.CUs1.memory_port[36] system.cpu1.CUs1.memory_port[37] system.cpu1.CUs1.memory_port[38] system.cpu1.CUs1.memory_port[39] system.cpu1.CUs1.memory_port[40] system.cpu1.CUs1.memory_port[41] system.cpu1.CUs1.memory_port[42] system.cpu1.CUs1.memory_port[43] system.cpu1.CUs1.memory_port[44] system.cpu1.CUs1.memory_port[45] system.cpu1.CUs1.memory_port[46] system.cpu1.CUs1.memory_port[47] system.cpu1.CUs1.memory_port[48] system.cpu1.CUs1.memory_port[49] system.cpu1.CUs1.memory_port[50] system.cpu1.CUs1.memory_port[51] system.cpu1.CUs1.memory_port[52] system.cpu1.CUs1.memory_port[53] system.cpu1.CUs1.memory_port[54] system.cpu1.CUs1.memory_port[55] system.cpu1.CUs1.memory_port[56] system.cpu1.CUs1.memory_port[57] system.cpu1.CUs1.memory_port[58] system.cpu1.CUs1.memory_port[59] system.cpu1.CUs1.memory_port[60] system.cpu1.CUs1.memory_port[61] system.cpu1.CUs1.memory_port[62] system.cpu1.CUs1.memory_port[63] + +[system.tcp_cntrl1.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl1.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[9] + +[system.tcp_cntrl1.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[8] + +[system.tcp_cntrl1.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[9] + +[system.tcp_cntrl1.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[10] + +[system.tcp_cntrl1.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=5 + +[system.tcp_cntrl1.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[10] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simerr b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simerr new file mode 100755 index 000000000..1e2b8911e --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simerr @@ -0,0 +1,5 @@ +warn: system.ruby.network adopting orphan SimObject param 'int_links' +warn: system.ruby.network adopting orphan SimObject param 'ext_links' +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (512 Mbytes) +warn: Sockets disabled, not accepting gdb connections +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simout b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simout new file mode 100755 index 000000000..8e5806b46 --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/simout @@ -0,0 +1,21 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 19 2016 13:45:43 +gem5 started Jan 19 2016 13:46:17 +gem5 executing on zizzer, pid 51290 +command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Region -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/04.gpu/x86/linux/gpu-ruby-GPU_VIPER_Region + +Using GPU kernel code file(s) /dist/m5/regression/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm +Global frequency set at 1000000000000 ticks per second +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +Forcing maxCoalescedReqs to 32 (TLB assoc.) +info: Entering event queue @ 0. Starting simulation... +keys = 0x7b2bc0, &keys = 0x798998, keys[0] = 23 +the gpu says: +elloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloelloe +Exiting @ tick 468854500 because target called exit() diff --git a/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/stats.txt b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/stats.txt new file mode 100644 index 000000000..6fbd50886 --- /dev/null +++ b/tests/quick/se/04.gpu/ref/x86/linux/gpu-ruby-GPU_VIPER_Region/stats.txt @@ -0,0 +1,3418 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000469 # Number of seconds simulated +sim_ticks 468854500 # Number of ticks simulated +final_tick 468854500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 67943 # Simulator instruction rate (inst/s) +host_op_rate 139717 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 475693968 # Simulator tick rate (ticks/s) +host_mem_usage 1301796 # Number of bytes of host memory used +host_seconds 0.99 # Real time elapsed on the host +sim_insts 66963 # Number of instructions simulated +sim_ops 137705 # Number of ops (including micro ops) simulated +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1000 # Clock period in ticks +system.mem_ctrls.bytes_read::dir_cntrl0 100032 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 100032 # Number of bytes read from this memory +system.mem_ctrls.num_reads::dir_cntrl0 1563 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 1563 # Number of read requests responded to by this memory +system.mem_ctrls.bw_read::dir_cntrl0 213354036 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 213354036 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::dir_cntrl0 213354036 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 213354036 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 1563 # Number of read requests accepted +system.mem_ctrls.writeReqs 0 # Number of write requests accepted +system.mem_ctrls.readBursts 1563 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 100032 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 0 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 100032 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 0 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 122 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 192 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 93 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 44 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 61 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 79 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 52 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 42 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 54 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 56 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 183 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 90 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 225 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 125 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 51 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 94 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 468627000 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 1563 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 0 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 1548 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 4 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 2 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see 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req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::9 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::10 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::11 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::12 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::13 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::14 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::15 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::16 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::17 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::18 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::19 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::20 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::44 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::45 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::46 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::47 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::48 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::49 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::50 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::51 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::52 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::53 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::54 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::55 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 450 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 221.297778 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 151.217299 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 224.192300 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::0-127 165 36.67% 36.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::128-255 148 32.89% 69.56% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::256-383 55 12.22% 81.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::384-511 28 6.22% 88.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 19 4.22% 92.22% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::640-767 11 2.44% 94.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::768-895 8 1.78% 96.44% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 6 1.33% 97.78% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 10 2.22% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 450 # Bytes accessed per row activation +system.mem_ctrls.totQLat 14130749 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 43436999 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 7815000 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 9040.79 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5000.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 27790.79 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 213.35 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 213.35 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 1.67 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 1.67 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.01 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 0.00 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 1109 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 70.95 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate nan # Row buffer hit rate for writes +system.mem_ctrls.avgGap 299825.34 # Average gap between requests +system.mem_ctrls.pageHitRate 70.95 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 1300320 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 709500 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 5335200 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 30513600 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 265391145 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 47661750 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 350911515 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 750.717244 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 79008000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 15600000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 374147000 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 2101680 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 1146750 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 6801600 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 30513600 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 276170130 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 38206500 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 354940260 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 759.336079 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 61948750 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 15600000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 389900000 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.ruby.clk_domain.clock 500 # Clock period in ticks +system.ruby.phys_mem.bytes_read::cpu0.inst 696760 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu0.data 119832 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs0.ComputeUnit 3280 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::cpu1.CUs1.ComputeUnit 3280 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_read::total 823152 # Number of bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu0.inst 696760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs0.ComputeUnit 2000 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::cpu1.CUs1.ComputeUnit 2000 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_inst_read::total 700760 # Number of instructions bytes read from this memory +system.ruby.phys_mem.bytes_written::cpu0.data 72767 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::cpu1.CUs0.ComputeUnit 256 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::cpu1.CUs1.ComputeUnit 256 # Number of bytes written to this memory +system.ruby.phys_mem.bytes_written::total 73279 # Number of bytes written to this memory +system.ruby.phys_mem.num_reads::cpu0.inst 87095 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu0.data 16686 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs0.ComputeUnit 555 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::cpu1.CUs1.ComputeUnit 555 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_reads::total 104891 # Number of read requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu0.data 10422 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu1.CUs0.ComputeUnit 256 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::cpu1.CUs1.ComputeUnit 256 # Number of write requests responded to by this memory +system.ruby.phys_mem.num_writes::total 10934 # Number of write requests responded to by this memory +system.ruby.phys_mem.bw_read::cpu0.inst 1486090034 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu0.data 255584622 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs0.ComputeUnit 6995774 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::cpu1.CUs1.ComputeUnit 6995774 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_read::total 1755666203 # Total read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu0.inst 1486090034 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs0.ComputeUnit 4265716 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::cpu1.CUs1.ComputeUnit 4265716 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_inst_read::total 1494621466 # Instruction read bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu0.data 155201667 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs0.ComputeUnit 546012 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::cpu1.CUs1.ComputeUnit 546012 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_write::total 156293690 # Write bandwidth from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.inst 1486090034 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu0.data 410786289 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs0.ComputeUnit 7541785 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::cpu1.CUs1.ComputeUnit 7541785 # Total bandwidth to/from this memory (bytes/s) +system.ruby.phys_mem.bw_total::total 1911959894 # Total bandwidth to/from this memory (bytes/s) +system.ruby.outstanding_req_hist::bucket_size 1 +system.ruby.outstanding_req_hist::max_bucket 9 +system.ruby.outstanding_req_hist::samples 114203 +system.ruby.outstanding_req_hist::mean 1.000035 +system.ruby.outstanding_req_hist::gmean 1.000024 +system.ruby.outstanding_req_hist::stdev 0.005918 +system.ruby.outstanding_req_hist | 0 0.00% 0.00% | 114199 100.00% 100.00% | 4 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 114203 +system.ruby.latency_hist::bucket_size 64 +system.ruby.latency_hist::max_bucket 639 +system.ruby.latency_hist::samples 114203 +system.ruby.latency_hist::mean 3.070988 +system.ruby.latency_hist::gmean 1.072272 +system.ruby.latency_hist::stdev 18.192328 +system.ruby.latency_hist | 112654 98.64% 98.64% | 11 0.01% 98.65% | 1238 1.08% 99.74% | 266 0.23% 99.97% | 14 0.01% 99.98% | 12 0.01% 99.99% | 7 0.01% 100.00% | 1 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 114203 +system.ruby.hit_latency_hist::bucket_size 64 +system.ruby.hit_latency_hist::max_bucket 639 +system.ruby.hit_latency_hist::samples 1549 +system.ruby.hit_latency_hist::mean 152.827631 +system.ruby.hit_latency_hist::gmean 149.009432 +system.ruby.hit_latency_hist::stdev 40.628532 +system.ruby.hit_latency_hist | 0 0.00% 0.00% | 11 0.71% 0.71% | 1238 79.92% 80.63% | 266 17.17% 97.81% | 14 0.90% 98.71% | 12 0.77% 99.48% | 7 0.45% 99.94% | 1 0.06% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 1549 +system.ruby.miss_latency_hist::bucket_size 2 +system.ruby.miss_latency_hist::max_bucket 19 +system.ruby.miss_latency_hist::samples 112654 +system.ruby.miss_latency_hist::mean 1.011824 +system.ruby.miss_latency_hist::gmean 1.001936 +system.ruby.miss_latency_hist::stdev 0.461184 +system.ruby.miss_latency_hist | 112580 99.93% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 0 0.00% 99.93% | 74 0.07% 100.00% +system.ruby.miss_latency_hist::total 112654 +system.ruby.L1Cache.incomplete_times 112580 +system.ruby.L2Cache.incomplete_times 74 +system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1D0cache.demand_misses 1556 # Number of cache demand misses +system.cp_cntrl0.L1D0cache.demand_accesses 1556 # Number of cache demand accesses +system.cp_cntrl0.L1D0cache.num_data_array_reads 16142 # number of data array reads +system.cp_cntrl0.L1D0cache.num_data_array_writes 11998 # number of data array writes +system.cp_cntrl0.L1D0cache.num_tag_array_reads 27136 # number of tag array reads +system.cp_cntrl0.L1D0cache.num_tag_array_writes 1431 # number of tag array writes +system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1D1cache.demand_misses 0 # Number of cache demand misses +system.cp_cntrl0.L1D1cache.demand_accesses 0 # Number of cache demand accesses +system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1Icache.demand_misses 1287 # Number of cache demand misses +system.cp_cntrl0.L1Icache.demand_accesses 1287 # Number of cache demand accesses +system.cp_cntrl0.L1Icache.num_data_array_reads 85994 # number of data array reads +system.cp_cntrl0.L1Icache.num_data_array_writes 67 # number of data array writes +system.cp_cntrl0.L1Icache.num_tag_array_reads 87697 # number of tag array reads +system.cp_cntrl0.L1Icache.num_tag_array_writes 67 # number of tag array writes +system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L2cache.demand_misses 1549 # Number of cache demand misses +system.cp_cntrl0.L2cache.demand_accesses 1549 # Number of cache demand accesses +system.cp_cntrl0.L2cache.num_data_array_reads 167 # number of data array reads +system.cp_cntrl0.L2cache.num_data_array_writes 11993 # number of data array writes +system.cp_cntrl0.L2cache.num_tag_array_reads 12092 # number of tag array reads +system.cp_cntrl0.L2cache.num_tag_array_writes 1694 # number of tag array writes +system.cpu0.clk_domain.clock 500 # Clock period in ticks +system.cpu0.apic_clk_domain.clock 8000 # Clock period in ticks +system.cpu0.workload.num_syscalls 21 # Number of system calls +system.cpu0.numCycles 937709 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 66963 # Number of instructions committed +system.cpu0.committedOps 137705 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 136380 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 1279 # Number of float alu accesses +system.cpu0.num_func_calls 3196 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 12151 # number of instructions that are conditional controls +system.cpu0.num_int_insts 136380 # number of integer instructions +system.cpu0.num_fp_insts 1279 # number of float instructions +system.cpu0.num_int_register_reads 257490 # number of times the integer registers were read +system.cpu0.num_int_register_writes 110039 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 1981 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 981 # number of times the floating registers were written +system.cpu0.num_cc_register_reads 78262 # number of times the CC registers were read +system.cpu0.num_cc_register_writes 42183 # number of times the CC registers were written +system.cpu0.num_mem_refs 27198 # number of memory refs +system.cpu0.num_load_insts 16684 # Number of load instructions +system.cpu0.num_store_insts 10514 # Number of store instructions +system.cpu0.num_idle_cycles 7323.003984 # Number of idle cycles +system.cpu0.num_busy_cycles 930385.996016 # Number of busy cycles +system.cpu0.not_idle_fraction 0.992191 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.007809 # Percentage of idle cycles +system.cpu0.Branches 16199 # Number of branches fetched +system.cpu0.op_class::No_OpClass 615 0.45% 0.45% # Class of executed instruction +system.cpu0.op_class::IntAlu 108791 79.00% 79.45% # Class of executed instruction +system.cpu0.op_class::IntMult 13 0.01% 79.46% # Class of executed instruction +system.cpu0.op_class::IntDiv 138 0.10% 79.56% # Class of executed instruction +system.cpu0.op_class::FloatAdd 950 0.69% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatDiv 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::FloatSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAdd 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAddAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdAlu 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMisc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdMultAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdShift 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdShiftAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAdd 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatAlu 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCmp 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatCvt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatDiv 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMisc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMult 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::SimdFloatSqrt 0 0.00% 80.25% # Class of executed instruction +system.cpu0.op_class::MemRead 16684 12.12% 92.36% # Class of executed instruction +system.cpu0.op_class::MemWrite 10514 7.64% 100.00% # Class of executed instruction +system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction +system.cpu0.op_class::total 137705 # Class of executed instruction +system.cpu1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.cpu1.clk_domain.clock 1000 # Clock period in ticks +system.cpu1.CUs0.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts00.timesBlockedDueRAWDependencies 271 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands 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source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands 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number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands 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source register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands 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+system.cpu1.CUs0.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts08.timesBlockedDueRAWDependencies 252 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts16.timesBlockedDueRAWDependencies 243 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts24.timesBlockedDueRAWDependencies 228 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs0.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs0.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs0.ExecStage.num_cycles_with_no_issue 4103 # number of cycles the CU issues nothing +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_issued 133 # number of cycles the CU issued at least one instruction +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1359 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 382 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 338 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 302 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::GM 373 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.num_cycles_with_instr_type_no_issue::LM 26 # Number of cycles no instruction of specific type issued +system.cpu1.CUs0.ExecStage.spc::samples 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::mean 0.033286 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::stdev 0.190882 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::0 4103 96.86% 96.86% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::1 126 2.97% 99.83% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::2 6 0.14% 99.98% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::3 1 0.02% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.spc::total 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs0.ExecStage.num_transitions_active_to_idle 68 # number of CU transitions from active to idle +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::samples 68 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::mean 53.455882 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::stdev 203.558231 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::0-4 48 70.59% 70.59% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::5-9 8 11.76% 82.35% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::10-14 1 1.47% 83.82% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::15-19 1 1.47% 85.29% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::20-24 2 2.94% 88.24% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::25-29 1 1.47% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::75 0 0.00% 89.71% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::overflows 7 10.29% 100.00% # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::max_value 1317 # duration of idle periods in cycles +system.cpu1.CUs0.ExecStage.idle_duration_in_cycles::total 68 # duration of idle periods in cycles +system.cpu1.CUs0.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF +system.cpu1.CUs0.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs0.tlb_requests 769 # number of uncoalesced requests +system.cpu1.CUs0.tlb_cycles -318202403000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs0.avg_translation_latency -413787260.078023 # Avg. translation latency for data translations +system.cpu1.CUs0.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs0.lds_bank_access_cnt 54 # Total number of LDS bank accesses +system.cpu1.CUs0.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::mean 8 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::stdev 6.196773 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::10-11 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::12-13 4 66.67% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs0.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs0.global_mem_instr_cnt 17 # dynamic global memory instructions count +system.cpu1.CUs0.local_mem_instr_cnt 6 # dynamic local memory intruction count +system.cpu1.CUs0.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity +system.cpu1.CUs0.num_instr_executed 141 # number of instructions executed +system.cpu1.CUs0.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::mean 84.978723 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::stdev 240.114362 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::6-7 31 21.99% 68.79% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::8-9 3 2.13% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::max_value 1320 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs0.num_vec_ops_executed 6769 # number of vec ops executed (e.g. VSZ/inst) +system.cpu1.CUs0.num_total_cycles 4236 # number of cycles the CU ran for +system.cpu1.CUs0.vpc 1.597970 # Vector Operations per cycle (this CU only) +system.cpu1.CUs0.ipc 0.033286 # Instructions per cycle (this CU only) +system.cpu1.CUs0.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::mean 48.007092 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::stdev 23.719942 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::9-12 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::13-16 36 25.53% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs0.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::mean 37.833333 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::stdev 27.064737 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::9-12 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::13-16 8 44.44% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction +system.cpu1.CUs0.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::mean 19.500000 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::stdev 22.322634 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::9-12 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::13-16 4 66.67% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction +system.cpu1.CUs0.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction +system.cpu1.CUs0.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed +system.cpu1.CUs0.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD +system.cpu1.CUs0.num_CAS_ops 0 # number of compare and swap operations +system.cpu1.CUs0.num_failed_CAS_ops 0 # number of compare and swap operations that failed +system.cpu1.CUs0.num_completed_wfs 4 # number of completed wavefronts +system.cpu1.CUs1.wavefronts00.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts00.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts00.timesBlockedDueRAWDependencies 276 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::samples 39 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::mean 0.794872 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::stdev 0.863880 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::0-1 28 71.79% 71.79% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::2-3 11 28.21% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.src_reg_operand_dist::total 39 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::samples 39 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::mean 0.589744 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::stdev 0.498310 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::0-1 39 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts00.dst_reg_operand_dist::total 39 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts01.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts01.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts01.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts02.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts02.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts02.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts03.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts03.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts03.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts04.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts04.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts04.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts05.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts05.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts05.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts06.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts06.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts06.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts07.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts07.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts07.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts08.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts08.timesBlockedDueRAWDependencies 254 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts08.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts09.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts09.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts09.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts10.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts10.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts10.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts11.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts11.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts11.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts12.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts12.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts12.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts13.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts13.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts13.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts14.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts14.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts14.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts15.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts15.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts15.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts16.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts16.timesBlockedDueRAWDependencies 251 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts16.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts17.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts17.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts17.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts18.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts18.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts18.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts19.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts19.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts19.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts20.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts20.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts20.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts21.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts21.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts21.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts22.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts22.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts22.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts23.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts23.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts23.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts24.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts24.timesBlockedDueRAWDependencies 236 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::samples 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::mean 0.852941 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::stdev 0.857493 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::0-1 24 70.59% 70.59% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::2-3 10 29.41% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::4 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::max_value 2 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.src_reg_operand_dist::total 34 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::samples 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::mean 0.617647 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::stdev 0.493270 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::underflows 0 0.00% 0.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::0-1 34 100.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::2-3 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::overflows 0 0.00% 100.00% # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::max_value 1 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts24.dst_reg_operand_dist::total 34 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts25.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts25.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts25.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts26.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts26.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts26.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts27.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts27.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts27.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts28.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts28.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts28.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts29.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts29.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts29.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts30.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts30.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts30.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.timesBlockedDueVrfPortAvail 0 # number of times instructions are blocked due to VRF port availability +system.cpu1.CUs1.wavefronts31.timesBlockedDueWAXDependencies 0 # number of times the wf's instructions are blocked due to WAW or WAR dependencies +system.cpu1.CUs1.wavefronts31.timesBlockedDueRAWDependencies 0 # number of times the wf's instructions are blocked due to RAW dependencies +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::samples 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::mean nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::stdev nan # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::underflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::0-1 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::2-3 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::4 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::overflows 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::min_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::max_value 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.src_reg_operand_dist::total 0 # number of executed instructions with N source register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::samples 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::mean nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::stdev nan # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::underflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::0-1 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::2-3 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::overflows 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::min_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::max_value 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.wavefronts31.dst_reg_operand_dist::total 0 # number of executed instructions with N destination register operands +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::samples 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::mean 5.813953 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::stdev 2.683777 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::underflows 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::1 0 0.00% 0.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::2 8 18.60% 18.60% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::3 8 18.60% 37.21% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::4 1 2.33% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::5 0 0.00% 39.53% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::6 1 2.33% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::7 0 0.00% 41.86% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::8 25 58.14% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::9 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::10 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::11 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::12 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::13 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::14 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::15 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::16 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::17 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::18 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::19 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::20 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::21 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::22 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::23 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::24 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::25 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::26 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::27 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::28 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::29 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::30 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::31 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::32 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::overflows 0 0.00% 100.00% # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::min_value 2 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::max_value 8 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.FetchStage.inst_fetch_instr_returned::total 43 # For each instruction fetch request recieved record how many instructions you got from it +system.cpu1.CUs1.ExecStage.num_cycles_with_no_issue 4105 # number of cycles the CU issues nothing +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_issued 131 # number of cycles the CU issued at least one instruction +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU0 30 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU1 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU2 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::ALU3 29 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::GM 18 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instrtype_issue::LM 6 # Number of cycles at least one instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU0 1525 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU1 346 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU2 363 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::ALU3 363 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::GM 363 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.num_cycles_with_instr_type_no_issue::LM 33 # Number of cycles no instruction of specific type issued +system.cpu1.CUs1.ExecStage.spc::samples 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::mean 0.033286 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::stdev 0.194558 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::underflows 0 0.00% 0.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::0 4105 96.91% 96.91% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::1 123 2.90% 99.81% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::2 6 0.14% 99.95% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::3 2 0.05% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::4 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::5 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::6 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::overflows 0 0.00% 100.00% # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::min_value 0 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::max_value 3 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.spc::total 4236 # Execution units active per cycle (Exec unit=SIMD,MemPipe) +system.cpu1.CUs1.ExecStage.num_transitions_active_to_idle 74 # number of CU transitions from active to idle +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::samples 74 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::mean 51.891892 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::stdev 210.095188 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::underflows 0 0.00% 0.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::0-4 56 75.68% 75.68% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::5-9 7 9.46% 85.14% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::10-14 0 0.00% 85.14% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::15-19 2 2.70% 87.84% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::20-24 1 1.35% 89.19% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::25-29 1 1.35% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::30-34 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::35-39 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::40-44 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::45-49 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::50-54 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::55-59 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::60-64 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::65-69 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::70-74 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::75 0 0.00% 90.54% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::overflows 7 9.46% 100.00% # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::min_value 1 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::max_value 1321 # duration of idle periods in cycles +system.cpu1.CUs1.ExecStage.idle_duration_in_cycles::total 74 # duration of idle periods in cycles +system.cpu1.CUs1.GlobalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles GM data are delayed before updating the VRF +system.cpu1.CUs1.LocalMemPipeline.load_vrf_bank_conflict_cycles 0 # total number of cycles LDS data are delayed before updating the VRF +system.cpu1.CUs1.tlb_requests 769 # number of uncoalesced requests +system.cpu1.CUs1.tlb_cycles -318199598000 # total number of cycles for all uncoalesced requests +system.cpu1.CUs1.avg_translation_latency -413783612.483745 # Avg. translation latency for data translations +system.cpu1.CUs1.TLB_hits_distribution::page_table 769 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L1_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L2_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.TLB_hits_distribution::L3_TLB 0 # TLB hits distribution (0 for page table, x for Lx-TLB +system.cpu1.CUs1.lds_bank_access_cnt 53 # Total number of LDS bank accesses +system.cpu1.CUs1.lds_bank_conflicts::samples 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::mean 7.833333 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::stdev 6.080022 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::underflows 0 0.00% 0.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::0-1 2 33.33% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::2-3 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::4-5 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::6-7 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::8-9 0 0.00% 33.33% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::10-11 1 16.67% 50.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::12-13 3 50.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::14-15 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::16-17 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::18-19 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::20-21 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::22-23 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::24-25 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::26-27 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::28-29 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::30-31 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::32-33 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::34-35 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::36-37 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::38-39 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::40-41 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::42-43 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::44-45 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::46-47 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::48-49 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::50-51 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::52-53 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::54-55 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::56-57 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::58-59 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::60-61 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::62-63 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::64 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::overflows 0 0.00% 100.00% # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::min_value 0 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::max_value 12 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.lds_bank_conflicts::total 6 # Number of bank conflicts per LDS memory packet +system.cpu1.CUs1.page_divergence_dist::samples 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::mean 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::stdev 0 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::underflows 0 0.00% 0.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::1-4 17 100.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::5-8 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::9-12 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::13-16 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::17-20 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::21-24 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::25-28 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::29-32 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::33-36 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::37-40 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::41-44 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::45-48 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::49-52 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::53-56 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::57-60 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::61-64 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::overflows 0 0.00% 100.00% # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::min_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::max_value 1 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.page_divergence_dist::total 17 # pages touched per wf (over all mem. instr.) +system.cpu1.CUs1.global_mem_instr_cnt 17 # dynamic global memory instructions count +system.cpu1.CUs1.local_mem_instr_cnt 6 # dynamic local memory intruction count +system.cpu1.CUs1.wg_blocked_due_lds_alloc 0 # Workgroup blocked due to LDS capacity +system.cpu1.CUs1.num_instr_executed 141 # number of instructions executed +system.cpu1.CUs1.inst_exec_rate::samples 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::mean 86.326241 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::stdev 246.713874 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::underflows 0 0.00% 0.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::0-1 1 0.71% 0.71% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::2-3 12 8.51% 9.22% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::4-5 53 37.59% 46.81% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::6-7 29 20.57% 67.38% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::8-9 5 3.55% 70.92% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::10 1 0.71% 71.63% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::overflows 40 28.37% 100.00% # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::min_value 1 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::max_value 1324 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.inst_exec_rate::total 141 # Instruction Execution Rate: Number of executed vector instructions per cycle +system.cpu1.CUs1.num_vec_ops_executed 6762 # number of vec ops executed (e.g. VSZ/inst) +system.cpu1.CUs1.num_total_cycles 4236 # number of cycles the CU ran for +system.cpu1.CUs1.vpc 1.596317 # Vector Operations per cycle (this CU only) +system.cpu1.CUs1.ipc 0.033286 # Instructions per cycle (this CU only) +system.cpu1.CUs1.warp_execution_dist::samples 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::mean 47.957447 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::stdev 23.818022 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::underflows 0 0.00% 0.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::1-4 5 3.55% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::5-8 0 0.00% 3.55% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::9-12 9 6.38% 9.93% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::13-16 27 19.15% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::17-20 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::21-24 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::25-28 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::29-32 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::33-36 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::37-40 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::41-44 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::45-48 0 0.00% 29.08% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::49-52 8 5.67% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::53-56 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::57-60 0 0.00% 34.75% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::61-64 92 65.25% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::overflows 0 0.00% 100.00% # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::min_value 1 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::max_value 64 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.warp_execution_dist::total 141 # number of lanes active per instruction (oval all instructions) +system.cpu1.CUs1.gmem_lanes_execution_dist::samples 18 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::mean 37.722222 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::stdev 27.174394 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::1-4 1 5.56% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::5-8 0 0.00% 5.56% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::9-12 2 11.11% 16.67% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::13-16 6 33.33% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::17-20 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::21-24 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::25-28 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::29-32 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::33-36 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::37-40 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::41-44 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::45-48 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::49-52 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::53-56 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::57-60 0 0.00% 50.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::61-64 9 50.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::min_value 1 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::max_value 64 # number of active lanes per global memory instruction +system.cpu1.CUs1.gmem_lanes_execution_dist::total 18 # number of active lanes per global memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::samples 6 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::mean 19.333333 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::stdev 22.384518 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::underflows 0 0.00% 0.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::1-4 1 16.67% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::5-8 0 0.00% 16.67% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::9-12 1 16.67% 33.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::13-16 3 50.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::17-20 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::21-24 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::25-28 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::29-32 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::33-36 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::37-40 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::41-44 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::45-48 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::49-52 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::53-56 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::57-60 0 0.00% 83.33% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::61-64 1 16.67% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::overflows 0 0.00% 100.00% # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::min_value 1 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::max_value 64 # number of active lanes per local memory instruction +system.cpu1.CUs1.lmem_lanes_execution_dist::total 6 # number of active lanes per local memory instruction +system.cpu1.CUs1.num_alu_insts_executed 118 # Number of dynamic non-GM memory insts executed +system.cpu1.CUs1.times_wg_blocked_due_vgpr_alloc 0 # Number of times WGs are blocked due to VGPR allocation per SIMD +system.cpu1.CUs1.num_CAS_ops 0 # number of compare and swap operations +system.cpu1.CUs1.num_failed_CAS_ops 0 # number of compare and swap operations that failed +system.cpu1.CUs1.num_completed_wfs 4 # number of completed wavefronts +system.cpu2.num_kernel_launched 1 # number of kernel launched +system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits +system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses +system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses +system.dir_cntrl0.L3CacheMemory.num_data_array_writes 1600 # number of data array writes +system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 1602 # number of tag array reads +system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 1572 # number of tag array writes +system.dispatcher_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.dispatcher_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_coalescer.uncoalesced_accesses 0 # Number of uncoalesced TLB accesses +system.dispatcher_coalescer.coalesced_accesses 0 # Number of coalesced TLB accesses +system.dispatcher_coalescer.queuing_cycles 0 # Number of cycles spent in queue +system.dispatcher_coalescer.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.dispatcher_coalescer.local_latency nan # Avg. latency over all incoming pkts +system.dispatcher_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.dispatcher_tlb.clk_domain.clock 1000 # Clock period in ticks +system.dispatcher_tlb.local_TLB_accesses 0 # Number of TLB accesses +system.dispatcher_tlb.local_TLB_hits 0 # Number of TLB hits +system.dispatcher_tlb.local_TLB_misses 0 # Number of TLB misses +system.dispatcher_tlb.local_TLB_miss_rate nan # TLB miss rate +system.dispatcher_tlb.global_TLB_accesses 0 # Number of TLB accesses +system.dispatcher_tlb.global_TLB_hits 0 # Number of TLB hits +system.dispatcher_tlb.global_TLB_misses 0 # Number of TLB misses +system.dispatcher_tlb.global_TLB_miss_rate nan # TLB miss rate +system.dispatcher_tlb.access_cycles 0 # Cycles spent accessing this TLB level +system.dispatcher_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.dispatcher_tlb.unique_pages 0 # Number of unique pages touched +system.dispatcher_tlb.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.dispatcher_tlb.local_latency nan # Avg. latency over incoming coalesced reqs +system.dispatcher_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l1_coalescer0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_coalescer0.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer0.uncoalesced_accesses 778 # Number of uncoalesced TLB accesses +system.l1_coalescer0.coalesced_accesses 0 # Number of coalesced TLB accesses +system.l1_coalescer0.queuing_cycles 0 # Number of cycles spent in queue +system.l1_coalescer0.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_coalescer0.local_latency 0 # Avg. latency over all incoming pkts +system.l1_coalescer1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_coalescer1.clk_domain.clock 1000 # Clock period in ticks +system.l1_coalescer1.uncoalesced_accesses 769 # Number of uncoalesced TLB accesses +system.l1_coalescer1.coalesced_accesses 0 # Number of coalesced TLB accesses +system.l1_coalescer1.queuing_cycles 0 # Number of cycles spent in queue +system.l1_coalescer1.local_queuing_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_coalescer1.local_latency 0 # Avg. latency over all incoming pkts +system.l1_tlb0.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_tlb0.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb0.local_TLB_accesses 778 # Number of TLB accesses +system.l1_tlb0.local_TLB_hits 774 # Number of TLB hits +system.l1_tlb0.local_TLB_misses 4 # Number of TLB misses +system.l1_tlb0.local_TLB_miss_rate 0.514139 # TLB miss rate +system.l1_tlb0.global_TLB_accesses 778 # Number of TLB accesses +system.l1_tlb0.global_TLB_hits 774 # Number of TLB hits +system.l1_tlb0.global_TLB_misses 4 # Number of TLB misses +system.l1_tlb0.global_TLB_miss_rate 0.514139 # TLB miss rate +system.l1_tlb0.access_cycles 0 # Cycles spent accessing this TLB level +system.l1_tlb0.page_table_cycles 0 # Cycles spent accessing the page table +system.l1_tlb0.unique_pages 4 # Number of unique pages touched +system.l1_tlb0.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_tlb0.local_latency 0 # Avg. latency over incoming coalesced reqs +system.l1_tlb0.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l1_tlb1.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l1_tlb1.clk_domain.clock 1000 # Clock period in ticks +system.l1_tlb1.local_TLB_accesses 769 # Number of TLB accesses +system.l1_tlb1.local_TLB_hits 766 # Number of TLB hits +system.l1_tlb1.local_TLB_misses 3 # Number of TLB misses +system.l1_tlb1.local_TLB_miss_rate 0.390117 # TLB miss rate +system.l1_tlb1.global_TLB_accesses 769 # Number of TLB accesses +system.l1_tlb1.global_TLB_hits 766 # Number of TLB hits +system.l1_tlb1.global_TLB_misses 3 # Number of TLB misses +system.l1_tlb1.global_TLB_miss_rate 0.390117 # TLB miss rate +system.l1_tlb1.access_cycles 0 # Cycles spent accessing this TLB level +system.l1_tlb1.page_table_cycles 0 # Cycles spent accessing the page table +system.l1_tlb1.unique_pages 3 # Number of unique pages touched +system.l1_tlb1.local_cycles 0 # Number of cycles spent in queue for all incoming reqs +system.l1_tlb1.local_latency 0 # Avg. latency over incoming coalesced reqs +system.l1_tlb1.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l2_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l2_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l2_coalescer.uncoalesced_accesses 8 # Number of uncoalesced TLB accesses +system.l2_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses +system.l2_coalescer.queuing_cycles 8000 # Number of cycles spent in queue +system.l2_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs +system.l2_coalescer.local_latency 125 # Avg. latency over all incoming pkts +system.l2_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l2_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l2_tlb.local_TLB_accesses 8 # Number of TLB accesses +system.l2_tlb.local_TLB_hits 3 # Number of TLB hits +system.l2_tlb.local_TLB_misses 5 # Number of TLB misses +system.l2_tlb.local_TLB_miss_rate 62.500000 # TLB miss rate +system.l2_tlb.global_TLB_accesses 15 # Number of TLB accesses +system.l2_tlb.global_TLB_hits 3 # Number of TLB hits +system.l2_tlb.global_TLB_misses 12 # Number of TLB misses +system.l2_tlb.global_TLB_miss_rate 80 # TLB miss rate +system.l2_tlb.access_cycles 552008 # Cycles spent accessing this TLB level +system.l2_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.l2_tlb.unique_pages 5 # Number of unique pages touched +system.l2_tlb.local_cycles 69001 # Number of cycles spent in queue for all incoming reqs +system.l2_tlb.local_latency 8625.125000 # Avg. latency over incoming coalesced reqs +system.l2_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.l3_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l3_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.l3_coalescer.uncoalesced_accesses 5 # Number of uncoalesced TLB accesses +system.l3_coalescer.coalesced_accesses 1 # Number of coalesced TLB accesses +system.l3_coalescer.queuing_cycles 8000 # Number of cycles spent in queue +system.l3_coalescer.local_queuing_cycles 1000 # Number of cycles spent in queue for all incoming reqs +system.l3_coalescer.local_latency 200 # Avg. latency over all incoming pkts +system.l3_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.l3_tlb.clk_domain.clock 1000 # Clock period in ticks +system.l3_tlb.local_TLB_accesses 5 # Number of TLB accesses +system.l3_tlb.local_TLB_hits 0 # Number of TLB hits +system.l3_tlb.local_TLB_misses 5 # Number of TLB misses +system.l3_tlb.local_TLB_miss_rate 100 # TLB miss rate +system.l3_tlb.global_TLB_accesses 12 # Number of TLB accesses +system.l3_tlb.global_TLB_hits 0 # Number of TLB hits +system.l3_tlb.global_TLB_misses 12 # Number of TLB misses +system.l3_tlb.global_TLB_miss_rate 100 # TLB miss rate +system.l3_tlb.access_cycles 1200000 # Cycles spent accessing this TLB level +system.l3_tlb.page_table_cycles 6000000 # Cycles spent accessing the page table +system.l3_tlb.unique_pages 5 # Number of unique pages touched +system.l3_tlb.local_cycles 150000 # Number of cycles spent in queue for all incoming reqs +system.l3_tlb.local_latency 30000 # Avg. latency over incoming coalesced reqs +system.l3_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.piobus.trans_dist::WriteReq 94 # Transaction distribution +system.piobus.trans_dist::WriteResp 94 # Transaction distribution +system.piobus.pkt_count_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 188 # Packet count per connected master and slave (bytes) +system.piobus.pkt_count::total 188 # Packet count per connected master and slave (bytes) +system.piobus.pkt_size_system.cp_cntrl0.sequencer.mem-master-port::system.cpu2.pio 748 # Cumulative packet size per connected master and slave (bytes) +system.piobus.pkt_size::total 748 # Cumulative packet size per connected master and slave (bytes) +system.piobus.reqLayer0.occupancy 188000 # Layer occupancy (ticks) +system.piobus.reqLayer0.utilization 0.0 # Layer utilization (%) +system.piobus.respLayer0.occupancy 94000 # Layer occupancy (ticks) +system.piobus.respLayer0.utilization 0.0 # Layer utilization (%) +system.rb_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits +system.rb_cntrl0.cacheMemory.demand_misses 0 # Number of cache demand misses +system.rb_cntrl0.cacheMemory.demand_accesses 0 # Number of cache demand accesses +system.rb_cntrl0.cacheMemory.num_tag_array_reads 1553 # number of tag array reads +system.rb_cntrl0.cacheMemory.num_tag_array_writes 3123 # number of tag array writes +system.reg_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits +system.reg_cntrl0.cacheMemory.demand_misses 0 # Number of cache demand misses +system.reg_cntrl0.cacheMemory.demand_accesses 0 # Number of cache demand accesses +system.reg_cntrl0.cacheMemory.num_tag_array_reads 279 # number of tag array reads +system.reg_cntrl0.cacheMemory.num_tag_array_writes 279 # number of tag array writes +system.ruby.network.ext_links0.int_node.percent_links_utilized 0.122493 +system.ruby.network.ext_links0.int_node.msg_count.Data::0 16 +system.ruby.network.ext_links0.int_node.msg_count.Request_Control::0 1558 +system.ruby.network.ext_links0.int_node.msg_count.Request_Control::5 279 +system.ruby.network.ext_links0.int_node.msg_count.Request_Control::7 279 +system.ruby.network.ext_links0.int_node.msg_count.Request_Control::8 8 +system.ruby.network.ext_links0.int_node.msg_count.Response_Data::2 1577 +system.ruby.network.ext_links0.int_node.msg_count.Response_Control::2 303 +system.ruby.network.ext_links0.int_node.msg_count.Response_Control::4 34 +system.ruby.network.ext_links0.int_node.msg_count.Writeback_Control::2 24 +system.ruby.network.ext_links0.int_node.msg_count.Unblock_Control::4 1556 +system.ruby.network.ext_links0.int_node.msg_bytes.Data::0 1152 +system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::0 12464 +system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::5 2232 +system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::7 2232 +system.ruby.network.ext_links0.int_node.msg_bytes.Request_Control::8 64 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Data::2 113544 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::2 2424 +system.ruby.network.ext_links0.int_node.msg_bytes.Response_Control::4 272 +system.ruby.network.ext_links0.int_node.msg_bytes.Writeback_Control::2 192 +system.ruby.network.ext_links0.int_node.msg_bytes.Unblock_Control::4 12448 +system.ruby.network.ext_links2.int_node.percent_links_utilized 0.185852 +system.ruby.network.ext_links2.int_node.msg_count.Control::0 23 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::0 3098 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::7 274 +system.ruby.network.ext_links2.int_node.msg_count.Request_Control::8 4 +system.ruby.network.ext_links2.int_node.msg_count.Response_Data::2 1568 +system.ruby.network.ext_links2.int_node.msg_count.Response_Control::2 281 +system.ruby.network.ext_links2.int_node.msg_count.Response_Control::4 23 +system.ruby.network.ext_links2.int_node.msg_count.Unblock_Control::4 3098 +system.ruby.network.ext_links2.int_node.msg_bytes.Control::0 184 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::0 24784 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::7 2192 +system.ruby.network.ext_links2.int_node.msg_bytes.Request_Control::8 32 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Data::2 112896 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::2 2248 +system.ruby.network.ext_links2.int_node.msg_bytes.Response_Control::4 184 +system.ruby.network.ext_links2.int_node.msg_bytes.Unblock_Control::4 24784 +system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl0.L1cache.num_data_array_reads 6 # number of data array reads +system.tcp_cntrl0.L1cache.num_data_array_writes 11 # number of data array writes +system.tcp_cntrl0.L1cache.num_tag_array_reads 1297 # number of tag array reads +system.tcp_cntrl0.L1cache.num_tag_array_writes 11 # number of tag array writes +system.tcp_cntrl0.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array +system.tcp_cntrl0.L1cache.num_data_array_stalls 2 # number of stalls caused by data array +system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl0.coalescer.gpu_ld_misses 5 # loads that miss in the GPU +system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl0.coalescer.gpu_st_misses 9 # stores that miss in the GPU +system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.ruby.network.ext_links4.int_node.percent_links_utilized 0.003510 +system.ruby.network.ext_links4.int_node.msg_count.Control::0 11 +system.ruby.network.ext_links4.int_node.msg_count.Data::0 34 +system.ruby.network.ext_links4.int_node.msg_count.Data::1 18 +system.ruby.network.ext_links4.int_node.msg_count.Request_Control::0 16 +system.ruby.network.ext_links4.int_node.msg_count.Request_Control::1 9 +system.ruby.network.ext_links4.int_node.msg_count.Request_Control::7 5 +system.ruby.network.ext_links4.int_node.msg_count.Request_Control::8 4 +system.ruby.network.ext_links4.int_node.msg_count.Response_Data::2 9 +system.ruby.network.ext_links4.int_node.msg_count.Response_Data::3 11 +system.ruby.network.ext_links4.int_node.msg_count.Response_Control::2 22 +system.ruby.network.ext_links4.int_node.msg_count.Response_Control::4 11 +system.ruby.network.ext_links4.int_node.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links4.int_node.msg_count.Writeback_Control::3 16 +system.ruby.network.ext_links4.int_node.msg_count.Unblock_Control::4 32 +system.ruby.network.ext_links4.int_node.msg_bytes.Control::0 88 +system.ruby.network.ext_links4.int_node.msg_bytes.Data::0 2448 +system.ruby.network.ext_links4.int_node.msg_bytes.Data::1 1296 +system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::0 128 +system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::1 72 +system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::7 40 +system.ruby.network.ext_links4.int_node.msg_bytes.Request_Control::8 32 +system.ruby.network.ext_links4.int_node.msg_bytes.Response_Data::2 648 +system.ruby.network.ext_links4.int_node.msg_bytes.Response_Data::3 792 +system.ruby.network.ext_links4.int_node.msg_bytes.Response_Control::2 176 +system.ruby.network.ext_links4.int_node.msg_bytes.Response_Control::4 88 +system.ruby.network.ext_links4.int_node.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links4.int_node.msg_bytes.Writeback_Control::3 128 +system.ruby.network.ext_links4.int_node.msg_bytes.Unblock_Control::4 256 +system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl1.L1cache.num_data_array_reads 6 # number of data array reads +system.tcp_cntrl1.L1cache.num_data_array_writes 11 # number of data array writes +system.tcp_cntrl1.L1cache.num_tag_array_reads 1297 # number of tag array reads +system.tcp_cntrl1.L1cache.num_tag_array_writes 11 # number of tag array writes +system.tcp_cntrl1.L1cache.num_tag_array_stalls 1271 # number of stalls caused by tag array +system.tcp_cntrl1.L1cache.num_data_array_stalls 2 # number of stalls caused by data array +system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl1.coalescer.gpu_ld_misses 5 # loads that miss in the GPU +system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl1.coalescer.gpu_st_misses 9 # stores that miss in the GPU +system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.sqc_cntrl0.L1cache.num_data_array_reads 86 # number of data array reads +system.sqc_cntrl0.L1cache.num_tag_array_reads 91 # number of tag array reads +system.sqc_cntrl0.L1cache.num_tag_array_writes 10 # number of tag array writes +system.sqc_cntrl0.sequencer.load_waiting_on_load 98 # Number of times a load aliased with a pending load +system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses +system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses +system.tcc_cntrl0.L2cache.num_data_array_writes 9 # number of data array writes +system.tcc_cntrl0.L2cache.num_tag_array_reads 45 # number of tag array reads +system.tcc_cntrl0.L2cache.num_tag_array_writes 21 # number of tag array writes +system.tcc_rb_cntrl0.cacheMemory.demand_hits 0 # Number of cache demand hits +system.tcc_rb_cntrl0.cacheMemory.demand_misses 0 # Number of cache demand misses +system.tcc_rb_cntrl0.cacheMemory.demand_accesses 0 # Number of cache demand accesses +system.tcc_rb_cntrl0.cacheMemory.num_tag_array_reads 29 # number of tag array reads +system.tcc_rb_cntrl0.cacheMemory.num_tag_array_writes 89 # number of tag array writes +system.tcc_rb_cntrl0.cacheMemory.num_tag_array_stalls 20 # number of stalls caused by tag array +system.ruby.network.msg_count.Control 34 +system.ruby.network.msg_count.Data 68 +system.ruby.network.msg_count.Request_Control 5534 +system.ruby.network.msg_count.Response_Data 3165 +system.ruby.network.msg_count.Response_Control 674 +system.ruby.network.msg_count.Writeback_Control 56 +system.ruby.network.msg_count.Unblock_Control 4686 +system.ruby.network.msg_byte.Control 272 +system.ruby.network.msg_byte.Data 4896 +system.ruby.network.msg_byte.Request_Control 44272 +system.ruby.network.msg_byte.Response_Data 227880 +system.ruby.network.msg_byte.Response_Control 5392 +system.ruby.network.msg_byte.Writeback_Control 448 +system.ruby.network.msg_byte.Unblock_Control 37488 +system.sqc_coalescer.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.sqc_coalescer.clk_domain.clock 1000 # Clock period in ticks +system.sqc_coalescer.uncoalesced_accesses 86 # Number of uncoalesced TLB accesses +system.sqc_coalescer.coalesced_accesses 66 # Number of coalesced TLB accesses +system.sqc_coalescer.queuing_cycles 288000 # Number of cycles spent in queue +system.sqc_coalescer.local_queuing_cycles 288000 # Number of cycles spent in queue for all incoming reqs +system.sqc_coalescer.local_latency 3348.837209 # Avg. latency over all incoming pkts +system.sqc_tlb.clk_domain.voltage_domain.voltage 1 # Voltage in Volts +system.sqc_tlb.clk_domain.clock 1000 # Clock period in ticks +system.sqc_tlb.local_TLB_accesses 66 # Number of TLB accesses +system.sqc_tlb.local_TLB_hits 65 # Number of TLB hits +system.sqc_tlb.local_TLB_misses 1 # Number of TLB misses +system.sqc_tlb.local_TLB_miss_rate 1.515152 # TLB miss rate +system.sqc_tlb.global_TLB_accesses 86 # Number of TLB accesses +system.sqc_tlb.global_TLB_hits 78 # Number of TLB hits +system.sqc_tlb.global_TLB_misses 8 # Number of TLB misses +system.sqc_tlb.global_TLB_miss_rate 9.302326 # TLB miss rate +system.sqc_tlb.access_cycles 86008 # Cycles spent accessing this TLB level +system.sqc_tlb.page_table_cycles 0 # Cycles spent accessing the page table +system.sqc_tlb.unique_pages 1 # Number of unique pages touched +system.sqc_tlb.local_cycles 66001 # Number of cycles spent in queue for all incoming reqs +system.sqc_tlb.local_latency 1000.015152 # Avg. latency over incoming coalesced reqs +system.sqc_tlb.avg_reuse_distance 0 # avg. reuse distance over all pages (in ticks) +system.ruby.network.ext_links0.int_node.throttle0.link_utilization 0.091873 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Data::0 16 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::0 1279 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Request_Control::5 279 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Data::2 19 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Response_Control::2 17 +system.ruby.network.ext_links0.int_node.throttle0.msg_count.Unblock_Control::4 1556 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Data::0 1152 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::0 10232 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Request_Control::5 2232 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Data::2 1368 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Response_Control::2 136 +system.ruby.network.ext_links0.int_node.throttle0.msg_bytes.Unblock_Control::4 12448 +system.ruby.network.ext_links0.int_node.throttle1.link_utilization 0.015277 +system.ruby.network.ext_links0.int_node.throttle1.msg_count.Request_Control::0 279 +system.ruby.network.ext_links0.int_node.throttle1.msg_count.Response_Control::2 286 +system.ruby.network.ext_links0.int_node.throttle1.msg_count.Writeback_Control::2 8 +system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Request_Control::0 2232 +system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Response_Control::2 2288 +system.ruby.network.ext_links0.int_node.throttle1.msg_bytes.Writeback_Control::2 64 +system.ruby.network.ext_links0.int_node.throttle2.link_utilization 0.379702 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Request_Control::7 274 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Request_Control::8 4 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Data::2 1549 +system.ruby.network.ext_links0.int_node.throttle2.msg_count.Response_Control::4 23 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Request_Control::7 2192 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Request_Control::8 32 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Data::2 111528 +system.ruby.network.ext_links0.int_node.throttle2.msg_bytes.Response_Control::4 184 +system.ruby.network.ext_links0.int_node.throttle3.link_utilization 0.003119 +system.ruby.network.ext_links0.int_node.throttle3.msg_count.Request_Control::7 5 +system.ruby.network.ext_links0.int_node.throttle3.msg_count.Request_Control::8 4 +system.ruby.network.ext_links0.int_node.throttle3.msg_count.Response_Data::2 9 +system.ruby.network.ext_links0.int_node.throttle3.msg_count.Response_Control::4 11 +system.ruby.network.ext_links0.int_node.throttle3.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Request_Control::7 40 +system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Request_Control::8 32 +system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Response_Data::2 648 +system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Response_Control::4 88 +system.ruby.network.ext_links0.int_node.throttle3.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links2.int_node.throttle0.link_utilization 0.372290 +system.ruby.network.ext_links2.int_node.throttle0.msg_count.Control::0 23 +system.ruby.network.ext_links2.int_node.throttle0.msg_count.Response_Data::2 1549 +system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Control::0 184 +system.ruby.network.ext_links2.int_node.throttle0.msg_bytes.Response_Data::2 111528 +system.ruby.network.ext_links2.int_node.throttle1.link_utilization 0.090620 +system.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::0 1549 +system.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::7 274 +system.ruby.network.ext_links2.int_node.throttle1.msg_count.Request_Control::8 4 +system.ruby.network.ext_links2.int_node.throttle1.msg_count.Response_Control::4 23 +system.ruby.network.ext_links2.int_node.throttle1.msg_count.Unblock_Control::4 1549 +system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::0 12392 +system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::7 2192 +system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Request_Control::8 32 +system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Response_Control::4 184 +system.ruby.network.ext_links2.int_node.throttle1.msg_bytes.Unblock_Control::4 12392 +system.ruby.network.ext_links2.int_node.throttle2.link_utilization 0.094646 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Request_Control::0 1549 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Data::2 19 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Response_Control::2 281 +system.ruby.network.ext_links2.int_node.throttle2.msg_count.Unblock_Control::4 1549 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Request_Control::0 12392 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Data::2 1368 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Response_Control::2 2248 +system.ruby.network.ext_links2.int_node.throttle2.msg_bytes.Unblock_Control::4 12392 +system.ruby.network.ext_links4.int_node.throttle0.link_utilization 0.000933 +system.ruby.network.ext_links4.int_node.throttle0.msg_count.Response_Data::3 3 +system.ruby.network.ext_links4.int_node.throttle0.msg_count.Writeback_Control::3 8 +system.ruby.network.ext_links4.int_node.throttle0.msg_bytes.Response_Data::3 216 +system.ruby.network.ext_links4.int_node.throttle0.msg_bytes.Writeback_Control::3 64 +system.ruby.network.ext_links4.int_node.throttle1.link_utilization 0.000933 +system.ruby.network.ext_links4.int_node.throttle1.msg_count.Response_Data::3 3 +system.ruby.network.ext_links4.int_node.throttle1.msg_count.Writeback_Control::3 8 +system.ruby.network.ext_links4.int_node.throttle1.msg_bytes.Response_Data::3 216 +system.ruby.network.ext_links4.int_node.throttle1.msg_bytes.Writeback_Control::3 64 +system.ruby.network.ext_links4.int_node.throttle2.link_utilization 0.007438 +system.ruby.network.ext_links4.int_node.throttle2.msg_count.Control::0 11 +system.ruby.network.ext_links4.int_node.throttle2.msg_count.Data::1 18 +system.ruby.network.ext_links4.int_node.throttle2.msg_count.Request_Control::1 9 +system.ruby.network.ext_links4.int_node.throttle2.msg_count.Response_Data::2 9 +system.ruby.network.ext_links4.int_node.throttle2.msg_count.Writeback_Control::2 16 +system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Control::0 88 +system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Data::1 1296 +system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Request_Control::1 72 +system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Response_Data::2 648 +system.ruby.network.ext_links4.int_node.throttle2.msg_bytes.Writeback_Control::2 128 +system.ruby.network.ext_links4.int_node.throttle3.link_utilization 0.001200 +system.ruby.network.ext_links4.int_node.throttle3.msg_count.Response_Data::3 5 +system.ruby.network.ext_links4.int_node.throttle3.msg_bytes.Response_Data::3 360 +system.ruby.network.ext_links4.int_node.throttle4.link_utilization 0.005705 +system.ruby.network.ext_links4.int_node.throttle4.msg_count.Data::0 18 +system.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::0 7 +system.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::7 5 +system.ruby.network.ext_links4.int_node.throttle4.msg_count.Request_Control::8 4 +system.ruby.network.ext_links4.int_node.throttle4.msg_count.Response_Control::4 11 +system.ruby.network.ext_links4.int_node.throttle4.msg_count.Unblock_Control::4 25 +system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Data::0 1296 +system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::0 56 +system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::7 40 +system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Request_Control::8 32 +system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Response_Control::4 88 +system.ruby.network.ext_links4.int_node.throttle4.msg_bytes.Unblock_Control::4 200 +system.ruby.network.ext_links4.int_node.throttle5.link_utilization 0.004852 +system.ruby.network.ext_links4.int_node.throttle5.msg_count.Data::0 16 +system.ruby.network.ext_links4.int_node.throttle5.msg_count.Request_Control::0 9 +system.ruby.network.ext_links4.int_node.throttle5.msg_count.Response_Control::2 22 +system.ruby.network.ext_links4.int_node.throttle5.msg_count.Unblock_Control::4 7 +system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Data::0 1152 +system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Request_Control::0 72 +system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Response_Control::2 176 +system.ruby.network.ext_links4.int_node.throttle5.msg_bytes.Unblock_Control::4 56 +system.ruby.CorePair_Controller.C0_Load_L1miss 193 0.00% 0.00% +system.ruby.CorePair_Controller.C0_Load_L1hit 16142 0.00% 0.00% +system.ruby.CorePair_Controller.Ifetch0_L1hit 85994 0.00% 0.00% +system.ruby.CorePair_Controller.Ifetch0_L1miss 1101 0.00% 0.00% +system.ruby.CorePair_Controller.C0_Store_L1miss 327 0.00% 0.00% +system.ruby.CorePair_Controller.C0_Store_L1hit 10446 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckS 1047 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckM 329 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckE 173 0.00% 0.00% +system.ruby.CorePair_Controller.L1I_Repl 602 0.00% 0.00% +system.ruby.CorePair_Controller.L1D0_Repl 28 0.00% 0.00% +system.ruby.CorePair_Controller.L2_to_L1D0 7 0.00% 0.00% +system.ruby.CorePair_Controller.L2_to_L1I 67 0.00% 0.00% +system.ruby.CorePair_Controller.PrbInvData 15 0.00% 0.00% +system.ruby.CorePair_Controller.PrbInvDataDemand 2 0.00% 0.00% +system.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00% +system.ruby.CorePair_Controller.PrbShrDataDemand 2 0.00% 0.00% +system.ruby.CorePair_Controller.I.C0_Load_L1miss 186 0.00% 0.00% +system.ruby.CorePair_Controller.I.Ifetch0_L1miss 1034 0.00% 0.00% +system.ruby.CorePair_Controller.I.C0_Store_L1miss 325 0.00% 0.00% +system.ruby.CorePair_Controller.I.PrbInvDataDemand 1 0.00% 0.00% +system.ruby.CorePair_Controller.S.C0_Load_L1hit 643 0.00% 0.00% +system.ruby.CorePair_Controller.S.Ifetch0_L1hit 85994 0.00% 0.00% +system.ruby.CorePair_Controller.S.Ifetch0_L1miss 67 0.00% 0.00% +system.ruby.CorePair_Controller.S.C0_Store_L1hit 4 0.00% 0.00% +system.ruby.CorePair_Controller.S.L1I_Repl 602 0.00% 0.00% +system.ruby.CorePair_Controller.E0.C0_Load_L1miss 2 0.00% 0.00% +system.ruby.CorePair_Controller.E0.C0_Load_L1hit 2728 0.00% 0.00% +system.ruby.CorePair_Controller.E0.C0_Store_L1hit 50 0.00% 0.00% +system.ruby.CorePair_Controller.E0.L1D0_Repl 16 0.00% 0.00% +system.ruby.CorePair_Controller.E0.PrbInvData 1 0.00% 0.00% +system.ruby.CorePair_Controller.E0.PrbShrData 1 0.00% 0.00% +system.ruby.CorePair_Controller.E0.PrbShrDataDemand 1 0.00% 0.00% +system.ruby.CorePair_Controller.O.PrbInvData 4 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Load_L1miss 5 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Load_L1hit 12771 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Store_L1miss 2 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Store_L1hit 10392 0.00% 0.00% +system.ruby.CorePair_Controller.M0.L1D0_Repl 12 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbInvData 10 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbInvDataDemand 1 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbShrData 3 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbShrDataDemand 1 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0.NB_AckM 325 0.00% 0.00% +system.ruby.CorePair_Controller.I_E0S.NB_AckS 13 0.00% 0.00% +system.ruby.CorePair_Controller.I_E0S.NB_AckE 173 0.00% 0.00% +system.ruby.CorePair_Controller.Si_F0.L2_to_L1I 67 0.00% 0.00% +system.ruby.CorePair_Controller.S_M0.NB_AckM 4 0.00% 0.00% +system.ruby.CorePair_Controller.S0.NB_AckS 1034 0.00% 0.00% +system.ruby.CorePair_Controller.E0_F.L2_to_L1D0 2 0.00% 0.00% +system.ruby.CorePair_Controller.M0_F.L2_to_L1D0 5 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkS 190 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkM 31 0.00% 0.00% +system.ruby.Directory_Controller.RdBlk 56 0.00% 0.00% +system.ruby.Directory_Controller.WriteThrough 1 0.00% 0.00% +system.ruby.Directory_Controller.Atomic 1 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkSP 844 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkMP 298 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkP 137 0.00% 0.00% +system.ruby.Directory_Controller.WriteThroughP 15 0.00% 0.00% +system.ruby.Directory_Controller.AtomicP 1 0.00% 0.00% +system.ruby.Directory_Controller.CPUPrbResp 28 0.00% 0.00% +system.ruby.Directory_Controller.LastCPUPrbResp 8 0.00% 0.00% +system.ruby.Directory_Controller.ProbeAcksComplete 271 0.00% 0.00% +system.ruby.Directory_Controller.L3Hit 11 0.00% 0.00% +system.ruby.Directory_Controller.MemData 1563 0.00% 0.00% +system.ruby.Directory_Controller.CoreUnblock 1556 0.00% 0.00% +system.ruby.Directory_Controller.UnblockWriteThrough 18 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkS 190 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkM 31 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlk 56 0.00% 0.00% +system.ruby.Directory_Controller.U.WriteThrough 1 0.00% 0.00% +system.ruby.Directory_Controller.U.Atomic 1 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkSP 844 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkMP 298 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkP 137 0.00% 0.00% +system.ruby.Directory_Controller.U.WriteThroughP 15 0.00% 0.00% +system.ruby.Directory_Controller.U.AtomicP 1 0.00% 0.00% +system.ruby.Directory_Controller.U.CPUPrbResp 28 0.00% 0.00% +system.ruby.Directory_Controller.BS_M.MemData 1034 0.00% 0.00% +system.ruby.Directory_Controller.BM_M.MemData 347 0.00% 0.00% +system.ruby.Directory_Controller.B_M.L3Hit 11 0.00% 0.00% +system.ruby.Directory_Controller.B_M.MemData 180 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.ProbeAcksComplete 190 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.LastCPUPrbResp 4 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 29 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.LastCPUPrbResp 2 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.ProbeAcksComplete 52 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.MemData 2 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.LastCPUPrbResp 2 0.00% 0.00% +system.ruby.Directory_Controller.B.CoreUnblock 1556 0.00% 0.00% +system.ruby.Directory_Controller.B.UnblockWriteThrough 18 0.00% 0.00% +system.ruby.RegionBuffer_Controller.CPURead | 1220 99.43% 99.43% | 7 0.57% 100.00% +system.ruby.RegionBuffer_Controller.CPURead::total 1227 +system.ruby.RegionBuffer_Controller.CPUWrite | 331 89.95% 89.95% | 37 10.05% 100.00% +system.ruby.RegionBuffer_Controller.CPUWrite::total 368 +system.ruby.RegionBuffer_Controller.PrivateNotify | 272 98.91% 98.91% | 3 1.09% 100.00% +system.ruby.RegionBuffer_Controller.PrivateNotify::total 275 +system.ruby.RegionBuffer_Controller.SharedNotify | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.RegionBuffer_Controller.SharedNotify::total 4 +system.ruby.RegionBuffer_Controller.InvRegion | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.RegionBuffer_Controller.InvRegion::total 4 +system.ruby.RegionBuffer_Controller.DowngradeRegion | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.RegionBuffer_Controller.DowngradeRegion::total 4 +system.ruby.RegionBuffer_Controller.InvAck | 23 67.65% 67.65% | 11 32.35% 100.00% +system.ruby.RegionBuffer_Controller.InvAck::total 34 +system.ruby.RegionBuffer_Controller.DoneAck | 1572 96.26% 96.26% | 61 3.74% 100.00% +system.ruby.RegionBuffer_Controller.DoneAck::total 1633 +system.ruby.RegionBuffer_Controller.AllOutstanding | 6 54.55% 54.55% | 5 45.45% 100.00% +system.ruby.RegionBuffer_Controller.AllOutstanding::total 11 +system.ruby.RegionBuffer_Controller.Evict | 64 66.67% 66.67% | 32 33.33% 100.00% +system.ruby.RegionBuffer_Controller.Evict::total 96 +system.ruby.RegionBuffer_Controller.LastAck_PrbResp | 4 50.00% 50.00% | 4 50.00% 100.00% +system.ruby.RegionBuffer_Controller.LastAck_PrbResp::total 8 +system.ruby.RegionBuffer_Controller.StallAccess | 0 0.00% 0.00% | 16 100.00% 100.00% +system.ruby.RegionBuffer_Controller.StallAccess::total 16 +system.ruby.RegionBuffer_Controller.NP.CPURead | 243 98.78% 98.78% | 3 1.22% 100.00% +system.ruby.RegionBuffer_Controller.NP.CPURead::total 246 +system.ruby.RegionBuffer_Controller.NP.CPUWrite | 29 96.67% 96.67% | 1 3.33% 100.00% +system.ruby.RegionBuffer_Controller.NP.CPUWrite::total 30 +system.ruby.RegionBuffer_Controller.P.CPURead | 965 99.59% 99.59% | 4 0.41% 100.00% +system.ruby.RegionBuffer_Controller.P.CPURead::total 969 +system.ruby.RegionBuffer_Controller.P.CPUWrite | 298 94.90% 94.90% | 16 5.10% 100.00% +system.ruby.RegionBuffer_Controller.P.CPUWrite::total 314 +system.ruby.RegionBuffer_Controller.P.InvRegion | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.RegionBuffer_Controller.P.InvRegion::total 1 +system.ruby.RegionBuffer_Controller.P.DowngradeRegion | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.RegionBuffer_Controller.P.DowngradeRegion::total 4 +system.ruby.RegionBuffer_Controller.P.DoneAck | 1535 98.52% 98.52% | 23 1.48% 100.00% +system.ruby.RegionBuffer_Controller.P.DoneAck::total 1558 +system.ruby.RegionBuffer_Controller.P.StallAccess | 0 0.00% 0.00% | 15 100.00% 100.00% +system.ruby.RegionBuffer_Controller.P.StallAccess::total 15 +system.ruby.RegionBuffer_Controller.S.CPURead | 12 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.RegionBuffer_Controller.S.CPURead::total 12 +system.ruby.RegionBuffer_Controller.S.CPUWrite | 2 66.67% 66.67% | 1 33.33% 100.00% +system.ruby.RegionBuffer_Controller.S.CPUWrite::total 3 +system.ruby.RegionBuffer_Controller.S.InvRegion | 1 33.33% 33.33% | 2 66.67% 100.00% +system.ruby.RegionBuffer_Controller.S.InvRegion::total 3 +system.ruby.RegionBuffer_Controller.S.DoneAck | 14 87.50% 87.50% | 2 12.50% 100.00% +system.ruby.RegionBuffer_Controller.S.DoneAck::total 16 +system.ruby.RegionBuffer_Controller.NP_PS.PrivateNotify | 270 99.26% 99.26% | 2 0.74% 100.00% +system.ruby.RegionBuffer_Controller.NP_PS.PrivateNotify::total 272 +system.ruby.RegionBuffer_Controller.NP_PS.SharedNotify | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.RegionBuffer_Controller.NP_PS.SharedNotify::total 4 +system.ruby.RegionBuffer_Controller.NP_PS.DoneAck | 8 25.81% 25.81% | 23 74.19% 100.00% +system.ruby.RegionBuffer_Controller.NP_PS.DoneAck::total 31 +system.ruby.RegionBuffer_Controller.NP_PS.StallAccess | 0 0.00% 0.00% | 1 100.00% 100.00% +system.ruby.RegionBuffer_Controller.NP_PS.StallAccess::total 1 +system.ruby.RegionBuffer_Controller.S_P.CPUWrite | 0 0.00% 0.00% | 18 100.00% 100.00% +system.ruby.RegionBuffer_Controller.S_P.CPUWrite::total 18 +system.ruby.RegionBuffer_Controller.S_P.PrivateNotify | 2 66.67% 66.67% | 1 33.33% 100.00% +system.ruby.RegionBuffer_Controller.S_P.PrivateNotify::total 3 +system.ruby.RegionBuffer_Controller.S_P.DoneAck | 15 53.57% 53.57% | 13 46.43% 100.00% +system.ruby.RegionBuffer_Controller.S_P.DoneAck::total 28 +system.ruby.RegionBuffer_Controller.P_NP.InvAck | 17 60.71% 60.71% | 11 39.29% 100.00% +system.ruby.RegionBuffer_Controller.P_NP.InvAck::total 28 +system.ruby.RegionBuffer_Controller.P_NP.Evict | 32 50.00% 50.00% | 32 50.00% 100.00% +system.ruby.RegionBuffer_Controller.P_NP.Evict::total 64 +system.ruby.RegionBuffer_Controller.P_NP.LastAck_PrbResp | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.RegionBuffer_Controller.P_NP.LastAck_PrbResp::total 4 +system.ruby.RegionBuffer_Controller.P_S.InvAck | 6 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.RegionBuffer_Controller.P_S.InvAck::total 6 +system.ruby.RegionBuffer_Controller.P_S.Evict | 32 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.RegionBuffer_Controller.P_S.Evict::total 32 +system.ruby.RegionBuffer_Controller.P_S.LastAck_PrbResp | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.RegionBuffer_Controller.P_S.LastAck_PrbResp::total 4 +system.ruby.RegionBuffer_Controller.P_NP_O.AllOutstanding | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.RegionBuffer_Controller.P_NP_O.AllOutstanding::total 4 +system.ruby.RegionBuffer_Controller.P_S_O.AllOutstanding | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.RegionBuffer_Controller.P_S_O.AllOutstanding::total 4 +system.ruby.RegionBuffer_Controller.S_O.AllOutstanding | 2 66.67% 66.67% | 1 33.33% 100.00% +system.ruby.RegionBuffer_Controller.S_O.AllOutstanding::total 3 +system.ruby.RegionBuffer_Controller.SS_P.CPUWrite | 2 66.67% 66.67% | 1 33.33% 100.00% +system.ruby.RegionBuffer_Controller.SS_P.CPUWrite::total 3 +system.ruby.RegionDir_Controller.SendInv 1 0.00% 0.00% +system.ruby.RegionDir_Controller.SendUpgrade 3 0.00% 0.00% +system.ruby.RegionDir_Controller.SendDowngrade 4 0.00% 0.00% +system.ruby.RegionDir_Controller.PrivateRequest 271 0.00% 0.00% +system.ruby.RegionDir_Controller.InvAckCore 4 0.00% 0.00% +system.ruby.RegionDir_Controller.InvAckCoreNoShare 4 0.00% 0.00% +system.ruby.RegionDir_Controller.CPUPrivateAck 278 0.00% 0.00% +system.ruby.RegionDir_Controller.LastAck 8 0.00% 0.00% +system.ruby.RegionDir_Controller.DirReadyAck 8 0.00% 0.00% +system.ruby.RegionDir_Controller.TriggerInv 4 0.00% 0.00% +system.ruby.RegionDir_Controller.TriggerDowngrade 4 0.00% 0.00% +system.ruby.RegionDir_Controller.NP.PrivateRequest 271 0.00% 0.00% +system.ruby.RegionDir_Controller.P.SendInv 1 0.00% 0.00% +system.ruby.RegionDir_Controller.P.SendDowngrade 4 0.00% 0.00% +system.ruby.RegionDir_Controller.S.SendUpgrade 3 0.00% 0.00% +system.ruby.RegionDir_Controller.NP_P.CPUPrivateAck 270 0.00% 0.00% +system.ruby.RegionDir_Controller.P_P.CPUPrivateAck 1 0.00% 0.00% +system.ruby.RegionDir_Controller.P_S.CPUPrivateAck 4 0.00% 0.00% +system.ruby.RegionDir_Controller.S_P.CPUPrivateAck 3 0.00% 0.00% +system.ruby.RegionDir_Controller.P_AS.InvAckCore 4 0.00% 0.00% +system.ruby.RegionDir_Controller.P_AS.LastAck 4 0.00% 0.00% +system.ruby.RegionDir_Controller.S_AP.InvAckCoreNoShare 3 0.00% 0.00% +system.ruby.RegionDir_Controller.S_AP.LastAck 3 0.00% 0.00% +system.ruby.RegionDir_Controller.P_AP.InvAckCoreNoShare 1 0.00% 0.00% +system.ruby.RegionDir_Controller.P_AP.LastAck 1 0.00% 0.00% +system.ruby.RegionDir_Controller.P_AP_W.DirReadyAck 1 0.00% 0.00% +system.ruby.RegionDir_Controller.P_AP_W.TriggerInv 1 0.00% 0.00% +system.ruby.RegionDir_Controller.P_AS_W.DirReadyAck 4 0.00% 0.00% +system.ruby.RegionDir_Controller.P_AS_W.TriggerDowngrade 4 0.00% 0.00% +system.ruby.RegionDir_Controller.S_AP_W.DirReadyAck 3 0.00% 0.00% +system.ruby.RegionDir_Controller.S_AP_W.TriggerInv 3 0.00% 0.00% +system.ruby.LD.latency_hist::bucket_size 64 +system.ruby.LD.latency_hist::max_bucket 639 +system.ruby.LD.latency_hist::samples 16335 +system.ruby.LD.latency_hist::mean 2.844751 +system.ruby.LD.latency_hist::gmean 1.060634 +system.ruby.LD.latency_hist::stdev 17.742972 +system.ruby.LD.latency_hist | 16149 98.86% 98.86% | 11 0.07% 98.93% | 119 0.73% 99.66% | 52 0.32% 99.98% | 2 0.01% 99.99% | 1 0.01% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 16335 +system.ruby.LD.hit_latency_hist::bucket_size 64 +system.ruby.LD.hit_latency_hist::max_bucket 639 +system.ruby.LD.hit_latency_hist::samples 186 +system.ruby.LD.hit_latency_hist::mean 162.333333 +system.ruby.LD.hit_latency_hist::gmean 157.431876 +system.ruby.LD.hit_latency_hist::stdev 43.755298 +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 11 5.91% 5.91% | 119 63.98% 69.89% | 52 27.96% 97.85% | 2 1.08% 98.92% | 1 0.54% 99.46% | 1 0.54% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 186 +system.ruby.LD.miss_latency_hist::bucket_size 2 +system.ruby.LD.miss_latency_hist::max_bucket 19 +system.ruby.LD.miss_latency_hist::samples 16149 +system.ruby.LD.miss_latency_hist::mean 1.007802 +system.ruby.LD.miss_latency_hist::gmean 1.001277 +system.ruby.LD.miss_latency_hist::stdev 0.374686 +system.ruby.LD.miss_latency_hist | 16142 99.96% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 0 0.00% 99.96% | 7 0.04% 100.00% +system.ruby.LD.miss_latency_hist::total 16149 +system.ruby.ST.latency_hist::bucket_size 64 +system.ruby.ST.latency_hist::max_bucket 639 +system.ruby.ST.latency_hist::samples 10412 +system.ruby.ST.latency_hist::mean 5.551287 +system.ruby.ST.latency_hist::gmean 1.167783 +system.ruby.ST.latency_hist::stdev 26.172531 +system.ruby.ST.latency_hist | 10087 96.88% 96.88% | 0 0.00% 96.88% | 289 2.78% 99.65% | 29 0.28% 99.93% | 4 0.04% 99.97% | 2 0.02% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 10412 +system.ruby.ST.hit_latency_hist::bucket_size 64 +system.ruby.ST.hit_latency_hist::max_bucket 639 +system.ruby.ST.hit_latency_hist::samples 325 +system.ruby.ST.hit_latency_hist::mean 146.809231 +system.ruby.ST.hit_latency_hist::gmean 143.903653 +system.ruby.ST.hit_latency_hist::stdev 36.751508 +system.ruby.ST.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 289 88.92% 88.92% | 29 8.92% 97.85% | 4 1.23% 99.08% | 2 0.62% 99.69% | 0 0.00% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 325 +system.ruby.ST.miss_latency_hist::bucket_size 1 +system.ruby.ST.miss_latency_hist::max_bucket 9 +system.ruby.ST.miss_latency_hist::samples 10087 +system.ruby.ST.miss_latency_hist::mean 1 +system.ruby.ST.miss_latency_hist::gmean 1 +system.ruby.ST.miss_latency_hist | 0 0.00% 0.00% | 10087 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 10087 +system.ruby.IFETCH.latency_hist::bucket_size 64 +system.ruby.IFETCH.latency_hist::max_bucket 639 +system.ruby.IFETCH.latency_hist::samples 87095 +system.ruby.IFETCH.latency_hist::mean 2.818945 +system.ruby.IFETCH.latency_hist::gmean 1.063630 +system.ruby.IFETCH.latency_hist::stdev 17.067789 +system.ruby.IFETCH.latency_hist | 86061 98.81% 98.81% | 0 0.00% 98.81% | 826 0.95% 99.76% | 185 0.21% 99.97% | 8 0.01% 99.98% | 9 0.01% 99.99% | 6 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 87095 +system.ruby.IFETCH.hit_latency_hist::bucket_size 64 +system.ruby.IFETCH.hit_latency_hist::max_bucket 639 +system.ruby.IFETCH.hit_latency_hist::samples 1034 +system.ruby.IFETCH.hit_latency_hist::mean 153.045455 +system.ruby.IFETCH.hit_latency_hist::gmean 149.192268 +system.ruby.IFETCH.hit_latency_hist::stdev 40.969954 +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 826 79.88% 79.88% | 185 17.89% 97.78% | 8 0.77% 98.55% | 9 0.87% 99.42% | 6 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 1034 +system.ruby.IFETCH.miss_latency_hist::bucket_size 2 +system.ruby.IFETCH.miss_latency_hist::max_bucket 19 +system.ruby.IFETCH.miss_latency_hist::samples 86061 +system.ruby.IFETCH.miss_latency_hist::mean 1.014013 +system.ruby.IFETCH.miss_latency_hist::gmean 1.002295 +system.ruby.IFETCH.miss_latency_hist::stdev 0.502042 +system.ruby.IFETCH.miss_latency_hist | 85994 99.92% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 0 0.00% 99.92% | 67 0.08% 100.00% +system.ruby.IFETCH.miss_latency_hist::total 86061 +system.ruby.RMW_Read.latency_hist::bucket_size 32 +system.ruby.RMW_Read.latency_hist::max_bucket 319 +system.ruby.RMW_Read.latency_hist::samples 341 +system.ruby.RMW_Read.latency_hist::mean 2.671554 +system.ruby.RMW_Read.latency_hist::gmean 1.059947 +system.ruby.RMW_Read.latency_hist::stdev 15.416875 +system.ruby.RMW_Read.latency_hist | 337 98.83% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 0 0.00% 98.83% | 3 0.88% 99.71% | 1 0.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.latency_hist::total 341 +system.ruby.RMW_Read.hit_latency_hist::bucket_size 32 +system.ruby.RMW_Read.hit_latency_hist::max_bucket 319 +system.ruby.RMW_Read.hit_latency_hist::samples 4 +system.ruby.RMW_Read.hit_latency_hist::mean 143.500000 +system.ruby.RMW_Read.hit_latency_hist::gmean 143.041358 +system.ruby.RMW_Read.hit_latency_hist::stdev 13.403980 +system.ruby.RMW_Read.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.hit_latency_hist::total 4 +system.ruby.RMW_Read.miss_latency_hist::bucket_size 1 +system.ruby.RMW_Read.miss_latency_hist::max_bucket 9 +system.ruby.RMW_Read.miss_latency_hist::samples 337 +system.ruby.RMW_Read.miss_latency_hist::mean 1 +system.ruby.RMW_Read.miss_latency_hist::gmean 1 +system.ruby.RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.miss_latency_hist::total 337 +system.ruby.Locked_RMW_Read.latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.latency_hist::samples 10 +system.ruby.Locked_RMW_Read.latency_hist::mean 1 +system.ruby.Locked_RMW_Read.latency_hist::gmean 1 +system.ruby.Locked_RMW_Read.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.latency_hist::total 10 +system.ruby.Locked_RMW_Read.miss_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.miss_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.miss_latency_hist::samples 10 +system.ruby.Locked_RMW_Read.miss_latency_hist::mean 1 +system.ruby.Locked_RMW_Read.miss_latency_hist::gmean 1 +system.ruby.Locked_RMW_Read.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.miss_latency_hist::total 10 +system.ruby.Locked_RMW_Write.latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.latency_hist::samples 10 +system.ruby.Locked_RMW_Write.latency_hist::mean 1 +system.ruby.Locked_RMW_Write.latency_hist::gmean 1 +system.ruby.Locked_RMW_Write.latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.latency_hist::total 10 +system.ruby.Locked_RMW_Write.miss_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.miss_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.miss_latency_hist::samples 10 +system.ruby.Locked_RMW_Write.miss_latency_hist::mean 1 +system.ruby.Locked_RMW_Write.miss_latency_hist::gmean 1 +system.ruby.Locked_RMW_Write.miss_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.miss_latency_hist::total 10 +system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 1 +system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 9 +system.ruby.L1Cache.miss_mach_latency_hist::samples 112580 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 1 +system.ruby.L1Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 112580 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 112580 +system.ruby.L2Cache.miss_mach_latency_hist::bucket_size 2 +system.ruby.L2Cache.miss_mach_latency_hist::max_bucket 19 +system.ruby.L2Cache.miss_mach_latency_hist::samples 74 +system.ruby.L2Cache.miss_mach_latency_hist::mean 19 +system.ruby.L2Cache.miss_mach_latency_hist::gmean 19.000000 +system.ruby.L2Cache.miss_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 74 100.00% 100.00% +system.ruby.L2Cache.miss_mach_latency_hist::total 74 +system.ruby.L3Cache.hit_mach_latency_hist::bucket_size 16 +system.ruby.L3Cache.hit_mach_latency_hist::max_bucket 159 +system.ruby.L3Cache.hit_mach_latency_hist::samples 11 +system.ruby.L3Cache.hit_mach_latency_hist::mean 107 +system.ruby.L3Cache.hit_mach_latency_hist::gmean 107.000000 +system.ruby.L3Cache.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L3Cache.hit_mach_latency_hist::total 11 +system.ruby.Directory.hit_mach_latency_hist::bucket_size 64 +system.ruby.Directory.hit_mach_latency_hist::max_bucket 639 +system.ruby.Directory.hit_mach_latency_hist::samples 1538 +system.ruby.Directory.hit_mach_latency_hist::mean 153.155397 +system.ruby.Directory.hit_mach_latency_hist::gmean 149.362802 +system.ruby.Directory.hit_mach_latency_hist::stdev 40.587599 +system.ruby.Directory.hit_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 1238 80.49% 80.49% | 266 17.30% 97.79% | 14 0.91% 98.70% | 12 0.78% 99.48% | 7 0.46% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.hit_mach_latency_hist::total 1538 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::samples 16142 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.LD.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 16142 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L1Cache.miss_type_mach_latency_hist::total 16142 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::bucket_size 2 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::max_bucket 19 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::samples 7 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::mean 19 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::gmean 19.000000 +system.ruby.LD.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 7 100.00% 100.00% +system.ruby.LD.L2Cache.miss_type_mach_latency_hist::total 7 +system.ruby.LD.L3Cache.hit_type_mach_latency_hist::bucket_size 16 +system.ruby.LD.L3Cache.hit_type_mach_latency_hist::max_bucket 159 +system.ruby.LD.L3Cache.hit_type_mach_latency_hist::samples 11 +system.ruby.LD.L3Cache.hit_type_mach_latency_hist::mean 107 +system.ruby.LD.L3Cache.hit_type_mach_latency_hist::gmean 107.000000 +system.ruby.LD.L3Cache.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 11 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.L3Cache.hit_type_mach_latency_hist::total 11 +system.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size 64 +system.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket 639 +system.ruby.LD.Directory.hit_type_mach_latency_hist::samples 175 +system.ruby.LD.Directory.hit_type_mach_latency_hist::mean 165.811429 +system.ruby.LD.Directory.hit_type_mach_latency_hist::gmean 161.300002 +system.ruby.LD.Directory.hit_type_mach_latency_hist::stdev 42.776536 +system.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 119 68.00% 68.00% | 52 29.71% 97.71% | 2 1.14% 98.86% | 1 0.57% 99.43% | 1 0.57% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.hit_type_mach_latency_hist::total 175 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 10087 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10087 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 10087 +system.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size 64 +system.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket 639 +system.ruby.ST.Directory.hit_type_mach_latency_hist::samples 325 +system.ruby.ST.Directory.hit_type_mach_latency_hist::mean 146.809231 +system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 143.903653 +system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 36.751508 +system.ruby.ST.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 289 88.92% 88.92% | 29 8.92% 97.85% | 4 1.23% 99.08% | 2 0.62% 99.69% | 0 0.00% 99.69% | 1 0.31% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.hit_type_mach_latency_hist::total 325 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::samples 85994 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 85994 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.L1Cache.miss_type_mach_latency_hist::total 85994 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::bucket_size 2 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::max_bucket 19 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::samples 67 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::mean 19 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::gmean 19.000000 +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 67 100.00% 100.00% +system.ruby.IFETCH.L2Cache.miss_type_mach_latency_hist::total 67 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 64 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 639 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1034 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 153.045455 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 149.192268 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev 40.969954 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 826 79.88% 79.88% | 185 17.89% 97.78% | 8 0.77% 98.55% | 9 0.87% 99.42% | 6 0.58% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1034 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 337 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 337 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.L1Cache.miss_type_mach_latency_hist::total 337 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::bucket_size 32 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::max_bucket 319 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::samples 4 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::mean 143.500000 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::gmean 143.041358 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::stdev 13.403980 +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 3 75.00% 75.00% | 1 25.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.RMW_Read.Directory.hit_type_mach_latency_hist::total 4 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::samples 10 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Read.L1Cache.miss_type_mach_latency_hist::total 10 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::bucket_size 1 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::max_bucket 9 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::samples 10 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::mean 1 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::gmean 1 +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist | 0 0.00% 0.00% | 10 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Locked_RMW_Write.L1Cache.miss_type_mach_latency_hist::total 10 +system.ruby.SQC_Controller.Fetch 86 0.00% 0.00% +system.ruby.SQC_Controller.Data 5 0.00% 0.00% +system.ruby.SQC_Controller.I.Fetch 5 0.00% 0.00% +system.ruby.SQC_Controller.I.Data 5 0.00% 0.00% +system.ruby.SQC_Controller.V.Fetch 81 0.00% 0.00% +system.ruby.TCC_Controller.RdBlk 9 0.00% 0.00% +system.ruby.TCC_Controller.WrVicBlk 16 0.00% 0.00% +system.ruby.TCC_Controller.Atomic 2 0.00% 0.00% +system.ruby.TCC_Controller.AtomicDone 1 0.00% 0.00% +system.ruby.TCC_Controller.Data 9 0.00% 0.00% +system.ruby.TCC_Controller.PrbInv 11 0.00% 0.00% +system.ruby.TCC_Controller.WBAck 16 0.00% 0.00% +system.ruby.TCC_Controller.V.PrbInv 1 0.00% 0.00% +system.ruby.TCC_Controller.I.RdBlk 7 0.00% 0.00% +system.ruby.TCC_Controller.I.WrVicBlk 16 0.00% 0.00% +system.ruby.TCC_Controller.I.Atomic 1 0.00% 0.00% +system.ruby.TCC_Controller.I.PrbInv 10 0.00% 0.00% +system.ruby.TCC_Controller.I.WBAck 16 0.00% 0.00% +system.ruby.TCC_Controller.IV.RdBlk 2 0.00% 0.00% +system.ruby.TCC_Controller.IV.Data 7 0.00% 0.00% +system.ruby.TCC_Controller.A.Atomic 1 0.00% 0.00% +system.ruby.TCC_Controller.A.AtomicDone 1 0.00% 0.00% +system.ruby.TCC_Controller.A.Data 2 0.00% 0.00% +system.ruby.TCP_Controller.Load | 5 50.00% 50.00% | 5 50.00% 100.00% +system.ruby.TCP_Controller.Load::total 10 +system.ruby.TCP_Controller.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.StoreThrough::total 16 +system.ruby.TCP_Controller.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.Atomic::total 2 +system.ruby.TCP_Controller.Flush | 768 50.00% 50.00% | 768 50.00% 100.00% +system.ruby.TCP_Controller.Flush::total 1536 +system.ruby.TCP_Controller.Evict | 512 50.00% 50.00% | 512 50.00% 100.00% +system.ruby.TCP_Controller.Evict::total 1024 +system.ruby.TCP_Controller.TCC_Ack | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.TCP_Controller.TCC_Ack::total 6 +system.ruby.TCP_Controller.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.TCC_AckWB::total 16 +system.ruby.TCP_Controller.I.Load | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.I.Load::total 4 +system.ruby.TCP_Controller.I.StoreThrough | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.I.StoreThrough::total 16 +system.ruby.TCP_Controller.I.Atomic | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.I.Atomic::total 2 +system.ruby.TCP_Controller.I.Flush | 766 50.00% 50.00% | 766 50.00% 100.00% +system.ruby.TCP_Controller.I.Flush::total 1532 +system.ruby.TCP_Controller.I.Evict | 510 50.00% 50.00% | 510 50.00% 100.00% +system.ruby.TCP_Controller.I.Evict::total 1020 +system.ruby.TCP_Controller.I.TCC_Ack | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.I.TCC_Ack::total 4 +system.ruby.TCP_Controller.I.TCC_AckWB | 8 50.00% 50.00% | 8 50.00% 100.00% +system.ruby.TCP_Controller.I.TCC_AckWB::total 16 +system.ruby.TCP_Controller.V.Load | 3 50.00% 50.00% | 3 50.00% 100.00% +system.ruby.TCP_Controller.V.Load::total 6 +system.ruby.TCP_Controller.V.Flush | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.V.Flush::total 4 +system.ruby.TCP_Controller.V.Evict | 2 50.00% 50.00% | 2 50.00% 100.00% +system.ruby.TCP_Controller.V.Evict::total 4 +system.ruby.TCP_Controller.A.TCC_Ack | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.A.TCC_Ack::total 2 + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/04.gpu/test.py b/tests/quick/se/04.gpu/test.py new file mode 100644 index 000000000..a074a8144 --- /dev/null +++ b/tests/quick/se/04.gpu/test.py @@ -0,0 +1,48 @@ +# +# Copyright (c) 2015 Advanced Micro Devices, Inc. +# All rights reserved. +# +# For use for simulation and test purposes only +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors +# may be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# Author: Brad Beckmann +# +executable = binpath('gpu-hello') +kernel_path = os.path.dirname(executable) +kernel_files = glob.glob(os.path.join(kernel_path, '*.asm')) +if kernel_files: + print "Using GPU kernel code file(s)", ",".join(kernel_files) +else: + fatal("Can't locate kernel code (.asm) in " + kernel_path) + +driver = ClDriver(filename="hsa", codefile=kernel_files) +root.system.cpu[2].cl_driver = driver +root.system.cpu[0].workload = LiveProcess(cmd = 'gpu-hello', + executable = binpath('gpu-hello'), + drivers = [driver]) + diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini new file mode 100644 index 000000000..06da5f023 --- /dev/null +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/config.ini @@ -0,0 +1,5862 @@ +[root] +type=Root +children=system +eventq_index=0 +full_system=false +sim_quantum=0 +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=clk_domain cp_cntrl0 cpu dir_cntrl0 dvfs_handler mem_ctrls ruby sqc_cntrl0 sqc_cntrl1 sys_port_proxy tcc_cntrl0 tccdir_cntrl0 tcp_cntrl0 tcp_cntrl1 tcp_cntrl2 tcp_cntrl3 tcp_cntrl4 tcp_cntrl5 tcp_cntrl6 tcp_cntrl7 voltage_domain +boot_osflags=a +cache_line_size=64 +clk_domain=system.clk_domain +eventq_index=0 +exit_on_work_items=false +init_param=0 +kernel= +kernel_addr_check=true +load_addr_mask=1099511627775 +load_offset=0 +mem_mode=timing +mem_ranges=0:268435455 +memories=system.mem_ctrls +mmap_using_noreserve=false +multi_thread=false +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.clk_domain] +type=SrcClockDomain +clock=1 +domain_id=-1 +eventq_index=0 +init_perf_level=0 +voltage_domain=system.voltage_domain + +[system.cp_cntrl0] +type=CorePair_Controller +children=L1D0cache L1D1cache L1Icache L2cache mandatoryQueue probeToCore requestFromCore responseFromCore responseToCore sequencer sequencer1 triggerQueue unblockFromCore +L1D0cache=system.cp_cntrl0.L1D0cache +L1D1cache=system.cp_cntrl0.L1D1cache +L1Icache=system.cp_cntrl0.L1Icache +L2cache=system.cp_cntrl0.L2cache +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +issue_latency=15 +l2_hit_latency=18 +mandatoryQueue=system.cp_cntrl0.mandatoryQueue +number_of_TBEs=256 +probeToCore=system.cp_cntrl0.probeToCore +recycle_latency=10 +requestFromCore=system.cp_cntrl0.requestFromCore +responseFromCore=system.cp_cntrl0.responseFromCore +responseToCore=system.cp_cntrl0.responseToCore +ruby_system=system.ruby +send_evictions=true +sequencer=system.cp_cntrl0.sequencer +sequencer1=system.cp_cntrl0.sequencer1 +system=system +transitions_per_cycle=32 +triggerQueue=system.cp_cntrl0.triggerQueue +unblockFromCore=system.cp_cntrl0.unblockFromCore +version=0 + +[system.cp_cntrl0.L1D0cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1D0cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.cp_cntrl0.L1D0cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.cp_cntrl0.L1D1cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1D1cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.cp_cntrl0.L1D1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.cp_cntrl0.L1Icache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L1Icache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=256 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.cp_cntrl0.L1Icache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=256 + +[system.cp_cntrl0.L2cache] +type=RubyCache +children=replacement_policy +assoc=2 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.cp_cntrl0.L2cache.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=512 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.cp_cntrl0.L2cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=2 +block_size=64 +eventq_index=0 +size=512 + +[system.cp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.cp_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[3] + +[system.cp_cntrl0.requestFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[2] + +[system.cp_cntrl0.responseFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[3] + +[system.cp_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[4] + +[system.cp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=0 +dcache=system.cp_cntrl0.L1D0cache +dcache_hit_latency=2 +deadlock_threshold=500000 +eventq_index=0 +icache=system.cp_cntrl0.L1Icache +icache_hit_latency=2 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=true +version=0 +slave=system.cpu.cpuInstDataPort[0] + +[system.cp_cntrl0.sequencer1] +type=RubySequencer +clk_domain=system.clk_domain +coreid=1 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system.tcp_cntrl2.coalescer.slave[0] system.tcp_cntrl3.coalescer.slave[0] system.tcp_cntrl4.coalescer.slave[0] system.tcp_cntrl5.coalescer.slave[0] system.tcp_cntrl6.coalescer.slave[0] system.tcp_cntrl7.coalescer.slave[0] +cpuInstDataPort=system.cp_cntrl0.sequencer.slave[0] system.cp_cntrl0.sequencer1.slave[0] +cpuInstPort=system.sqc_cntrl0.sequencer.slave[0] system.sqc_cntrl1.sequencer.slave[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=L3CacheMemory L3triggerQueue directory probeToCore requestFromCores responseFromCores responseFromMemory responseToCore triggerQueue unblockFromCores +CPUonly=false +L3CacheMemory=system.dir_cntrl0.L3CacheMemory +L3triggerQueue=system.dir_cntrl0.L3triggerQueue +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +directory=system.dir_cntrl0.directory +eventq_index=0 +l3_hit_latency=15 +noTCCdir=false +number_of_TBEs=20480 +probeToCore=system.dir_cntrl0.probeToCore +recycle_latency=10 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int_link_buffers31 int_link_buffers32 int_link_buffers33 int_link_buffers34 int_link_buffers35 int_link_buffers36 int_link_buffers37 int_link_buffers38 int_link_buffers39 int_links0 int_links1 +adaptive_routing=false +buffer_size=0 +clk_domain=system.ruby.clk_domain +control_msg_size=8 +endpoint_bandwidth=1000 +eventq_index=0 +ext_links=system.ruby.network.ext_links00 system.ruby.network.ext_links01 system.ruby.network.ext_links02 system.ruby.network.ext_links03 system.ruby.network.ext_links04 system.ruby.network.ext_links05 system.ruby.network.ext_links06 system.ruby.network.ext_links07 system.ruby.network.ext_links08 system.ruby.network.ext_links09 system.ruby.network.ext_links10 system.ruby.network.ext_links11 system.ruby.network.ext_links12 system.ruby.network.ext_links13 +int_link_buffers=system.ruby.network.int_link_buffers00 system.ruby.network.int_link_buffers01 system.ruby.network.int_link_buffers02 system.ruby.network.int_link_buffers03 system.ruby.network.int_link_buffers04 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system.tcp_cntrl1.responseToTCP.slave system.tcp_cntrl2.probeToTCP.slave system.tcp_cntrl2.responseToTCP.slave system.tcp_cntrl3.probeToTCP.slave system.tcp_cntrl3.responseToTCP.slave system.tcp_cntrl4.probeToTCP.slave system.tcp_cntrl4.responseToTCP.slave system.tcp_cntrl5.probeToTCP.slave system.tcp_cntrl5.responseToTCP.slave system.tcp_cntrl6.probeToTCP.slave system.tcp_cntrl6.responseToTCP.slave system.tcp_cntrl7.probeToTCP.slave system.tcp_cntrl7.responseToTCP.slave system.sqc_cntrl0.probeToSQC.slave system.sqc_cntrl0.responseToSQC.slave system.sqc_cntrl1.probeToSQC.slave system.sqc_cntrl1.responseToSQC.slave system.tcc_cntrl0.responseToTCC.slave system.tccdir_cntrl0.requestFromTCP.slave system.tccdir_cntrl0.responseFromTCP.slave system.tccdir_cntrl0.unblockFromTCP.slave system.tccdir_cntrl0.probeFromNB.slave system.tccdir_cntrl0.responseFromNB.slave +slave=system.dir_cntrl0.probeToCore.master system.dir_cntrl0.responseToCore.master system.cp_cntrl0.requestFromCore.master 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+ruby_system=system.ruby +size=32768 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=4 + +[system.sqc_cntrl1.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=32768 + +[system.sqc_cntrl1.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.sqc_cntrl1.probeToSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[23] + +[system.sqc_cntrl1.requestFromSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[32] + +[system.sqc_cntrl1.responseFromSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[33] + +[system.sqc_cntrl1.responseToSQC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[24] + +[system.sqc_cntrl1.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.sqc_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.sqc_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=16 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=false +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=true +version=19 +slave=system.cpu.cpuInstPort[1] + +[system.sqc_cntrl1.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[34] + +[system.sys_port_proxy] +type=RubyPortProxy +clk_domain=system.clk_domain +eventq_index=0 +is_cpu_sequencer=true +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_ruby_tester=false +version=0 +slave=system.system_port + +[system.tcc_cntrl0] +type=TCC_Controller +children=L2cache responseFromTCC responseToTCC w_TCCUnblockToTCCDir w_probeToTCC w_reqToTCC w_reqToTCCDir w_respToTCC w_respToTCCDir +L2cache=system.tcc_cntrl0.L2cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +eventq_index=0 +l2_request_latency=1 +l2_response_latency=16 +number_of_TBEs=2048 +recycle_latency=10 +responseFromTCC=system.tcc_cntrl0.responseFromTCC +responseToTCC=system.tcc_cntrl0.responseToTCC +ruby_system=system.ruby +system=system +transitions_per_cycle=32 +version=0 +w_TCCUnblockToTCCDir=system.tcc_cntrl0.w_TCCUnblockToTCCDir +w_probeToTCC=system.tcc_cntrl0.w_probeToTCC +w_reqToTCC=system.tcc_cntrl0.w_reqToTCC +w_reqToTCCDir=system.tcc_cntrl0.w_reqToTCCDir +w_respToTCC=system.tcc_cntrl0.w_respToTCC +w_respToTCCDir=system.tcc_cntrl0.w_respToTCCDir + +[system.tcc_cntrl0.L2cache] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=8 +dataArrayBanks=256 +eventq_index=0 +is_icache=false +replacement_policy=system.tcc_cntrl0.L2cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=262144.0 +start_index_bit=6 +tagAccessLatency=2 +tagArrayBanks=256 + +[system.tcc_cntrl0.L2cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=262144.0 + +[system.tcc_cntrl0.responseFromTCC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[35] + +[system.tcc_cntrl0.responseToTCC] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[25] + +[system.tcc_cntrl0.w_TCCUnblockToTCCDir] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_probeToTCC] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_reqToTCC] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_reqToTCCDir] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_respToTCC] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tcc_cntrl0.w_respToTCCDir] +type=RubyWireBuffer +eventq_index=0 +ruby_system=system.ruby + +[system.tccdir_cntrl0] +type=TCCdir_Controller +children=directory probeFromNB probeToCore requestFromTCP requestToNB responseFromNB responseFromTCP responseToCore responseToNB triggerQueue unblockFromTCP unblockToNB +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +directory=system.tccdir_cntrl0.directory +directory_latency=6 +eventq_index=0 +issue_latency=120 +number_of_TBEs=1024 +probeFromNB=system.tccdir_cntrl0.probeFromNB +probeToCore=system.tccdir_cntrl0.probeToCore +recycle_latency=10 +requestFromTCP=system.tccdir_cntrl0.requestFromTCP +requestToNB=system.tccdir_cntrl0.requestToNB +responseFromNB=system.tccdir_cntrl0.responseFromNB +responseFromTCP=system.tccdir_cntrl0.responseFromTCP +responseToCore=system.tccdir_cntrl0.responseToCore +responseToNB=system.tccdir_cntrl0.responseToNB +response_latency=5 +ruby_system=system.ruby +system=system +transitions_per_cycle=32 +triggerQueue=system.tccdir_cntrl0.triggerQueue +unblockFromTCP=system.tccdir_cntrl0.unblockFromTCP +unblockToNB=system.tccdir_cntrl0.unblockToNB +version=0 +w_TCCUnblockToTCCDir=system.tcc_cntrl0.w_TCCUnblockToTCCDir +w_probeToTCC=system.tcc_cntrl0.w_probeToTCC +w_reqToTCC=system.tcc_cntrl0.w_reqToTCC +w_reqToTCCDir=system.tcc_cntrl0.w_reqToTCCDir +w_respToTCC=system.tcc_cntrl0.w_respToTCC +w_respToTCCDir=system.tcc_cntrl0.w_respToTCCDir + +[system.tccdir_cntrl0.directory] +type=RubyCache +children=replacement_policy +assoc=16 +block_size=0 +dataAccessLatency=1 +dataArrayBanks=1 +eventq_index=0 +is_icache=false +replacement_policy=system.tccdir_cntrl0.directory.replacement_policy +resourceStalls=false +ruby_system=system.ruby +size=786432 +start_index_bit=6 +tagAccessLatency=1 +tagArrayBanks=1 + +[system.tccdir_cntrl0.directory.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=16 +block_size=64 +eventq_index=0 +size=786432 + +[system.tccdir_cntrl0.probeFromNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[29] + +[system.tccdir_cntrl0.probeToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[36] + +[system.tccdir_cntrl0.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[26] + +[system.tccdir_cntrl0.requestToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[38] + +[system.tccdir_cntrl0.responseFromNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +slave=system.ruby.network.master[30] + +[system.tccdir_cntrl0.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[27] + +[system.tccdir_cntrl0.responseToCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[37] + +[system.tccdir_cntrl0.responseToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[39] + +[system.tccdir_cntrl0.triggerQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false + +[system.tccdir_cntrl0.unblockFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[28] + +[system.tccdir_cntrl0.unblockToNB] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false +master=system.ruby.network.slave[40] + +[system.tcp_cntrl0] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl0.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl0.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl0.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl0.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl0.requestFromTCP +responseFromTCP=system.tcp_cntrl0.responseFromTCP +responseToTCP=system.tcp_cntrl0.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl0.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl0.unblockFromCore +use_seq_not_coal=false +version=0 + +[system.tcp_cntrl0.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl0.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl0.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl0.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2560 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=true +version=2 +slave=system.cpu.cpuDataPort[0] + +[system.tcp_cntrl0.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl0.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[5] + +[system.tcp_cntrl0.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[5] + +[system.tcp_cntrl0.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[6] + +[system.tcp_cntrl0.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[6] + +[system.tcp_cntrl0.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl0.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl0.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=3 + +[system.tcp_cntrl0.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[7] + +[system.tcp_cntrl1] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl1.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl1.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl1.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl1.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl1.requestFromTCP +responseFromTCP=system.tcp_cntrl1.responseFromTCP +responseToTCP=system.tcp_cntrl1.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl1.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl1.unblockFromCore +use_seq_not_coal=false +version=1 + +[system.tcp_cntrl1.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl1.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl1.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl1.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2560 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=true +version=4 +slave=system.cpu.cpuDataPort[1] + +[system.tcp_cntrl1.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl1.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[7] + +[system.tcp_cntrl1.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[8] + +[system.tcp_cntrl1.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[9] + +[system.tcp_cntrl1.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[8] + +[system.tcp_cntrl1.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl1.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl1.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=5 + +[system.tcp_cntrl1.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[10] + +[system.tcp_cntrl2] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl2.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl2.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl2.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl2.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl2.requestFromTCP +responseFromTCP=system.tcp_cntrl2.responseFromTCP +responseToTCP=system.tcp_cntrl2.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl2.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl2.unblockFromCore +use_seq_not_coal=false +version=2 + +[system.tcp_cntrl2.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl2.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl2.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl2.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl2.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl2.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2560 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=true +version=6 +slave=system.cpu.cpuDataPort[2] + +[system.tcp_cntrl2.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl2.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[9] + +[system.tcp_cntrl2.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[11] + +[system.tcp_cntrl2.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[12] + +[system.tcp_cntrl2.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[10] + +[system.tcp_cntrl2.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl2.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl2.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=7 + +[system.tcp_cntrl2.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[13] + +[system.tcp_cntrl3] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl3.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl3.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl3.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl3.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl3.requestFromTCP +responseFromTCP=system.tcp_cntrl3.responseFromTCP +responseToTCP=system.tcp_cntrl3.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl3.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl3.unblockFromCore +use_seq_not_coal=false +version=3 + +[system.tcp_cntrl3.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl3.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl3.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl3.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl3.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl3.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2560 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=true +version=8 +slave=system.cpu.cpuDataPort[3] + +[system.tcp_cntrl3.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl3.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[11] + +[system.tcp_cntrl3.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[14] + +[system.tcp_cntrl3.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[15] + +[system.tcp_cntrl3.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[12] + +[system.tcp_cntrl3.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl3.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl3.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=9 + +[system.tcp_cntrl3.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[16] + +[system.tcp_cntrl4] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl4.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl4.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl4.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl4.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl4.requestFromTCP +responseFromTCP=system.tcp_cntrl4.responseFromTCP +responseToTCP=system.tcp_cntrl4.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl4.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl4.unblockFromCore +use_seq_not_coal=false +version=4 + +[system.tcp_cntrl4.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl4.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl4.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl4.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl4.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl4.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2560 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=true +version=10 +slave=system.cpu.cpuDataPort[4] + +[system.tcp_cntrl4.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl4.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[13] + +[system.tcp_cntrl4.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[17] + +[system.tcp_cntrl4.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[18] + +[system.tcp_cntrl4.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[14] + +[system.tcp_cntrl4.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl4.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl4.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=11 + +[system.tcp_cntrl4.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[19] + +[system.tcp_cntrl5] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl5.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl5.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl5.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl5.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl5.requestFromTCP +responseFromTCP=system.tcp_cntrl5.responseFromTCP +responseToTCP=system.tcp_cntrl5.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl5.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl5.unblockFromCore +use_seq_not_coal=false +version=5 + +[system.tcp_cntrl5.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl5.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl5.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl5.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl5.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl5.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2560 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=true +version=12 +slave=system.cpu.cpuDataPort[5] + +[system.tcp_cntrl5.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl5.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[15] + +[system.tcp_cntrl5.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[20] + +[system.tcp_cntrl5.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[21] + +[system.tcp_cntrl5.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[16] + +[system.tcp_cntrl5.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl5.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl5.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=13 + +[system.tcp_cntrl5.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[22] + +[system.tcp_cntrl6] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl6.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl6.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl6.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl6.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl6.requestFromTCP +responseFromTCP=system.tcp_cntrl6.responseFromTCP +responseToTCP=system.tcp_cntrl6.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl6.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl6.unblockFromCore +use_seq_not_coal=false +version=6 + +[system.tcp_cntrl6.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl6.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl6.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl6.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl6.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl6.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2560 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=true +version=14 +slave=system.cpu.cpuDataPort[6] + +[system.tcp_cntrl6.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl6.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[17] + +[system.tcp_cntrl6.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[23] + +[system.tcp_cntrl6.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[24] + +[system.tcp_cntrl6.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[18] + +[system.tcp_cntrl6.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl6.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl6.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=15 + +[system.tcp_cntrl6.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[25] + +[system.tcp_cntrl7] +type=TCP_Controller +children=L1cache coalescer mandatoryQueue probeToTCP requestFromTCP responseFromTCP responseToTCP sequencer unblockFromCore +L1cache=system.tcp_cntrl7.L1cache +TCC_select_num_bits=0 +buffer_size=0 +clk_domain=system.clk_domain +cluster_id=0 +coalescer=system.tcp_cntrl7.coalescer +eventq_index=0 +issue_latency=40 +l2_hit_latency=18 +mandatoryQueue=system.tcp_cntrl7.mandatoryQueue +number_of_TBEs=2560 +probeToTCP=system.tcp_cntrl7.probeToTCP +recycle_latency=10 +requestFromTCP=system.tcp_cntrl7.requestFromTCP +responseFromTCP=system.tcp_cntrl7.responseFromTCP +responseToTCP=system.tcp_cntrl7.responseToTCP +ruby_system=system.ruby +sequencer=system.tcp_cntrl7.sequencer +system=system +transitions_per_cycle=32 +unblockFromCore=system.tcp_cntrl7.unblockFromCore +use_seq_not_coal=false +version=7 + +[system.tcp_cntrl7.L1cache] +type=RubyCache +children=replacement_policy +assoc=8 +block_size=0 +dataAccessLatency=4 +dataArrayBanks=16 +eventq_index=0 +is_icache=false +replacement_policy=system.tcp_cntrl7.L1cache.replacement_policy +resourceStalls=true +ruby_system=system.ruby +size=16384 +start_index_bit=6 +tagAccessLatency=4 +tagArrayBanks=4 + +[system.tcp_cntrl7.L1cache.replacement_policy] +type=PseudoLRUReplacementPolicy +assoc=8 +block_size=64 +eventq_index=0 +size=16384 + +[system.tcp_cntrl7.coalescer] +type=RubyGPUCoalescer +assume_rfo=true +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl7.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl7.L1cache +icache_hit_latency=1 +is_cpu_sequencer=false +max_outstanding_requests=2560 +no_retry_on_stall=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=false +system=system +using_network_tester=false +using_ruby_tester=true +version=16 +slave=system.cpu.cpuDataPort[7] + +[system.tcp_cntrl7.mandatoryQueue] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=false +randomization=false + +[system.tcp_cntrl7.probeToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[19] + +[system.tcp_cntrl7.requestFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[26] + +[system.tcp_cntrl7.responseFromTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[27] + +[system.tcp_cntrl7.responseToTCP] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +slave=system.ruby.network.master[20] + +[system.tcp_cntrl7.sequencer] +type=RubySequencer +clk_domain=system.clk_domain +coreid=99 +dcache=system.tcp_cntrl7.L1cache +dcache_hit_latency=1 +deadlock_threshold=500000 +eventq_index=0 +icache=system.tcp_cntrl7.L1cache +icache_hit_latency=1 +is_cpu_sequencer=true +max_outstanding_requests=16 +no_retry_on_stall=false +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=17 + +[system.tcp_cntrl7.unblockFromCore] +type=MessageBuffer +buffer_size=0 +eventq_index=0 +ordered=true +randomization=false +master=system.ruby.network.slave[28] + +[system.voltage_domain] +type=VoltageDomain +eventq_index=0 +voltage=1.000000 + diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr new file mode 100755 index 000000000..13060c953 --- /dev/null +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simerr @@ -0,0 +1,10 @@ +warn: system.ruby.network adopting orphan SimObject param 'int_links' +warn: system.ruby.network adopting orphan SimObject param 'ext_links' +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: rounding error > tolerance + 1.250000 rounded to 1 +warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) +warn: Replacement policy updates recently became the responsibility of SLICC state machines. Make sure to setMRU() near callbacks in .sm files! diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout new file mode 100755 index 000000000..62d7346d7 --- /dev/null +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/simout @@ -0,0 +1,11 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled Jan 19 2016 13:28:55 +gem5 started Jan 19 2016 13:29:16 +gem5 executing on zizzer, pid 48851 +command line: build/HSAIL_X86/gem5.opt -d build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO -re /z/atgutier/gem5/gem5-commit/tests/run.py build/HSAIL_X86/tests/opt/quick/se/60.gpu-randomtest/x86/linux/gpu-randomtest-ruby-GPU_RfO + +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Exiting @ tick 14181 because Ruby Tester completed diff --git a/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt new file mode 100644 index 000000000..75065fd02 --- /dev/null +++ b/tests/quick/se/60.gpu-randomtest/ref/x86/linux/gpu-randomtest-ruby-GPU_RfO/stats.txt @@ -0,0 +1,1072 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000014 # Number of seconds simulated +sim_ticks 14181 # Number of ticks simulated +final_tick 14181 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_tick_rate 88786 # Simulator tick rate (ticks/s) +host_mem_usage 463996 # Number of bytes of host memory used +host_seconds 0.16 # Real time elapsed on the host +system.voltage_domain.voltage 1 # Voltage in Volts +system.clk_domain.clock 1 # Clock period in ticks +system.mem_ctrls.bytes_read::dir_cntrl0 16576 # Number of bytes read from this memory +system.mem_ctrls.bytes_read::total 16576 # Number of bytes read from this memory +system.mem_ctrls.bytes_written::dir_cntrl0 576 # Number of bytes written to this memory +system.mem_ctrls.bytes_written::total 576 # Number of bytes written to this memory +system.mem_ctrls.num_reads::dir_cntrl0 259 # Number of read requests responded to by this memory +system.mem_ctrls.num_reads::total 259 # Number of read requests responded to by this memory +system.mem_ctrls.num_writes::dir_cntrl0 9 # Number of write requests responded to by this memory +system.mem_ctrls.num_writes::total 9 # Number of write requests responded to by this memory +system.mem_ctrls.bw_read::dir_cntrl0 1168887949 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_read::total 1168887949 # Total read bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::dir_cntrl0 40617728 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_write::total 40617728 # Write bandwidth from this memory (bytes/s) +system.mem_ctrls.bw_total::dir_cntrl0 1209505677 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.bw_total::total 1209505677 # Total bandwidth to/from this memory (bytes/s) +system.mem_ctrls.readReqs 259 # Number of read requests accepted +system.mem_ctrls.writeReqs 9 # Number of write requests accepted +system.mem_ctrls.readBursts 259 # Number of DRAM read bursts, including those serviced by the write queue +system.mem_ctrls.writeBursts 9 # Number of DRAM write bursts, including those merged in the write queue +system.mem_ctrls.bytesReadDRAM 15936 # Total number of bytes read from DRAM +system.mem_ctrls.bytesReadWrQ 640 # Total number of bytes read from write queue +system.mem_ctrls.bytesWritten 0 # Total number of bytes written to DRAM +system.mem_ctrls.bytesReadSys 16576 # Total read bytes from the system interface side +system.mem_ctrls.bytesWrittenSys 576 # Total written bytes from the system interface side +system.mem_ctrls.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue +system.mem_ctrls.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one +system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write +system.mem_ctrls.perBankRdBursts::0 100 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::1 71 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::2 66 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::3 12 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankRdBursts::15 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::0 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::4 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::5 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::6 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::7 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::8 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::9 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::10 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::11 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::12 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::13 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::14 0 # Per bank write bursts +system.mem_ctrls.perBankWrBursts::15 0 # Per bank write bursts +system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry +system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry +system.mem_ctrls.totGap 13941 # Total gap between requests +system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) +system.mem_ctrls.readPktSize::6 259 # Read request sizes (log2) +system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) +system.mem_ctrls.writePktSize::6 9 # Write request sizes (log2) +system.mem_ctrls.rdQLenPdf::0 214 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::1 27 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::2 7 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::3 1 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::9 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::10 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::11 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::12 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::13 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::14 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::15 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::16 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::17 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::18 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::19 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::20 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::21 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::22 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::23 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::24 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::25 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::26 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::27 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::28 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::29 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::30 0 # What read queue length does an incoming req see +system.mem_ctrls.rdQLenPdf::31 0 # What read queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::0 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::1 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::2 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::3 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::4 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::5 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::6 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::21 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::22 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::23 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::24 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::25 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::26 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::27 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::28 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::29 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::30 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::31 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::32 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::42 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::43 0 # What write queue length does an incoming req see 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an incoming req see +system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see +system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see +system.mem_ctrls.bytesPerActivate::samples 15 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::mean 913.066667 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::gmean 883.543279 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::stdev 210.139908 # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::512-639 3 20.00% 20.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::896-1023 1 6.67% 26.67% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::1024-1151 11 73.33% 100.00% # Bytes accessed per row activation +system.mem_ctrls.bytesPerActivate::total 15 # Bytes accessed per row activation +system.mem_ctrls.totQLat 973 # Total ticks spent queuing +system.mem_ctrls.totMemAccLat 5704 # Total ticks spent from burst creation until serviced by the DRAM +system.mem_ctrls.totBusLat 1245 # Total ticks spent in databus transfers +system.mem_ctrls.avgQLat 3.91 # Average queueing delay per DRAM burst +system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst +system.mem_ctrls.avgMemAccLat 22.91 # Average memory access latency per DRAM burst +system.mem_ctrls.avgRdBW 1123.76 # Average DRAM read bandwidth in MiByte/s +system.mem_ctrls.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s +system.mem_ctrls.avgRdBWSys 1168.89 # Average system read bandwidth in MiByte/s +system.mem_ctrls.avgWrBWSys 40.62 # Average system write bandwidth in MiByte/s +system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s +system.mem_ctrls.busUtil 8.78 # Data bus utilization in percentage +system.mem_ctrls.busUtilRead 8.78 # Data bus utilization in percentage for reads +system.mem_ctrls.busUtilWrite 0.00 # Data bus utilization in percentage for writes +system.mem_ctrls.avgRdQLen 1.17 # Average read queue length when enqueuing +system.mem_ctrls.avgWrQLen 2.63 # Average write queue length when enqueuing +system.mem_ctrls.readRowHits 230 # Number of row buffer hits during reads +system.mem_ctrls.writeRowHits 0 # Number of row buffer hits during writes +system.mem_ctrls.readRowHitRate 92.37 # Row buffer hit rate for reads +system.mem_ctrls.writeRowHitRate 0.00 # Row buffer hit rate for writes +system.mem_ctrls.avgGap 52.02 # Average gap between requests +system.mem_ctrls.pageHitRate 89.15 # Row buffer hit rate, read and write combined +system.mem_ctrls_0.actEnergy 83160 # Energy for activate commands per rank (pJ) +system.mem_ctrls_0.preEnergy 46200 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_0.readEnergy 1872000 # Energy for read commands per rank (pJ) +system.mem_ctrls_0.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_0.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_0.actBackEnergy 5437116 # Energy for active background per rank (pJ) +system.mem_ctrls_0.preBackEnergy 58200 # Energy for precharge background per rank (pJ) +system.mem_ctrls_0.totalEnergy 8005236 # Total energy per rank (pJ) +system.mem_ctrls_0.averagePower 994.933632 # Core power per rank (mW) +system.mem_ctrls_0.memoryStateTime::IDLE 83 # Time in different power states +system.mem_ctrls_0.memoryStateTime::REF 260 # Time in different power states +system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT 7717 # Time in different power states +system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states +system.mem_ctrls_1.actEnergy 0 # Energy for activate commands per rank (pJ) +system.mem_ctrls_1.preEnergy 0 # Energy for precharge commands per rank (pJ) +system.mem_ctrls_1.readEnergy 0 # Energy for read commands per rank (pJ) +system.mem_ctrls_1.writeEnergy 0 # Energy for write commands per rank (pJ) +system.mem_ctrls_1.refreshEnergy 508560 # Energy for refresh commands per rank (pJ) +system.mem_ctrls_1.actBackEnergy 168264 # Energy for active background per rank (pJ) +system.mem_ctrls_1.preBackEnergy 4671600 # Energy for precharge background per rank (pJ) +system.mem_ctrls_1.totalEnergy 5348424 # Total energy per rank (pJ) +system.mem_ctrls_1.averagePower 665.889442 # Core power per rank (mW) +system.mem_ctrls_1.memoryStateTime::IDLE 7786 # Time in different power states +system.mem_ctrls_1.memoryStateTime::REF 260 # Time in different power states +system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT 0 # Time in different power states +system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states +system.ruby.clk_domain.clock 1 # Clock period in ticks +system.ruby.outstanding_req_hist::bucket_size 2 +system.ruby.outstanding_req_hist::max_bucket 19 +system.ruby.outstanding_req_hist::samples 63 +system.ruby.outstanding_req_hist::mean 12.920635 +system.ruby.outstanding_req_hist::gmean 11.694862 +system.ruby.outstanding_req_hist::stdev 4.228557 +system.ruby.outstanding_req_hist | 1 1.59% 1.59% | 2 3.17% 4.76% | 2 3.17% 7.94% | 5 7.94% 15.87% | 4 6.35% 22.22% | 3 4.76% 26.98% | 5 7.94% 34.92% | 14 22.22% 57.14% | 27 42.86% 100.00% | 0 0.00% 100.00% +system.ruby.outstanding_req_hist::total 63 +system.ruby.latency_hist::bucket_size 1024 +system.ruby.latency_hist::max_bucket 10239 +system.ruby.latency_hist::samples 48 +system.ruby.latency_hist::mean 3351.354167 +system.ruby.latency_hist::gmean 1865.352879 +system.ruby.latency_hist::stdev 1934.275107 +system.ruby.latency_hist | 11 22.92% 22.92% | 3 6.25% 29.17% | 3 6.25% 35.42% | 7 14.58% 50.00% | 18 37.50% 87.50% | 6 12.50% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.latency_hist::total 48 +system.ruby.hit_latency_hist::bucket_size 1024 +system.ruby.hit_latency_hist::max_bucket 10239 +system.ruby.hit_latency_hist::samples 42 +system.ruby.hit_latency_hist::mean 3684.428571 +system.ruby.hit_latency_hist::gmean 2778.454716 +system.ruby.hit_latency_hist::stdev 1783.107224 +system.ruby.hit_latency_hist | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.hit_latency_hist::total 42 +system.ruby.miss_latency_hist::bucket_size 512 +system.ruby.miss_latency_hist::max_bucket 5119 +system.ruby.miss_latency_hist::samples 6 +system.ruby.miss_latency_hist::mean 1019.833333 +system.ruby.miss_latency_hist::gmean 114.673945 +system.ruby.miss_latency_hist::stdev 1281.644790 +system.ruby.miss_latency_hist | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.miss_latency_hist::total 6 +system.ruby.L1Cache.incomplete_times 6 +system.cp_cntrl0.L1D0cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1D0cache.demand_misses 45 # Number of cache demand misses +system.cp_cntrl0.L1D0cache.demand_accesses 45 # Number of cache demand accesses +system.cp_cntrl0.L1D0cache.num_data_array_writes 43 # number of data array writes +system.cp_cntrl0.L1D0cache.num_tag_array_reads 154 # number of tag array reads +system.cp_cntrl0.L1D0cache.num_tag_array_writes 41 # number of tag array writes +system.cp_cntrl0.L1D1cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1D1cache.demand_misses 43 # Number of cache demand misses +system.cp_cntrl0.L1D1cache.demand_accesses 43 # Number of cache demand accesses +system.cp_cntrl0.L1D1cache.num_data_array_writes 41 # number of data array writes +system.cp_cntrl0.L1D1cache.num_tag_array_reads 73 # number of tag array reads +system.cp_cntrl0.L1D1cache.num_tag_array_writes 41 # number of tag array writes +system.cp_cntrl0.L1Icache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L1Icache.demand_misses 3 # Number of cache demand misses +system.cp_cntrl0.L1Icache.demand_accesses 3 # Number of cache demand accesses +system.cp_cntrl0.L1Icache.num_tag_array_reads 3 # number of tag array reads +system.cp_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.cp_cntrl0.L2cache.demand_misses 91 # Number of cache demand misses +system.cp_cntrl0.L2cache.demand_accesses 91 # Number of cache demand accesses +system.cp_cntrl0.L2cache.num_data_array_reads 81 # number of data array reads +system.cp_cntrl0.L2cache.num_data_array_writes 84 # number of data array writes +system.cp_cntrl0.L2cache.num_tag_array_reads 380 # number of tag array reads +system.cp_cntrl0.L2cache.num_tag_array_writes 371 # number of tag array writes +system.cp_cntrl0.sequencer.store_waiting_on_load 2 # Number of times a store aliased with a pending load +system.cp_cntrl0.sequencer.store_waiting_on_store 3 # Number of times a store aliased with a pending store +system.cp_cntrl0.sequencer1.store_waiting_on_load 1 # Number of times a store aliased with a pending load +system.cp_cntrl0.sequencer1.store_waiting_on_store 4 # Number of times a store aliased with a pending store +system.cp_cntrl0.fully_busy_cycles 2 # cycles for which number of transistions == max transitions +system.dir_cntrl0.L3CacheMemory.demand_hits 0 # Number of cache demand hits +system.dir_cntrl0.L3CacheMemory.demand_misses 0 # Number of cache demand misses +system.dir_cntrl0.L3CacheMemory.demand_accesses 0 # Number of cache demand accesses +system.dir_cntrl0.L3CacheMemory.num_data_array_writes 374 # number of data array writes +system.dir_cntrl0.L3CacheMemory.num_tag_array_reads 378 # number of tag array reads +system.dir_cntrl0.L3CacheMemory.num_tag_array_writes 378 # number of tag array writes +system.dir_cntrl0.L3CacheMemory.num_tag_array_stalls 10169 # number of stalls caused by tag array +system.dir_cntrl0.L3CacheMemory.num_data_array_stalls 5502 # number of stalls caused by data array +system.ruby.network.ext_links00.int_node.percent_links_utilized 0.199210 +system.ruby.network.ext_links00.int_node.msg_count.Control::0 308 +system.ruby.network.ext_links00.int_node.msg_count.Request_Control::0 385 +system.ruby.network.ext_links00.int_node.msg_count.Response_Data::2 393 +system.ruby.network.ext_links00.int_node.msg_count.Response_Control::2 227 +system.ruby.network.ext_links00.int_node.msg_count.Writeback_Data::2 66 +system.ruby.network.ext_links00.int_node.msg_count.Writeback_Control::2 70 +system.ruby.network.ext_links00.int_node.msg_count.Unblock_Control::4 303 +system.ruby.network.ext_links00.int_node.msg_bytes.Control::0 2464 +system.ruby.network.ext_links00.int_node.msg_bytes.Request_Control::0 3080 +system.ruby.network.ext_links00.int_node.msg_bytes.Response_Data::2 28296 +system.ruby.network.ext_links00.int_node.msg_bytes.Response_Control::2 1816 +system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Data::2 4752 +system.ruby.network.ext_links00.int_node.msg_bytes.Writeback_Control::2 560 +system.ruby.network.ext_links00.int_node.msg_bytes.Unblock_Control::4 2424 +system.ruby.network.ext_links01.int_node.percent_links_utilized 0.120981 +system.ruby.network.ext_links01.int_node.msg_count.Control::0 227 +system.ruby.network.ext_links01.int_node.msg_count.Request_Control::0 153 +system.ruby.network.ext_links01.int_node.msg_count.Response_Data::2 95 +system.ruby.network.ext_links01.int_node.msg_count.Response_Control::2 217 +system.ruby.network.ext_links01.int_node.msg_count.Writeback_Data::2 66 +system.ruby.network.ext_links01.int_node.msg_count.Writeback_Control::2 70 +system.ruby.network.ext_links01.int_node.msg_count.Unblock_Control::4 80 +system.ruby.network.ext_links01.int_node.msg_bytes.Control::0 1816 +system.ruby.network.ext_links01.int_node.msg_bytes.Request_Control::0 1224 +system.ruby.network.ext_links01.int_node.msg_bytes.Response_Data::2 6840 +system.ruby.network.ext_links01.int_node.msg_bytes.Response_Control::2 1736 +system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Data::2 4752 +system.ruby.network.ext_links01.int_node.msg_bytes.Writeback_Control::2 560 +system.ruby.network.ext_links01.int_node.msg_bytes.Unblock_Control::4 640 +system.tcp_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl0.L1cache.num_data_array_reads 14 # number of data array reads +system.tcp_cntrl0.L1cache.num_data_array_writes 116 # number of data array writes +system.tcp_cntrl0.L1cache.num_tag_array_reads 314 # number of tag array reads +system.tcp_cntrl0.L1cache.num_tag_array_writes 305 # number of tag array writes +system.tcp_cntrl0.L1cache.num_tag_array_stalls 38 # number of stalls caused by tag array +system.tcp_cntrl0.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl0.coalescer.gpu_tcp_ld_transfers 5 # TCP to TCP load transfers +system.tcp_cntrl0.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl0.coalescer.gpu_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl0.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP +system.tcp_cntrl0.coalescer.gpu_tcp_st_transfers 79 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl0.coalescer.gpu_st_misses 21 # stores that miss in the GPU +system.tcp_cntrl0.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl0.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl0.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl0.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl0.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl0.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl0.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl0.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.ruby.network.ext_links02.int_node.percent_links_utilized 0.173894 +system.ruby.network.ext_links02.int_node.msg_count.Control::0 81 +system.ruby.network.ext_links02.int_node.msg_count.Control::1 814 +system.ruby.network.ext_links02.int_node.msg_count.Request_Control::0 232 +system.ruby.network.ext_links02.int_node.msg_count.Request_Control::1 846 +system.ruby.network.ext_links02.int_node.msg_count.Response_Data::2 298 +system.ruby.network.ext_links02.int_node.msg_count.Response_Data::3 1644 +system.ruby.network.ext_links02.int_node.msg_count.Response_Control::2 10 +system.ruby.network.ext_links02.int_node.msg_count.Response_Control::3 2 +system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::4 223 +system.ruby.network.ext_links02.int_node.msg_count.Unblock_Control::5 831 +system.ruby.network.ext_links02.int_node.msg_bytes.Control::0 648 +system.ruby.network.ext_links02.int_node.msg_bytes.Control::1 6512 +system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::0 1856 +system.ruby.network.ext_links02.int_node.msg_bytes.Request_Control::1 6768 +system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::2 21456 +system.ruby.network.ext_links02.int_node.msg_bytes.Response_Data::3 118368 +system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::2 80 +system.ruby.network.ext_links02.int_node.msg_bytes.Response_Control::3 16 +system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::4 1784 +system.ruby.network.ext_links02.int_node.msg_bytes.Unblock_Control::5 6648 +system.tcp_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl1.L1cache.num_data_array_reads 10 # number of data array reads +system.tcp_cntrl1.L1cache.num_data_array_writes 108 # number of data array writes +system.tcp_cntrl1.L1cache.num_tag_array_reads 300 # number of tag array reads +system.tcp_cntrl1.L1cache.num_tag_array_writes 289 # number of tag array writes +system.tcp_cntrl1.L1cache.num_tag_array_stalls 44 # number of stalls caused by tag array +system.tcp_cntrl1.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP +system.tcp_cntrl1.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers +system.tcp_cntrl1.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl1.coalescer.gpu_ld_misses 1 # loads that miss in the GPU +system.tcp_cntrl1.coalescer.gpu_tcp_st_hits 9 # stores that hit in the TCP +system.tcp_cntrl1.coalescer.gpu_tcp_st_transfers 74 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl1.coalescer.gpu_st_misses 20 # stores that miss in the GPU +system.tcp_cntrl1.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl1.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl1.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl1.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl1.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl1.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl1.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl1.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl2.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl2.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl2.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl2.L1cache.num_data_array_reads 19 # number of data array reads +system.tcp_cntrl2.L1cache.num_data_array_writes 108 # number of data array writes +system.tcp_cntrl2.L1cache.num_tag_array_reads 302 # number of tag array reads +system.tcp_cntrl2.L1cache.num_tag_array_writes 292 # number of tag array writes +system.tcp_cntrl2.L1cache.num_tag_array_stalls 36 # number of stalls caused by tag array +system.tcp_cntrl2.L1cache.num_data_array_stalls 3 # number of stalls caused by data array +system.tcp_cntrl2.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP +system.tcp_cntrl2.coalescer.gpu_tcp_ld_transfers 9 # TCP to TCP load transfers +system.tcp_cntrl2.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl2.coalescer.gpu_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl2.coalescer.gpu_tcp_st_hits 7 # stores that hit in the TCP +system.tcp_cntrl2.coalescer.gpu_tcp_st_transfers 72 # TCP to TCP store transfers +system.tcp_cntrl2.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl2.coalescer.gpu_st_misses 18 # stores that miss in the GPU +system.tcp_cntrl2.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl2.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl2.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl2.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl2.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl2.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl2.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl2.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl3.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl3.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl3.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl3.L1cache.num_data_array_reads 7 # number of data array reads +system.tcp_cntrl3.L1cache.num_data_array_writes 104 # number of data array writes +system.tcp_cntrl3.L1cache.num_tag_array_reads 272 # number of tag array reads +system.tcp_cntrl3.L1cache.num_tag_array_writes 262 # number of tag array writes +system.tcp_cntrl3.L1cache.num_tag_array_stalls 16 # number of stalls caused by tag array +system.tcp_cntrl3.L1cache.num_data_array_stalls 3 # number of stalls caused by data array +system.tcp_cntrl3.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl3.coalescer.gpu_tcp_ld_transfers 13 # TCP to TCP load transfers +system.tcp_cntrl3.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl3.coalescer.gpu_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl3.coalescer.gpu_tcp_st_hits 10 # stores that hit in the TCP +system.tcp_cntrl3.coalescer.gpu_tcp_st_transfers 63 # TCP to TCP store transfers +system.tcp_cntrl3.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl3.coalescer.gpu_st_misses 18 # stores that miss in the GPU +system.tcp_cntrl3.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl3.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl3.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl3.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl3.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl3.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl3.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl3.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl4.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl4.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl4.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl4.L1cache.num_data_array_reads 14 # number of data array reads +system.tcp_cntrl4.L1cache.num_data_array_writes 115 # number of data array writes +system.tcp_cntrl4.L1cache.num_tag_array_reads 317 # number of tag array reads +system.tcp_cntrl4.L1cache.num_tag_array_writes 309 # number of tag array writes +system.tcp_cntrl4.L1cache.num_tag_array_stalls 29 # number of stalls caused by tag array +system.tcp_cntrl4.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl4.coalescer.gpu_tcp_ld_transfers 4 # TCP to TCP load transfers +system.tcp_cntrl4.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl4.coalescer.gpu_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl4.coalescer.gpu_tcp_st_hits 6 # stores that hit in the TCP +system.tcp_cntrl4.coalescer.gpu_tcp_st_transfers 76 # TCP to TCP store transfers +system.tcp_cntrl4.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl4.coalescer.gpu_st_misses 26 # stores that miss in the GPU +system.tcp_cntrl4.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl4.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl4.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl4.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl4.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl4.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl4.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl4.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl5.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl5.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl5.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl5.L1cache.num_data_array_reads 10 # number of data array reads +system.tcp_cntrl5.L1cache.num_data_array_writes 107 # number of data array writes +system.tcp_cntrl5.L1cache.num_tag_array_reads 295 # number of tag array reads +system.tcp_cntrl5.L1cache.num_tag_array_writes 287 # number of tag array writes +system.tcp_cntrl5.L1cache.num_tag_array_stalls 31 # number of stalls caused by tag array +system.tcp_cntrl5.coalescer.gpu_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl5.coalescer.gpu_tcp_ld_transfers 6 # TCP to TCP load transfers +system.tcp_cntrl5.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl5.coalescer.gpu_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl5.coalescer.gpu_tcp_st_hits 8 # stores that hit in the TCP +system.tcp_cntrl5.coalescer.gpu_tcp_st_transfers 69 # TCP to TCP store transfers +system.tcp_cntrl5.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl5.coalescer.gpu_st_misses 23 # stores that miss in the GPU +system.tcp_cntrl5.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl5.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl5.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl5.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl5.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl5.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl5.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl5.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl6.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl6.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl6.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl6.L1cache.num_data_array_reads 13 # number of data array reads +system.tcp_cntrl6.L1cache.num_data_array_writes 123 # number of data array writes +system.tcp_cntrl6.L1cache.num_tag_array_reads 342 # number of tag array reads +system.tcp_cntrl6.L1cache.num_tag_array_writes 335 # number of tag array writes +system.tcp_cntrl6.L1cache.num_tag_array_stalls 49 # number of stalls caused by tag array +system.tcp_cntrl6.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP +system.tcp_cntrl6.coalescer.gpu_tcp_ld_transfers 11 # TCP to TCP load transfers +system.tcp_cntrl6.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl6.coalescer.gpu_ld_misses 1 # loads that miss in the GPU +system.tcp_cntrl6.coalescer.gpu_tcp_st_hits 5 # stores that hit in the TCP +system.tcp_cntrl6.coalescer.gpu_tcp_st_transfers 86 # TCP to TCP store transfers +system.tcp_cntrl6.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl6.coalescer.gpu_st_misses 19 # stores that miss in the GPU +system.tcp_cntrl6.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl6.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl6.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl6.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl6.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl6.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl6.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl6.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.tcp_cntrl7.L1cache.demand_hits 0 # Number of cache demand hits +system.tcp_cntrl7.L1cache.demand_misses 0 # Number of cache demand misses +system.tcp_cntrl7.L1cache.demand_accesses 0 # Number of cache demand accesses +system.tcp_cntrl7.L1cache.num_data_array_reads 10 # number of data array reads +system.tcp_cntrl7.L1cache.num_data_array_writes 97 # number of data array writes +system.tcp_cntrl7.L1cache.num_tag_array_reads 263 # number of tag array reads +system.tcp_cntrl7.L1cache.num_tag_array_writes 256 # number of tag array writes +system.tcp_cntrl7.L1cache.num_tag_array_stalls 11 # number of stalls caused by tag array +system.tcp_cntrl7.coalescer.gpu_tcp_ld_hits 1 # loads that hit in the TCP +system.tcp_cntrl7.coalescer.gpu_tcp_ld_transfers 10 # TCP to TCP load transfers +system.tcp_cntrl7.coalescer.gpu_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl7.coalescer.gpu_ld_misses 1 # loads that miss in the GPU +system.tcp_cntrl7.coalescer.gpu_tcp_st_hits 6 # stores that hit in the TCP +system.tcp_cntrl7.coalescer.gpu_tcp_st_transfers 63 # TCP to TCP store transfers +system.tcp_cntrl7.coalescer.gpu_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl7.coalescer.gpu_st_misses 16 # stores that miss in the GPU +system.tcp_cntrl7.coalescer.cp_tcp_ld_hits 0 # loads that hit in the TCP +system.tcp_cntrl7.coalescer.cp_tcp_ld_transfers 0 # TCP to TCP load transfers +system.tcp_cntrl7.coalescer.cp_tcc_ld_hits 0 # loads that hit in the TCC +system.tcp_cntrl7.coalescer.cp_ld_misses 0 # loads that miss in the GPU +system.tcp_cntrl7.coalescer.cp_tcp_st_hits 0 # stores that hit in the TCP +system.tcp_cntrl7.coalescer.cp_tcp_st_transfers 0 # TCP to TCP store transfers +system.tcp_cntrl7.coalescer.cp_tcc_st_hits 0 # stores that hit in the TCC +system.tcp_cntrl7.coalescer.cp_st_misses 0 # stores that miss in the GPU +system.sqc_cntrl0.L1cache.demand_hits 0 # Number of cache demand hits +system.sqc_cntrl0.L1cache.demand_misses 0 # Number of cache demand misses +system.sqc_cntrl0.L1cache.demand_accesses 0 # Number of cache demand accesses +system.sqc_cntrl0.L1cache.num_data_array_reads 12 # number of data array reads +system.sqc_cntrl0.L1cache.num_data_array_writes 12 # number of data array writes +system.sqc_cntrl0.L1cache.num_tag_array_reads 22 # number of tag array reads +system.sqc_cntrl0.L1cache.num_tag_array_writes 22 # number of tag array writes +system.sqc_cntrl1.L1cache.demand_hits 0 # Number of cache demand hits +system.sqc_cntrl1.L1cache.demand_misses 0 # Number of cache demand misses +system.sqc_cntrl1.L1cache.demand_accesses 0 # Number of cache demand accesses +system.sqc_cntrl1.L1cache.num_data_array_reads 15 # number of data array reads +system.sqc_cntrl1.L1cache.num_data_array_writes 15 # number of data array writes +system.sqc_cntrl1.L1cache.num_tag_array_reads 29 # number of tag array reads +system.sqc_cntrl1.L1cache.num_tag_array_writes 29 # number of tag array writes +system.tcc_cntrl0.L2cache.demand_hits 0 # Number of cache demand hits +system.tcc_cntrl0.L2cache.demand_misses 0 # Number of cache demand misses +system.tcc_cntrl0.L2cache.demand_accesses 0 # Number of cache demand accesses +system.tccdir_cntrl0.directory.demand_hits 0 # Number of cache demand hits +system.tccdir_cntrl0.directory.demand_misses 0 # Number of cache demand misses +system.tccdir_cntrl0.directory.demand_accesses 0 # Number of cache demand accesses +system.tccdir_cntrl0.directory.num_tag_array_reads 917 # number of tag array reads +system.tccdir_cntrl0.directory.num_tag_array_writes 902 # number of tag array writes +system.ruby.network.msg_count.Control 1430 +system.ruby.network.msg_count.Request_Control 1616 +system.ruby.network.msg_count.Response_Data 2430 +system.ruby.network.msg_count.Response_Control 456 +system.ruby.network.msg_count.Writeback_Data 132 +system.ruby.network.msg_count.Writeback_Control 140 +system.ruby.network.msg_count.Unblock_Control 1437 +system.ruby.network.msg_byte.Control 11440 +system.ruby.network.msg_byte.Request_Control 12928 +system.ruby.network.msg_byte.Response_Data 174960 +system.ruby.network.msg_byte.Response_Control 3648 +system.ruby.network.msg_byte.Writeback_Data 9504 +system.ruby.network.msg_byte.Writeback_Control 1120 +system.ruby.network.msg_byte.Unblock_Control 11496 +system.ruby.network.ext_links00.int_node.throttle0.link_utilization 0.250555 +system.ruby.network.ext_links00.int_node.throttle0.msg_count.Request_Control::0 385 +system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Data::2 85 +system.ruby.network.ext_links00.int_node.throttle0.msg_count.Response_Control::2 227 +system.ruby.network.ext_links00.int_node.throttle0.msg_count.Writeback_Data::2 66 +system.ruby.network.ext_links00.int_node.throttle0.msg_count.Unblock_Control::4 303 +system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Request_Control::0 3080 +system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Data::2 6120 +system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Response_Control::2 1816 +system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Writeback_Data::2 4752 +system.ruby.network.ext_links00.int_node.throttle0.msg_bytes.Unblock_Control::4 2424 +system.ruby.network.ext_links00.int_node.throttle1.link_utilization 0.113047 +system.ruby.network.ext_links00.int_node.throttle1.msg_count.Control::0 227 +system.ruby.network.ext_links00.int_node.throttle1.msg_count.Response_Data::2 81 +system.ruby.network.ext_links00.int_node.throttle1.msg_count.Writeback_Control::2 70 +system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Control::0 1816 +system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Response_Data::2 5832 +system.ruby.network.ext_links00.int_node.throttle1.msg_bytes.Writeback_Control::2 560 +system.ruby.network.ext_links00.int_node.throttle2.link_utilization 0.234028 +system.ruby.network.ext_links00.int_node.throttle2.msg_count.Control::0 81 +system.ruby.network.ext_links00.int_node.throttle2.msg_count.Response_Data::2 227 +system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Control::0 648 +system.ruby.network.ext_links00.int_node.throttle2.msg_bytes.Response_Data::2 16344 +system.ruby.network.ext_links01.int_node.throttle0.link_utilization 0.113047 +system.ruby.network.ext_links01.int_node.throttle0.msg_count.Control::0 227 +system.ruby.network.ext_links01.int_node.throttle0.msg_count.Response_Data::2 81 +system.ruby.network.ext_links01.int_node.throttle0.msg_count.Writeback_Control::2 70 +system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Control::0 1816 +system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Response_Data::2 5832 +system.ruby.network.ext_links01.int_node.throttle0.msg_bytes.Writeback_Control::2 560 +system.ruby.network.ext_links01.int_node.throttle1.link_utilization 0.128914 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Request_Control::0 153 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Data::2 14 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Response_Control::2 217 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Writeback_Data::2 66 +system.ruby.network.ext_links01.int_node.throttle1.msg_count.Unblock_Control::4 80 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Request_Control::0 1224 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Data::2 1008 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Response_Control::2 1736 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Writeback_Data::2 4752 +system.ruby.network.ext_links01.int_node.throttle1.msg_bytes.Unblock_Control::4 640 +system.ruby.network.ext_links02.int_node.throttle0.link_utilization 0.115361 +system.ruby.network.ext_links02.int_node.throttle0.msg_count.Control::1 102 +system.ruby.network.ext_links02.int_node.throttle0.msg_count.Response_Data::3 105 +system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Control::1 816 +system.ruby.network.ext_links02.int_node.throttle0.msg_bytes.Response_Data::3 7560 +system.ruby.network.ext_links02.int_node.throttle1.link_utilization 0.108750 +system.ruby.network.ext_links02.int_node.throttle1.msg_count.Control::1 96 +system.ruby.network.ext_links02.int_node.throttle1.msg_count.Response_Data::3 99 +system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Control::1 768 +system.ruby.network.ext_links02.int_node.throttle1.msg_bytes.Response_Data::3 7128 +system.ruby.network.ext_links02.int_node.throttle2.link_utilization 0.109742 +system.ruby.network.ext_links02.int_node.throttle2.msg_count.Control::1 105 +system.ruby.network.ext_links02.int_node.throttle2.msg_count.Response_Data::3 99 +system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Control::1 840 +system.ruby.network.ext_links02.int_node.throttle2.msg_bytes.Response_Data::3 7128 +system.ruby.network.ext_links02.int_node.throttle3.link_utilization 0.102690 +system.ruby.network.ext_links02.int_node.throttle3.msg_count.Control::1 86 +system.ruby.network.ext_links02.int_node.throttle3.msg_count.Response_Data::3 94 +system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Control::1 688 +system.ruby.network.ext_links02.int_node.throttle3.msg_bytes.Response_Data::3 6768 +system.ruby.network.ext_links02.int_node.throttle4.link_utilization 0.116573 +system.ruby.network.ext_links02.int_node.throttle4.msg_count.Control::1 104 +system.ruby.network.ext_links02.int_node.throttle4.msg_count.Response_Data::3 106 +system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Control::1 832 +system.ruby.network.ext_links02.int_node.throttle4.msg_bytes.Response_Data::3 7632 +system.ruby.network.ext_links02.int_node.throttle5.link_utilization 0.107759 +system.ruby.network.ext_links02.int_node.throttle5.msg_count.Control::1 96 +system.ruby.network.ext_links02.int_node.throttle5.msg_count.Response_Data::3 98 +system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Control::1 768 +system.ruby.network.ext_links02.int_node.throttle5.msg_bytes.Response_Data::3 7056 +system.ruby.network.ext_links02.int_node.throttle6.link_utilization 0.128473 +system.ruby.network.ext_links02.int_node.throttle6.msg_count.Control::1 113 +system.ruby.network.ext_links02.int_node.throttle6.msg_count.Response_Data::3 117 +system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Control::1 904 +system.ruby.network.ext_links02.int_node.throttle6.msg_bytes.Response_Data::3 8424 +system.ruby.network.ext_links02.int_node.throttle7.link_utilization 0.098944 +system.ruby.network.ext_links02.int_node.throttle7.msg_count.Control::1 88 +system.ruby.network.ext_links02.int_node.throttle7.msg_count.Response_Data::3 90 +system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Control::1 704 +system.ruby.network.ext_links02.int_node.throttle7.msg_bytes.Response_Data::3 6480 +system.ruby.network.ext_links02.int_node.throttle8.link_utilization 0 +system.ruby.network.ext_links02.int_node.throttle9.link_utilization 1.221264 +system.ruby.network.ext_links02.int_node.throttle9.msg_count.Control::0 81 +system.ruby.network.ext_links02.int_node.throttle9.msg_count.Request_Control::1 846 +system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::2 227 +system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Data::3 809 +system.ruby.network.ext_links02.int_node.throttle9.msg_count.Response_Control::3 2 +system.ruby.network.ext_links02.int_node.throttle9.msg_count.Unblock_Control::5 831 +system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Control::0 648 +system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Request_Control::1 6768 +system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::2 16344 +system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Data::3 58248 +system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Response_Control::3 16 +system.ruby.network.ext_links02.int_node.throttle9.msg_bytes.Unblock_Control::5 6648 +system.ruby.network.ext_links02.int_node.throttle10.link_utilization 0.013002 +system.ruby.network.ext_links02.int_node.throttle10.msg_count.Control::1 10 +system.ruby.network.ext_links02.int_node.throttle10.msg_count.Response_Data::3 12 +system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Control::1 80 +system.ruby.network.ext_links02.int_node.throttle10.msg_bytes.Response_Data::3 864 +system.ruby.network.ext_links02.int_node.throttle11.link_utilization 0.016417 +system.ruby.network.ext_links02.int_node.throttle11.msg_count.Control::1 14 +system.ruby.network.ext_links02.int_node.throttle11.msg_count.Response_Data::3 15 +system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Control::1 112 +system.ruby.network.ext_links02.int_node.throttle11.msg_bytes.Response_Data::3 1080 +system.ruby.network.ext_links02.int_node.throttle12.link_utilization 0.121642 +system.ruby.network.ext_links02.int_node.throttle12.msg_count.Request_Control::0 232 +system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Data::2 71 +system.ruby.network.ext_links02.int_node.throttle12.msg_count.Response_Control::2 10 +system.ruby.network.ext_links02.int_node.throttle12.msg_count.Unblock_Control::4 223 +system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Request_Control::0 1856 +system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Data::2 5112 +system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Response_Control::2 80 +system.ruby.network.ext_links02.int_node.throttle12.msg_bytes.Unblock_Control::4 1784 +system.ruby.CorePair_Controller.C0_Load_L1miss 1 0.00% 0.00% +system.ruby.CorePair_Controller.C1_Load_L1miss 1 0.00% 0.00% +system.ruby.CorePair_Controller.Ifetch0_L1miss 2 0.00% 0.00% +system.ruby.CorePair_Controller.Ifetch1_L1miss 1 0.00% 0.00% +system.ruby.CorePair_Controller.C0_Store_L1miss 45 0.00% 0.00% +system.ruby.CorePair_Controller.C0_Store_L1hit 2 0.00% 0.00% +system.ruby.CorePair_Controller.C1_Store_L1miss 73 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckS 4 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckM 77 0.00% 0.00% +system.ruby.CorePair_Controller.NB_AckWB 70 0.00% 0.00% +system.ruby.CorePair_Controller.L1D0_Repl 19 0.00% 0.00% +system.ruby.CorePair_Controller.L2_Repl 36624 0.00% 0.00% +system.ruby.CorePair_Controller.PrbInvData 223 0.00% 0.00% +system.ruby.CorePair_Controller.PrbShrData 4 0.00% 0.00% +system.ruby.CorePair_Controller.I.C0_Load_L1miss 1 0.00% 0.00% +system.ruby.CorePair_Controller.I.C1_Load_L1miss 1 0.00% 0.00% +system.ruby.CorePair_Controller.I.Ifetch0_L1miss 2 0.00% 0.00% +system.ruby.CorePair_Controller.I.Ifetch1_L1miss 1 0.00% 0.00% +system.ruby.CorePair_Controller.I.C0_Store_L1miss 41 0.00% 0.00% +system.ruby.CorePair_Controller.I.C1_Store_L1miss 37 0.00% 0.00% +system.ruby.CorePair_Controller.I.PrbInvData 209 0.00% 0.00% +system.ruby.CorePair_Controller.I.PrbShrData 3 0.00% 0.00% +system.ruby.CorePair_Controller.S.L2_Repl 3 0.00% 0.00% +system.ruby.CorePair_Controller.S.PrbInvData 1 0.00% 0.00% +system.ruby.CorePair_Controller.O.PrbInvData 1 0.00% 0.00% +system.ruby.CorePair_Controller.M0.C0_Store_L1hit 2 0.00% 0.00% +system.ruby.CorePair_Controller.M0.L2_Repl 33 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbInvData 5 0.00% 0.00% +system.ruby.CorePair_Controller.M0.PrbShrData 1 0.00% 0.00% +system.ruby.CorePair_Controller.M1.C0_Store_L1miss 1 0.00% 0.00% +system.ruby.CorePair_Controller.M1.L2_Repl 36 0.00% 0.00% +system.ruby.CorePair_Controller.M1.PrbInvData 2 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0.C1_Store_L1miss 5 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0.NB_AckM 35 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0.L1D0_Repl 11 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0.L2_Repl 16208 0.00% 0.00% +system.ruby.CorePair_Controller.I_M1.C0_Store_L1miss 3 0.00% 0.00% +system.ruby.CorePair_Controller.I_M1.NB_AckM 34 0.00% 0.00% +system.ruby.CorePair_Controller.I_M1.L2_Repl 14782 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0M1.NB_AckM 5 0.00% 0.00% +system.ruby.CorePair_Controller.I_M0M1.L2_Repl 3020 0.00% 0.00% +system.ruby.CorePair_Controller.I_M1M0.NB_AckM 3 0.00% 0.00% +system.ruby.CorePair_Controller.I_M1M0.L2_Repl 1059 0.00% 0.00% +system.ruby.CorePair_Controller.I_E0S.NB_AckS 1 0.00% 0.00% +system.ruby.CorePair_Controller.I_E0S.L1D0_Repl 8 0.00% 0.00% +system.ruby.CorePair_Controller.I_E0S.L2_Repl 493 0.00% 0.00% +system.ruby.CorePair_Controller.I_E1S.NB_AckS 1 0.00% 0.00% +system.ruby.CorePair_Controller.I_E1S.L2_Repl 638 0.00% 0.00% +system.ruby.CorePair_Controller.ES_I.NB_AckWB 2 0.00% 0.00% +system.ruby.CorePair_Controller.MO_I.NB_AckWB 64 0.00% 0.00% +system.ruby.CorePair_Controller.MO_I.PrbInvData 5 0.00% 0.00% +system.ruby.CorePair_Controller.S0.C1_Store_L1miss 31 0.00% 0.00% +system.ruby.CorePair_Controller.S0.NB_AckS 1 0.00% 0.00% +system.ruby.CorePair_Controller.S0.L2_Repl 352 0.00% 0.00% +system.ruby.CorePair_Controller.S1.NB_AckS 1 0.00% 0.00% +system.ruby.CorePair_Controller.I_C.NB_AckWB 4 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkS 3 0.00% 0.00% +system.ruby.Directory_Controller.RdBlkM 309 0.00% 0.00% +system.ruby.Directory_Controller.RdBlk 6 0.00% 0.00% +system.ruby.Directory_Controller.VicDirty 68 0.00% 0.00% +system.ruby.Directory_Controller.VicClean 2 0.00% 0.00% +system.ruby.Directory_Controller.CPUData 66 0.00% 0.00% +system.ruby.Directory_Controller.StaleWB 4 0.00% 0.00% +system.ruby.Directory_Controller.CPUPrbResp 308 0.00% 0.00% +system.ruby.Directory_Controller.ProbeAcksComplete 308 0.00% 0.00% +system.ruby.Directory_Controller.L3Hit 49 0.00% 0.00% +system.ruby.Directory_Controller.MemData 259 0.00% 0.00% +system.ruby.Directory_Controller.WBAck 9 0.00% 0.00% +system.ruby.Directory_Controller.CoreUnblock 303 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkS 3 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlkM 300 0.00% 0.00% +system.ruby.Directory_Controller.U.RdBlk 5 0.00% 0.00% +system.ruby.Directory_Controller.U.VicDirty 68 0.00% 0.00% +system.ruby.Directory_Controller.U.VicClean 2 0.00% 0.00% +system.ruby.Directory_Controller.U.WBAck 9 0.00% 0.00% +system.ruby.Directory_Controller.BL.RdBlkM 1 0.00% 0.00% +system.ruby.Directory_Controller.BL.CPUData 66 0.00% 0.00% +system.ruby.Directory_Controller.BL.StaleWB 4 0.00% 0.00% +system.ruby.Directory_Controller.BM_M.MemData 8 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.L3Hit 1 0.00% 0.00% +system.ruby.Directory_Controller.BS_PM.MemData 2 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.RdBlkM 1 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.CPUPrbResp 12 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.ProbeAcksComplete 8 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.L3Hit 46 0.00% 0.00% +system.ruby.Directory_Controller.BM_PM.MemData 246 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.L3Hit 2 0.00% 0.00% +system.ruby.Directory_Controller.B_PM.MemData 3 0.00% 0.00% +system.ruby.Directory_Controller.BS_Pm.CPUPrbResp 3 0.00% 0.00% +system.ruby.Directory_Controller.BS_Pm.ProbeAcksComplete 3 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.RdBlkM 3 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.CPUPrbResp 288 0.00% 0.00% +system.ruby.Directory_Controller.BM_Pm.ProbeAcksComplete 292 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.CPUPrbResp 5 0.00% 0.00% +system.ruby.Directory_Controller.B_Pm.ProbeAcksComplete 5 0.00% 0.00% +system.ruby.Directory_Controller.B.RdBlkM 4 0.00% 0.00% +system.ruby.Directory_Controller.B.RdBlk 1 0.00% 0.00% +system.ruby.Directory_Controller.B.CoreUnblock 303 0.00% 0.00% +system.ruby.LD.latency_hist::bucket_size 1024 +system.ruby.LD.latency_hist::max_bucket 10239 +system.ruby.LD.latency_hist::samples 1 +system.ruby.LD.latency_hist::mean 5324 +system.ruby.LD.latency_hist::gmean 5324.000000 +system.ruby.LD.latency_hist::stdev nan +system.ruby.LD.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.latency_hist::total 1 +system.ruby.LD.hit_latency_hist::bucket_size 1024 +system.ruby.LD.hit_latency_hist::max_bucket 10239 +system.ruby.LD.hit_latency_hist::samples 1 +system.ruby.LD.hit_latency_hist::mean 5324 +system.ruby.LD.hit_latency_hist::gmean 5324.000000 +system.ruby.LD.hit_latency_hist::stdev nan +system.ruby.LD.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.hit_latency_hist::total 1 +system.ruby.ST.latency_hist::bucket_size 1024 +system.ruby.ST.latency_hist::max_bucket 10239 +system.ruby.ST.latency_hist::samples 46 +system.ruby.ST.latency_hist::mean 3269.239130 +system.ruby.ST.latency_hist::gmean 1783.447677 +system.ruby.ST.latency_hist::stdev 1934.416354 +system.ruby.ST.latency_hist | 11 23.91% 23.91% | 3 6.52% 30.43% | 3 6.52% 36.96% | 7 15.22% 52.17% | 18 39.13% 91.30% | 4 8.70% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.latency_hist::total 46 +system.ruby.ST.hit_latency_hist::bucket_size 1024 +system.ruby.ST.hit_latency_hist::max_bucket 10239 +system.ruby.ST.hit_latency_hist::samples 40 +system.ruby.ST.hit_latency_hist::mean 3606.650000 +system.ruby.ST.hit_latency_hist::gmean 2691.718970 +system.ruby.ST.hit_latency_hist::stdev 1792.166924 +system.ruby.ST.hit_latency_hist | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.hit_latency_hist::total 40 +system.ruby.ST.miss_latency_hist::bucket_size 512 +system.ruby.ST.miss_latency_hist::max_bucket 5119 +system.ruby.ST.miss_latency_hist::samples 6 +system.ruby.ST.miss_latency_hist::mean 1019.833333 +system.ruby.ST.miss_latency_hist::gmean 114.673945 +system.ruby.ST.miss_latency_hist::stdev 1281.644790 +system.ruby.ST.miss_latency_hist | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.miss_latency_hist::total 6 +system.ruby.IFETCH.latency_hist::bucket_size 1024 +system.ruby.IFETCH.latency_hist::max_bucket 10239 +system.ruby.IFETCH.latency_hist::samples 1 +system.ruby.IFETCH.latency_hist::mean 5156 +system.ruby.IFETCH.latency_hist::gmean 5156.000000 +system.ruby.IFETCH.latency_hist::stdev nan +system.ruby.IFETCH.latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.latency_hist::total 1 +system.ruby.IFETCH.hit_latency_hist::bucket_size 1024 +system.ruby.IFETCH.hit_latency_hist::max_bucket 10239 +system.ruby.IFETCH.hit_latency_hist::samples 1 +system.ruby.IFETCH.hit_latency_hist::mean 5156 +system.ruby.IFETCH.hit_latency_hist::gmean 5156.000000 +system.ruby.IFETCH.hit_latency_hist::stdev nan +system.ruby.IFETCH.hit_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.hit_latency_hist::total 1 +system.ruby.L1Cache.miss_mach_latency_hist::bucket_size 512 +system.ruby.L1Cache.miss_mach_latency_hist::max_bucket 5119 +system.ruby.L1Cache.miss_mach_latency_hist::samples 6 +system.ruby.L1Cache.miss_mach_latency_hist::mean 1019.833333 +system.ruby.L1Cache.miss_mach_latency_hist::gmean 114.673945 +system.ruby.L1Cache.miss_mach_latency_hist::stdev 1281.644790 +system.ruby.L1Cache.miss_mach_latency_hist | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.L1Cache.miss_mach_latency_hist::total 6 +system.ruby.Directory.hit_mach_latency_hist::bucket_size 1024 +system.ruby.Directory.hit_mach_latency_hist::max_bucket 10239 +system.ruby.Directory.hit_mach_latency_hist::samples 42 +system.ruby.Directory.hit_mach_latency_hist::mean 3684.428571 +system.ruby.Directory.hit_mach_latency_hist::gmean 2778.454716 +system.ruby.Directory.hit_mach_latency_hist::stdev 1783.107224 +system.ruby.Directory.hit_mach_latency_hist | 7 16.67% 16.67% | 3 7.14% 23.81% | 1 2.38% 26.19% | 7 16.67% 42.86% | 18 42.86% 85.71% | 6 14.29% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.Directory.hit_mach_latency_hist::total 42 +system.ruby.LD.Directory.hit_type_mach_latency_hist::bucket_size 1024 +system.ruby.LD.Directory.hit_type_mach_latency_hist::max_bucket 10239 +system.ruby.LD.Directory.hit_type_mach_latency_hist::samples 1 +system.ruby.LD.Directory.hit_type_mach_latency_hist::mean 5324 +system.ruby.LD.Directory.hit_type_mach_latency_hist::gmean 5324.000000 +system.ruby.LD.Directory.hit_type_mach_latency_hist::stdev nan +system.ruby.LD.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.LD.Directory.hit_type_mach_latency_hist::total 1 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::bucket_size 512 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::max_bucket 5119 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::samples 6 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::mean 1019.833333 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::gmean 114.673945 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::stdev 1281.644790 +system.ruby.ST.L1Cache.miss_type_mach_latency_hist | 3 50.00% 50.00% | 1 16.67% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 0 0.00% 66.67% | 2 33.33% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.L1Cache.miss_type_mach_latency_hist::total 6 +system.ruby.ST.Directory.hit_type_mach_latency_hist::bucket_size 1024 +system.ruby.ST.Directory.hit_type_mach_latency_hist::max_bucket 10239 +system.ruby.ST.Directory.hit_type_mach_latency_hist::samples 40 +system.ruby.ST.Directory.hit_type_mach_latency_hist::mean 3606.650000 +system.ruby.ST.Directory.hit_type_mach_latency_hist::gmean 2691.718970 +system.ruby.ST.Directory.hit_type_mach_latency_hist::stdev 1792.166924 +system.ruby.ST.Directory.hit_type_mach_latency_hist | 7 17.50% 17.50% | 3 7.50% 25.00% | 1 2.50% 27.50% | 7 17.50% 45.00% | 18 45.00% 90.00% | 4 10.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.ST.Directory.hit_type_mach_latency_hist::total 40 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::bucket_size 1024 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::max_bucket 10239 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::samples 1 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::mean 5156 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::gmean 5156.000000 +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::stdev nan +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.IFETCH.Directory.hit_type_mach_latency_hist::total 1 +system.ruby.SQC_Controller.Fetch | 12 44.44% 44.44% | 15 55.56% 100.00% +system.ruby.SQC_Controller.Fetch::total 27 +system.ruby.SQC_Controller.TCC_AckS | 12 44.44% 44.44% | 15 55.56% 100.00% +system.ruby.SQC_Controller.TCC_AckS::total 27 +system.ruby.SQC_Controller.PrbInvData | 10 41.67% 41.67% | 14 58.33% 100.00% +system.ruby.SQC_Controller.PrbInvData::total 24 +system.ruby.SQC_Controller.I.Fetch | 12 44.44% 44.44% | 15 55.56% 100.00% +system.ruby.SQC_Controller.I.Fetch::total 27 +system.ruby.SQC_Controller.S.PrbInvData | 10 41.67% 41.67% | 14 58.33% 100.00% +system.ruby.SQC_Controller.S.PrbInvData::total 24 +system.ruby.SQC_Controller.I_S.TCC_AckS | 12 44.44% 44.44% | 15 55.56% 100.00% +system.ruby.SQC_Controller.I_S.TCC_AckS::total 27 +system.ruby.TCCdir_Controller.RdBlk 174 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlkM 2638 0.00% 0.00% +system.ruby.TCCdir_Controller.RdBlkS 195 0.00% 0.00% +system.ruby.TCCdir_Controller.CPUPrbResp 811 0.00% 0.00% +system.ruby.TCCdir_Controller.ProbeAcksComplete 751 0.00% 0.00% +system.ruby.TCCdir_Controller.CoreUnblock 829 0.00% 0.00% +system.ruby.TCCdir_Controller.LastCoreUnblock 2 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckS 2 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckE 2 0.00% 0.00% +system.ruby.TCCdir_Controller.NB_AckM 223 0.00% 0.00% +system.ruby.TCCdir_Controller.PrbInvData 112 0.00% 0.00% +system.ruby.TCCdir_Controller.PrbShrData 4 0.00% 0.00% +system.ruby.TCCdir_Controller.I.RdBlk 3 0.00% 0.00% +system.ruby.TCCdir_Controller.I.RdBlkM 156 0.00% 0.00% +system.ruby.TCCdir_Controller.I.RdBlkS 1 0.00% 0.00% +system.ruby.TCCdir_Controller.I.PrbInvData 9 0.00% 0.00% +system.ruby.TCCdir_Controller.S.RdBlkM 2 0.00% 0.00% +system.ruby.TCCdir_Controller.S.RdBlkS 1 0.00% 0.00% +system.ruby.TCCdir_Controller.E.RdBlkM 1 0.00% 0.00% +system.ruby.TCCdir_Controller.O.RdBlk 1 0.00% 0.00% +system.ruby.TCCdir_Controller.O.RdBlkM 70 0.00% 0.00% +system.ruby.TCCdir_Controller.O.PrbInvData 6 0.00% 0.00% +system.ruby.TCCdir_Controller.M.RdBlk 61 0.00% 0.00% +system.ruby.TCCdir_Controller.M.RdBlkM 521 0.00% 0.00% +system.ruby.TCCdir_Controller.M.RdBlkS 25 0.00% 0.00% +system.ruby.TCCdir_Controller.M.PrbInvData 59 0.00% 0.00% +system.ruby.TCCdir_Controller.M.PrbShrData 4 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_I.RdBlk 9 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_I.RdBlkM 15 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_I.RdBlkS 7 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_I.CPUPrbResp 71 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_I.ProbeAcksComplete 65 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_O.RdBlkM 4 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_O.CPUPrbResp 4 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_O.ProbeAcksComplete 4 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_IOM.RdBlkM 5 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_IOM.CPUPrbResp 2 0.00% 0.00% +system.ruby.TCCdir_Controller.CP_IOM.ProbeAcksComplete 2 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.RdBlkM 897 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.RdBlkS 30 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.NB_AckM 156 0.00% 0.00% +system.ruby.TCCdir_Controller.I_M.PrbInvData 1 0.00% 0.00% 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+system.ruby.TCCdir_Controller.BBS_M.RdBlkM 18 0.00% 0.00% +system.ruby.TCCdir_Controller.BBS_M.CPUPrbResp 4 0.00% 0.00% +system.ruby.TCCdir_Controller.BBS_M.ProbeAcksComplete 3 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_M.RdBlkM 20 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_M.CPUPrbResp 122 0.00% 0.00% +system.ruby.TCCdir_Controller.BBO_M.ProbeAcksComplete 69 0.00% 0.00% +system.ruby.TCCdir_Controller.S_M.RdBlk 28 0.00% 0.00% +system.ruby.TCCdir_Controller.S_M.RdBlkM 69 0.00% 0.00% +system.ruby.TCCdir_Controller.S_M.NB_AckM 3 0.00% 0.00% +system.ruby.TCCdir_Controller.O_M.RdBlk 20 0.00% 0.00% +system.ruby.TCCdir_Controller.O_M.RdBlkM 249 0.00% 0.00% +system.ruby.TCCdir_Controller.O_M.RdBlkS 51 0.00% 0.00% +system.ruby.TCCdir_Controller.O_M.NB_AckM 64 0.00% 0.00% +system.ruby.TCCdir_Controller.O_M.PrbInvData 2 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.RdBlk 3 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.RdBlkM 23 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.RdBlkS 5 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_S.CoreUnblock 2 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlk 9 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlkM 206 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.RdBlkS 14 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_M.CoreUnblock 223 0.00% 0.00% +system.ruby.TCCdir_Controller.BBB_E.CoreUnblock 2 0.00% 0.00% +system.ruby.TCP_Controller.Load | 5 7.04% 7.04% | 6 8.45% 15.49% | 10 14.08% 29.58% | 13 18.31% 47.89% | 6 8.45% 56.34% | 6 8.45% 64.79% | 13 18.31% 83.10% | 12 16.90% 100.00% +system.ruby.TCP_Controller.Load::total 71 +system.ruby.TCP_Controller.Store | 109 13.39% 13.39% | 104 12.78% 26.17% | 98 12.04% 38.21% | 93 11.43% 49.63% | 109 13.39% 63.02% | 102 12.53% 75.55% | 113 13.88% 89.43% | 86 10.57% 100.00% +system.ruby.TCP_Controller.Store::total 814 +system.ruby.TCP_Controller.TCC_AckS | 5 7.94% 7.94% | 5 7.94% 15.87% | 9 14.29% 30.16% | 13 20.63% 50.79% | 4 6.35% 57.14% | 6 9.52% 66.67% | 11 17.46% 84.13% | 10 15.87% 100.00% +system.ruby.TCP_Controller.TCC_AckS::total 63 +system.ruby.TCP_Controller.TCC_AckE | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.TCC_AckE::total 2 +system.ruby.TCP_Controller.TCC_AckM | 100 13.46% 13.46% | 94 12.65% 26.11% | 90 12.11% 38.22% | 81 10.90% 49.13% | 102 13.73% 62.85% | 92 12.38% 75.24% | 105 14.13% 89.37% | 79 10.63% 100.00% +system.ruby.TCP_Controller.TCC_AckM::total 743 +system.ruby.TCP_Controller.PrbInvData | 88 12.61% 12.61% | 87 12.46% 25.07% | 88 12.61% 37.68% | 79 11.32% 49.00% | 90 12.89% 61.89% | 86 12.32% 74.21% | 101 14.47% 88.68% | 79 11.32% 100.00% +system.ruby.TCP_Controller.PrbInvData::total 698 +system.ruby.TCP_Controller.PrbShrData | 14 15.22% 15.22% | 9 9.78% 25.00% | 17 18.48% 43.48% | 7 7.61% 51.09% | 14 15.22% 66.30% | 10 10.87% 77.17% | 12 13.04% 90.22% | 9 9.78% 100.00% +system.ruby.TCP_Controller.PrbShrData::total 92 +system.ruby.TCP_Controller.I.Load | 5 7.46% 7.46% | 5 7.46% 14.93% | 9 13.43% 28.36% | 13 19.40% 47.76% | 6 8.96% 56.72% | 6 8.96% 65.67% | 12 17.91% 83.58% | 11 16.42% 100.00% +system.ruby.TCP_Controller.I.Load::total 67 +system.ruby.TCP_Controller.I.Store | 98 13.26% 13.26% | 95 12.86% 26.12% | 89 12.04% 38.16% | 82 11.10% 49.26% | 99 13.40% 62.65% | 93 12.58% 75.24% | 105 14.21% 89.45% | 78 10.55% 100.00% +system.ruby.TCP_Controller.I.Store::total 739 +system.ruby.TCP_Controller.I.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.I.PrbInvData::total 2 +system.ruby.TCP_Controller.S.Store | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 20.00% 20.00% | 1 20.00% 40.00% | 0 0.00% 40.00% | 2 40.00% 80.00% | 1 20.00% 100.00% +system.ruby.TCP_Controller.S.Store::total 5 +system.ruby.TCP_Controller.S.PrbInvData | 4 8.33% 8.33% | 4 8.33% 16.67% | 8 16.67% 33.33% | 9 18.75% 52.08% | 3 6.25% 58.33% | 4 8.33% 66.67% | 8 16.67% 83.33% | 8 16.67% 100.00% +system.ruby.TCP_Controller.S.PrbInvData::total 48 +system.ruby.TCP_Controller.S.PrbShrData | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.S.PrbShrData::total 1 +system.ruby.TCP_Controller.E.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.E.PrbInvData::total 1 +system.ruby.TCP_Controller.O.Store | 2 20.00% 20.00% | 0 0.00% 20.00% | 2 20.00% 40.00% | 0 0.00% 40.00% | 3 30.00% 70.00% | 1 10.00% 80.00% | 1 10.00% 90.00% | 1 10.00% 100.00% +system.ruby.TCP_Controller.O.Store::total 10 +system.ruby.TCP_Controller.O.PrbInvData | 9 13.64% 13.64% | 7 10.61% 24.24% | 12 18.18% 42.42% | 7 10.61% 53.03% | 10 15.15% 68.18% | 5 7.58% 75.76% | 10 15.15% 90.91% | 6 9.09% 100.00% +system.ruby.TCP_Controller.O.PrbInvData::total 66 +system.ruby.TCP_Controller.O.PrbShrData | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.O.PrbShrData::total 1 +system.ruby.TCP_Controller.M.Load | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% +system.ruby.TCP_Controller.M.Load::total 4 +system.ruby.TCP_Controller.M.Store | 9 15.00% 15.00% | 9 15.00% 30.00% | 7 11.67% 41.67% | 10 16.67% 58.33% | 6 10.00% 68.33% | 8 13.33% 81.67% | 5 8.33% 90.00% | 6 10.00% 100.00% +system.ruby.TCP_Controller.M.Store::total 60 +system.ruby.TCP_Controller.M.PrbInvData | 75 12.93% 12.93% | 76 13.10% 26.03% | 67 11.55% 37.59% | 62 10.69% 48.28% | 76 13.10% 61.38% | 77 13.28% 74.66% | 82 14.14% 88.79% | 65 11.21% 100.00% +system.ruby.TCP_Controller.M.PrbInvData::total 580 +system.ruby.TCP_Controller.M.PrbShrData | 14 15.56% 15.56% | 8 8.89% 24.44% | 16 17.78% 42.22% | 7 7.78% 50.00% | 14 15.56% 65.56% | 10 11.11% 76.67% | 12 13.33% 90.00% | 9 10.00% 100.00% +system.ruby.TCP_Controller.M.PrbShrData::total 90 +system.ruby.TCP_Controller.I_M.TCC_AckM | 98 13.42% 13.42% | 94 12.88% 26.30% | 89 12.19% 38.49% | 80 10.96% 49.45% | 98 13.42% 62.88% | 91 12.47% 75.34% | 103 14.11% 89.45% | 77 10.55% 100.00% +system.ruby.TCP_Controller.I_M.TCC_AckM::total 730 +system.ruby.TCP_Controller.I_ES.TCC_AckS | 5 7.94% 7.94% | 5 7.94% 15.87% | 9 14.29% 30.16% | 13 20.63% 50.79% | 4 6.35% 57.14% | 6 9.52% 66.67% | 11 17.46% 84.13% | 10 15.87% 100.00% +system.ruby.TCP_Controller.I_ES.TCC_AckS::total 63 +system.ruby.TCP_Controller.I_ES.TCC_AckE | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 50.00% 50.00% | 1 50.00% 100.00% +system.ruby.TCP_Controller.I_ES.TCC_AckE::total 2 +system.ruby.TCP_Controller.S_M.TCC_AckM | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 25.00% 25.00% | 1 25.00% 50.00% | 0 0.00% 50.00% | 1 25.00% 75.00% | 1 25.00% 100.00% +system.ruby.TCP_Controller.S_M.TCC_AckM::total 4 +system.ruby.TCP_Controller.O_M.TCC_AckM | 2 22.22% 22.22% | 0 0.00% 22.22% | 1 11.11% 33.33% | 0 0.00% 33.33% | 3 33.33% 66.67% | 1 11.11% 77.78% | 1 11.11% 88.89% | 1 11.11% 100.00% +system.ruby.TCP_Controller.O_M.TCC_AckM::total 9 +system.ruby.TCP_Controller.O_M.PrbInvData | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% +system.ruby.TCP_Controller.O_M.PrbInvData::total 1 + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/60.gpu-randomtest/test.py b/tests/quick/se/60.gpu-randomtest/test.py new file mode 100644 index 000000000..d47bac621 --- /dev/null +++ b/tests/quick/se/60.gpu-randomtest/test.py @@ -0,0 +1,35 @@ +# +# Copyright (c) 2010-2015 Advanced Micro Devices, Inc. +# All rights reserved. +# +# For use for simulation and test purposes only +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# 1. Redistributions of source code must retain the above copyright notice, +# this list of conditions and the following disclaimer. +# +# 2. Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# 3. Neither the name of the copyright holder nor the names of its contributors +# may be used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +# Author: Brad Beckmann +# + diff --git a/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello b/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello Binary files differnew file mode 100755 index 000000000..de248ee4a --- /dev/null +++ b/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello diff --git a/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm b/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm Binary files differnew file mode 100644 index 000000000..a4ad14488 --- /dev/null +++ b/tests/test-progs/gpu-hello/bin/x86/linux/gpu-hello-kernel.asm diff --git a/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl b/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl new file mode 100755 index 000000000..1f61a6fab --- /dev/null +++ b/tests/test-progs/gpu-hello/src/gpu-hello-kernel.cl @@ -0,0 +1,78 @@ +/* + * Copyright (c) 2014-2015 Advanced Micro Devices, Inc. + * All rights reserved. + * + * For use for simulation and test purposes only + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Marc Orr + */ + + +__kernel void read_kernel(size_t code_size, + __global char *code_in, + __global int *key_arr, + __global char *msg_out, + __global int *chars_decoded) +{ + size_t gid = get_global_id(0); + size_t my_idx = gid % code_size; + bool decode = 0; + __local atomic_int lcount; + + if (get_local_id(0) == 0) { + lcount=0; + } + barrier(CLK_LOCAL_MEM_FENCE); + + // read code + char mycode = code_in[my_idx]; + + // decode + int my_key = key_arr[my_idx]; + if (my_key) { + decode = 1; + for (int n = 0; n < my_key; n++) { + mycode++; + } + } + + // write out msg + msg_out[gid] = mycode; + + if (decode) { + atomic_fetch_add((atomic_int *)(&lcount), 1); + } + barrier(CLK_LOCAL_MEM_FENCE); + + + if(get_local_id(0) == 0) { + int _lcount = atomic_load(&lcount); + atomic_fetch_add((atomic_int *)chars_decoded, _lcount); + } +} diff --git a/tests/test-progs/gpu-hello/src/gpu-hello.cpp b/tests/test-progs/gpu-hello/src/gpu-hello.cpp new file mode 100755 index 000000000..b6fff6e32 --- /dev/null +++ b/tests/test-progs/gpu-hello/src/gpu-hello.cpp @@ -0,0 +1,332 @@ +/* + * Copyright (c) 2015 Advanced Micro Devices, Inc. + * All rights reserved. + * + * For use for simulation and test purposes only + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. Neither the name of the copyright holder nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + * Author: Marc Orr, Brad Beckmann + */ + +#include <CL/cl.h> +#include <malloc.h> + +#include <cstdio> +#include <cstring> +#include <fstream> +#include <string> + +#define SUCCESS 0 +#define FAILURE 1 + +// OpenCL datastructures +cl_context context; +cl_device_id *devices; +cl_command_queue commandQueue; +cl_program program; +cl_kernel readKernel; + +// Application datastructures +const int CACHE_LINE_SIZE = 64; +size_t grid_size = 512; +size_t work_group_size = 256; + +// arguments +const int code_size = 5; +const char *code = "hello"; +int *keys; +char *msg; +int chars_decoded = 0; + +/* + Setup data structures for application/algorithm +*/ +int +setupDataStructs() +{ + msg = (char *)memalign(CACHE_LINE_SIZE, (grid_size + 1) * sizeof(char)); + if(msg == NULL) { + printf("%s:%d: error: %s\n", __FILE__, __LINE__, + "could not allocate host buffers\n"); + exit(-1); + } + msg[grid_size] = '\0'; + + keys = (int *)memalign(CACHE_LINE_SIZE, code_size * sizeof(int)); + keys[0] = 23; + keys[1] = 0; + keys[2] = 0; + keys[3] = 0; + keys[4] = 0; + + return SUCCESS; +} + +/* Setup OpenCL data structures */ +int +setupOpenCL() +{ + cl_int status = 0; + size_t deviceListSize; + + // 1. Get platform + cl_uint numPlatforms; + cl_platform_id platform = NULL; + status = clGetPlatformIDs(0, NULL, &numPlatforms); + if (status != CL_SUCCESS) { + printf("Error: Getting Platforms. (clGetPlatformsIDs)\n"); + return FAILURE; + } + + if (numPlatforms > 0) { + cl_platform_id *platforms = new cl_platform_id[numPlatforms]; + status = clGetPlatformIDs(numPlatforms, platforms, NULL); + if (status != CL_SUCCESS) { + printf("Error: Getting Platform Ids. (clGetPlatformsIDs)\n"); + return FAILURE; + } + for (int i = 0; i < numPlatforms; ++i) { + char pbuff[100]; + status = clGetPlatformInfo(platforms[i], CL_PLATFORM_VENDOR, + sizeof(pbuff), pbuff, NULL); + if (status != CL_SUCCESS) { + printf("Error: Getting Platform Info.(clGetPlatformInfo)\n"); + return FAILURE; + } + platform = platforms[i]; + if (!strcmp(pbuff, "Advanced Micro Devices, Inc.")) { + break; + } + } + delete platforms; + } + + if(NULL == platform) { + printf("NULL platform found so Exiting Application.\n"); + return FAILURE; + } + + // 2. create context from platform + cl_context_properties cps[3] = + {CL_CONTEXT_PLATFORM, (cl_context_properties)platform, 0}; + context = clCreateContextFromType(cps, CL_DEVICE_TYPE_GPU, NULL, NULL, + &status); + if (status != CL_SUCCESS) { + printf("Error: Creating Context. (clCreateContextFromType)\n"); + return FAILURE; + } + + // 3. Get device info + // 3a. Get # of devices + status = clGetContextInfo(context, CL_CONTEXT_DEVICES, 0, NULL, + &deviceListSize); + if (status != CL_SUCCESS) { + printf("Error: Getting Context Info (1st clGetContextInfo)\n"); + return FAILURE; + } + + // 3b. Get the device list data + devices = (cl_device_id *)malloc(deviceListSize); + if (devices == 0) { + printf("Error: No devices found.\n"); + return FAILURE; + } + status = clGetContextInfo(context, CL_CONTEXT_DEVICES, deviceListSize, + devices, NULL); + if (status != CL_SUCCESS) { + printf("Error: Getting Context Info (2nd clGetContextInfo)\n"); + return FAILURE; + } + + // 4. Create command queue for device + commandQueue = clCreateCommandQueue(context, devices[0], 0, &status); + if (status != CL_SUCCESS) { + printf("Creating Command Queue. (clCreateCommandQueue)\n"); + return FAILURE; + } + + const char *source = "dummy text"; + + size_t sourceSize[] = {strlen(source)}; + + // 5b. Register the kernel with the runtime + program = clCreateProgramWithSource(context, 1, &source, sourceSize, + &status); + if (status != CL_SUCCESS) { + printf("Error: Loading kernel (clCreateProgramWithSource)\n"); + return FAILURE; + } + + status = clBuildProgram(program, 1, devices, NULL, NULL, NULL); + if (status != CL_SUCCESS) { + printf("Error: Building kernel (clBuildProgram)\n"); + return FAILURE; + } + + readKernel = clCreateKernel(program, "read_kernel", &status); + if (status != CL_SUCCESS) { + printf("Error: Creating readKernel from program. (clCreateKernel)\n"); + return FAILURE; + } + + return SUCCESS; +} + + +/* Run kernels */ +int +runCLKernel(cl_kernel kernel) +{ + cl_int status; + cl_event event; + size_t globalThreads[1] = {grid_size}; + size_t localThreads[1] = {work_group_size}; + + // 1. Set arguments + // 1a. code size + size_t code_size = strlen(code); + status = clSetKernelArg(kernel, 0, sizeof(size_t), &code_size); + if (status != CL_SUCCESS) { + printf("Error: Setting kernel argument. (code_size)\n"); + return FAILURE; + } + + // 1b. code + status = clSetKernelArg(kernel, 1, sizeof(char *), (void *)&code); + if (status != CL_SUCCESS) { + printf("Error: Setting kernel argument. (code_in)\n"); + return FAILURE; + } + + // 1c. keys + printf("keys = %p, &keys = %p, keys[0] = %d\n", keys, &keys, keys[0]); + status = clSetKernelArg(kernel, 2, sizeof(int *), (void *)&keys); + if (status != CL_SUCCESS) { + printf("Error: Setting kernel argument. (key_arr)\n"); + return FAILURE; + } + + // 1d. msg + status = clSetKernelArg(kernel, 3, sizeof(char *), (void *)&msg); + if (status != CL_SUCCESS) { + printf("Error: Setting kernel argument. (memOut)\n"); + return FAILURE; + } + + // 1e. chars_decoded + int *chars_decoded_ptr = &chars_decoded; + status = clSetKernelArg(kernel, 4, sizeof(int *), + (void *)&chars_decoded_ptr); + if (status != CL_SUCCESS) { + printf("Error: Setting kernel argument. (memOut)\n"); + return FAILURE; + } + + // 2. Launch kernel + status = clEnqueueNDRangeKernel(commandQueue, kernel, 1, NULL, + globalThreads, localThreads, 0, NULL, + &event); + if (status != CL_SUCCESS) { + printf("Error: Enqueue failed. (clEnqueueNDRangeKernel)\n"); + return FAILURE; + } + + // 3. Wait for the kernel + status = clWaitForEvents(1, &event); + if (status != CL_SUCCESS) { + printf("Error: Waiting for kernel run to finish. (clWaitForEvents)\n"); + return FAILURE; + } + + // 4. Cleanup + status = clReleaseEvent(event); + if (status != CL_SUCCESS) { + printf("Error: Release event object. (clReleaseEvent)\n"); + return FAILURE; + } + + return SUCCESS; +} + + +/* Release OpenCL resources (Context, Memory etc.) */ +int +cleanupCL() +{ + cl_int status; + status = clReleaseKernel(readKernel); + if (status != CL_SUCCESS) { + printf("Error: In clReleaseKernel \n"); + return FAILURE; + } + status = clReleaseProgram(program); + if (status != CL_SUCCESS) { + printf("Error: In clReleaseProgram\n"); + return FAILURE; + } + status = clReleaseCommandQueue(commandQueue); + if (status != CL_SUCCESS) { + printf("Error: In clReleaseCommandQueue\n"); + return FAILURE; + } + status = clReleaseContext(context); + if (status != CL_SUCCESS) { + printf("Error: In clReleaseContext\n"); + return FAILURE; + } + + return SUCCESS; +} + +int +main(int argc, char * argv[]) +{ + // Initialize Host application + if (setupDataStructs() != SUCCESS) { + return FAILURE; + } + + // Initialize OpenCL resources + if (setupOpenCL() != SUCCESS) { + return FAILURE; + } + + // Run the CL program + if (runCLKernel(readKernel) != SUCCESS) { + return FAILURE; + } + printf("the gpu says:\n"); + printf("%s\n", msg); + + // Releases OpenCL resources + if (cleanupCL()!= SUCCESS) { + return FAILURE; + } + + return SUCCESS; +} |