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-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini315
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out308
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt305
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr6
-rw-r--r--tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout14
-rw-r--r--tests/quick/01.hello-2T-smt/test.py32
6 files changed, 980 insertions, 0 deletions
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
new file mode 100644
index 000000000..bd25cdab9
--- /dev/null
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -0,0 +1,315 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[debug]
+break_cycles=
+
+[exetrace]
+intel_format=false
+pc_symbol=true
+print_cpseq=false
+print_cycle=true
+print_data=true
+print_effaddr=true
+print_fetchseq=false
+print_iregs=false
+print_opclass=true
+print_thread=true
+speculative=true
+trace_system=client
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=timing
+physmem=system.physmem
+
+[system.cpu]
+type=DerivO3CPU
+children=fuPool workload0 workload1
+BTBEntries=4096
+BTBTagSize=16
+LFSTSize=1024
+LQEntries=32
+RASSize=16
+SQEntries=32
+SSITSize=1024
+activity=0
+backComSize=5
+choiceCtrBits=2
+choicePredictorSize=8192
+clock=1
+commitToDecodeDelay=1
+commitToFetchDelay=1
+commitToIEWDelay=1
+commitToRenameDelay=1
+commitWidth=8
+decodeToFetchDelay=1
+decodeToRenameDelay=1
+decodeWidth=8
+defer_registration=false
+dispatchWidth=8
+fetchToDecodeDelay=1
+fetchTrapLatency=1
+fetchWidth=8
+forwardComSize=5
+fuPool=system.cpu.fuPool
+function_trace=false
+function_trace_start=0
+globalCtrBits=2
+globalHistoryBits=13
+globalPredictorSize=8192
+iewToCommitDelay=1
+iewToDecodeDelay=1
+iewToFetchDelay=1
+iewToRenameDelay=1
+instShiftAmt=2
+issueToExecuteDelay=1
+issueWidth=8
+localCtrBits=2
+localHistoryBits=11
+localHistoryTableSize=2048
+localPredictorSize=2048
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+mem=system.physmem
+numIQEntries=64
+numPhysFloatRegs=256
+numPhysIntRegs=256
+numROBEntries=192
+numRobs=1
+numThreads=1
+predType=tournament
+progress_interval=0
+renameToDecodeDelay=1
+renameToFetchDelay=1
+renameToIEWDelay=2
+renameToROBDelay=1
+renameWidth=8
+squashWidth=8
+system=system
+trapLatency=13
+wbDepth=1
+wbWidth=8
+workload=system.cpu.workload0 system.cpu.workload1
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.fuPool]
+type=FUPool
+children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+children=opList0
+count=6
+opList=system.cpu.fuPool.FUList0.opList0
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntAlu
+opLat=1
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+children=opList0 opList1
+count=2
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+issueLat=1
+opClass=IntMult
+opLat=3
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+issueLat=19
+opClass=IntDiv
+opLat=20
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+children=opList0 opList1 opList2
+count=4
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatAdd
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+issueLat=1
+opClass=FloatCmp
+opLat=2
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+issueLat=1
+opClass=FloatCvt
+opLat=2
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+children=opList0 opList1 opList2
+count=2
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+issueLat=1
+opClass=FloatMult
+opLat=4
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+issueLat=12
+opClass=FloatDiv
+opLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+issueLat=24
+opClass=FloatSqrt
+opLat=24
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList4.opList0
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+children=opList0
+count=0
+opList=system.cpu.fuPool.FUList5.opList0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+children=opList0 opList1
+count=4
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+issueLat=1
+opClass=MemRead
+opLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+issueLat=1
+opClass=MemWrite
+opLat=1
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+children=opList0
+count=1
+opList=system.cpu.fuPool.FUList7.opList0
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+issueLat=3
+opClass=IprAccess
+opLat=3
+
+[system.cpu.workload0]
+type=LiveProcess
+cmd=tests/test-progs/hello/bin/alpha/linux/hello
+egid=100
+env=
+euid=100
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.cpu.workload1]
+type=LiveProcess
+cmd=tests/test-progs/hello/bin/alpha/linux/hello
+egid=100
+env=
+euid=100
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+port=system.membus.port[0]
+
+[trace]
+bufsize=0
+cycle=0
+dump_on_exit=false
+file=cout
+flags=
+ignore=
+start=0
+
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out
new file mode 100644
index 000000000..6d68de2a1
--- /dev/null
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out
@@ -0,0 +1,308 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=timing
+
+[system.membus]
+type=Bus
+bus_id=0
+
+[system.cpu.workload0]
+type=LiveProcess
+cmd=tests/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+env=
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu.workload1]
+type=LiveProcess
+cmd=tests/test-progs/hello/bin/alpha/linux/hello
+executable=tests/test-progs/hello/bin/alpha/linux/hello
+input=cin
+output=cout
+env=
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu.fuPool.FUList0.opList0]
+type=OpDesc
+opClass=IntAlu
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList0]
+type=FUDesc
+opList=system.cpu.fuPool.FUList0.opList0
+count=6
+
+[system.cpu.fuPool.FUList1.opList0]
+type=OpDesc
+opClass=IntMult
+opLat=3
+issueLat=1
+
+[system.cpu.fuPool.FUList1.opList1]
+type=OpDesc
+opClass=IntDiv
+opLat=20
+issueLat=19
+
+[system.cpu.fuPool.FUList1]
+type=FUDesc
+opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
+count=2
+
+[system.cpu.fuPool.FUList2.opList0]
+type=OpDesc
+opClass=FloatAdd
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList1]
+type=OpDesc
+opClass=FloatCmp
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2.opList2]
+type=OpDesc
+opClass=FloatCvt
+opLat=2
+issueLat=1
+
+[system.cpu.fuPool.FUList2]
+type=FUDesc
+opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
+count=4
+
+[system.cpu.fuPool.FUList3.opList0]
+type=OpDesc
+opClass=FloatMult
+opLat=4
+issueLat=1
+
+[system.cpu.fuPool.FUList3.opList1]
+type=OpDesc
+opClass=FloatDiv
+opLat=12
+issueLat=12
+
+[system.cpu.fuPool.FUList3.opList2]
+type=OpDesc
+opClass=FloatSqrt
+opLat=24
+issueLat=24
+
+[system.cpu.fuPool.FUList3]
+type=FUDesc
+opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
+count=2
+
+[system.cpu.fuPool.FUList4.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList4]
+type=FUDesc
+opList=system.cpu.fuPool.FUList4.opList0
+count=0
+
+[system.cpu.fuPool.FUList5.opList0]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList5]
+type=FUDesc
+opList=system.cpu.fuPool.FUList5.opList0
+count=0
+
+[system.cpu.fuPool.FUList6.opList0]
+type=OpDesc
+opClass=MemRead
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6.opList1]
+type=OpDesc
+opClass=MemWrite
+opLat=1
+issueLat=1
+
+[system.cpu.fuPool.FUList6]
+type=FUDesc
+opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1
+count=4
+
+[system.cpu.fuPool.FUList7.opList0]
+type=OpDesc
+opClass=IprAccess
+opLat=3
+issueLat=3
+
+[system.cpu.fuPool.FUList7]
+type=FUDesc
+opList=system.cpu.fuPool.FUList7.opList0
+count=1
+
+[system.cpu.fuPool]
+type=FUPool
+FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7
+
+[system.cpu]
+type=DerivO3CPU
+clock=1
+numThreads=1
+activity=0
+workload=system.cpu.workload0 system.cpu.workload1
+mem=system.physmem
+checker=null
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+cachePorts=200
+decodeToFetchDelay=1
+renameToFetchDelay=1
+iewToFetchDelay=1
+commitToFetchDelay=1
+fetchWidth=8
+renameToDecodeDelay=1
+iewToDecodeDelay=1
+commitToDecodeDelay=1
+fetchToDecodeDelay=1
+decodeWidth=8
+iewToRenameDelay=1
+commitToRenameDelay=1
+decodeToRenameDelay=1
+renameWidth=8
+commitToIEWDelay=1
+renameToIEWDelay=2
+issueToExecuteDelay=1
+dispatchWidth=8
+issueWidth=8
+wbWidth=8
+wbDepth=1
+fuPool=system.cpu.fuPool
+iewToCommitDelay=1
+renameToROBDelay=1
+commitWidth=8
+squashWidth=8
+trapLatency=13
+backComSize=5
+forwardComSize=5
+predType=tournament
+localPredictorSize=2048
+localCtrBits=2
+localHistoryTableSize=2048
+localHistoryBits=11
+globalPredictorSize=8192
+globalCtrBits=2
+globalHistoryBits=13
+choicePredictorSize=8192
+choiceCtrBits=2
+BTBEntries=4096
+BTBTagSize=16
+RASSize=16
+LQEntries=32
+SQEntries=32
+LFSTSize=1024
+SSITSize=1024
+numPhysIntRegs=256
+numPhysFloatRegs=256
+numIQEntries=64
+numROBEntries=192
+smtNumFetchingThreads=1
+smtFetchPolicy=SingleThread
+smtLSQPolicy=Partitioned
+smtLSQThreshold=100
+smtIQPolicy=Partitioned
+smtIQThreshold=100
+smtROBPolicy=Partitioned
+smtROBThreshold=100
+smtCommitPolicy=RoundRobin
+instShiftAmt=2
+defer_registration=false
+function_trace=false
+function_trace_start=0
+
+[trace]
+flags=
+start=0
+cycle=0
+bufsize=0
+file=cout
+dump_on_exit=false
+ignore=
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[random]
+seed=1
+
+[exetrace]
+speculative=true
+print_cycle=true
+print_opclass=true
+print_thread=true
+print_effaddr=true
+print_data=true
+print_iregs=false
+print_fetchseq=false
+print_cpseq=false
+print_reg_delta=false
+pc_symbol=true
+intel_format=false
+trace_system=client
+
+[debug]
+break_cycles=
+
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
new file mode 100644
index 000000000..4473a39f8
--- /dev/null
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt
@@ -0,0 +1,305 @@
+
+---------- Begin Simulation Statistics ----------
+global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
+global.BPredUnit.BTBHits 669 # Number of BTB hits
+global.BPredUnit.BTBLookups 3666 # Number of BTB lookups
+global.BPredUnit.RASInCorrect 78 # Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 1050 # Number of conditional branches incorrect
+global.BPredUnit.condPredicted 2479 # Number of conditional branches predicted
+global.BPredUnit.lookups 4216 # Number of BP lookups
+global.BPredUnit.usedRAS 545 # Number of times the RAS was used to get a target.
+host_inst_rate 13879 # Simulator instruction rate (inst/s)
+host_mem_usage 150244 # Number of bytes of host memory used
+host_seconds 0.82 # Real time elapsed on the host
+host_tick_rate 9101 # Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 21 # Number of conflicting loads.
+memdepunit.memDep.conflictingLoads 25 # Number of conflicting loads.
+memdepunit.memDep.conflictingStores 0 # Number of conflicting stores.
+memdepunit.memDep.conflictingStores 214 # Number of conflicting stores.
+memdepunit.memDep.insertedLoads 1795 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 1734 # Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1066 # Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 1051 # Number of stores inserted to the mem dependence unit.
+sim_freq 1000000000000 # Frequency of simulated ticks
+sim_insts 11399 # Number of instructions simulated
+sim_seconds 0.000000 # Number of seconds simulated
+sim_ticks 7478 # Number of ticks simulated
+system.cpu.commit.COM:branches 1756 # Number of branches committed
+system.cpu.commit.COM:branches_0 878 # Number of branches committed
+system.cpu.commit.COM:branches_1 878 # Number of branches committed
+system.cpu.commit.COM:bw_lim_events 177 # number cycles where commit BW limit reached
+system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:bw_limited_0 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:bw_limited_1 0 # number of insts not committed due to BW limits
+system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle
+system.cpu.commit.COM:committed_per_cycle.samples 7424
+system.cpu.commit.COM:committed_per_cycle.min_value 0
+ 0 3237 4360.18%
+ 1 1635 2202.32%
+ 2 920 1239.22%
+ 3 476 641.16%
+ 4 347 467.40%
+ 5 246 331.36%
+ 6 206 277.48%
+ 7 180 242.46%
+ 8 177 238.42%
+system.cpu.commit.COM:committed_per_cycle.max_value 8
+system.cpu.commit.COM:committed_per_cycle.end_dist
+
+system.cpu.commit.COM:count 11433 # Number of instructions committed
+system.cpu.commit.COM:count_0 5716 # Number of instructions committed
+system.cpu.commit.COM:count_1 5717 # Number of instructions committed
+system.cpu.commit.COM:loads 1976 # Number of loads committed
+system.cpu.commit.COM:loads_0 988 # Number of loads committed
+system.cpu.commit.COM:loads_1 988 # Number of loads committed
+system.cpu.commit.COM:membars 0 # Number of memory barriers committed
+system.cpu.commit.COM:membars_0 0 # Number of memory barriers committed
+system.cpu.commit.COM:membars_1 0 # Number of memory barriers committed
+system.cpu.commit.COM:refs 3600 # Number of memory references committed
+system.cpu.commit.COM:refs_0 1800 # Number of memory references committed
+system.cpu.commit.COM:refs_1 1800 # Number of memory references committed
+system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed
+system.cpu.commit.COM:swp_count_0 0 # Number of s/w prefetches committed
+system.cpu.commit.COM:swp_count_1 0 # Number of s/w prefetches committed
+system.cpu.commit.branchMispredicts 789 # The number of times a branch was mispredicted
+system.cpu.commit.commitCommittedInsts 11433 # The number of committed instructions
+system.cpu.commit.commitNonSpecStalls 34 # The number of times commit has been forced to stall to communicate backwards
+system.cpu.commit.commitSquashedInsts 6802 # The number of squashed insts skipped by commit
+system.cpu.committedInsts_0 5699 # Number of Instructions Simulated
+system.cpu.committedInsts_1 5700 # Number of Instructions Simulated
+system.cpu.committedInsts_total 11399 # Number of Instructions Simulated
+system.cpu.cpi_0 1.312160 # CPI: Cycles Per Instruction
+system.cpu.cpi_1 1.311930 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 0.656022 # CPI: Total CPI of All Threads
+system.cpu.decode.DECODE:BlockedCycles 1617 # Number of cycles decode is blocked
+system.cpu.decode.DECODE:BranchMispred 282 # Number of times decode detected a branch misprediction
+system.cpu.decode.DECODE:BranchResolved 364 # Number of times decode resolved a branch
+system.cpu.decode.DECODE:DecodedInsts 22220 # Number of instructions handled by decode
+system.cpu.decode.DECODE:IdleCycles 8058 # Number of cycles decode is idle
+system.cpu.decode.DECODE:RunCycles 3571 # Number of cycles decode is running
+system.cpu.decode.DECODE:SquashCycles 1260 # Number of cycles decode is squashing
+system.cpu.decode.DECODE:SquashedInsts 200 # Number of squashed instructions handled by decode
+system.cpu.decode.DECODE:UnblockCycles 277 # Number of cycles decode is unblocking
+system.cpu.fetch.Branches 4216 # Number of branches that fetch encountered
+system.cpu.fetch.CacheLines 2762 # Number of cache lines fetched
+system.cpu.fetch.Cycles 6837 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.Insts 25142 # Number of instructions fetch has processed
+system.cpu.fetch.SquashCycles 1098 # Number of cycles fetch has spent squashing
+system.cpu.fetch.branchRate 0.563712 # Number of branch fetches per cycle
+system.cpu.fetch.icacheStallCycles 2762 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.predictedBranches 1214 # Number of branches that fetch has predicted taken
+system.cpu.fetch.rate 3.361679 # Number of inst fetches per cycle
+system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist.samples 7479
+system.cpu.fetch.rateDist.min_value 0
+ 0 3407 4555.42%
+ 1 266 355.66%
+ 2 222 296.83%
+ 3 265 354.33%
+ 4 317 423.85%
+ 5 275 367.70%
+ 6 279 373.04%
+ 7 264 352.99%
+ 8 2184 2920.18%
+system.cpu.fetch.rateDist.max_value 8
+system.cpu.fetch.rateDist.end_dist
+
+system.cpu.iew.EXEC:branches 2294 # Number of branches executed
+system.cpu.iew.EXEC:branches_0 1156 # Number of branches executed
+system.cpu.iew.EXEC:branches_1 1138 # Number of branches executed
+system.cpu.iew.EXEC:nop 59 # number of nop insts executed
+system.cpu.iew.EXEC:nop_0 31 # number of nop insts executed
+system.cpu.iew.EXEC:nop_1 28 # number of nop insts executed
+system.cpu.iew.EXEC:rate 1.993582 # Inst execution rate
+system.cpu.iew.EXEC:refs 4718 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_0 2364 # number of memory reference insts executed
+system.cpu.iew.EXEC:refs_1 2354 # number of memory reference insts executed
+system.cpu.iew.EXEC:stores 1857 # Number of stores executed
+system.cpu.iew.EXEC:stores_0 924 # Number of stores executed
+system.cpu.iew.EXEC:stores_1 933 # Number of stores executed
+system.cpu.iew.EXEC:swp 0 # number of swp insts executed
+system.cpu.iew.EXEC:swp_0 0 # number of swp insts executed
+system.cpu.iew.EXEC:swp_1 0 # number of swp insts executed
+system.cpu.iew.WB:consumers 9920 # num instructions consuming a value
+system.cpu.iew.WB:consumers_0 4998 # num instructions consuming a value
+system.cpu.iew.WB:consumers_1 4922 # num instructions consuming a value
+system.cpu.iew.WB:count 14666 # cumulative count of insts written-back
+system.cpu.iew.WB:count_0 7373 # cumulative count of insts written-back
+system.cpu.iew.WB:count_1 7293 # cumulative count of insts written-back
+system.cpu.iew.WB:fanout 0.776915 # average fanout of values written-back
+system.cpu.iew.WB:fanout_0 0.775710 # average fanout of values written-back
+system.cpu.iew.WB:fanout_1 0.778139 # average fanout of values written-back
+system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_0 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_1 0 # number of instrctions required to write to 'other' IQ
+system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:penalized_rate_0 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:penalized_rate_1 0 # fraction of instructions written-back that wrote to 'other' IQ
+system.cpu.iew.WB:producers 7707 # num instructions producing a value
+system.cpu.iew.WB:producers_0 3877 # num instructions producing a value
+system.cpu.iew.WB:producers_1 3830 # num instructions producing a value
+system.cpu.iew.WB:rate 1.960957 # insts written-back per cycle
+system.cpu.iew.WB:rate_0 0.985827 # insts written-back per cycle
+system.cpu.iew.WB:rate_1 0.975130 # insts written-back per cycle
+system.cpu.iew.WB:sent 14753 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_0 7419 # cumulative count of insts sent to commit
+system.cpu.iew.WB:sent_1 7334 # cumulative count of insts sent to commit
+system.cpu.iew.branchMispredicts 869 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewBlockCycles 3 # Number of cycles IEW is blocking
+system.cpu.iew.iewDispLoadInsts 3529 # Number of dispatched load instructions
+system.cpu.iew.iewDispNonSpecInsts 39 # Number of dispatched non-speculative instructions
+system.cpu.iew.iewDispSquashedInsts 789 # Number of squashed instructions skipped by dispatch
+system.cpu.iew.iewDispStoreInsts 2117 # Number of dispatched store instructions
+system.cpu.iew.iewDispatchedInsts 18235 # Number of instructions dispatched to IQ
+system.cpu.iew.iewExecLoadInsts 2861 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_0 1440 # Number of load instructions executed
+system.cpu.iew.iewExecLoadInsts_1 1421 # Number of load instructions executed
+system.cpu.iew.iewExecSquashedInsts 1188 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewExecutedInsts 14910 # Number of executed instructions
+system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
+system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.iewSquashCycles 1260 # Number of cycles IEW is squashing
+system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking
+system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.0.forwLoads 45 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.0.memOrderViolation 27 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.0.squashedLoads 807 # Number of loads squashed
+system.cpu.iew.lsq.thread.0.squashedStores 254 # Number of stores squashed
+system.cpu.iew.lsq.thread.1.blockedLoads 1 # Number of blocked loads due to partial load-store forwarding
+system.cpu.iew.lsq.thread.1.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread.1.forwLoads 43 # Number of loads that had data forwarded from stores
+system.cpu.iew.lsq.thread.1.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread.1.invAddrLoads 0 # Number of loads ignored due to an invalid address
+system.cpu.iew.lsq.thread.1.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
+system.cpu.iew.lsq.thread.1.memOrderViolation 29 # Number of memory ordering violations
+system.cpu.iew.lsq.thread.1.rescheduledLoads 1 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread.1.squashedLoads 746 # Number of loads squashed
+system.cpu.iew.lsq.thread.1.squashedStores 239 # Number of stores squashed
+system.cpu.iew.memOrderViolationEvents 56 # Number of memory order violations
+system.cpu.iew.predictedNotTakenIncorrect 733 # Number of branches that were predicted not taken incorrectly
+system.cpu.iew.predictedTakenIncorrect 136 # Number of branches that were predicted taken incorrectly
+system.cpu.ipc_0 0.762102 # IPC: Instructions Per Cycle
+system.cpu.ipc_1 0.762236 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 1.524338 # IPC: Total IPC of All Threads
+system.cpu.iq.ISSUE:FU_type_0 8140 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.start_dist
+(null) 2 0.02% # Type of FU issued
+IntAlu 5556 68.26% # Type of FU issued
+IntMult 1 0.01% # Type of FU issued
+IntDiv 0 0.00% # Type of FU issued
+FloatAdd 2 0.02% # Type of FU issued
+FloatCmp 0 0.00% # Type of FU issued
+FloatCvt 0 0.00% # Type of FU issued
+FloatMult 0 0.00% # Type of FU issued
+FloatDiv 0 0.00% # Type of FU issued
+FloatSqrt 0 0.00% # Type of FU issued
+MemRead 1619 19.89% # Type of FU issued
+MemWrite 960 11.79% # Type of FU issued
+IprAccess 0 0.00% # Type of FU issued
+InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_0.end_dist
+system.cpu.iq.ISSUE:FU_type_1 7958 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1.start_dist
+ (null) 2 0.03% # Type of FU issued
+ IntAlu 5440 68.36% # Type of FU issued
+ IntMult 1 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 2 0.03% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 1553 19.51% # Type of FU issued
+ MemWrite 960 12.06% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type_1.end_dist
+system.cpu.iq.ISSUE:FU_type 16098 # Type of FU issued
+system.cpu.iq.ISSUE:FU_type.start_dist
+ (null) 4 0.02% # Type of FU issued
+ IntAlu 10996 68.31% # Type of FU issued
+ IntMult 2 0.01% # Type of FU issued
+ IntDiv 0 0.00% # Type of FU issued
+ FloatAdd 4 0.02% # Type of FU issued
+ FloatCmp 0 0.00% # Type of FU issued
+ FloatCvt 0 0.00% # Type of FU issued
+ FloatMult 0 0.00% # Type of FU issued
+ FloatDiv 0 0.00% # Type of FU issued
+ FloatSqrt 0 0.00% # Type of FU issued
+ MemRead 3172 19.70% # Type of FU issued
+ MemWrite 1920 11.93% # Type of FU issued
+ IprAccess 0 0.00% # Type of FU issued
+ InstPrefetch 0 0.00% # Type of FU issued
+system.cpu.iq.ISSUE:FU_type.end_dist
+system.cpu.iq.ISSUE:fu_busy_cnt 198 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_0 101 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_cnt_1 97 # FU busy when requested
+system.cpu.iq.ISSUE:fu_busy_rate 0.012300 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_0 0.006274 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_busy_rate_1 0.006026 # FU busy rate (busy events/executed inst)
+system.cpu.iq.ISSUE:fu_full.start_dist
+ (null) 0 0.00% # attempts to use FU when none available
+ IntAlu 9 4.55% # attempts to use FU when none available
+ IntMult 0 0.00% # attempts to use FU when none available
+ IntDiv 0 0.00% # attempts to use FU when none available
+ FloatAdd 0 0.00% # attempts to use FU when none available
+ FloatCmp 0 0.00% # attempts to use FU when none available
+ FloatCvt 0 0.00% # attempts to use FU when none available
+ FloatMult 0 0.00% # attempts to use FU when none available
+ FloatDiv 0 0.00% # attempts to use FU when none available
+ FloatSqrt 0 0.00% # attempts to use FU when none available
+ MemRead 114 57.58% # attempts to use FU when none available
+ MemWrite 75 37.88% # attempts to use FU when none available
+ IprAccess 0 0.00% # attempts to use FU when none available
+ InstPrefetch 0 0.00% # attempts to use FU when none available
+system.cpu.iq.ISSUE:fu_full.end_dist
+system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle
+system.cpu.iq.ISSUE:issued_per_cycle.samples 7479
+system.cpu.iq.ISSUE:issued_per_cycle.min_value 0
+ 0 2160 2888.09%
+ 1 1088 1454.74%
+ 2 1332 1780.99%
+ 3 1011 1351.78%
+ 4 818 1093.73%
+ 5 568 759.46%
+ 6 358 478.67%
+ 7 99 132.37%
+ 8 45 60.17%
+system.cpu.iq.ISSUE:issued_per_cycle.max_value 8
+system.cpu.iq.ISSUE:issued_per_cycle.end_dist
+
+system.cpu.iq.ISSUE:rate 2.152427 # Inst issue rate
+system.cpu.iq.iqInstsAdded 18137 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqInstsIssued 16098 # Number of instructions issued
+system.cpu.iq.iqNonSpecInstsAdded 39 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqSquashedInstsExamined 5869 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedInstsIssued 22 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedNonSpecRemoved 5 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.iqSquashedOperandsExamined 3337 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.numCycles 7479 # number of cpu cycles simulated
+system.cpu.rename.RENAME:BlockCycles 350 # Number of cycles rename is blocking
+system.cpu.rename.RENAME:CommittedMaps 8222 # Number of HB maps that are committed
+system.cpu.rename.RENAME:IdleCycles 8416 # Number of cycles rename is idle
+system.cpu.rename.RENAME:LSQFullEvents 695 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.RENAME:RenameLookups 26609 # Number of register rename lookups that rename has made
+system.cpu.rename.RENAME:RenamedInsts 20867 # Number of instructions processed by rename
+system.cpu.rename.RENAME:RenamedOperands 15602 # Number of destination operands rename has renamed
+system.cpu.rename.RENAME:RunCycles 3486 # Number of cycles rename is running
+system.cpu.rename.RENAME:SquashCycles 1260 # Number of cycles rename is squashing
+system.cpu.rename.RENAME:UnblockCycles 771 # Number of cycles rename is unblocking
+system.cpu.rename.RENAME:UndoneMaps 7380 # Number of HB maps that are undone due to squashing
+system.cpu.rename.RENAME:serializeStallCycles 500 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RENAME:serializingInsts 49 # count of serializing insts renamed
+system.cpu.rename.RENAME:skidInsts 2217 # count of insts added to the skid buffer
+system.cpu.rename.RENAME:tempSerializingInsts 38 # count of temporary serializing insts renamed
+system.cpu.workload0.PROG:num_syscalls 17 # Number of system calls
+system.cpu.workload1.PROG:num_syscalls 17 # Number of system calls
+
+---------- End Simulation Statistics ----------
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
new file mode 100644
index 000000000..a0835d526
--- /dev/null
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stderr
@@ -0,0 +1,6 @@
+warn: Entering event queue @ 0. Starting simulation...
+warn: cycle 0: fault (page_table_fault) detected @ PC 0x000000
+warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
+warn: Increasing stack 0x11ff92000:0x11ff9b000 to 0x11ff90000:0x11ff9b000 because of access to 0x11ff91ff0
+warn: cycle 5368: fault (page_table_fault) detected @ PC 0x000000
+warn: cycle 5369: fault (page_table_fault) detected @ PC 0x000000
diff --git a/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
new file mode 100644
index 000000000..5210b5740
--- /dev/null
+++ b/tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout
@@ -0,0 +1,14 @@
+Hello world!
+Hello world!
+M5 Simulator System
+
+Copyright (c) 2001-2006
+The Regents of The University of Michigan
+All Rights Reserved
+
+
+M5 compiled Oct 6 2006 00:21:18
+M5 started Fri Oct 6 02:55:30 2006
+M5 executing on zizzer.eecs.umich.edu
+command line: build/ALPHA_SE/m5.debug configs/example/se.py -d --cmd=tests/test-progs/hello/bin/alpha/linux/hello;tests/test-progs/hello/bin/alpha/linux/hello
+Exiting @ tick 7478 because target called exit()
diff --git a/tests/quick/01.hello-2T-smt/test.py b/tests/quick/01.hello-2T-smt/test.py
new file mode 100644
index 000000000..04ff8c2e6
--- /dev/null
+++ b/tests/quick/01.hello-2T-smt/test.py
@@ -0,0 +1,32 @@
+# Copyright (c) 2006 The Regents of The University of Michigan
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Korey Sewell
+
+process1 = LiveProcess(cmd = 'hello', executable = binpath('hello'))
+process2 = LiveProcess(cmd = 'hello', executable = binpath('hello'))
+
+root.system.cpu.workload = [process1, process2]