392 files changed, 37626 insertions, 15592 deletions

diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
index 4ffad8c19..586920bf4 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/config.ini
@@ -8,10 +8,11 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 console=/dist/m5/system/binaries/console
 init_param=0
 kernel=/dist/m5/system/binaries/vmlinux
@@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=8796093022208:18446744073709551615
 req_size=16
@@ -44,6 +45,11 @@ resp_size=16
 master=system.iobus.slave[0]
 slave=system.membus.master[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
@@ -58,7 +64,7 @@ backComSize=5
 branchPred=system.cpu0.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -137,11 +143,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -149,10 +153,10 @@ predType=tournament
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -163,12 +167,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=AlphaTLB
 size=64
@@ -438,10 +451,10 @@ opLat=3
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -452,12 +465,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=AlphaInterrupts
 
@@ -485,7 +507,7 @@ backComSize=5
 branchPred=system.cpu1.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -564,11 +586,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -576,10 +596,10 @@ predType=tournament
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -590,12 +610,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=AlphaTLB
 size=64
@@ -865,10 +894,10 @@ opLat=3
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -879,12 +908,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=AlphaInterrupts
 
@@ -898,6 +936,11 @@ size=48
 [system.cpu1.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.disk0]
 type=IdeDisk
 children=image
@@ -944,8 +987,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -955,10 +997,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -969,18 +1011,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -991,17 +1042,25 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -1012,7 +1071,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -1030,19 +1089,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -1053,7 +1117,6 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[1]
 
 [system.simple_disk]
@@ -1076,8 +1139,7 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -1093,7 +1155,7 @@ system=system
 
 [system.tsunami.backdoor]
 type=AlphaBackdoor
-clock=1000
+clk_domain=system.clk_domain
 cpu=system.cpu0
 disk=system.simple_disk
 pio_addr=8804682956800
@@ -1105,7 +1167,7 @@ pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8803072344064
 pio_latency=100000
 system=system
@@ -1152,7 +1214,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=2000
+clk_domain=system.clk_domain
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -1183,7 +1245,7 @@ pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -1200,7 +1262,7 @@ pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -1217,7 +1279,7 @@ pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -1234,7 +1296,7 @@ pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -1251,7 +1313,7 @@ pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -1268,7 +1330,7 @@ pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -1285,7 +1347,7 @@ pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -1302,7 +1364,7 @@ pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -1319,7 +1381,7 @@ pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -1336,7 +1398,7 @@ pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -1353,7 +1415,7 @@ pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -1370,7 +1432,7 @@ pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -1387,7 +1449,7 @@ pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -1404,7 +1466,7 @@ pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -1421,7 +1483,7 @@ pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -1438,7 +1500,7 @@ pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -1455,7 +1517,7 @@ pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -1472,7 +1534,7 @@ pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -1489,7 +1551,7 @@ pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -1506,7 +1568,7 @@ pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
-clock=1000
+clk_domain=system.clk_domain
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=100000
@@ -1553,7 +1615,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
@@ -1570,7 +1632,7 @@ pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
-clock=1000
+clk_domain=system.clk_domain
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -1582,7 +1644,7 @@ pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8802535473152
 pio_latency=100000
 system=system
@@ -1592,7 +1654,8 @@ pio=system.iobus.master[1]
 [system.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.tsunami
 size=16777216
@@ -1601,7 +1664,7 @@ pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8804615848952
 pio_latency=100000
 platform=system.tsunami
@@ -1609,3 +1672,7 @@ system=system
 terminal=system.terminal
 pio=system.iobus.master[23]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
index cf67b1361..3648b647f 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
@@ -1,15 +1,13 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 28 2013 09:43:29
-gem5 started Mar 28 2013 09:43:43
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:33:13
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 110215000
-Exiting @ tick 1900727697500 because m5_exit instruction encountered
+info: Launching CPU 1 @ 125036000
+Exiting @ tick 1902738973500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
index 6c5842787..25fe063e3 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/system.terminal
@@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles
 
SMP: 2 CPUs probed -- cpu_present_mask = 3
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
index d2daed3ce..d23f48fda 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/config.ini
@@ -8,10 +8,11 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
+children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 console=/dist/m5/system/binaries/console
 init_param=0
 kernel=/dist/m5/system/binaries/vmlinux
@@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=8796093022208:18446744073709551615
 req_size=16
@@ -44,6 +45,11 @@ resp_size=16
 master=system.iobus.slave[0]
 slave=system.membus.master[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
@@ -58,7 +64,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -137,11 +143,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -149,10 +153,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -163,12 +167,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -438,10 +451,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -452,12 +465,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -470,10 +492,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -484,16 +506,24 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -504,6 +534,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.disk0]
 type=IdeDisk
 children=image
@@ -550,8 +585,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -561,10 +595,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -575,17 +609,25 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -596,7 +638,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -614,19 +656,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -637,7 +684,6 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[1]
 
 [system.simple_disk]
@@ -666,7 +712,7 @@ system=system
 
 [system.tsunami.backdoor]
 type=AlphaBackdoor
-clock=1000
+clk_domain=system.clk_domain
 cpu=system.cpu
 disk=system.simple_disk
 pio_addr=8804682956800
@@ -678,7 +724,7 @@ pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8803072344064
 pio_latency=100000
 system=system
@@ -725,7 +771,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=2000
+clk_domain=system.clk_domain
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -756,7 +802,7 @@ pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -773,7 +819,7 @@ pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -790,7 +836,7 @@ pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -807,7 +853,7 @@ pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -824,7 +870,7 @@ pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -841,7 +887,7 @@ pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -858,7 +904,7 @@ pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -875,7 +921,7 @@ pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -892,7 +938,7 @@ pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -909,7 +955,7 @@ pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -926,7 +972,7 @@ pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -943,7 +989,7 @@ pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -960,7 +1006,7 @@ pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -977,7 +1023,7 @@ pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -994,7 +1040,7 @@ pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -1011,7 +1057,7 @@ pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -1028,7 +1074,7 @@ pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -1045,7 +1091,7 @@ pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -1062,7 +1108,7 @@ pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -1079,7 +1125,7 @@ pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
-clock=1000
+clk_domain=system.clk_domain
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=100000
@@ -1126,7 +1172,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
@@ -1143,7 +1189,7 @@ pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
-clock=1000
+clk_domain=system.clk_domain
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -1155,7 +1201,7 @@ pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8802535473152
 pio_latency=100000
 system=system
@@ -1165,7 +1211,8 @@ pio=system.iobus.master[1]
 [system.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.tsunami
 size=16777216
@@ -1174,7 +1221,7 @@ pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8804615848952
 pio_latency=100000
 platform=system.tsunami
@@ -1182,3 +1229,7 @@ system=system
 terminal=system.terminal
 pio=system.iobus.master[23]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
index e4e5656be..646f2a7f4 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 23:18:16
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:33:00
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3 -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1854315933000 because m5_exit instruction encountered
+Exiting @ tick 1860200687500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
index 1b4012ef1..f09f72d29 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-o3/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 32 cycles, load miss latency 115 cycles
+
4096K Bcache detected; load hit latency 30 cycles, load miss latency 134 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
index 84c3aa0ce..a2e0a4348 100644
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/config.ini
@@ -8,10 +8,11 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+children=bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 console=/dist/m5/system/binaries/console
 init_param=0
 kernel=/dist/m5/system/binaries/vmlinux
@@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=8796093022208:18446744073709551615
 req_size=16
@@ -44,12 +45,16 @@ resp_size=16
 master=system.iobus.slave[0]
 slave=system.membus.master[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -84,10 +89,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -98,22 +103,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -124,12 +138,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=AlphaInterrupts
 
@@ -145,10 +168,9 @@ type=ExeTracer
 
 [system.cpu1]
 type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer
-branchPred=Null
+children=dtb isa itb tracer
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -156,7 +178,7 @@ do_statistics_insts=true
 dtb=system.cpu1.dtb
 function_trace=false
 function_trace_start=0
-interrupts=system.cpu1.interrupts
+interrupts=Null
 isa=system.cpu1.isa
 itb=system.cpu1.itb
 max_insts_all_threads=0
@@ -176,9 +198,6 @@ workload=
 type=AlphaTLB
 size=64
 
-[system.cpu1.interrupts]
-type=AlphaInterrupts
-
 [system.cpu1.isa]
 type=AlphaISA
 
@@ -191,7 +210,7 @@ type=ExeTracer
 
 [system.cpu2]
 type=DerivO3CPU
-children=branchPred dtb fuPool interrupts isa itb tracer
+children=branchPred dtb fuPool isa itb tracer
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
@@ -203,7 +222,7 @@ backComSize=5
 branchPred=system.cpu2.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -229,7 +248,7 @@ iewToCommitDelay=1
 iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
-interrupts=system.cpu2.interrupts
+interrupts=Null
 isa=system.cpu2.isa
 issueToExecuteDelay=1
 issueWidth=8
@@ -280,11 +299,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -557,9 +574,6 @@ issueLat=3
 opClass=IprAccess
 opLat=3
 
-[system.cpu2.interrupts]
-type=AlphaInterrupts
-
 [system.cpu2.isa]
 type=AlphaISA
 
@@ -570,6 +584,11 @@ size=48
 [system.cpu2.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.disk0]
 type=IdeDisk
 children=image
@@ -616,8 +635,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -627,10 +645,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -641,18 +659,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -663,17 +690,25 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -684,7 +719,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -702,19 +737,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -725,7 +765,6 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[1]
 
 [system.simple_disk]
@@ -748,8 +787,7 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -765,7 +803,7 @@ system=system
 
 [system.tsunami.backdoor]
 type=AlphaBackdoor
-clock=1000
+clk_domain=system.clk_domain
 cpu=system.cpu0
 disk=system.simple_disk
 pio_addr=8804682956800
@@ -777,7 +815,7 @@ pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8803072344064
 pio_latency=100000
 system=system
@@ -824,7 +862,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=2000
+clk_domain=system.clk_domain
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -855,7 +893,7 @@ pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -872,7 +910,7 @@ pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -889,7 +927,7 @@ pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -906,7 +944,7 @@ pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -923,7 +961,7 @@ pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -940,7 +978,7 @@ pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -957,7 +995,7 @@ pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -974,7 +1012,7 @@ pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -991,7 +1029,7 @@ pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -1008,7 +1046,7 @@ pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -1025,7 +1063,7 @@ pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -1042,7 +1080,7 @@ pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -1059,7 +1097,7 @@ pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -1076,7 +1114,7 @@ pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -1093,7 +1131,7 @@ pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -1110,7 +1148,7 @@ pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -1127,7 +1165,7 @@ pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -1144,7 +1182,7 @@ pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -1161,7 +1199,7 @@ pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -1178,7 +1216,7 @@ pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
-clock=1000
+clk_domain=system.clk_domain
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=100000
@@ -1225,7 +1263,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
@@ -1242,7 +1280,7 @@ pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
-clock=1000
+clk_domain=system.clk_domain
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -1254,7 +1292,7 @@ pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8802535473152
 pio_latency=100000
 system=system
@@ -1264,7 +1302,8 @@ pio=system.iobus.master[1]
 [system.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.tsunami
 size=16777216
@@ -1273,7 +1312,7 @@ pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8804615848952
 pio_latency=100000
 platform=system.tsunami
@@ -1281,3 +1320,7 @@ system=system
 terminal=system.terminal
 pio=system.iobus.master[23]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
index 9227d5948..bb27cc97c 100755
--- a/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/alpha/linux/tsunami-switcheroo-full/simout
@@ -1,14 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 23:27:13
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:34:17
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-switcheroo-full
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 Switching CPUs...
@@ -18,207 +16,201 @@ info: Entering event queue @ 1000000000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 info: Entering event queue @ 2000000000.  Starting simulation...
-info: Entering event queue @ 2000003000.  Starting simulation...
+info: Entering event queue @ 2000005000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2000005500.  Starting simulation...
+info: Entering event queue @ 2000007000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3000005500.  Starting simulation...
+info: Entering event queue @ 3000007000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 3000041000.  Starting simulation...
+info: Entering event queue @ 3000031000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 4000041000.  Starting simulation...
+info: Entering event queue @ 4000031000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 5000041000.  Starting simulation...
-info: Entering event queue @ 5000053000.  Starting simulation...
+info: Entering event queue @ 5000031000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 5000056500.  Starting simulation...
+info: Entering event queue @ 5000032000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000056500.  Starting simulation...
-info: Entering event queue @ 7458944500.  Starting simulation...
-info: Entering event queue @ 7459012000.  Starting simulation...
+info: Entering event queue @ 6000032000.  Starting simulation...
+info: Entering event queue @ 7566911500.  Starting simulation...
+info: Entering event queue @ 7566971250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 7459016500.  Starting simulation...
+info: Entering event queue @ 7566976000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 8459016500.  Starting simulation...
+info: Entering event queue @ 8566976000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 9459016500.  Starting simulation...
+info: Entering event queue @ 9566976000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 9459024000.  Starting simulation...
+info: Entering event queue @ 9566983500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 10459024000.  Starting simulation...
+info: Entering event queue @ 10566983500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 10459031500.  Starting simulation...
+info: Entering event queue @ 10567083000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 11459031500.  Starting simulation...
+info: Entering event queue @ 11567083000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 12459031500.  Starting simulation...
-info: Entering event queue @ 12459047000.  Starting simulation...
+info: Entering event queue @ 12567083000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 12459242750.  Starting simulation...
+info: Entering event queue @ 12567090500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 13459242750.  Starting simulation...
-info: Entering event queue @ 13459250250.  Starting simulation...
-info: Entering event queue @ 13459254000.  Starting simulation...
+info: Entering event queue @ 13567090500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 13459258500.  Starting simulation...
+info: Entering event queue @ 13567098000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 14459258500.  Starting simulation...
+info: Entering event queue @ 14567098000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 15459258500.  Starting simulation...
+info: Entering event queue @ 15567098000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 15459266000.  Starting simulation...
+info: Entering event queue @ 15567105500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 16459266000.  Starting simulation...
+info: Entering event queue @ 16567105500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 16459273500.  Starting simulation...
+info: Entering event queue @ 16567113000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 17459273500.  Starting simulation...
+info: Entering event queue @ 17567113000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 18459273500.  Starting simulation...
-info: Entering event queue @ 18459284000.  Starting simulation...
+info: Entering event queue @ 18567113000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 18459287500.  Starting simulation...
+info: Entering event queue @ 18567120500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 19459287500.  Starting simulation...
+info: Entering event queue @ 19567120500.  Starting simulation...
+info: Entering event queue @ 19567148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 19459295000.  Starting simulation...
+info: Entering event queue @ 19567153500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 20459295000.  Starting simulation...
+info: Entering event queue @ 20567153500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 21459295000.  Starting simulation...
+info: Entering event queue @ 21567153500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 21459296000.  Starting simulation...
+info: Entering event queue @ 21567161000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 22459296000.  Starting simulation...
+info: Entering event queue @ 22567161000.  Starting simulation...
+info: Entering event queue @ 22567173500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 22459303500.  Starting simulation...
+info: Entering event queue @ 22567179000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 23459303500.  Starting simulation...
+info: Entering event queue @ 23567179000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 24459303500.  Starting simulation...
+info: Entering event queue @ 24567179000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 24459311000.  Starting simulation...
+info: Entering event queue @ 24567186500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 25459311000.  Starting simulation...
-info: Entering event queue @ 25459330000.  Starting simulation...
-info: Entering event queue @ 25459339500.  Starting simulation...
-info: Entering event queue @ 25459344000.  Starting simulation...
+info: Entering event queue @ 25567186500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 25459345000.  Starting simulation...
+info: Entering event queue @ 25567194000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 26459345000.  Starting simulation...
+info: Entering event queue @ 26567194000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 27459345000.  Starting simulation...
-info: Entering event queue @ 27459352500.  Starting simulation...
+info: Entering event queue @ 27567194000.  Starting simulation...
+info: Entering event queue @ 27567201500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 27459355500.  Starting simulation...
+info: Entering event queue @ 27567202500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 28459355500.  Starting simulation...
-info: Entering event queue @ 28459377000.  Starting simulation...
+info: Entering event queue @ 28567202500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 28459573000.  Starting simulation...
+info: Entering event queue @ 28567210000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 29459573000.  Starting simulation...
+info: Entering event queue @ 29567210000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 30459573000.  Starting simulation...
+info: Entering event queue @ 30567210000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 30459580500.  Starting simulation...
+info: Entering event queue @ 30567217500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 31459580500.  Starting simulation...
-info: Entering event queue @ 31459590000.  Starting simulation...
+info: Entering event queue @ 31567217500.  Starting simulation...
+info: Entering event queue @ 31567226000.  Starting simulation...
+info: Entering event queue @ 31567232000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 31459594500.  Starting simulation...
+info: Entering event queue @ 31567236500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 32459594500.  Starting simulation...
+info: Entering event queue @ 32567236500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 33459594500.  Starting simulation...
+info: Entering event queue @ 33567236500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 33459602000.  Starting simulation...
+info: Entering event queue @ 33567244000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 34459602000.  Starting simulation...
+info: Entering event queue @ 34567244000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 34459605000.  Starting simulation...
+info: Entering event queue @ 34567251500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 35459605000.  Starting simulation...
+info: Entering event queue @ 35567251500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 36459605000.  Starting simulation...
+info: Entering event queue @ 36567251500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 36459612500.  Starting simulation...
+info: Entering event queue @ 36567259000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 37459612500.  Starting simulation...
+info: Entering event queue @ 37567259000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 37459615500.  Starting simulation...
+info: Entering event queue @ 37567266500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 38459615500.  Starting simulation...
+info: Entering event queue @ 38567266500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 39459615500.  Starting simulation...
+info: Entering event queue @ 39567266500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 39459623000.  Starting simulation...
+info: Entering event queue @ 39567274000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 40459623000.  Starting simulation...
+info: Entering event queue @ 40567274000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 40459626000.  Starting simulation...
+info: Entering event queue @ 40567277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 41459626000.  Starting simulation...
+info: Entering event queue @ 41567277000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 42459626000.  Starting simulation...
+info: Entering event queue @ 42567277000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 42459633500.  Starting simulation...
+info: Entering event queue @ 42567284500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 43459633500.  Starting simulation...
+info: Entering event queue @ 43567284500.  Starting simulation...
 switching cpus
 info: Entering event queue @ 43945335500.  Starting simulation...
 Switching CPUs...
@@ -565,11 +557,12 @@ switching cpus
 info: Entering event queue @ 146507835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-switching cpus
 info: Entering event queue @ 147507835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 147507843000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 148507835500.  Starting simulation...
+info: Entering event queue @ 148507843000.  Starting simulation...
 switching cpus
 info: Entering event queue @ 149414085500.  Starting simulation...
 Switching CPUs...
@@ -916,11 +909,12 @@ switching cpus
 info: Entering event queue @ 251976585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-switching cpus
 info: Entering event queue @ 252976585500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 252976593000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 253976585500.  Starting simulation...
+info: Entering event queue @ 253976593000.  Starting simulation...
 switching cpus
 info: Entering event queue @ 254882835500.  Starting simulation...
 Switching CPUs...
@@ -1091,5164 +1085,5170 @@ Switching CPUs...
 Next CPU: AtomicSimpleCPU
 info: Entering event queue @ 304757835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 304757908000.  Starting simulation...
+info: Entering event queue @ 305664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 305757908000.  Starting simulation...
+info: Entering event queue @ 306664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 306757908000.  Starting simulation...
+info: Entering event queue @ 307664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 307757908000.  Starting simulation...
+info: Entering event queue @ 308664085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 308593773000.  Starting simulation...
+info: Entering event queue @ 309570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 309593773000.  Starting simulation...
+info: Entering event queue @ 310570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 310593773000.  Starting simulation...
+info: Entering event queue @ 311570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 311593773000.  Starting simulation...
+info: Entering event queue @ 312570335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 312500023000.  Starting simulation...
+info: Entering event queue @ 313476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 313500023000.  Starting simulation...
+info: Entering event queue @ 314476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 314500023000.  Starting simulation...
+info: Entering event queue @ 315476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 315500023000.  Starting simulation...
+info: Entering event queue @ 316476585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 316406273000.  Starting simulation...
+info: Entering event queue @ 317382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 317406273000.  Starting simulation...
+info: Entering event queue @ 318382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 318406273000.  Starting simulation...
+info: Entering event queue @ 319382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 319406273000.  Starting simulation...
+info: Entering event queue @ 320382835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 320312523000.  Starting simulation...
+info: Entering event queue @ 321289085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 321312523000.  Starting simulation...
+info: Entering event queue @ 322289085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 322312523000.  Starting simulation...
+info: Entering event queue @ 323289085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 323312523000.  Starting simulation...
+info: Entering event queue @ 324289085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 324218773000.  Starting simulation...
+info: Entering event queue @ 325195335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 325218773000.  Starting simulation...
+info: Entering event queue @ 326195335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 326218773000.  Starting simulation...
+info: Entering event queue @ 327195335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 327218773000.  Starting simulation...
+info: Entering event queue @ 328195335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 328125023000.  Starting simulation...
+info: Entering event queue @ 329101585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 329125023000.  Starting simulation...
+info: Entering event queue @ 330101585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 330125023000.  Starting simulation...
+info: Entering event queue @ 331101585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 331125023000.  Starting simulation...
+info: Entering event queue @ 332101585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 332031273000.  Starting simulation...
+info: Entering event queue @ 333007835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 333031273000.  Starting simulation...
+info: Entering event queue @ 334007835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 334031273000.  Starting simulation...
+info: Entering event queue @ 335007835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 335031273000.  Starting simulation...
+info: Entering event queue @ 336007835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 335937523000.  Starting simulation...
+info: Entering event queue @ 336914085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 336937523000.  Starting simulation...
+info: Entering event queue @ 337914085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 337937523000.  Starting simulation...
+info: Entering event queue @ 338914085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 338937523000.  Starting simulation...
+info: Entering event queue @ 339914085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 339843773000.  Starting simulation...
+info: Entering event queue @ 340820335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 340843773000.  Starting simulation...
+info: Entering event queue @ 341820335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 341843773000.  Starting simulation...
+info: Entering event queue @ 342820335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 342843773000.  Starting simulation...
+info: Entering event queue @ 343820335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 343750023000.  Starting simulation...
+info: Entering event queue @ 344726585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 344750023000.  Starting simulation...
+info: Entering event queue @ 345726585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 345750023000.  Starting simulation...
+info: Entering event queue @ 346726585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 346750023000.  Starting simulation...
+info: Entering event queue @ 347726585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 347656273000.  Starting simulation...
+info: Entering event queue @ 348632835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 348656273000.  Starting simulation...
+info: Entering event queue @ 349632835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 349656273000.  Starting simulation...
+info: Entering event queue @ 350632835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 350656273000.  Starting simulation...
+info: Entering event queue @ 351632835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 351562523000.  Starting simulation...
+info: Entering event queue @ 352539085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 352562523000.  Starting simulation...
+info: Entering event queue @ 353539085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 353562523000.  Starting simulation...
+info: Entering event queue @ 354539085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 354562523000.  Starting simulation...
+info: Entering event queue @ 355539085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 355468773000.  Starting simulation...
+info: Entering event queue @ 356445335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 356468773000.  Starting simulation...
+info: Entering event queue @ 357445335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 357468773000.  Starting simulation...
+info: Entering event queue @ 358445335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 358468773000.  Starting simulation...
+info: Entering event queue @ 359445335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 359375023000.  Starting simulation...
+info: Entering event queue @ 360351585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 360375023000.  Starting simulation...
+info: Entering event queue @ 361351585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 361375023000.  Starting simulation...
+info: Entering event queue @ 362351585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 362375023000.  Starting simulation...
+info: Entering event queue @ 363351585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 363281273000.  Starting simulation...
+info: Entering event queue @ 364257835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 364281273000.  Starting simulation...
+info: Entering event queue @ 365257835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 365281273000.  Starting simulation...
+info: Entering event queue @ 366257835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 366281273000.  Starting simulation...
+info: Entering event queue @ 367257835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 367187523000.  Starting simulation...
+info: Entering event queue @ 368164085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 368187523000.  Starting simulation...
+info: Entering event queue @ 369164085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 369187523000.  Starting simulation...
+info: Entering event queue @ 370164085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 370187523000.  Starting simulation...
+info: Entering event queue @ 371164085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 371093773000.  Starting simulation...
+info: Entering event queue @ 372070335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 372093773000.  Starting simulation...
+info: Entering event queue @ 373070335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 373093773000.  Starting simulation...
+info: Entering event queue @ 374070335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 374093773000.  Starting simulation...
+info: Entering event queue @ 375070335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 375000023000.  Starting simulation...
+info: Entering event queue @ 375976585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 376000023000.  Starting simulation...
+info: Entering event queue @ 376976585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 377000023000.  Starting simulation...
+info: Entering event queue @ 377976585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 378000023000.  Starting simulation...
+info: Entering event queue @ 378976585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 378906273000.  Starting simulation...
+info: Entering event queue @ 379882835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 379906273000.  Starting simulation...
+info: Entering event queue @ 380882835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 380906273000.  Starting simulation...
+info: Entering event queue @ 381882835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 381906273000.  Starting simulation...
+info: Entering event queue @ 382882835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 382812523000.  Starting simulation...
+info: Entering event queue @ 383789085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 383812523000.  Starting simulation...
+info: Entering event queue @ 384789085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 384812523000.  Starting simulation...
+info: Entering event queue @ 385789085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 385812523000.  Starting simulation...
+info: Entering event queue @ 386789085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 386718773000.  Starting simulation...
+info: Entering event queue @ 387695335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 387718773000.  Starting simulation...
+info: Entering event queue @ 388695335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 388718773000.  Starting simulation...
+info: Entering event queue @ 389695335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 389718773000.  Starting simulation...
+info: Entering event queue @ 390695335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 390625023000.  Starting simulation...
+info: Entering event queue @ 391601585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 391625023000.  Starting simulation...
+info: Entering event queue @ 392601585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 392625023000.  Starting simulation...
+info: Entering event queue @ 393601585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 393625023000.  Starting simulation...
+info: Entering event queue @ 394601585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 394531273000.  Starting simulation...
+info: Entering event queue @ 395507835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 395531273000.  Starting simulation...
+info: Entering event queue @ 396507835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 396531273000.  Starting simulation...
+info: Entering event queue @ 397507835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 397531273000.  Starting simulation...
+info: Entering event queue @ 398507835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 398437523000.  Starting simulation...
+info: Entering event queue @ 399414085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 399437523000.  Starting simulation...
+info: Entering event queue @ 400414085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 400437523000.  Starting simulation...
+info: Entering event queue @ 401414085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 401437523000.  Starting simulation...
+info: Entering event queue @ 402414085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 402343773000.  Starting simulation...
+info: Entering event queue @ 403320335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 403343773000.  Starting simulation...
+info: Entering event queue @ 404320335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 404343773000.  Starting simulation...
+info: Entering event queue @ 405320335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 405343773000.  Starting simulation...
+info: Entering event queue @ 406320335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 406250023000.  Starting simulation...
+info: Entering event queue @ 407226585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 407250023000.  Starting simulation...
+info: Entering event queue @ 408226585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 408250023000.  Starting simulation...
+info: Entering event queue @ 409226585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 409250023000.  Starting simulation...
+info: Entering event queue @ 410226585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 410156273000.  Starting simulation...
+info: Entering event queue @ 411132835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 411156273000.  Starting simulation...
+info: Entering event queue @ 412132835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 412156273000.  Starting simulation...
+info: Entering event queue @ 413132835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 413156273000.  Starting simulation...
+info: Entering event queue @ 414132835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 414062523000.  Starting simulation...
+info: Entering event queue @ 415039085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 415062523000.  Starting simulation...
+info: Entering event queue @ 416039085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 416062523000.  Starting simulation...
+info: Entering event queue @ 417039085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 417062523000.  Starting simulation...
+info: Entering event queue @ 418039085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 417968773000.  Starting simulation...
+info: Entering event queue @ 418945335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 418968773000.  Starting simulation...
+info: Entering event queue @ 419945335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 419968773000.  Starting simulation...
+info: Entering event queue @ 420945335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 420968773000.  Starting simulation...
+info: Entering event queue @ 421945335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 421875023000.  Starting simulation...
+info: Entering event queue @ 422851585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 422875023000.  Starting simulation...
+info: Entering event queue @ 423851585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 423875023000.  Starting simulation...
+info: Entering event queue @ 424851585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 424875023000.  Starting simulation...
+info: Entering event queue @ 425851585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 425781273000.  Starting simulation...
+info: Entering event queue @ 426757835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 426781273000.  Starting simulation...
+info: Entering event queue @ 427757835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 427781273000.  Starting simulation...
+info: Entering event queue @ 428757835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 428781273000.  Starting simulation...
+info: Entering event queue @ 429757835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 429687523000.  Starting simulation...
+info: Entering event queue @ 430664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 430687523000.  Starting simulation...
+info: Entering event queue @ 431664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 431687523000.  Starting simulation...
+info: Entering event queue @ 432664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 432687523000.  Starting simulation...
+info: Entering event queue @ 433664085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 433593773000.  Starting simulation...
+info: Entering event queue @ 434570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 434593773000.  Starting simulation...
+info: Entering event queue @ 435570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 435593773000.  Starting simulation...
+info: Entering event queue @ 436570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 436593773000.  Starting simulation...
+info: Entering event queue @ 437570335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 437500023000.  Starting simulation...
+info: Entering event queue @ 438476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 438500023000.  Starting simulation...
+info: Entering event queue @ 439476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 439500023000.  Starting simulation...
+info: Entering event queue @ 440476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 440500023000.  Starting simulation...
+info: Entering event queue @ 441476585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 441406273000.  Starting simulation...
+info: Entering event queue @ 442382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 442406273000.  Starting simulation...
+info: Entering event queue @ 443382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 443406273000.  Starting simulation...
+info: Entering event queue @ 444382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 444406273000.  Starting simulation...
+info: Entering event queue @ 445382835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 445312523000.  Starting simulation...
+info: Entering event queue @ 446289085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 446312523000.  Starting simulation...
+info: Entering event queue @ 447289085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 447312523000.  Starting simulation...
+info: Entering event queue @ 448289085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 448312523000.  Starting simulation...
+info: Entering event queue @ 449289085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 449218773000.  Starting simulation...
+info: Entering event queue @ 450195335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 450218773000.  Starting simulation...
+info: Entering event queue @ 451195335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 451218773000.  Starting simulation...
+info: Entering event queue @ 452195335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 452218773000.  Starting simulation...
+info: Entering event queue @ 453195335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 453125023000.  Starting simulation...
+info: Entering event queue @ 454101585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 454125023000.  Starting simulation...
+info: Entering event queue @ 455101585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 455125023000.  Starting simulation...
+info: Entering event queue @ 456101585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 456125023000.  Starting simulation...
+info: Entering event queue @ 457101585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 457031273000.  Starting simulation...
+info: Entering event queue @ 458007835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 458031273000.  Starting simulation...
+info: Entering event queue @ 459007835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 459031273000.  Starting simulation...
+info: Entering event queue @ 460007835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 460031273000.  Starting simulation...
+info: Entering event queue @ 461007835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 460937523000.  Starting simulation...
+info: Entering event queue @ 461914085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 461937523000.  Starting simulation...
+info: Entering event queue @ 462914085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 462937523000.  Starting simulation...
+info: Entering event queue @ 463914085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 463937523000.  Starting simulation...
+info: Entering event queue @ 464914085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 464843773000.  Starting simulation...
+info: Entering event queue @ 465820335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 465843773000.  Starting simulation...
+info: Entering event queue @ 466820335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 466843773000.  Starting simulation...
+info: Entering event queue @ 467820335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 467843773000.  Starting simulation...
+info: Entering event queue @ 468820335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 468750023000.  Starting simulation...
+info: Entering event queue @ 469726585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 469750023000.  Starting simulation...
+info: Entering event queue @ 470726585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 470750023000.  Starting simulation...
+info: Entering event queue @ 471726585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 471750023000.  Starting simulation...
+info: Entering event queue @ 472726585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 472656273000.  Starting simulation...
+info: Entering event queue @ 473632835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 473656273000.  Starting simulation...
+info: Entering event queue @ 474632835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 474656273000.  Starting simulation...
+info: Entering event queue @ 475632835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 475656273000.  Starting simulation...
+info: Entering event queue @ 476632835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 476562523000.  Starting simulation...
+info: Entering event queue @ 477539085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 477562523000.  Starting simulation...
+info: Entering event queue @ 478539085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 478562523000.  Starting simulation...
+info: Entering event queue @ 479539085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 479562523000.  Starting simulation...
+info: Entering event queue @ 480539085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 480468773000.  Starting simulation...
+info: Entering event queue @ 481445335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 481468773000.  Starting simulation...
+info: Entering event queue @ 482445335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 482468773000.  Starting simulation...
+info: Entering event queue @ 483445335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 483468773000.  Starting simulation...
+info: Entering event queue @ 484445335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 484375023000.  Starting simulation...
+info: Entering event queue @ 485351585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 485375023000.  Starting simulation...
+info: Entering event queue @ 486351585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 486375023000.  Starting simulation...
+info: Entering event queue @ 487351585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 487375023000.  Starting simulation...
+info: Entering event queue @ 488351585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 488281273000.  Starting simulation...
+info: Entering event queue @ 489257835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 489281273000.  Starting simulation...
+info: Entering event queue @ 490257835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 490281273000.  Starting simulation...
+info: Entering event queue @ 491257835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 491281273000.  Starting simulation...
+info: Entering event queue @ 492257835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 492187523000.  Starting simulation...
+info: Entering event queue @ 493164085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 493187523000.  Starting simulation...
+info: Entering event queue @ 494164085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 494187523000.  Starting simulation...
+info: Entering event queue @ 495164085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 495187523000.  Starting simulation...
+info: Entering event queue @ 496164085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 496093773000.  Starting simulation...
+info: Entering event queue @ 497070335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 497093773000.  Starting simulation...
+info: Entering event queue @ 498070335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 498093773000.  Starting simulation...
+info: Entering event queue @ 499070335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 499093773000.  Starting simulation...
+info: Entering event queue @ 500070335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 500000023000.  Starting simulation...
+info: Entering event queue @ 500976585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 501000023000.  Starting simulation...
+info: Entering event queue @ 501976585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 502000023000.  Starting simulation...
+info: Entering event queue @ 502976585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 503000023000.  Starting simulation...
+info: Entering event queue @ 503976585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 503906273000.  Starting simulation...
+info: Entering event queue @ 504882835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 504906273000.  Starting simulation...
+info: Entering event queue @ 505882835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 505906273000.  Starting simulation...
+info: Entering event queue @ 506882835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 506906273000.  Starting simulation...
+info: Entering event queue @ 507882835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 507812523000.  Starting simulation...
+info: Entering event queue @ 508789085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 508812523000.  Starting simulation...
+info: Entering event queue @ 509789085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 509812523000.  Starting simulation...
+info: Entering event queue @ 510789085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 510812523000.  Starting simulation...
+info: Entering event queue @ 511789085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 511718773000.  Starting simulation...
+info: Entering event queue @ 512695335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 512718773000.  Starting simulation...
+info: Entering event queue @ 513695335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 513718773000.  Starting simulation...
+info: Entering event queue @ 514695335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 514718773000.  Starting simulation...
+info: Entering event queue @ 515695335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 515625023000.  Starting simulation...
+info: Entering event queue @ 516601585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 516625023000.  Starting simulation...
+info: Entering event queue @ 517601585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 517625023000.  Starting simulation...
+info: Entering event queue @ 518601585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 518625023000.  Starting simulation...
+info: Entering event queue @ 519601585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 519531273000.  Starting simulation...
+info: Entering event queue @ 520507835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 520531273000.  Starting simulation...
+info: Entering event queue @ 521507835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 521531273000.  Starting simulation...
+info: Entering event queue @ 522507835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 522531273000.  Starting simulation...
+info: Entering event queue @ 523507835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 523437523000.  Starting simulation...
+info: Entering event queue @ 524414085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 524437523000.  Starting simulation...
+info: Entering event queue @ 525414085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 525437523000.  Starting simulation...
+info: Entering event queue @ 526414085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 526437523000.  Starting simulation...
+info: Entering event queue @ 527414085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 527343773000.  Starting simulation...
+info: Entering event queue @ 528320335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 528343773000.  Starting simulation...
+info: Entering event queue @ 529320335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 529343773000.  Starting simulation...
+info: Entering event queue @ 530320335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 530343773000.  Starting simulation...
+info: Entering event queue @ 531320335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 531250023000.  Starting simulation...
+info: Entering event queue @ 532226585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 532250023000.  Starting simulation...
+info: Entering event queue @ 533226585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 533250023000.  Starting simulation...
+info: Entering event queue @ 534226585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 534250023000.  Starting simulation...
+info: Entering event queue @ 535226585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 535156273000.  Starting simulation...
+info: Entering event queue @ 536132835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 536156273000.  Starting simulation...
+info: Entering event queue @ 537132835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 537156273000.  Starting simulation...
+info: Entering event queue @ 538132835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 538156273000.  Starting simulation...
+info: Entering event queue @ 539132835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 539062523000.  Starting simulation...
+info: Entering event queue @ 540039085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 540062523000.  Starting simulation...
+info: Entering event queue @ 541039085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 541062523000.  Starting simulation...
+info: Entering event queue @ 542039085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 542062523000.  Starting simulation...
+info: Entering event queue @ 543039085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 542968773000.  Starting simulation...
+info: Entering event queue @ 543945335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 543968773000.  Starting simulation...
+info: Entering event queue @ 544945335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 544968773000.  Starting simulation...
+info: Entering event queue @ 545945335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 545968773000.  Starting simulation...
+info: Entering event queue @ 546945335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 546875023000.  Starting simulation...
+info: Entering event queue @ 547851585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 547875023000.  Starting simulation...
+info: Entering event queue @ 548851585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 548875023000.  Starting simulation...
+info: Entering event queue @ 549851585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 549875023000.  Starting simulation...
+info: Entering event queue @ 550851585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 550781273000.  Starting simulation...
+info: Entering event queue @ 551757835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 551781273000.  Starting simulation...
+info: Entering event queue @ 552757835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 552781273000.  Starting simulation...
+info: Entering event queue @ 553757835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 553781273000.  Starting simulation...
+info: Entering event queue @ 554757835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 554687523000.  Starting simulation...
+info: Entering event queue @ 555664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 555687523000.  Starting simulation...
+info: Entering event queue @ 556664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 556687523000.  Starting simulation...
+info: Entering event queue @ 557664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 557687523000.  Starting simulation...
+info: Entering event queue @ 558664085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 558593773000.  Starting simulation...
+info: Entering event queue @ 559570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 559593773000.  Starting simulation...
+info: Entering event queue @ 560570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 560593773000.  Starting simulation...
+info: Entering event queue @ 561570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 561593773000.  Starting simulation...
+info: Entering event queue @ 562570335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 562500023000.  Starting simulation...
+info: Entering event queue @ 563476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 563500023000.  Starting simulation...
+info: Entering event queue @ 564476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 564500023000.  Starting simulation...
+info: Entering event queue @ 565476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 565500023000.  Starting simulation...
+info: Entering event queue @ 566476585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 566406273000.  Starting simulation...
+info: Entering event queue @ 567382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 567406273000.  Starting simulation...
+info: Entering event queue @ 568382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 568406273000.  Starting simulation...
+info: Entering event queue @ 569382835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 568406377000.  Starting simulation...
+info: Entering event queue @ 569382939000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 569406377000.  Starting simulation...
+info: Entering event queue @ 570382939000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 570312523000.  Starting simulation...
+info: Entering event queue @ 571289085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 571312523000.  Starting simulation...
+info: Entering event queue @ 572289085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 572312523000.  Starting simulation...
+info: Entering event queue @ 573289085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 573312523000.  Starting simulation...
+info: Entering event queue @ 574289085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 574218773000.  Starting simulation...
+info: Entering event queue @ 575195335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 575218773000.  Starting simulation...
+info: Entering event queue @ 576195335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 576218773000.  Starting simulation...
+info: Entering event queue @ 577195335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 577218773000.  Starting simulation...
+info: Entering event queue @ 578195335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 578125023000.  Starting simulation...
+info: Entering event queue @ 579101585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 579125023000.  Starting simulation...
+info: Entering event queue @ 580101585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 580125023000.  Starting simulation...
+info: Entering event queue @ 581101585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 581125023000.  Starting simulation...
+info: Entering event queue @ 582101585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 582031273000.  Starting simulation...
+info: Entering event queue @ 583007835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 583031273000.  Starting simulation...
+info: Entering event queue @ 584007835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 584031273000.  Starting simulation...
+info: Entering event queue @ 585007835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 585031273000.  Starting simulation...
+info: Entering event queue @ 586007835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 585937523000.  Starting simulation...
+info: Entering event queue @ 586914085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 586937523000.  Starting simulation...
+info: Entering event queue @ 587914085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 587937523000.  Starting simulation...
+info: Entering event queue @ 588914085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 588937523000.  Starting simulation...
+info: Entering event queue @ 589914085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 589843773000.  Starting simulation...
+info: Entering event queue @ 590820335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 590843773000.  Starting simulation...
+info: Entering event queue @ 591820335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 591843773000.  Starting simulation...
+info: Entering event queue @ 592820335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 592843773000.  Starting simulation...
+info: Entering event queue @ 593820335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 593750023000.  Starting simulation...
+info: Entering event queue @ 594726585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 594750023000.  Starting simulation...
+info: Entering event queue @ 595726585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 595750023000.  Starting simulation...
+info: Entering event queue @ 596726585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 596750023000.  Starting simulation...
+info: Entering event queue @ 597726585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 597656273000.  Starting simulation...
+info: Entering event queue @ 598632835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 598656273000.  Starting simulation...
+info: Entering event queue @ 599632835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 599656273000.  Starting simulation...
+info: Entering event queue @ 600632835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 600656273000.  Starting simulation...
+info: Entering event queue @ 601632835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 601562523000.  Starting simulation...
+info: Entering event queue @ 602539085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 602562523000.  Starting simulation...
+info: Entering event queue @ 603539085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 603562523000.  Starting simulation...
+info: Entering event queue @ 604539085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 604562523000.  Starting simulation...
+info: Entering event queue @ 605539085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 605468773000.  Starting simulation...
+info: Entering event queue @ 606445335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 606468773000.  Starting simulation...
+info: Entering event queue @ 607445335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 607468773000.  Starting simulation...
+info: Entering event queue @ 608445335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 608468773000.  Starting simulation...
+info: Entering event queue @ 609445335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 609375023000.  Starting simulation...
+info: Entering event queue @ 610351585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 610375023000.  Starting simulation...
+info: Entering event queue @ 611351585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 611375023000.  Starting simulation...
+info: Entering event queue @ 612351585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 612375023000.  Starting simulation...
+info: Entering event queue @ 613351585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 613281273000.  Starting simulation...
+info: Entering event queue @ 614257835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 614281273000.  Starting simulation...
+info: Entering event queue @ 615257835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 615281273000.  Starting simulation...
+info: Entering event queue @ 616257835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 616281273000.  Starting simulation...
+info: Entering event queue @ 617257835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 617187523000.  Starting simulation...
+info: Entering event queue @ 618164085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 618187523000.  Starting simulation...
+info: Entering event queue @ 619164085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 619187523000.  Starting simulation...
+info: Entering event queue @ 620164085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 620187523000.  Starting simulation...
+info: Entering event queue @ 621164085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 621093773000.  Starting simulation...
+info: Entering event queue @ 622070335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 622093773000.  Starting simulation...
+info: Entering event queue @ 623070335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 623093773000.  Starting simulation...
+info: Entering event queue @ 624070335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 623093773500.  Starting simulation...
+info: Entering event queue @ 624070336500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 624093773500.  Starting simulation...
+info: Entering event queue @ 625070336500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 624218753000.  Starting simulation...
+info: Entering event queue @ 625195317000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 625218753000.  Starting simulation...
+info: Entering event queue @ 626195317000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 626218753000.  Starting simulation...
+info: Entering event queue @ 627195317000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 627218753000.  Starting simulation...
+info: Entering event queue @ 628195317000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 627929709000.  Starting simulation...
+info: Entering event queue @ 628906271500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 628929709000.  Starting simulation...
+info: Entering event queue @ 629906271500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 629929709000.  Starting simulation...
+info: Entering event queue @ 630906271500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 630929709000.  Starting simulation...
+info: Entering event queue @ 631906271500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 631835960500.  Starting simulation...
+info: Entering event queue @ 632812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 632835960500.  Starting simulation...
+info: Entering event queue @ 633812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 633835960500.  Starting simulation...
+info: Entering event queue @ 634812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 634835960500.  Starting simulation...
+info: Entering event queue @ 635812523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 635742210500.  Starting simulation...
+info: Entering event queue @ 636718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 636742210500.  Starting simulation...
+info: Entering event queue @ 637718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 637742210500.  Starting simulation...
+info: Entering event queue @ 638718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 638742210500.  Starting simulation...
+info: Entering event queue @ 639718773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 639648460500.  Starting simulation...
+info: Entering event queue @ 640625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 640648460500.  Starting simulation...
+info: Entering event queue @ 641625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 641648460500.  Starting simulation...
+info: Entering event queue @ 642625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 642648460500.  Starting simulation...
+info: Entering event queue @ 643625023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 643554710500.  Starting simulation...
+info: Entering event queue @ 644531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 644554710500.  Starting simulation...
+info: Entering event queue @ 645531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 645554710500.  Starting simulation...
+info: Entering event queue @ 646531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 646554710500.  Starting simulation...
+info: Entering event queue @ 647531273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 647460960500.  Starting simulation...
+info: Entering event queue @ 648437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 648460960500.  Starting simulation...
+info: Entering event queue @ 649437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 649460960500.  Starting simulation...
+info: Entering event queue @ 650437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 650460960500.  Starting simulation...
+info: Entering event queue @ 651437523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 651367210500.  Starting simulation...
+info: Entering event queue @ 652343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 652367210500.  Starting simulation...
+info: Entering event queue @ 653343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 653367210500.  Starting simulation...
+info: Entering event queue @ 654343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 654367210500.  Starting simulation...
+info: Entering event queue @ 655343773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 655273460500.  Starting simulation...
+info: Entering event queue @ 656250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 656273460500.  Starting simulation...
+info: Entering event queue @ 657250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 657273460500.  Starting simulation...
+info: Entering event queue @ 658250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 658273460500.  Starting simulation...
+info: Entering event queue @ 659250023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 659179710500.  Starting simulation...
+info: Entering event queue @ 660156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 660179710500.  Starting simulation...
+info: Entering event queue @ 661156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 661179710500.  Starting simulation...
+info: Entering event queue @ 662156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 662179710500.  Starting simulation...
+info: Entering event queue @ 663156273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 663085960500.  Starting simulation...
+info: Entering event queue @ 664062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 664085960500.  Starting simulation...
+info: Entering event queue @ 665062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 665085960500.  Starting simulation...
+info: Entering event queue @ 666062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 666085960500.  Starting simulation...
+info: Entering event queue @ 667062523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 666992210500.  Starting simulation...
+info: Entering event queue @ 667968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 667992210500.  Starting simulation...
+info: Entering event queue @ 668968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 668992210500.  Starting simulation...
+info: Entering event queue @ 669968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 669992210500.  Starting simulation...
+info: Entering event queue @ 670968773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 670898460500.  Starting simulation...
+info: Entering event queue @ 671875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 671898460500.  Starting simulation...
+info: Entering event queue @ 672875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 672898460500.  Starting simulation...
+info: Entering event queue @ 673875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 673898460500.  Starting simulation...
+info: Entering event queue @ 674875023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 674804710500.  Starting simulation...
+info: Entering event queue @ 675781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 675804710500.  Starting simulation...
+info: Entering event queue @ 676781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 676804710500.  Starting simulation...
+info: Entering event queue @ 677781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 677804710500.  Starting simulation...
+info: Entering event queue @ 678781273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 678710960500.  Starting simulation...
+info: Entering event queue @ 679687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 679710960500.  Starting simulation...
+info: Entering event queue @ 680687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 680710960500.  Starting simulation...
+info: Entering event queue @ 681687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 681710960500.  Starting simulation...
+info: Entering event queue @ 682687523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 682617210500.  Starting simulation...
+info: Entering event queue @ 683593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 683617210500.  Starting simulation...
+info: Entering event queue @ 684593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 684617210500.  Starting simulation...
+info: Entering event queue @ 685593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 685617210500.  Starting simulation...
+info: Entering event queue @ 686593773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 686523460500.  Starting simulation...
+info: Entering event queue @ 687500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 687523460500.  Starting simulation...
+info: Entering event queue @ 688500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 688523460500.  Starting simulation...
+info: Entering event queue @ 689500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 689523460500.  Starting simulation...
+info: Entering event queue @ 690500023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 690429710500.  Starting simulation...
+info: Entering event queue @ 691406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 691429710500.  Starting simulation...
+info: Entering event queue @ 692406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 692429710500.  Starting simulation...
+info: Entering event queue @ 693406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 693429710500.  Starting simulation...
+info: Entering event queue @ 694406273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 694335960500.  Starting simulation...
+info: Entering event queue @ 695312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 695335960500.  Starting simulation...
+info: Entering event queue @ 696312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 696335960500.  Starting simulation...
+info: Entering event queue @ 697312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 697335960500.  Starting simulation...
+info: Entering event queue @ 698312523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 698242210500.  Starting simulation...
+info: Entering event queue @ 699218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 699242210500.  Starting simulation...
+info: Entering event queue @ 700218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 700242210500.  Starting simulation...
+info: Entering event queue @ 701218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 701242210500.  Starting simulation...
+info: Entering event queue @ 702218773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 702148460500.  Starting simulation...
+info: Entering event queue @ 703125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 703148460500.  Starting simulation...
+info: Entering event queue @ 704125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 704148460500.  Starting simulation...
+info: Entering event queue @ 705125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 705148460500.  Starting simulation...
+info: Entering event queue @ 706125023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 706054710500.  Starting simulation...
+info: Entering event queue @ 707031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 707054710500.  Starting simulation...
+info: Entering event queue @ 708031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 708054710500.  Starting simulation...
+info: Entering event queue @ 709031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 709054710500.  Starting simulation...
+info: Entering event queue @ 710031273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 709960960500.  Starting simulation...
+info: Entering event queue @ 710937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 710960960500.  Starting simulation...
+info: Entering event queue @ 711937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 711960960500.  Starting simulation...
+info: Entering event queue @ 712937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 712960960500.  Starting simulation...
+info: Entering event queue @ 713937523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 713867210500.  Starting simulation...
+info: Entering event queue @ 714843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 714867210500.  Starting simulation...
+info: Entering event queue @ 715843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 715867210500.  Starting simulation...
+info: Entering event queue @ 716843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 716867210500.  Starting simulation...
+info: Entering event queue @ 717843773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 717773460500.  Starting simulation...
+info: Entering event queue @ 718750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 718773460500.  Starting simulation...
+info: Entering event queue @ 719750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 719773460500.  Starting simulation...
+info: Entering event queue @ 720750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 720773460500.  Starting simulation...
+info: Entering event queue @ 721750023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 721679710500.  Starting simulation...
+info: Entering event queue @ 722656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 722679710500.  Starting simulation...
+info: Entering event queue @ 723656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 723679710500.  Starting simulation...
+info: Entering event queue @ 724656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 724679710500.  Starting simulation...
+info: Entering event queue @ 725656273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 725585960500.  Starting simulation...
+info: Entering event queue @ 726562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 726585960500.  Starting simulation...
+info: Entering event queue @ 727562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 727585960500.  Starting simulation...
+info: Entering event queue @ 728562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 728585960500.  Starting simulation...
+info: Entering event queue @ 729562523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 729492210500.  Starting simulation...
+info: Entering event queue @ 730468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 730492210500.  Starting simulation...
+info: Entering event queue @ 731468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
+info: Entering event queue @ 732468773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 731492210500.  Starting simulation...
+info: Entering event queue @ 732468780500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 732492210500.  Starting simulation...
+info: Entering event queue @ 733468780500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 733398460500.  Starting simulation...
+info: Entering event queue @ 734375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 734398460500.  Starting simulation...
+info: Entering event queue @ 735375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 735398460500.  Starting simulation...
+info: Entering event queue @ 736375023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 735398468000.  Starting simulation...
+info: Entering event queue @ 736375030500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 736398468000.  Starting simulation...
+info: Entering event queue @ 737375030500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 737304710500.  Starting simulation...
+info: Entering event queue @ 738281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 738304710500.  Starting simulation...
+info: Entering event queue @ 739281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
+info: Entering event queue @ 740281273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 739304710500.  Starting simulation...
+info: Entering event queue @ 740281280500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 740304710500.  Starting simulation...
+info: Entering event queue @ 741281280500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 741210960500.  Starting simulation...
+info: Entering event queue @ 742187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 742210960500.  Starting simulation...
+info: Entering event queue @ 743187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 743210960500.  Starting simulation...
+info: Entering event queue @ 744187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 744210960500.  Starting simulation...
+info: Entering event queue @ 745187523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 745117210500.  Starting simulation...
+info: Entering event queue @ 746093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 746117210500.  Starting simulation...
+info: Entering event queue @ 747093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 747117210500.  Starting simulation...
+info: Entering event queue @ 748093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 748117210500.  Starting simulation...
+info: Entering event queue @ 749093773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 749023460500.  Starting simulation...
+info: Entering event queue @ 750000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 750023460500.  Starting simulation...
+info: Entering event queue @ 751000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 751023460500.  Starting simulation...
+info: Entering event queue @ 752000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 752023460500.  Starting simulation...
+info: Entering event queue @ 753000023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 752929710500.  Starting simulation...
+info: Entering event queue @ 753906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 753929710500.  Starting simulation...
+info: Entering event queue @ 754906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
+info: Entering event queue @ 755906273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 754929710500.  Starting simulation...
+info: Entering event queue @ 755906280500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 755929710500.  Starting simulation...
+info: Entering event queue @ 756906280500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 756835960500.  Starting simulation...
+info: Entering event queue @ 757812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 757835960500.  Starting simulation...
+info: Entering event queue @ 758812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 758835960500.  Starting simulation...
+info: Entering event queue @ 759812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 759835960500.  Starting simulation...
+info: Entering event queue @ 760812523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 760742210500.  Starting simulation...
+info: Entering event queue @ 761718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 761742210500.  Starting simulation...
+info: Entering event queue @ 762718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 762742210500.  Starting simulation...
+info: Entering event queue @ 763718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 763742210500.  Starting simulation...
+info: Entering event queue @ 764718773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 764648460500.  Starting simulation...
+info: Entering event queue @ 765625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 765648460500.  Starting simulation...
+info: Entering event queue @ 766625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 766648460500.  Starting simulation...
+info: Entering event queue @ 767625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 767648460500.  Starting simulation...
+info: Entering event queue @ 768625023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 768554710500.  Starting simulation...
+info: Entering event queue @ 769531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 769554710500.  Starting simulation...
+info: Entering event queue @ 770531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 770554710500.  Starting simulation...
+info: Entering event queue @ 771531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 771554710500.  Starting simulation...
+info: Entering event queue @ 772531273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 772460960500.  Starting simulation...
+info: Entering event queue @ 773437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 773460960500.  Starting simulation...
+info: Entering event queue @ 774437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 774460960500.  Starting simulation...
+info: Entering event queue @ 775437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 775460960500.  Starting simulation...
+info: Entering event queue @ 776437523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 776367210500.  Starting simulation...
+info: Entering event queue @ 777343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 777367210500.  Starting simulation...
+info: Entering event queue @ 778343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 778367210500.  Starting simulation...
+info: Entering event queue @ 779343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 779367210500.  Starting simulation...
+info: Entering event queue @ 780343773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 780273460500.  Starting simulation...
+info: Entering event queue @ 781250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 781273460500.  Starting simulation...
+info: Entering event queue @ 782250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 782273460500.  Starting simulation...
+info: Entering event queue @ 783250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 783273460500.  Starting simulation...
+info: Entering event queue @ 784250023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 784179710500.  Starting simulation...
+info: Entering event queue @ 785156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 785179710500.  Starting simulation...
+info: Entering event queue @ 786156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 786179710500.  Starting simulation...
+info: Entering event queue @ 787156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 787179710500.  Starting simulation...
+info: Entering event queue @ 788156273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 788085960500.  Starting simulation...
+info: Entering event queue @ 789062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 789085960500.  Starting simulation...
+info: Entering event queue @ 790062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 790085960500.  Starting simulation...
+info: Entering event queue @ 791062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 791085960500.  Starting simulation...
+info: Entering event queue @ 792062523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 791992210500.  Starting simulation...
+info: Entering event queue @ 792968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 792992210500.  Starting simulation...
+info: Entering event queue @ 793968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 793992210500.  Starting simulation...
+info: Entering event queue @ 794968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 794992210500.  Starting simulation...
+info: Entering event queue @ 795968773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 795898460500.  Starting simulation...
+info: Entering event queue @ 796875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 796898460500.  Starting simulation...
+info: Entering event queue @ 797875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 797898460500.  Starting simulation...
+info: Entering event queue @ 798875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 798898460500.  Starting simulation...
+info: Entering event queue @ 799875023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 799804710500.  Starting simulation...
+info: Entering event queue @ 800781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 800804710500.  Starting simulation...
+info: Entering event queue @ 801781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 801804710500.  Starting simulation...
+info: Entering event queue @ 802781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 802804710500.  Starting simulation...
+info: Entering event queue @ 803781273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 803710960500.  Starting simulation...
+info: Entering event queue @ 804687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 804710960500.  Starting simulation...
+info: Entering event queue @ 805687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 805710960500.  Starting simulation...
+info: Entering event queue @ 806687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 806710960500.  Starting simulation...
+info: Entering event queue @ 807687523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 807617210500.  Starting simulation...
+info: Entering event queue @ 808593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 808617210500.  Starting simulation...
+info: Entering event queue @ 809593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 809617210500.  Starting simulation...
+info: Entering event queue @ 810593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 810617210500.  Starting simulation...
+info: Entering event queue @ 811593773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 811523460500.  Starting simulation...
+info: Entering event queue @ 812500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 812523460500.  Starting simulation...
+info: Entering event queue @ 813500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 813523460500.  Starting simulation...
+info: Entering event queue @ 814500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 814523460500.  Starting simulation...
+info: Entering event queue @ 815500023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 815429710500.  Starting simulation...
+info: Entering event queue @ 816406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 816429710500.  Starting simulation...
+info: Entering event queue @ 817406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 817429710500.  Starting simulation...
+info: Entering event queue @ 818406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 818429710500.  Starting simulation...
+info: Entering event queue @ 819406273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 819335960500.  Starting simulation...
+info: Entering event queue @ 820312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 820335960500.  Starting simulation...
+info: Entering event queue @ 821312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 821335960500.  Starting simulation...
+info: Entering event queue @ 822312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 822335960500.  Starting simulation...
+info: Entering event queue @ 823312523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 823242210500.  Starting simulation...
+info: Entering event queue @ 824218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 824242210500.  Starting simulation...
+info: Entering event queue @ 825218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 825242210500.  Starting simulation...
+info: Entering event queue @ 826218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 826242210500.  Starting simulation...
+info: Entering event queue @ 827218773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 827148460500.  Starting simulation...
+info: Entering event queue @ 828125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 828148460500.  Starting simulation...
+info: Entering event queue @ 829125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 829148460500.  Starting simulation...
+info: Entering event queue @ 830125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 830148460500.  Starting simulation...
+info: Entering event queue @ 831125023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 831054710500.  Starting simulation...
+info: Entering event queue @ 832031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 832054710500.  Starting simulation...
+info: Entering event queue @ 833031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 833054710500.  Starting simulation...
+info: Entering event queue @ 834031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 834054710500.  Starting simulation...
+info: Entering event queue @ 835031273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 834960960500.  Starting simulation...
+info: Entering event queue @ 835937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 835960960500.  Starting simulation...
+info: Entering event queue @ 836937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 836960960500.  Starting simulation...
+info: Entering event queue @ 837937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 837960960500.  Starting simulation...
+info: Entering event queue @ 838937523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 838867210500.  Starting simulation...
+info: Entering event queue @ 839843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 839867210500.  Starting simulation...
+info: Entering event queue @ 840843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 840867210500.  Starting simulation...
+info: Entering event queue @ 841843773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 840867218000.  Starting simulation...
+info: Entering event queue @ 841843780500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 841867218000.  Starting simulation...
+info: Entering event queue @ 842843780500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 842773460500.  Starting simulation...
+info: Entering event queue @ 843750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 843773460500.  Starting simulation...
+info: Entering event queue @ 844750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 844773460500.  Starting simulation...
+info: Entering event queue @ 845750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 845773460500.  Starting simulation...
+info: Entering event queue @ 846750023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 846679710500.  Starting simulation...
+info: Entering event queue @ 847656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 847679710500.  Starting simulation...
+info: Entering event queue @ 848656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 848679710500.  Starting simulation...
+info: Entering event queue @ 849656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 849679710500.  Starting simulation...
+info: Entering event queue @ 850656273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 850585960500.  Starting simulation...
+info: Entering event queue @ 851562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 851585960500.  Starting simulation...
+info: Entering event queue @ 852562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 852585960500.  Starting simulation...
+info: Entering event queue @ 853562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 853585960500.  Starting simulation...
+info: Entering event queue @ 854562523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 854492210500.  Starting simulation...
+info: Entering event queue @ 855468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 855492210500.  Starting simulation...
+info: Entering event queue @ 856468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 856492210500.  Starting simulation...
+info: Entering event queue @ 857468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 857492210500.  Starting simulation...
+info: Entering event queue @ 858468773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 858398460500.  Starting simulation...
+info: Entering event queue @ 859375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 859398460500.  Starting simulation...
+info: Entering event queue @ 860375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 860398460500.  Starting simulation...
+info: Entering event queue @ 861375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 861398460500.  Starting simulation...
+info: Entering event queue @ 862375023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 862304710500.  Starting simulation...
+info: Entering event queue @ 863281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 863304710500.  Starting simulation...
+info: Entering event queue @ 864281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 864304710500.  Starting simulation...
+info: Entering event queue @ 865281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 865304710500.  Starting simulation...
+info: Entering event queue @ 866281273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 866210960500.  Starting simulation...
+info: Entering event queue @ 867187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 867210960500.  Starting simulation...
+info: Entering event queue @ 868187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 868210960500.  Starting simulation...
+info: Entering event queue @ 869187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 869210960500.  Starting simulation...
+info: Entering event queue @ 870187523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 870117210500.  Starting simulation...
+info: Entering event queue @ 871093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 871117210500.  Starting simulation...
+info: Entering event queue @ 872093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 872117210500.  Starting simulation...
+info: Entering event queue @ 873093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 873117210500.  Starting simulation...
+info: Entering event queue @ 874093773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 874023460500.  Starting simulation...
+info: Entering event queue @ 875000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 875023460500.  Starting simulation...
+info: Entering event queue @ 876000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 876023460500.  Starting simulation...
+info: Entering event queue @ 877000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 877023460500.  Starting simulation...
+info: Entering event queue @ 878000023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 877929710500.  Starting simulation...
+info: Entering event queue @ 878906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 878929710500.  Starting simulation...
+info: Entering event queue @ 879906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 879929710500.  Starting simulation...
+info: Entering event queue @ 880906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 880929710500.  Starting simulation...
+info: Entering event queue @ 881906273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 881835960500.  Starting simulation...
+info: Entering event queue @ 882812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 882835960500.  Starting simulation...
+info: Entering event queue @ 883812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 883835960500.  Starting simulation...
+info: Entering event queue @ 884812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 884835960500.  Starting simulation...
+info: Entering event queue @ 885812523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 885742210500.  Starting simulation...
+info: Entering event queue @ 886718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 886742210500.  Starting simulation...
+info: Entering event queue @ 887718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 887742210500.  Starting simulation...
+info: Entering event queue @ 888718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 888742210500.  Starting simulation...
+info: Entering event queue @ 889718773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 889648460500.  Starting simulation...
+info: Entering event queue @ 890625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 890648460500.  Starting simulation...
+info: Entering event queue @ 891625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 891648460500.  Starting simulation...
+info: Entering event queue @ 892625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 892648460500.  Starting simulation...
+info: Entering event queue @ 893625023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 893554710500.  Starting simulation...
+info: Entering event queue @ 894531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 894554710500.  Starting simulation...
+info: Entering event queue @ 895531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 895554710500.  Starting simulation...
+info: Entering event queue @ 896531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 896554710500.  Starting simulation...
+info: Entering event queue @ 897531273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 897460960500.  Starting simulation...
+info: Entering event queue @ 898437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 898460960500.  Starting simulation...
+info: Entering event queue @ 899437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 899460960500.  Starting simulation...
+info: Entering event queue @ 900437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 900460960500.  Starting simulation...
+info: Entering event queue @ 901437523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 901367210500.  Starting simulation...
+info: Entering event queue @ 902343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 902367210500.  Starting simulation...
+info: Entering event queue @ 903343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 903367210500.  Starting simulation...
+info: Entering event queue @ 904343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 904367210500.  Starting simulation...
+info: Entering event queue @ 905343773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 905273460500.  Starting simulation...
+info: Entering event queue @ 906250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 906273460500.  Starting simulation...
+info: Entering event queue @ 907250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 907273460500.  Starting simulation...
+info: Entering event queue @ 908250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 908273460500.  Starting simulation...
+info: Entering event queue @ 909250023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 909179710500.  Starting simulation...
+info: Entering event queue @ 910156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 910179710500.  Starting simulation...
+info: Entering event queue @ 911156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 911179710500.  Starting simulation...
+info: Entering event queue @ 912156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 912179710500.  Starting simulation...
+info: Entering event queue @ 913156273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 913085960500.  Starting simulation...
+info: Entering event queue @ 914062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 914085960500.  Starting simulation...
+info: Entering event queue @ 915062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 915085960500.  Starting simulation...
+info: Entering event queue @ 916062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 916085960500.  Starting simulation...
+info: Entering event queue @ 917062523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 916992210500.  Starting simulation...
+info: Entering event queue @ 917968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 917992210500.  Starting simulation...
+info: Entering event queue @ 918968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 918992210500.  Starting simulation...
+info: Entering event queue @ 919968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 919992210500.  Starting simulation...
+info: Entering event queue @ 920968773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 920898460500.  Starting simulation...
+info: Entering event queue @ 921875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 921898460500.  Starting simulation...
+info: Entering event queue @ 922875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 922898460500.  Starting simulation...
+info: Entering event queue @ 923875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 923898460500.  Starting simulation...
+info: Entering event queue @ 924875023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 924804710500.  Starting simulation...
+info: Entering event queue @ 925781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 925804710500.  Starting simulation...
+info: Entering event queue @ 926781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 926804710500.  Starting simulation...
+info: Entering event queue @ 927781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 927804710500.  Starting simulation...
+info: Entering event queue @ 928781273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 928710960500.  Starting simulation...
+info: Entering event queue @ 929687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 929710960500.  Starting simulation...
+info: Entering event queue @ 930687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 930710960500.  Starting simulation...
+info: Entering event queue @ 931687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 931710960500.  Starting simulation...
+info: Entering event queue @ 932687523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 932617210500.  Starting simulation...
+info: Entering event queue @ 933593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 933617210500.  Starting simulation...
+info: Entering event queue @ 934593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 934617210500.  Starting simulation...
+info: Entering event queue @ 935593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 935617210500.  Starting simulation...
+info: Entering event queue @ 936593773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 936523460500.  Starting simulation...
+info: Entering event queue @ 937500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 937523460500.  Starting simulation...
+info: Entering event queue @ 938500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 938523460500.  Starting simulation...
+info: Entering event queue @ 939500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 939523460500.  Starting simulation...
+info: Entering event queue @ 940500023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 940429710500.  Starting simulation...
+info: Entering event queue @ 941406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 941429710500.  Starting simulation...
+info: Entering event queue @ 942406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 942429710500.  Starting simulation...
+info: Entering event queue @ 943406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 943429710500.  Starting simulation...
+info: Entering event queue @ 944406273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 944335960500.  Starting simulation...
+info: Entering event queue @ 945312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 945335960500.  Starting simulation...
+info: Entering event queue @ 946312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 946335960500.  Starting simulation...
+info: Entering event queue @ 947312523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 946335968000.  Starting simulation...
+info: Entering event queue @ 947312530500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 947335968000.  Starting simulation...
+info: Entering event queue @ 948312530500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 948242210500.  Starting simulation...
+info: Entering event queue @ 949218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 949242210500.  Starting simulation...
+info: Entering event queue @ 950218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 950242210500.  Starting simulation...
+info: Entering event queue @ 951218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 951242210500.  Starting simulation...
+info: Entering event queue @ 952218773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 952148460500.  Starting simulation...
+info: Entering event queue @ 953125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 953148460500.  Starting simulation...
+info: Entering event queue @ 954125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 954148460500.  Starting simulation...
+info: Entering event queue @ 955125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 955148460500.  Starting simulation...
+info: Entering event queue @ 956125023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 956054710500.  Starting simulation...
+info: Entering event queue @ 957031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 957054710500.  Starting simulation...
+info: Entering event queue @ 958031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 958054710500.  Starting simulation...
+info: Entering event queue @ 959031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 959054710500.  Starting simulation...
+info: Entering event queue @ 960031273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 959960960500.  Starting simulation...
+info: Entering event queue @ 960937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 960960960500.  Starting simulation...
+info: Entering event queue @ 961937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 961960960500.  Starting simulation...
+info: Entering event queue @ 962937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 962960960500.  Starting simulation...
+info: Entering event queue @ 963937523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 963867210500.  Starting simulation...
+info: Entering event queue @ 964843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 964867210500.  Starting simulation...
+info: Entering event queue @ 965843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 965867210500.  Starting simulation...
+info: Entering event queue @ 966843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 966867210500.  Starting simulation...
+info: Entering event queue @ 967843773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 967773460500.  Starting simulation...
+info: Entering event queue @ 968750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 968773460500.  Starting simulation...
+info: Entering event queue @ 969750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 969773460500.  Starting simulation...
+info: Entering event queue @ 970750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 970773460500.  Starting simulation...
+info: Entering event queue @ 971750023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 971679710500.  Starting simulation...
+info: Entering event queue @ 972656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 972679710500.  Starting simulation...
+info: Entering event queue @ 973656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 973679710500.  Starting simulation...
+info: Entering event queue @ 974656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 974679710500.  Starting simulation...
+info: Entering event queue @ 975656273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 975585960500.  Starting simulation...
+info: Entering event queue @ 976562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 976585960500.  Starting simulation...
+info: Entering event queue @ 977562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 977585960500.  Starting simulation...
+info: Entering event queue @ 978562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 978585960500.  Starting simulation...
+info: Entering event queue @ 979562523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 979492210500.  Starting simulation...
+info: Entering event queue @ 980468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 980492210500.  Starting simulation...
+info: Entering event queue @ 981468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 981492210500.  Starting simulation...
+info: Entering event queue @ 982468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 982492210500.  Starting simulation...
+info: Entering event queue @ 983468773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 983398460500.  Starting simulation...
+info: Entering event queue @ 984375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 984398460500.  Starting simulation...
+info: Entering event queue @ 985375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 985398460500.  Starting simulation...
+info: Entering event queue @ 986375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 986398460500.  Starting simulation...
+info: Entering event queue @ 987375023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 987304710500.  Starting simulation...
+info: Entering event queue @ 988281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 988304710500.  Starting simulation...
+info: Entering event queue @ 989281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 989304710500.  Starting simulation...
+info: Entering event queue @ 990281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 990304710500.  Starting simulation...
+info: Entering event queue @ 991281273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 991210960500.  Starting simulation...
+info: Entering event queue @ 992187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 992210960500.  Starting simulation...
+info: Entering event queue @ 993187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 993210960500.  Starting simulation...
+info: Entering event queue @ 994187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 994210960500.  Starting simulation...
+info: Entering event queue @ 995187523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 995117210500.  Starting simulation...
+info: Entering event queue @ 996093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 996117210500.  Starting simulation...
+info: Entering event queue @ 997093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 997117210500.  Starting simulation...
+info: Entering event queue @ 998093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 998117210500.  Starting simulation...
+info: Entering event queue @ 999093773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 999023460500.  Starting simulation...
+info: Entering event queue @ 1000000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1000023460500.  Starting simulation...
+info: Entering event queue @ 1001000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1001023460500.  Starting simulation...
+info: Entering event queue @ 1002000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1002023460500.  Starting simulation...
+info: Entering event queue @ 1003000023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1002929710500.  Starting simulation...
+info: Entering event queue @ 1003906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1003929710500.  Starting simulation...
+info: Entering event queue @ 1004906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1004929710500.  Starting simulation...
+info: Entering event queue @ 1005906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1005929710500.  Starting simulation...
+info: Entering event queue @ 1006906273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1006835960500.  Starting simulation...
+info: Entering event queue @ 1007812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1007835960500.  Starting simulation...
+info: Entering event queue @ 1008812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1008835960500.  Starting simulation...
+info: Entering event queue @ 1009812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1009835960500.  Starting simulation...
+info: Entering event queue @ 1010812523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1010742210500.  Starting simulation...
+info: Entering event queue @ 1011718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1011742210500.  Starting simulation...
+info: Entering event queue @ 1012718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
+info: Entering event queue @ 1013718773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1012742210500.  Starting simulation...
+info: Entering event queue @ 1013718780500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1013742210500.  Starting simulation...
+info: Entering event queue @ 1014718780500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1014648460500.  Starting simulation...
+info: Entering event queue @ 1015625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1015648460500.  Starting simulation...
+info: Entering event queue @ 1016625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1016648460500.  Starting simulation...
+info: Entering event queue @ 1017625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1017648460500.  Starting simulation...
+info: Entering event queue @ 1018625023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1018554710500.  Starting simulation...
+info: Entering event queue @ 1019531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1019554710500.  Starting simulation...
+info: Entering event queue @ 1020531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1020554710500.  Starting simulation...
+info: Entering event queue @ 1021531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1021554710500.  Starting simulation...
+info: Entering event queue @ 1022531273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1022460960500.  Starting simulation...
+info: Entering event queue @ 1023437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1023460960500.  Starting simulation...
+info: Entering event queue @ 1024437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1024460960500.  Starting simulation...
+info: Entering event queue @ 1025437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1025460960500.  Starting simulation...
+info: Entering event queue @ 1026437523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1026367210500.  Starting simulation...
+info: Entering event queue @ 1027343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1027367210500.  Starting simulation...
+info: Entering event queue @ 1028343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1028367210500.  Starting simulation...
+info: Entering event queue @ 1029343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1029367210500.  Starting simulation...
+info: Entering event queue @ 1030343773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1030273460500.  Starting simulation...
+info: Entering event queue @ 1031250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1031273460500.  Starting simulation...
+info: Entering event queue @ 1032250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1032273460500.  Starting simulation...
+info: Entering event queue @ 1033250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1033273460500.  Starting simulation...
+info: Entering event queue @ 1034250023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1034179710500.  Starting simulation...
+info: Entering event queue @ 1035156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1035179710500.  Starting simulation...
+info: Entering event queue @ 1036156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1036179710500.  Starting simulation...
+info: Entering event queue @ 1037156273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1037179710500.  Starting simulation...
+info: Entering event queue @ 1038156273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1038085960500.  Starting simulation...
+info: Entering event queue @ 1039062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1039085960500.  Starting simulation...
+info: Entering event queue @ 1040062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1040085960500.  Starting simulation...
+info: Entering event queue @ 1041062523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1041085960500.  Starting simulation...
+info: Entering event queue @ 1042062523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1041992210500.  Starting simulation...
+info: Entering event queue @ 1042968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1042992210500.  Starting simulation...
+info: Entering event queue @ 1043968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1043992210500.  Starting simulation...
+info: Entering event queue @ 1044968773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1044992210500.  Starting simulation...
+info: Entering event queue @ 1045968773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1045898460500.  Starting simulation...
+info: Entering event queue @ 1046875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1046898460500.  Starting simulation...
+info: Entering event queue @ 1047875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1047898460500.  Starting simulation...
+info: Entering event queue @ 1048875023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1048898460500.  Starting simulation...
+info: Entering event queue @ 1049875023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1049804710500.  Starting simulation...
+info: Entering event queue @ 1050781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1050804710500.  Starting simulation...
+info: Entering event queue @ 1051781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1051804710500.  Starting simulation...
+info: Entering event queue @ 1052781273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1052804710500.  Starting simulation...
+info: Entering event queue @ 1053781273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1053710960500.  Starting simulation...
+info: Entering event queue @ 1054687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1054710960500.  Starting simulation...
+info: Entering event queue @ 1055687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1055710960500.  Starting simulation...
+info: Entering event queue @ 1056687523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1056710960500.  Starting simulation...
+info: Entering event queue @ 1057687523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1057617210500.  Starting simulation...
+info: Entering event queue @ 1058593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1058617210500.  Starting simulation...
+info: Entering event queue @ 1059593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1059617210500.  Starting simulation...
+info: Entering event queue @ 1060593773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1060617210500.  Starting simulation...
+info: Entering event queue @ 1061593773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1061523460500.  Starting simulation...
+info: Entering event queue @ 1062500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1062523460500.  Starting simulation...
+info: Entering event queue @ 1063500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1063523460500.  Starting simulation...
+info: Entering event queue @ 1064500023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1064523460500.  Starting simulation...
+info: Entering event queue @ 1065500023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1065429710500.  Starting simulation...
+info: Entering event queue @ 1066406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1066429710500.  Starting simulation...
+info: Entering event queue @ 1067406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1067429710500.  Starting simulation...
+info: Entering event queue @ 1068406273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1068429710500.  Starting simulation...
+info: Entering event queue @ 1069406273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1069335960500.  Starting simulation...
+info: Entering event queue @ 1070312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1070335960500.  Starting simulation...
+info: Entering event queue @ 1071312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1071335960500.  Starting simulation...
+info: Entering event queue @ 1072312523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1072335960500.  Starting simulation...
+info: Entering event queue @ 1073312523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1073242210500.  Starting simulation...
+info: Entering event queue @ 1074218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1074242210500.  Starting simulation...
+info: Entering event queue @ 1075218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1075242210500.  Starting simulation...
+info: Entering event queue @ 1076218773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1076242210500.  Starting simulation...
+info: Entering event queue @ 1077218773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1077148460500.  Starting simulation...
+info: Entering event queue @ 1078125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1078148460500.  Starting simulation...
+info: Entering event queue @ 1079125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1079148460500.  Starting simulation...
+info: Entering event queue @ 1080125023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1080148460500.  Starting simulation...
+info: Entering event queue @ 1081125023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1081054710500.  Starting simulation...
+info: Entering event queue @ 1082031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1082054710500.  Starting simulation...
+info: Entering event queue @ 1083031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1083054710500.  Starting simulation...
+info: Entering event queue @ 1084031273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1084054710500.  Starting simulation...
+info: Entering event queue @ 1085031273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1084960960500.  Starting simulation...
+info: Entering event queue @ 1085937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1085960960500.  Starting simulation...
+info: Entering event queue @ 1086937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1086960960500.  Starting simulation...
+info: Entering event queue @ 1087937523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1087960960500.  Starting simulation...
+info: Entering event queue @ 1088937523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1088867210500.  Starting simulation...
+info: Entering event queue @ 1089843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1089867210500.  Starting simulation...
+info: Entering event queue @ 1090843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1090867210500.  Starting simulation...
+info: Entering event queue @ 1091843773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1091867210500.  Starting simulation...
+info: Entering event queue @ 1092843773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1092773460500.  Starting simulation...
+info: Entering event queue @ 1093750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1093773460500.  Starting simulation...
+info: Entering event queue @ 1094750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1094773460500.  Starting simulation...
+info: Entering event queue @ 1095750023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1095773460500.  Starting simulation...
+info: Entering event queue @ 1096750023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1096679710500.  Starting simulation...
+info: Entering event queue @ 1097656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1097679710500.  Starting simulation...
+info: Entering event queue @ 1098656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1098679710500.  Starting simulation...
+info: Entering event queue @ 1099656273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1099679710500.  Starting simulation...
+info: Entering event queue @ 1100656273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1100585960500.  Starting simulation...
+info: Entering event queue @ 1101562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1101585960500.  Starting simulation...
+info: Entering event queue @ 1102562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1102585960500.  Starting simulation...
+info: Entering event queue @ 1103562523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1103585960500.  Starting simulation...
+info: Entering event queue @ 1104562523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1104492210500.  Starting simulation...
+info: Entering event queue @ 1105468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1105492210500.  Starting simulation...
+info: Entering event queue @ 1106468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1106492210500.  Starting simulation...
+info: Entering event queue @ 1107468773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1107492210500.  Starting simulation...
+info: Entering event queue @ 1108468773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1108398460500.  Starting simulation...
+info: Entering event queue @ 1109375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1109398460500.  Starting simulation...
+info: Entering event queue @ 1110375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1110398460500.  Starting simulation...
+info: Entering event queue @ 1111375023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1111398460500.  Starting simulation...
+info: Entering event queue @ 1112375023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1112304710500.  Starting simulation...
+info: Entering event queue @ 1113281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1113304710500.  Starting simulation...
+info: Entering event queue @ 1114281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1114304710500.  Starting simulation...
+info: Entering event queue @ 1115281273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1115304710500.  Starting simulation...
+info: Entering event queue @ 1116281273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1116210960500.  Starting simulation...
+info: Entering event queue @ 1117187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1117210960500.  Starting simulation...
+info: Entering event queue @ 1118187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1118210960500.  Starting simulation...
+info: Entering event queue @ 1119187523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1119210960500.  Starting simulation...
+info: Entering event queue @ 1120187523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1120117210500.  Starting simulation...
+info: Entering event queue @ 1121093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1121117210500.  Starting simulation...
+info: Entering event queue @ 1122093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1122117210500.  Starting simulation...
+info: Entering event queue @ 1123093773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1123117210500.  Starting simulation...
+info: Entering event queue @ 1124093773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1124023460500.  Starting simulation...
+info: Entering event queue @ 1125000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1125023460500.  Starting simulation...
+info: Entering event queue @ 1126000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1126023460500.  Starting simulation...
+info: Entering event queue @ 1127000023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1127023460500.  Starting simulation...
+info: Entering event queue @ 1128000023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1127929710500.  Starting simulation...
+info: Entering event queue @ 1128906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1128929710500.  Starting simulation...
+info: Entering event queue @ 1129906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1129929710500.  Starting simulation...
+info: Entering event queue @ 1130906273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1130929710500.  Starting simulation...
+info: Entering event queue @ 1131906273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1131835960500.  Starting simulation...
+info: Entering event queue @ 1132812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1132835960500.  Starting simulation...
+info: Entering event queue @ 1133812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1133835960500.  Starting simulation...
+info: Entering event queue @ 1134812523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1134835960500.  Starting simulation...
+info: Entering event queue @ 1135812523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1135742210500.  Starting simulation...
+info: Entering event queue @ 1136718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1136742210500.  Starting simulation...
+info: Entering event queue @ 1137718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1137742210500.  Starting simulation...
+info: Entering event queue @ 1138718773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1138742210500.  Starting simulation...
+info: Entering event queue @ 1139718773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1139648460500.  Starting simulation...
+info: Entering event queue @ 1140625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1140648460500.  Starting simulation...
+info: Entering event queue @ 1141625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1141648460500.  Starting simulation...
+info: Entering event queue @ 1142625023000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1142648460500.  Starting simulation...
+info: Entering event queue @ 1143625023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1143554710500.  Starting simulation...
+info: Entering event queue @ 1144531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1144554710500.  Starting simulation...
+info: Entering event queue @ 1145531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1145554710500.  Starting simulation...
+info: Entering event queue @ 1146531273000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1146554710500.  Starting simulation...
+info: Entering event queue @ 1147531273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1147460960500.  Starting simulation...
+info: Entering event queue @ 1148437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1148460960500.  Starting simulation...
+info: Entering event queue @ 1149437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1149460960500.  Starting simulation...
+info: Entering event queue @ 1150437523000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1150460960500.  Starting simulation...
+info: Entering event queue @ 1151437523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1151367210500.  Starting simulation...
+info: Entering event queue @ 1152343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1152367210500.  Starting simulation...
+info: Entering event queue @ 1153343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1153367210500.  Starting simulation...
+info: Entering event queue @ 1154343773000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1154367210500.  Starting simulation...
+info: Entering event queue @ 1155343773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1155273460500.  Starting simulation...
+info: Entering event queue @ 1156250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1156273460500.  Starting simulation...
+info: Entering event queue @ 1157250023000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1157273460500.  Starting simulation...
+info: Entering event queue @ 1158250023000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1157273468000.  Starting simulation...
+info: Entering event queue @ 1158250030500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1158273468000.  Starting simulation...
+info: Entering event queue @ 1159250030500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1159362057000.  Starting simulation...
+info: Entering event queue @ 1160338579500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1160362057000.  Starting simulation...
+info: Entering event queue @ 1161338579500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1161362057000.  Starting simulation...
+info: Entering event queue @ 1162338579500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1162362057000.  Starting simulation...
+info: Entering event queue @ 1163338579500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1162362060000.  Starting simulation...
+info: Entering event queue @ 1163338582500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1163362060000.  Starting simulation...
+info: Entering event queue @ 1164338582500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1164362060000.  Starting simulation...
+info: Entering event queue @ 1165338582500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1165362060000.  Starting simulation...
+info: Entering event queue @ 1166338582500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1165362063000.  Starting simulation...
+info: Entering event queue @ 1166338585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1166362063000.  Starting simulation...
+info: Entering event queue @ 1167338585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1167362063000.  Starting simulation...
+info: Entering event queue @ 1168338585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1168362063000.  Starting simulation...
+info: Entering event queue @ 1169338585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1168945335500.  Starting simulation...
+info: Entering event queue @ 1169921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1169945335500.  Starting simulation...
+info: Entering event queue @ 1170921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1170945335500.  Starting simulation...
+info: Entering event queue @ 1171921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1171945335500.  Starting simulation...
+info: Entering event queue @ 1172921898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1172851585500.  Starting simulation...
+info: Entering event queue @ 1173828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1173851585500.  Starting simulation...
+info: Entering event queue @ 1174828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1174851585500.  Starting simulation...
+info: Entering event queue @ 1175828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1175851585500.  Starting simulation...
+info: Entering event queue @ 1176828148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1176757835500.  Starting simulation...
+info: Entering event queue @ 1177734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1177757835500.  Starting simulation...
+info: Entering event queue @ 1178734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1178757835500.  Starting simulation...
+info: Entering event queue @ 1179734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1179757835500.  Starting simulation...
+info: Entering event queue @ 1180734398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1180664085500.  Starting simulation...
+info: Entering event queue @ 1181640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1181664085500.  Starting simulation...
+info: Entering event queue @ 1182640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1182664085500.  Starting simulation...
+info: Entering event queue @ 1183640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1183664085500.  Starting simulation...
+info: Entering event queue @ 1184640648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1184570335500.  Starting simulation...
+info: Entering event queue @ 1185546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1185570335500.  Starting simulation...
+info: Entering event queue @ 1186546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1186570335500.  Starting simulation...
+info: Entering event queue @ 1187546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1187570335500.  Starting simulation...
+info: Entering event queue @ 1188546898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1188476585500.  Starting simulation...
+info: Entering event queue @ 1189453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1189476585500.  Starting simulation...
+info: Entering event queue @ 1190453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1190476585500.  Starting simulation...
+info: Entering event queue @ 1191453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1191476585500.  Starting simulation...
+info: Entering event queue @ 1192453148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1192382835500.  Starting simulation...
+info: Entering event queue @ 1193359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1193382835500.  Starting simulation...
+info: Entering event queue @ 1194359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1194382835500.  Starting simulation...
+info: Entering event queue @ 1195359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1195382835500.  Starting simulation...
+info: Entering event queue @ 1196359398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1196289085500.  Starting simulation...
+info: Entering event queue @ 1197265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1197289085500.  Starting simulation...
+info: Entering event queue @ 1198265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1198289085500.  Starting simulation...
+info: Entering event queue @ 1199265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1199289085500.  Starting simulation...
+info: Entering event queue @ 1200265648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1200195335500.  Starting simulation...
+info: Entering event queue @ 1201171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1201195335500.  Starting simulation...
+info: Entering event queue @ 1202171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1202195335500.  Starting simulation...
+info: Entering event queue @ 1203171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1203195335500.  Starting simulation...
+info: Entering event queue @ 1204171898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1204101585500.  Starting simulation...
+info: Entering event queue @ 1205078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1205101585500.  Starting simulation...
+info: Entering event queue @ 1206078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1206101585500.  Starting simulation...
+info: Entering event queue @ 1207078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1207101585500.  Starting simulation...
+info: Entering event queue @ 1208078148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1208007835500.  Starting simulation...
+info: Entering event queue @ 1208984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1209007835500.  Starting simulation...
+info: Entering event queue @ 1209984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1210007835500.  Starting simulation...
+info: Entering event queue @ 1210984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1211007835500.  Starting simulation...
+info: Entering event queue @ 1211984398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1211914085500.  Starting simulation...
+info: Entering event queue @ 1212890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1212914085500.  Starting simulation...
+info: Entering event queue @ 1213890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1213914085500.  Starting simulation...
+info: Entering event queue @ 1214890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1214914085500.  Starting simulation...
+info: Entering event queue @ 1215890648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1215820335500.  Starting simulation...
+info: Entering event queue @ 1216796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1216820335500.  Starting simulation...
+info: Entering event queue @ 1217796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1217820335500.  Starting simulation...
+info: Entering event queue @ 1218796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1218820335500.  Starting simulation...
+info: Entering event queue @ 1219796898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1219726585500.  Starting simulation...
+info: Entering event queue @ 1220703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1220726585500.  Starting simulation...
+info: Entering event queue @ 1221703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1221726585500.  Starting simulation...
+info: Entering event queue @ 1222703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1222726585500.  Starting simulation...
+info: Entering event queue @ 1223703148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1223632835500.  Starting simulation...
+info: Entering event queue @ 1224609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1224632835500.  Starting simulation...
+info: Entering event queue @ 1225609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1225632835500.  Starting simulation...
+info: Entering event queue @ 1226609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1226632835500.  Starting simulation...
+info: Entering event queue @ 1227609398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1227539085500.  Starting simulation...
+info: Entering event queue @ 1228515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1228539085500.  Starting simulation...
+info: Entering event queue @ 1229515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1229539085500.  Starting simulation...
+info: Entering event queue @ 1230515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1230539085500.  Starting simulation...
+info: Entering event queue @ 1231515648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1231445335500.  Starting simulation...
+info: Entering event queue @ 1232421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1232445335500.  Starting simulation...
+info: Entering event queue @ 1233421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1233445335500.  Starting simulation...
+info: Entering event queue @ 1234421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1234445335500.  Starting simulation...
+info: Entering event queue @ 1235421898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1235351585500.  Starting simulation...
+info: Entering event queue @ 1236328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1236351585500.  Starting simulation...
+info: Entering event queue @ 1237328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1237351585500.  Starting simulation...
+info: Entering event queue @ 1238328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1238351585500.  Starting simulation...
+info: Entering event queue @ 1239328148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1239257835500.  Starting simulation...
+info: Entering event queue @ 1240234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1240257835500.  Starting simulation...
+info: Entering event queue @ 1241234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1241257835500.  Starting simulation...
+info: Entering event queue @ 1242234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1242257835500.  Starting simulation...
+info: Entering event queue @ 1243234398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1243164085500.  Starting simulation...
+info: Entering event queue @ 1244140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1244164085500.  Starting simulation...
+info: Entering event queue @ 1245140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1245164085500.  Starting simulation...
+info: Entering event queue @ 1246140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1246164085500.  Starting simulation...
+info: Entering event queue @ 1247140648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1247070335500.  Starting simulation...
+info: Entering event queue @ 1248046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1248070335500.  Starting simulation...
+info: Entering event queue @ 1249046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1249070335500.  Starting simulation...
+info: Entering event queue @ 1250046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1250070335500.  Starting simulation...
+info: Entering event queue @ 1251046898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1250976585500.  Starting simulation...
+info: Entering event queue @ 1251953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1251976585500.  Starting simulation...
+info: Entering event queue @ 1252953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1252976585500.  Starting simulation...
+info: Entering event queue @ 1253953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1253976585500.  Starting simulation...
+info: Entering event queue @ 1254953148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1254882835500.  Starting simulation...
+info: Entering event queue @ 1255859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1255882835500.  Starting simulation...
+info: Entering event queue @ 1256859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1256882835500.  Starting simulation...
+info: Entering event queue @ 1257859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1257882835500.  Starting simulation...
+info: Entering event queue @ 1258859398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1258789085500.  Starting simulation...
+info: Entering event queue @ 1259765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1259789085500.  Starting simulation...
+info: Entering event queue @ 1260765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1260789085500.  Starting simulation...
+info: Entering event queue @ 1261765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1261789085500.  Starting simulation...
+info: Entering event queue @ 1262765648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1262695335500.  Starting simulation...
+info: Entering event queue @ 1263671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1263695335500.  Starting simulation...
+info: Entering event queue @ 1264671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1264695335500.  Starting simulation...
+info: Entering event queue @ 1265671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1265695335500.  Starting simulation...
+info: Entering event queue @ 1266671898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1266601585500.  Starting simulation...
+info: Entering event queue @ 1267578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1267601585500.  Starting simulation...
+info: Entering event queue @ 1268578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1268601585500.  Starting simulation...
+info: Entering event queue @ 1269578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1269601585500.  Starting simulation...
+info: Entering event queue @ 1270578148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1270507835500.  Starting simulation...
+info: Entering event queue @ 1271484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1271507835500.  Starting simulation...
+info: Entering event queue @ 1272484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1272507835500.  Starting simulation...
+info: Entering event queue @ 1273484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1273507835500.  Starting simulation...
+info: Entering event queue @ 1274484398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1274414085500.  Starting simulation...
+info: Entering event queue @ 1275390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1275414085500.  Starting simulation...
+info: Entering event queue @ 1276390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1276414085500.  Starting simulation...
+info: Entering event queue @ 1277390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1277414085500.  Starting simulation...
+info: Entering event queue @ 1278390648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1278320335500.  Starting simulation...
+info: Entering event queue @ 1279296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1279320335500.  Starting simulation...
+info: Entering event queue @ 1280296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1280320335500.  Starting simulation...
+info: Entering event queue @ 1281296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1281320335500.  Starting simulation...
+info: Entering event queue @ 1282296898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1282226585500.  Starting simulation...
+info: Entering event queue @ 1283203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1283226585500.  Starting simulation...
+info: Entering event queue @ 1284203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1284226585500.  Starting simulation...
+info: Entering event queue @ 1285203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1285226585500.  Starting simulation...
+info: Entering event queue @ 1286203148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1286132835500.  Starting simulation...
+info: Entering event queue @ 1287109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1287132835500.  Starting simulation...
+info: Entering event queue @ 1288109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1288132835500.  Starting simulation...
+info: Entering event queue @ 1289109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1289132835500.  Starting simulation...
+info: Entering event queue @ 1290109398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1290039085500.  Starting simulation...
+info: Entering event queue @ 1291015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1291039085500.  Starting simulation...
+info: Entering event queue @ 1292015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1292039085500.  Starting simulation...
+info: Entering event queue @ 1293015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1293039085500.  Starting simulation...
+info: Entering event queue @ 1294015648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1293945335500.  Starting simulation...
+info: Entering event queue @ 1294921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1294945335500.  Starting simulation...
+info: Entering event queue @ 1295921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1295945335500.  Starting simulation...
+info: Entering event queue @ 1296921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1296945335500.  Starting simulation...
+info: Entering event queue @ 1297921898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1297851585500.  Starting simulation...
+info: Entering event queue @ 1298828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1298851585500.  Starting simulation...
+info: Entering event queue @ 1299828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1299851585500.  Starting simulation...
+info: Entering event queue @ 1300828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1300851585500.  Starting simulation...
+info: Entering event queue @ 1301828148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1301757835500.  Starting simulation...
+info: Entering event queue @ 1302734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1302757835500.  Starting simulation...
+info: Entering event queue @ 1303734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1303757835500.  Starting simulation...
+info: Entering event queue @ 1304734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1304757835500.  Starting simulation...
+info: Entering event queue @ 1305734398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1305664085500.  Starting simulation...
+info: Entering event queue @ 1306640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1306664085500.  Starting simulation...
+info: Entering event queue @ 1307640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1307664085500.  Starting simulation...
+info: Entering event queue @ 1308640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1308664085500.  Starting simulation...
+info: Entering event queue @ 1309640648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1309570335500.  Starting simulation...
+info: Entering event queue @ 1310546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1310570335500.  Starting simulation...
+info: Entering event queue @ 1311546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1311570335500.  Starting simulation...
+info: Entering event queue @ 1312546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1312570335500.  Starting simulation...
+info: Entering event queue @ 1313546898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1313476585500.  Starting simulation...
+info: Entering event queue @ 1314453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1314476585500.  Starting simulation...
+info: Entering event queue @ 1315453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1315476585500.  Starting simulation...
+info: Entering event queue @ 1316453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1316476585500.  Starting simulation...
+info: Entering event queue @ 1317453148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1317382835500.  Starting simulation...
+info: Entering event queue @ 1318359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1318382835500.  Starting simulation...
+info: Entering event queue @ 1319359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1319382835500.  Starting simulation...
+info: Entering event queue @ 1320359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1320382835500.  Starting simulation...
+info: Entering event queue @ 1321359398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1321289085500.  Starting simulation...
+info: Entering event queue @ 1322265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1322289085500.  Starting simulation...
+info: Entering event queue @ 1323265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1323289085500.  Starting simulation...
+info: Entering event queue @ 1324265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1324289085500.  Starting simulation...
+info: Entering event queue @ 1325265648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1325195335500.  Starting simulation...
+info: Entering event queue @ 1326171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1326195335500.  Starting simulation...
+info: Entering event queue @ 1327171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1327195335500.  Starting simulation...
+info: Entering event queue @ 1328171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1328195335500.  Starting simulation...
+info: Entering event queue @ 1329171898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1329101585500.  Starting simulation...
+info: Entering event queue @ 1330078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1330101585500.  Starting simulation...
+info: Entering event queue @ 1331078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1331101585500.  Starting simulation...
+info: Entering event queue @ 1332078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1332101585500.  Starting simulation...
+info: Entering event queue @ 1333078148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1333007835500.  Starting simulation...
+info: Entering event queue @ 1333984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1334007835500.  Starting simulation...
+info: Entering event queue @ 1334984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1335007835500.  Starting simulation...
+info: Entering event queue @ 1335984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1336007835500.  Starting simulation...
+info: Entering event queue @ 1336984398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1336914085500.  Starting simulation...
+info: Entering event queue @ 1337890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1337914085500.  Starting simulation...
+info: Entering event queue @ 1338890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1338914085500.  Starting simulation...
+info: Entering event queue @ 1339890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1339914085500.  Starting simulation...
+info: Entering event queue @ 1340890648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1340820335500.  Starting simulation...
+info: Entering event queue @ 1341796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1341820335500.  Starting simulation...
+info: Entering event queue @ 1342796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1342820335500.  Starting simulation...
+info: Entering event queue @ 1343796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1343820335500.  Starting simulation...
+info: Entering event queue @ 1344796898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1344726585500.  Starting simulation...
+info: Entering event queue @ 1345703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1345726585500.  Starting simulation...
+info: Entering event queue @ 1346703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1346726585500.  Starting simulation...
+info: Entering event queue @ 1347703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1347726585500.  Starting simulation...
+info: Entering event queue @ 1348703148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1348632835500.  Starting simulation...
+info: Entering event queue @ 1349609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1349632835500.  Starting simulation...
+info: Entering event queue @ 1350609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1350632835500.  Starting simulation...
+info: Entering event queue @ 1351609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1351632835500.  Starting simulation...
+info: Entering event queue @ 1352609398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1352539085500.  Starting simulation...
+info: Entering event queue @ 1353515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1353539085500.  Starting simulation...
+info: Entering event queue @ 1354515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1354539085500.  Starting simulation...
+info: Entering event queue @ 1355515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1355539085500.  Starting simulation...
+info: Entering event queue @ 1356515648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1356445335500.  Starting simulation...
+info: Entering event queue @ 1357421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1357445335500.  Starting simulation...
+info: Entering event queue @ 1358421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1358445335500.  Starting simulation...
+info: Entering event queue @ 1359421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1359445335500.  Starting simulation...
+info: Entering event queue @ 1360421898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1360351585500.  Starting simulation...
+info: Entering event queue @ 1361328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1361351585500.  Starting simulation...
+info: Entering event queue @ 1362328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1362351585500.  Starting simulation...
+info: Entering event queue @ 1363328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1363351585500.  Starting simulation...
+info: Entering event queue @ 1364328148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1364257835500.  Starting simulation...
+info: Entering event queue @ 1365234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1365257835500.  Starting simulation...
+info: Entering event queue @ 1366234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1366257835500.  Starting simulation...
+info: Entering event queue @ 1367234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1367257835500.  Starting simulation...
+info: Entering event queue @ 1368234398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1368164085500.  Starting simulation...
+info: Entering event queue @ 1369140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1369164085500.  Starting simulation...
+info: Entering event queue @ 1370140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1370164085500.  Starting simulation...
+info: Entering event queue @ 1371140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1371164085500.  Starting simulation...
+info: Entering event queue @ 1372140648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1372070335500.  Starting simulation...
+info: Entering event queue @ 1373046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1373070335500.  Starting simulation...
+info: Entering event queue @ 1374046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1374070335500.  Starting simulation...
+info: Entering event queue @ 1375046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1375070335500.  Starting simulation...
+info: Entering event queue @ 1376046898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1375976585500.  Starting simulation...
+info: Entering event queue @ 1376953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1376976585500.  Starting simulation...
+info: Entering event queue @ 1377953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1377976585500.  Starting simulation...
+info: Entering event queue @ 1378953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1378976585500.  Starting simulation...
+info: Entering event queue @ 1379953148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1379882835500.  Starting simulation...
+info: Entering event queue @ 1380859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1380882835500.  Starting simulation...
+info: Entering event queue @ 1381859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1381882835500.  Starting simulation...
+info: Entering event queue @ 1382859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1382882835500.  Starting simulation...
+info: Entering event queue @ 1383859398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1383789085500.  Starting simulation...
+info: Entering event queue @ 1384765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1384789085500.  Starting simulation...
+info: Entering event queue @ 1385765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1385789085500.  Starting simulation...
+info: Entering event queue @ 1386765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1386789085500.  Starting simulation...
+info: Entering event queue @ 1387765648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1387695335500.  Starting simulation...
+info: Entering event queue @ 1388671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1388695335500.  Starting simulation...
+info: Entering event queue @ 1389671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1389695335500.  Starting simulation...
+info: Entering event queue @ 1390671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1390695335500.  Starting simulation...
+info: Entering event queue @ 1391671898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1391601585500.  Starting simulation...
+info: Entering event queue @ 1392578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1392601585500.  Starting simulation...
+info: Entering event queue @ 1393578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1393601585500.  Starting simulation...
+info: Entering event queue @ 1394578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1394601585500.  Starting simulation...
+info: Entering event queue @ 1395578148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1395507835500.  Starting simulation...
+info: Entering event queue @ 1396484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1396507835500.  Starting simulation...
+info: Entering event queue @ 1397484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1397507835500.  Starting simulation...
+info: Entering event queue @ 1398484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1398507835500.  Starting simulation...
+info: Entering event queue @ 1399484398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1399414085500.  Starting simulation...
+info: Entering event queue @ 1400390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1400414085500.  Starting simulation...
+info: Entering event queue @ 1401390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1401414085500.  Starting simulation...
+info: Entering event queue @ 1402390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1402414085500.  Starting simulation...
+info: Entering event queue @ 1403390648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1403320335500.  Starting simulation...
+info: Entering event queue @ 1404296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1404320335500.  Starting simulation...
+info: Entering event queue @ 1405296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1405320335500.  Starting simulation...
+info: Entering event queue @ 1406296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1406320335500.  Starting simulation...
+info: Entering event queue @ 1407296898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1407226585500.  Starting simulation...
+info: Entering event queue @ 1408203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1408226585500.  Starting simulation...
+info: Entering event queue @ 1409203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1409226585500.  Starting simulation...
+info: Entering event queue @ 1410203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1410226585500.  Starting simulation...
+info: Entering event queue @ 1411203148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1411132835500.  Starting simulation...
+info: Entering event queue @ 1412109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1412132835500.  Starting simulation...
+info: Entering event queue @ 1413109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1413132835500.  Starting simulation...
+info: Entering event queue @ 1414109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1414132835500.  Starting simulation...
+info: Entering event queue @ 1415109398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1415039085500.  Starting simulation...
+info: Entering event queue @ 1416015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1416039085500.  Starting simulation...
+info: Entering event queue @ 1417015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1417039085500.  Starting simulation...
+info: Entering event queue @ 1418015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1418039085500.  Starting simulation...
+info: Entering event queue @ 1419015648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1418945335500.  Starting simulation...
+info: Entering event queue @ 1419921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1419945335500.  Starting simulation...
+info: Entering event queue @ 1420921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1420945335500.  Starting simulation...
+info: Entering event queue @ 1421921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1421945335500.  Starting simulation...
+info: Entering event queue @ 1422921898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1422851585500.  Starting simulation...
+info: Entering event queue @ 1423828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1423851585500.  Starting simulation...
+info: Entering event queue @ 1424828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1424851585500.  Starting simulation...
+info: Entering event queue @ 1425828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1425851585500.  Starting simulation...
+info: Entering event queue @ 1426828148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1426757835500.  Starting simulation...
+info: Entering event queue @ 1427734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1427757835500.  Starting simulation...
+info: Entering event queue @ 1428734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1428757835500.  Starting simulation...
+info: Entering event queue @ 1429734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1429757835500.  Starting simulation...
+info: Entering event queue @ 1430734398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1430664085500.  Starting simulation...
+info: Entering event queue @ 1431640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1431664085500.  Starting simulation...
+info: Entering event queue @ 1432640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1432664085500.  Starting simulation...
+info: Entering event queue @ 1433640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1433664085500.  Starting simulation...
+info: Entering event queue @ 1434640648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1434570335500.  Starting simulation...
+info: Entering event queue @ 1435546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1435570335500.  Starting simulation...
+info: Entering event queue @ 1436546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1436570335500.  Starting simulation...
+info: Entering event queue @ 1437546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1437570335500.  Starting simulation...
+info: Entering event queue @ 1438546898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1438476585500.  Starting simulation...
+info: Entering event queue @ 1439453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1439476585500.  Starting simulation...
+info: Entering event queue @ 1440453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1440476585500.  Starting simulation...
+info: Entering event queue @ 1441453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1441476585500.  Starting simulation...
+info: Entering event queue @ 1442453148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1442382835500.  Starting simulation...
+info: Entering event queue @ 1443359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1443382835500.  Starting simulation...
+info: Entering event queue @ 1444359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1444382835500.  Starting simulation...
+info: Entering event queue @ 1445359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1445382835500.  Starting simulation...
+info: Entering event queue @ 1446359398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1446289085500.  Starting simulation...
+info: Entering event queue @ 1447265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1447289085500.  Starting simulation...
+info: Entering event queue @ 1448265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1448289085500.  Starting simulation...
+info: Entering event queue @ 1449265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1449289085500.  Starting simulation...
+info: Entering event queue @ 1450265648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1450195335500.  Starting simulation...
+info: Entering event queue @ 1451171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1451195335500.  Starting simulation...
+info: Entering event queue @ 1452171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1452195335500.  Starting simulation...
+info: Entering event queue @ 1453171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1453195335500.  Starting simulation...
+info: Entering event queue @ 1454171898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1454101585500.  Starting simulation...
+info: Entering event queue @ 1455078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1455101585500.  Starting simulation...
+info: Entering event queue @ 1456078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1456101585500.  Starting simulation...
+info: Entering event queue @ 1457078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1457101585500.  Starting simulation...
+info: Entering event queue @ 1458078148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1458007835500.  Starting simulation...
+info: Entering event queue @ 1458984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1459007835500.  Starting simulation...
+info: Entering event queue @ 1459984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1460007835500.  Starting simulation...
+info: Entering event queue @ 1460984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1461007835500.  Starting simulation...
+info: Entering event queue @ 1461984398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1461914085500.  Starting simulation...
+info: Entering event queue @ 1462890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1462914085500.  Starting simulation...
+info: Entering event queue @ 1463890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1463914085500.  Starting simulation...
+info: Entering event queue @ 1464890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1464914085500.  Starting simulation...
+info: Entering event queue @ 1465890648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1465820335500.  Starting simulation...
+info: Entering event queue @ 1466796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1466820335500.  Starting simulation...
+info: Entering event queue @ 1467796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1467820335500.  Starting simulation...
+info: Entering event queue @ 1468796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1468820335500.  Starting simulation...
+info: Entering event queue @ 1469796898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1469726585500.  Starting simulation...
+info: Entering event queue @ 1470703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1470726585500.  Starting simulation...
+info: Entering event queue @ 1471703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1471726585500.  Starting simulation...
+info: Entering event queue @ 1472703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1472726585500.  Starting simulation...
+info: Entering event queue @ 1473703148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1473632835500.  Starting simulation...
+info: Entering event queue @ 1474609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1474632835500.  Starting simulation...
+info: Entering event queue @ 1475609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1475632835500.  Starting simulation...
+info: Entering event queue @ 1476609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1476632835500.  Starting simulation...
+info: Entering event queue @ 1477609398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1477539085500.  Starting simulation...
+info: Entering event queue @ 1478515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1478539085500.  Starting simulation...
+info: Entering event queue @ 1479515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1479539085500.  Starting simulation...
+info: Entering event queue @ 1480515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1480539085500.  Starting simulation...
+info: Entering event queue @ 1481515648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1481445335500.  Starting simulation...
+info: Entering event queue @ 1482421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1482445335500.  Starting simulation...
+info: Entering event queue @ 1483421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1483445335500.  Starting simulation...
+info: Entering event queue @ 1484421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1484445335500.  Starting simulation...
+info: Entering event queue @ 1485421898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1485351585500.  Starting simulation...
+info: Entering event queue @ 1486328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1486351585500.  Starting simulation...
+info: Entering event queue @ 1487328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1487351585500.  Starting simulation...
+info: Entering event queue @ 1488328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1488351585500.  Starting simulation...
+info: Entering event queue @ 1489328148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1489257835500.  Starting simulation...
+info: Entering event queue @ 1490234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1490257835500.  Starting simulation...
+info: Entering event queue @ 1491234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1491257835500.  Starting simulation...
+info: Entering event queue @ 1492234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1492257835500.  Starting simulation...
+info: Entering event queue @ 1493234398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1493164085500.  Starting simulation...
+info: Entering event queue @ 1494140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1494164085500.  Starting simulation...
+info: Entering event queue @ 1495140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1495164085500.  Starting simulation...
+info: Entering event queue @ 1496140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1496164085500.  Starting simulation...
+info: Entering event queue @ 1497140648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1497070335500.  Starting simulation...
+info: Entering event queue @ 1498046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1498070335500.  Starting simulation...
+info: Entering event queue @ 1499046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1499070335500.  Starting simulation...
+info: Entering event queue @ 1500046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1500070335500.  Starting simulation...
+info: Entering event queue @ 1501046898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1500976585500.  Starting simulation...
+info: Entering event queue @ 1501953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1501976585500.  Starting simulation...
+info: Entering event queue @ 1502953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1502976585500.  Starting simulation...
+info: Entering event queue @ 1503953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1503976585500.  Starting simulation...
+info: Entering event queue @ 1504953148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1504882835500.  Starting simulation...
+info: Entering event queue @ 1505859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1505882835500.  Starting simulation...
+info: Entering event queue @ 1506859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1506882835500.  Starting simulation...
+info: Entering event queue @ 1507859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1507882835500.  Starting simulation...
+info: Entering event queue @ 1508859398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1508789085500.  Starting simulation...
+info: Entering event queue @ 1509765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1509789085500.  Starting simulation...
+info: Entering event queue @ 1510765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1510789085500.  Starting simulation...
+info: Entering event queue @ 1511765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1511789085500.  Starting simulation...
+info: Entering event queue @ 1512765648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1512695335500.  Starting simulation...
+info: Entering event queue @ 1513671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1513695335500.  Starting simulation...
+info: Entering event queue @ 1514671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1514695335500.  Starting simulation...
+info: Entering event queue @ 1515671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1515695335500.  Starting simulation...
+info: Entering event queue @ 1516671898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1516601585500.  Starting simulation...
+info: Entering event queue @ 1517578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1517601585500.  Starting simulation...
+info: Entering event queue @ 1518578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1518601585500.  Starting simulation...
+info: Entering event queue @ 1519578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1519601585500.  Starting simulation...
+info: Entering event queue @ 1520578148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1520507835500.  Starting simulation...
+info: Entering event queue @ 1521484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1521507835500.  Starting simulation...
+info: Entering event queue @ 1522484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1522507835500.  Starting simulation...
+info: Entering event queue @ 1523484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1523507835500.  Starting simulation...
+info: Entering event queue @ 1524484398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1524414085500.  Starting simulation...
+info: Entering event queue @ 1525390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1525414085500.  Starting simulation...
+info: Entering event queue @ 1526390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1526414085500.  Starting simulation...
+info: Entering event queue @ 1527390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1527414085500.  Starting simulation...
+info: Entering event queue @ 1528390648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1528320335500.  Starting simulation...
+info: Entering event queue @ 1529296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1529320335500.  Starting simulation...
+info: Entering event queue @ 1530296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1530320335500.  Starting simulation...
+info: Entering event queue @ 1531296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1531320335500.  Starting simulation...
+info: Entering event queue @ 1532296898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1532226585500.  Starting simulation...
+info: Entering event queue @ 1533203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1533226585500.  Starting simulation...
+info: Entering event queue @ 1534203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1534226585500.  Starting simulation...
+info: Entering event queue @ 1535203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1535226585500.  Starting simulation...
+info: Entering event queue @ 1536203148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1536132835500.  Starting simulation...
+info: Entering event queue @ 1537109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1537132835500.  Starting simulation...
+info: Entering event queue @ 1538109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1538132835500.  Starting simulation...
+info: Entering event queue @ 1539109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1539132835500.  Starting simulation...
+info: Entering event queue @ 1540109398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1540039085500.  Starting simulation...
+info: Entering event queue @ 1541015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1541039085500.  Starting simulation...
+info: Entering event queue @ 1542015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1542039085500.  Starting simulation...
+info: Entering event queue @ 1543015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1543039085500.  Starting simulation...
+info: Entering event queue @ 1544015648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1543945335500.  Starting simulation...
+info: Entering event queue @ 1544921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1544945335500.  Starting simulation...
+info: Entering event queue @ 1545921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1545945335500.  Starting simulation...
+info: Entering event queue @ 1546921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1546945335500.  Starting simulation...
+info: Entering event queue @ 1547921898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1547851585500.  Starting simulation...
+info: Entering event queue @ 1548828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1548851585500.  Starting simulation...
+info: Entering event queue @ 1549828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1549851585500.  Starting simulation...
+info: Entering event queue @ 1550828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1550851585500.  Starting simulation...
+info: Entering event queue @ 1551828148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1551757835500.  Starting simulation...
+info: Entering event queue @ 1552734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1552757835500.  Starting simulation...
+info: Entering event queue @ 1553734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1553757835500.  Starting simulation...
+info: Entering event queue @ 1554734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1554757835500.  Starting simulation...
+info: Entering event queue @ 1555734398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1555664085500.  Starting simulation...
+info: Entering event queue @ 1556640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1556664085500.  Starting simulation...
+info: Entering event queue @ 1557640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1557664085500.  Starting simulation...
+info: Entering event queue @ 1558640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1558664085500.  Starting simulation...
+info: Entering event queue @ 1559640648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1559570335500.  Starting simulation...
+info: Entering event queue @ 1560546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1560570335500.  Starting simulation...
+info: Entering event queue @ 1561546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1561570335500.  Starting simulation...
+info: Entering event queue @ 1562546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1562570335500.  Starting simulation...
+info: Entering event queue @ 1563546898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1563476585500.  Starting simulation...
+info: Entering event queue @ 1564453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1564476585500.  Starting simulation...
+info: Entering event queue @ 1565453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1565476585500.  Starting simulation...
+info: Entering event queue @ 1566453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1566476585500.  Starting simulation...
+info: Entering event queue @ 1567453148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1567382835500.  Starting simulation...
+info: Entering event queue @ 1568359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1568382835500.  Starting simulation...
+info: Entering event queue @ 1569359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1569382835500.  Starting simulation...
+info: Entering event queue @ 1570359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1570382835500.  Starting simulation...
+info: Entering event queue @ 1571359398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1571289085500.  Starting simulation...
+info: Entering event queue @ 1572265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1572289085500.  Starting simulation...
+info: Entering event queue @ 1573265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1573289085500.  Starting simulation...
+info: Entering event queue @ 1574265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1574289085500.  Starting simulation...
+info: Entering event queue @ 1575265648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1575195335500.  Starting simulation...
+info: Entering event queue @ 1576171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1576195335500.  Starting simulation...
+info: Entering event queue @ 1577171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1577195335500.  Starting simulation...
+info: Entering event queue @ 1578171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1578195335500.  Starting simulation...
+info: Entering event queue @ 1579171898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1579101585500.  Starting simulation...
+info: Entering event queue @ 1580078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1580101585500.  Starting simulation...
+info: Entering event queue @ 1581078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1581101585500.  Starting simulation...
+info: Entering event queue @ 1582078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1582101585500.  Starting simulation...
+info: Entering event queue @ 1583078148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1583007835500.  Starting simulation...
+info: Entering event queue @ 1583984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1584007835500.  Starting simulation...
+info: Entering event queue @ 1584984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1585007835500.  Starting simulation...
+info: Entering event queue @ 1585984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1586007835500.  Starting simulation...
+info: Entering event queue @ 1586984398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1586914085500.  Starting simulation...
+info: Entering event queue @ 1587890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1587914085500.  Starting simulation...
+info: Entering event queue @ 1588890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1588914085500.  Starting simulation...
+info: Entering event queue @ 1589890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1589914085500.  Starting simulation...
+info: Entering event queue @ 1590890648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1590820335500.  Starting simulation...
+info: Entering event queue @ 1591796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1591820335500.  Starting simulation...
+info: Entering event queue @ 1592796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1592820335500.  Starting simulation...
+info: Entering event queue @ 1593796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1593820335500.  Starting simulation...
+info: Entering event queue @ 1594796898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1594726585500.  Starting simulation...
+info: Entering event queue @ 1595703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1595726585500.  Starting simulation...
+info: Entering event queue @ 1596703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1596726585500.  Starting simulation...
+info: Entering event queue @ 1597703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1597726585500.  Starting simulation...
+info: Entering event queue @ 1598703148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1598632835500.  Starting simulation...
+info: Entering event queue @ 1599609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1599632835500.  Starting simulation...
+info: Entering event queue @ 1600609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1600632835500.  Starting simulation...
+info: Entering event queue @ 1601609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1601632835500.  Starting simulation...
+info: Entering event queue @ 1602609398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1602539085500.  Starting simulation...
+info: Entering event queue @ 1603515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1603539085500.  Starting simulation...
+info: Entering event queue @ 1604515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1604539085500.  Starting simulation...
+info: Entering event queue @ 1605515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1605539085500.  Starting simulation...
+info: Entering event queue @ 1606515648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1606445335500.  Starting simulation...
+info: Entering event queue @ 1607421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1607445335500.  Starting simulation...
+info: Entering event queue @ 1608421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1608445335500.  Starting simulation...
+info: Entering event queue @ 1609421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1609445335500.  Starting simulation...
+info: Entering event queue @ 1610421898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1610351585500.  Starting simulation...
+info: Entering event queue @ 1611328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1611351585500.  Starting simulation...
+info: Entering event queue @ 1612328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1612351585500.  Starting simulation...
+info: Entering event queue @ 1613328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1613351585500.  Starting simulation...
+info: Entering event queue @ 1614328148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1614257835500.  Starting simulation...
+info: Entering event queue @ 1615234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1615257835500.  Starting simulation...
+info: Entering event queue @ 1616234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1616257835500.  Starting simulation...
+info: Entering event queue @ 1617234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1617257835500.  Starting simulation...
+info: Entering event queue @ 1618234398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1618164085500.  Starting simulation...
+info: Entering event queue @ 1619140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1619164085500.  Starting simulation...
+info: Entering event queue @ 1620140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1620164085500.  Starting simulation...
+info: Entering event queue @ 1621140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1621164085500.  Starting simulation...
+info: Entering event queue @ 1622140648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1622070335500.  Starting simulation...
+info: Entering event queue @ 1623046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1623070335500.  Starting simulation...
+info: Entering event queue @ 1624046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1624070335500.  Starting simulation...
+info: Entering event queue @ 1625046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1625070335500.  Starting simulation...
+info: Entering event queue @ 1626046898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1625976585500.  Starting simulation...
+info: Entering event queue @ 1626953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1626976585500.  Starting simulation...
+info: Entering event queue @ 1627953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1627976585500.  Starting simulation...
+info: Entering event queue @ 1628953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1628976585500.  Starting simulation...
+info: Entering event queue @ 1629953148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1629882835500.  Starting simulation...
+info: Entering event queue @ 1630859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1630882835500.  Starting simulation...
+info: Entering event queue @ 1631859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1631882835500.  Starting simulation...
+info: Entering event queue @ 1632859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1632882835500.  Starting simulation...
+info: Entering event queue @ 1633859398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1633789085500.  Starting simulation...
+info: Entering event queue @ 1634765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1634789085500.  Starting simulation...
+info: Entering event queue @ 1635765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1635789085500.  Starting simulation...
+info: Entering event queue @ 1636765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1636789085500.  Starting simulation...
+info: Entering event queue @ 1637765648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1637695335500.  Starting simulation...
+info: Entering event queue @ 1638671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1638695335500.  Starting simulation...
+info: Entering event queue @ 1639671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1639695335500.  Starting simulation...
+info: Entering event queue @ 1640671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1640695335500.  Starting simulation...
+info: Entering event queue @ 1641671898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1641601585500.  Starting simulation...
+info: Entering event queue @ 1642578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1642601585500.  Starting simulation...
+info: Entering event queue @ 1643578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1643601585500.  Starting simulation...
+info: Entering event queue @ 1644578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1644601585500.  Starting simulation...
+info: Entering event queue @ 1645578148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1645507835500.  Starting simulation...
+info: Entering event queue @ 1646484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1646507835500.  Starting simulation...
+info: Entering event queue @ 1647484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1647507835500.  Starting simulation...
+info: Entering event queue @ 1648484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1648507835500.  Starting simulation...
+info: Entering event queue @ 1649484398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1649414085500.  Starting simulation...
+info: Entering event queue @ 1650390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1650414085500.  Starting simulation...
+info: Entering event queue @ 1651390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1651414085500.  Starting simulation...
+info: Entering event queue @ 1652390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1652414085500.  Starting simulation...
+info: Entering event queue @ 1653390648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1653320335500.  Starting simulation...
+info: Entering event queue @ 1654296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1654320335500.  Starting simulation...
+info: Entering event queue @ 1655296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1655320335500.  Starting simulation...
+info: Entering event queue @ 1656296898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1656320335500.  Starting simulation...
+info: Entering event queue @ 1657296898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1657226585500.  Starting simulation...
+info: Entering event queue @ 1658203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1658226585500.  Starting simulation...
+info: Entering event queue @ 1659203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1659226585500.  Starting simulation...
+info: Entering event queue @ 1660203148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1660226585500.  Starting simulation...
+info: Entering event queue @ 1661203148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1661132835500.  Starting simulation...
+info: Entering event queue @ 1662109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1662132835500.  Starting simulation...
+info: Entering event queue @ 1663109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1663132835500.  Starting simulation...
+info: Entering event queue @ 1664109398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1664132835500.  Starting simulation...
+info: Entering event queue @ 1665109398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1665039085500.  Starting simulation...
+info: Entering event queue @ 1666015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1666039085500.  Starting simulation...
+info: Entering event queue @ 1667015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1667039085500.  Starting simulation...
+info: Entering event queue @ 1668015648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1668039085500.  Starting simulation...
+info: Entering event queue @ 1669015648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1668945335500.  Starting simulation...
+info: Entering event queue @ 1669921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1669945335500.  Starting simulation...
+info: Entering event queue @ 1670921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1670945335500.  Starting simulation...
+info: Entering event queue @ 1671921898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1671945335500.  Starting simulation...
+info: Entering event queue @ 1672921898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1672851585500.  Starting simulation...
+info: Entering event queue @ 1673828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1673851585500.  Starting simulation...
+info: Entering event queue @ 1674828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1674851585500.  Starting simulation...
+info: Entering event queue @ 1675828148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1675851585500.  Starting simulation...
+info: Entering event queue @ 1676828148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1676757835500.  Starting simulation...
+info: Entering event queue @ 1677734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1677757835500.  Starting simulation...
+info: Entering event queue @ 1678734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1678757835500.  Starting simulation...
+info: Entering event queue @ 1679734398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1679757835500.  Starting simulation...
+info: Entering event queue @ 1680734398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1680664085500.  Starting simulation...
+info: Entering event queue @ 1681640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1681664085500.  Starting simulation...
+info: Entering event queue @ 1682640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1682664085500.  Starting simulation...
+info: Entering event queue @ 1683640648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1683664085500.  Starting simulation...
+info: Entering event queue @ 1684640648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1684570335500.  Starting simulation...
+info: Entering event queue @ 1685546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1685570335500.  Starting simulation...
+info: Entering event queue @ 1686546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1686570335500.  Starting simulation...
+info: Entering event queue @ 1687546898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1687570335500.  Starting simulation...
+info: Entering event queue @ 1688546898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1688476585500.  Starting simulation...
+info: Entering event queue @ 1689453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1689476585500.  Starting simulation...
+info: Entering event queue @ 1690453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1690476585500.  Starting simulation...
+info: Entering event queue @ 1691453148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1691476585500.  Starting simulation...
+info: Entering event queue @ 1692453148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1692382835500.  Starting simulation...
+info: Entering event queue @ 1693359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1693382835500.  Starting simulation...
+info: Entering event queue @ 1694359398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1694382835500.  Starting simulation...
+info: Entering event queue @ 1695359398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1694382843000.  Starting simulation...
+info: Entering event queue @ 1695359405500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1695382843000.  Starting simulation...
+info: Entering event queue @ 1696359405500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1696289085500.  Starting simulation...
+info: Entering event queue @ 1697265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1697289085500.  Starting simulation...
+info: Entering event queue @ 1698265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1698289085500.  Starting simulation...
+info: Entering event queue @ 1699265648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1699289085500.  Starting simulation...
+info: Entering event queue @ 1700265648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1700195335500.  Starting simulation...
+info: Entering event queue @ 1701171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1701195335500.  Starting simulation...
+info: Entering event queue @ 1702171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1702195335500.  Starting simulation...
+info: Entering event queue @ 1703171898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1703195335500.  Starting simulation...
+info: Entering event queue @ 1704171898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1704101585500.  Starting simulation...
+info: Entering event queue @ 1705078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1705101585500.  Starting simulation...
+info: Entering event queue @ 1706078148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1706101585500.  Starting simulation...
+info: Entering event queue @ 1707078148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1706101593000.  Starting simulation...
+info: Entering event queue @ 1707078155500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1707101593000.  Starting simulation...
+info: Entering event queue @ 1708078155500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1708007835500.  Starting simulation...
+info: Entering event queue @ 1708984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1709007835500.  Starting simulation...
+info: Entering event queue @ 1709984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1710007835500.  Starting simulation...
+info: Entering event queue @ 1710984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1711007835500.  Starting simulation...
+info: Entering event queue @ 1711984398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1711914085500.  Starting simulation...
+info: Entering event queue @ 1712890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1712914085500.  Starting simulation...
+info: Entering event queue @ 1713890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1713914085500.  Starting simulation...
+info: Entering event queue @ 1714890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1714914085500.  Starting simulation...
+info: Entering event queue @ 1715890648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1715820335500.  Starting simulation...
+info: Entering event queue @ 1716796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1716820335500.  Starting simulation...
+info: Entering event queue @ 1717796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1717820335500.  Starting simulation...
+info: Entering event queue @ 1718796898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1718820335500.  Starting simulation...
+info: Entering event queue @ 1719796898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1719726585500.  Starting simulation...
+info: Entering event queue @ 1720703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1720726585500.  Starting simulation...
+info: Entering event queue @ 1721703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1721726585500.  Starting simulation...
+info: Entering event queue @ 1722703148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1722726585500.  Starting simulation...
+info: Entering event queue @ 1723703148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1723632835500.  Starting simulation...
+info: Entering event queue @ 1724609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1724632835500.  Starting simulation...
+info: Entering event queue @ 1725609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1725632835500.  Starting simulation...
+info: Entering event queue @ 1726609398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1726632835500.  Starting simulation...
+info: Entering event queue @ 1727609398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1727539085500.  Starting simulation...
+info: Entering event queue @ 1728515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1728539085500.  Starting simulation...
+info: Entering event queue @ 1729515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1729539085500.  Starting simulation...
+info: Entering event queue @ 1730515648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1730539085500.  Starting simulation...
+info: Entering event queue @ 1731515648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1731445335500.  Starting simulation...
+info: Entering event queue @ 1732421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1732445335500.  Starting simulation...
+info: Entering event queue @ 1733421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1733445335500.  Starting simulation...
+info: Entering event queue @ 1734421898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1734445335500.  Starting simulation...
+info: Entering event queue @ 1735421898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1735351585500.  Starting simulation...
+info: Entering event queue @ 1736328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1736351585500.  Starting simulation...
+info: Entering event queue @ 1737328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1737351585500.  Starting simulation...
+info: Entering event queue @ 1738328148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1738351585500.  Starting simulation...
+info: Entering event queue @ 1739328148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1739257835500.  Starting simulation...
+info: Entering event queue @ 1740234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1740257835500.  Starting simulation...
+info: Entering event queue @ 1741234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1741257835500.  Starting simulation...
+info: Entering event queue @ 1742234398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1742257835500.  Starting simulation...
+info: Entering event queue @ 1743234398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1743164085500.  Starting simulation...
+info: Entering event queue @ 1744140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1744164085500.  Starting simulation...
+info: Entering event queue @ 1745140648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1745164085500.  Starting simulation...
+info: Entering event queue @ 1746140648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1745164093000.  Starting simulation...
+info: Entering event queue @ 1746140655500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1746164093000.  Starting simulation...
+info: Entering event queue @ 1747140655500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1747070335500.  Starting simulation...
+info: Entering event queue @ 1748046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1748070335500.  Starting simulation...
+info: Entering event queue @ 1749046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1749070335500.  Starting simulation...
+info: Entering event queue @ 1750046898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1750070335500.  Starting simulation...
+info: Entering event queue @ 1751046898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1750976585500.  Starting simulation...
+info: Entering event queue @ 1751953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1751976585500.  Starting simulation...
+info: Entering event queue @ 1752953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1752976585500.  Starting simulation...
+info: Entering event queue @ 1753953148000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1753976585500.  Starting simulation...
+info: Entering event queue @ 1754953148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1754882835500.  Starting simulation...
+info: Entering event queue @ 1755859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1755882835500.  Starting simulation...
+info: Entering event queue @ 1756859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1756882835500.  Starting simulation...
+info: Entering event queue @ 1757859398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1757882835500.  Starting simulation...
+info: Entering event queue @ 1758859398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1758789085500.  Starting simulation...
+info: Entering event queue @ 1759765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1759789085500.  Starting simulation...
+info: Entering event queue @ 1760765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1760789085500.  Starting simulation...
+info: Entering event queue @ 1761765648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1761789085500.  Starting simulation...
+info: Entering event queue @ 1762765648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1762695335500.  Starting simulation...
+info: Entering event queue @ 1763671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1763695335500.  Starting simulation...
+info: Entering event queue @ 1764671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1764695335500.  Starting simulation...
+info: Entering event queue @ 1765671898000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1765695335500.  Starting simulation...
+info: Entering event queue @ 1766671898000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1766601585500.  Starting simulation...
+info: Entering event queue @ 1767578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1767601585500.  Starting simulation...
+info: Entering event queue @ 1768578148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1768601585500.  Starting simulation...
+info: Entering event queue @ 1769578148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1768601593000.  Starting simulation...
+info: Entering event queue @ 1769578155500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1769601593000.  Starting simulation...
+info: Entering event queue @ 1770578155500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1770507835500.  Starting simulation...
+info: Entering event queue @ 1771484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1771507835500.  Starting simulation...
+info: Entering event queue @ 1772484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1772507835500.  Starting simulation...
+info: Entering event queue @ 1773484398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1773507835500.  Starting simulation...
+info: Entering event queue @ 1774484398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1774414085500.  Starting simulation...
+info: Entering event queue @ 1775390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1775414085500.  Starting simulation...
+info: Entering event queue @ 1776390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1776414085500.  Starting simulation...
+info: Entering event queue @ 1777390648000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1777414085500.  Starting simulation...
+info: Entering event queue @ 1778390648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1777415067000.  Starting simulation...
+info: Entering event queue @ 1778390871500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1778415067000.  Starting simulation...
+info: Entering event queue @ 1779390871500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1779415067000.  Starting simulation...
+info: Entering event queue @ 1780390871500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1780415067000.  Starting simulation...
+info: Entering event queue @ 1781390871500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1781250023000.  Starting simulation...
+info: Entering event queue @ 1782226585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1782250023000.  Starting simulation...
+info: Entering event queue @ 1783226585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1783250023000.  Starting simulation...
+info: Entering event queue @ 1784226585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1783250030500.  Starting simulation...
+info: Entering event queue @ 1784226593000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1784250030500.  Starting simulation...
+info: Entering event queue @ 1785226593000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1785156273000.  Starting simulation...
+info: Entering event queue @ 1786132835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1786156273000.  Starting simulation...
+info: Entering event queue @ 1787132835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1787156273000.  Starting simulation...
+info: Entering event queue @ 1788132835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1788156273000.  Starting simulation...
+info: Entering event queue @ 1789132835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1789062523000.  Starting simulation...
+info: Entering event queue @ 1790039085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1790062523000.  Starting simulation...
+info: Entering event queue @ 1791039085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1791062523000.  Starting simulation...
+info: Entering event queue @ 1792039085500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1792062523000.  Starting simulation...
+info: Entering event queue @ 1793039085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1792968773000.  Starting simulation...
+info: Entering event queue @ 1793945335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1793968773000.  Starting simulation...
+info: Entering event queue @ 1794945335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1794968773000.  Starting simulation...
+info: Entering event queue @ 1795945335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1794968780500.  Starting simulation...
+info: Entering event queue @ 1795945343000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1795968780500.  Starting simulation...
+info: Entering event queue @ 1796945343000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1796875023000.  Starting simulation...
+info: Entering event queue @ 1797851585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1797875023000.  Starting simulation...
+info: Entering event queue @ 1798851585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1798875023000.  Starting simulation...
+info: Entering event queue @ 1799851585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1799875023000.  Starting simulation...
+info: Entering event queue @ 1800851585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1800781273000.  Starting simulation...
+info: Entering event queue @ 1801757835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1801781273000.  Starting simulation...
+info: Entering event queue @ 1802757835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1802781273000.  Starting simulation...
+info: Entering event queue @ 1803757835500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1803781273000.  Starting simulation...
+info: Entering event queue @ 1804757835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1804687523000.  Starting simulation...
+info: Entering event queue @ 1805664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1805687523000.  Starting simulation...
+info: Entering event queue @ 1806664085500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1806687523000.  Starting simulation...
+info: Entering event queue @ 1807664085500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1806687530500.  Starting simulation...
+info: Entering event queue @ 1807664093000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1807687530500.  Starting simulation...
+info: Entering event queue @ 1808664093000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1808593773000.  Starting simulation...
+info: Entering event queue @ 1809570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1809593773000.  Starting simulation...
+info: Entering event queue @ 1810570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1810593773000.  Starting simulation...
+info: Entering event queue @ 1811570335500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1811593773000.  Starting simulation...
+info: Entering event queue @ 1812570335500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1812500023000.  Starting simulation...
+info: Entering event queue @ 1813476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1813500023000.  Starting simulation...
+info: Entering event queue @ 1814476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1814500023000.  Starting simulation...
+info: Entering event queue @ 1815476585500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1815500023000.  Starting simulation...
+info: Entering event queue @ 1816476585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1816406273000.  Starting simulation...
+info: Entering event queue @ 1817382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1817406273000.  Starting simulation...
+info: Entering event queue @ 1818382835500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1818406273000.  Starting simulation...
+info: Entering event queue @ 1819382835500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1818406280500.  Starting simulation...
+info: Entering event queue @ 1819382844500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1819406280500.  Starting simulation...
+info: Entering event queue @ 1820382844500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1819406919000.  Starting simulation...
+info: Entering event queue @ 1820383742000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1820406919000.  Starting simulation...
+info: Entering event queue @ 1821383742000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1821406919000.  Starting simulation...
+info: Entering event queue @ 1822383742000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1821406926500.  Starting simulation...
+info: Entering event queue @ 1822383749500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1822406926500.  Starting simulation...
+info: Entering event queue @ 1823383749500.  Starting simulation...
+info: Entering event queue @ 1823383883000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1822406934000.  Starting simulation...
+info: Entering event queue @ 1823383890500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1823406934000.  Starting simulation...
+info: Entering event queue @ 1824383890500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1824406934000.  Starting simulation...
+info: Entering event queue @ 1825383890500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1825406934000.  Starting simulation...
+info: Entering event queue @ 1826383890500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1826171898000.  Starting simulation...
+info: Entering event queue @ 1827148460500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1827171898000.  Starting simulation...
+info: Entering event queue @ 1828148460500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1828171898000.  Starting simulation...
+info: Entering event queue @ 1829148460500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1829171898000.  Starting simulation...
-info: Entering event queue @ 1829171905500.  Starting simulation...
-info: Entering event queue @ 1829171910500.  Starting simulation...
+info: Entering event queue @ 1830148460500.  Starting simulation...
+info: Entering event queue @ 1830148471500.  Starting simulation...
+info: Entering event queue @ 1830148476000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1829171915000.  Starting simulation...
+info: Entering event queue @ 1830148477000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1830171915000.  Starting simulation...
+info: Entering event queue @ 1831148477000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1831171915000.  Starting simulation...
+info: Entering event queue @ 1832148477000.  Starting simulation...
+info: Entering event queue @ 1832148513000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1831171922500.  Starting simulation...
+info: Entering event queue @ 1832148757750.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1832171922500.  Starting simulation...
+info: Entering event queue @ 1833148757750.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1833007835500.  Starting simulation...
+info: Entering event queue @ 1833984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1834007835500.  Starting simulation...
+info: Entering event queue @ 1834984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1835007835500.  Starting simulation...
+info: Entering event queue @ 1835984398000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1836007835500.  Starting simulation...
+info: Entering event queue @ 1836984398000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1836914085500.  Starting simulation...
+info: Entering event queue @ 1837890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1837914085500.  Starting simulation...
+info: Entering event queue @ 1838890648000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1838914085500.  Starting simulation...
-info: Entering event queue @ 1838914097000.  Starting simulation...
+info: Entering event queue @ 1839890648000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1838914100500.  Starting simulation...
+info: Entering event queue @ 1839890655500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1839914100500.  Starting simulation...
-info: Entering event queue @ 1839914110000.  Starting simulation...
+info: Entering event queue @ 1840890655500.  Starting simulation...
+info: Entering event queue @ 1840890668000.  Starting simulation...
+info: Entering event queue @ 1840890674500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1839914114500.  Starting simulation...
+info: Entering event queue @ 1840890679000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1840914114500.  Starting simulation...
+info: Entering event queue @ 1841890679000.  Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
index 4ca026c3a..3a7534dfa 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/config.ini
@@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
+children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
@@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -70,6 +71,11 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
@@ -84,7 +90,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=system.cpu.checker
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -163,11 +169,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -176,9 +180,8 @@ predType=tournament
 [system.cpu.checker]
 type=O3Checker
 children=dtb isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -213,7 +216,7 @@ walker=system.cpu.checker.dtb.walker
 
 [system.cpu.checker.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[5]
@@ -243,7 +246,7 @@ walker=system.cpu.checker.itb.walker
 
 [system.cpu.checker.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[4]
@@ -253,10 +256,10 @@ type=ExeTracer
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -267,12 +270,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -281,7 +293,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -551,10 +563,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -565,12 +577,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -599,17 +620,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -620,16 +641,24 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -640,14 +669,18 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -656,10 +689,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -670,28 +703,36 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -709,19 +750,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -732,8 +778,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -746,16 +791,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -802,7 +847,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -820,7 +865,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -834,7 +879,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -843,7 +888,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -860,7 +905,7 @@ pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
-clock=1000
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -869,12 +914,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -884,7 +929,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -894,7 +939,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -904,7 +949,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -918,7 +963,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -931,7 +976,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -944,23 +989,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -970,19 +1015,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -994,7 +1038,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -1007,7 +1051,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -1017,7 +1061,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -1027,7 +1071,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -1037,7 +1081,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -1047,7 +1091,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -1061,7 +1105,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -1074,7 +1118,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -1089,7 +1133,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -1099,7 +1143,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -1109,7 +1153,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -1119,7 +1163,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -1139,3 +1183,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
index 9c29c3bb4..90faba56d 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simerr
@@ -11,23 +11,22 @@ warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr dccimvac' unimplemented
 warn: 	instruction 'mcr dccmvau' unimplemented
 warn: 	instruction 'mcr icimvau' unimplemented
-warn: 5695245000: Instruction results do not match! (Values may not actually be integers) Inst: 0x3744, checker: 0x3748
-warn: 5701912500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
-warn: 5710381500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
-warn: 5745167500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
-warn: 5760086500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
-warn: 6281852500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
+warn: 6117297500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3704, checker: 0x3708
+warn: 6125706500: Instruction results do not match! (Values may not actually be integers) Inst: 0x36c4, checker: 0x36c8
+warn: 6160975500: Instruction results do not match! (Values may not actually be integers) Inst: 0x3604, checker: 0x3608
+warn: 6176055500: Instruction results do not match! (Values may not actually be integers) Inst: 0x35c4, checker: 0x35c8
+warn: 6715294500: Instruction results do not match! (Values may not actually be integers) Inst: 0x34f0, checker: 0x34f8
 warn: LCD dual screen mode not supported
-warn: 52533955500: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
-warn: 2291148077500: Instruction results do not match! (Values may not actually be integers) Inst: 0x2, checker: 0
+warn: 51807478000: Instruction results do not match! (Values may not actually be integers) Inst: 0x19dc, checker: 0x1a04
 warn: 	instruction 'mcr icialluis' unimplemented
 warn: 	instruction 'mcr bpiallis' unimplemented
-warn: 2483713797000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
-warn: 2498675085000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
-warn: 2519713161000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2520226805000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
-warn: 2525908166000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
-warn: 2526415429500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
-warn: 2526974192500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
-warn: 2526975291500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
+warn: 2474714862500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9debc, checker: 0
+warn: 2488540668500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2489750451500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2a4, checker: 0
+warn: 2510845218000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2511359133500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d2b4, checker: 0
+warn: 2517064152000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d974, checker: 0
+warn: 2517573704500: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d954, checker: 0
+warn: 2518135055000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9d9fc, checker: 0
+warn: 2518136146000: Instruction results do not match! (Values may not actually be integers) Inst: 0x9da34, checker: 0
 hack: be nice to actually delete the event here
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
index ccb217f9b..4638446ac 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-checker/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 28 2013 10:14:28
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:14:57
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2533114761500 because m5_exit instruction encountered
+Exiting @ tick 2524309551500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
index 0c5e2cb7e..83b4b4ad3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/config.ini
@@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
@@ -24,7 +25,7 @@ load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -70,6 +71,11 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
@@ -84,7 +90,7 @@ backComSize=5
 branchPred=system.cpu0.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -163,11 +169,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -175,10 +179,10 @@ predType=tournament
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -189,12 +193,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=ArmTLB
 children=walker
@@ -203,7 +216,7 @@ walker=system.cpu0.dtb.walker
 
 [system.cpu0.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[3]
@@ -473,10 +486,10 @@ opLat=3
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -487,12 +500,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=ArmInterrupts
 
@@ -521,7 +543,7 @@ walker=system.cpu0.itb.walker
 
 [system.cpu0.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[2]
@@ -543,7 +565,7 @@ backComSize=5
 branchPred=system.cpu1.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -622,11 +644,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -634,10 +654,10 @@ predType=tournament
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -648,12 +668,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=ArmTLB
 children=walker
@@ -662,7 +691,7 @@ walker=system.cpu1.dtb.walker
 
 [system.cpu1.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[7]
@@ -932,10 +961,10 @@ opLat=3
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -946,12 +975,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=ArmInterrupts
 
@@ -980,7 +1018,7 @@ walker=system.cpu1.itb.walker
 
 [system.cpu1.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[6]
@@ -988,14 +1026,18 @@ port=system.toL2Bus.slave[6]
 [system.cpu1.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -1004,10 +1046,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -1018,18 +1060,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -1040,28 +1091,36 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -1079,19 +1138,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -1102,8 +1166,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -1116,16 +1179,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -1172,7 +1235,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -1190,7 +1253,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -1204,7 +1267,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -1213,7 +1276,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -1230,7 +1293,7 @@ pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
-clock=1000
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -1239,12 +1302,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -1254,7 +1317,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -1264,7 +1327,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -1274,7 +1337,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -1288,7 +1351,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -1301,7 +1364,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -1314,23 +1377,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -1340,19 +1403,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -1364,7 +1426,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -1377,7 +1439,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -1387,7 +1449,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -1397,7 +1459,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -1407,7 +1469,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -1417,7 +1479,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -1431,7 +1493,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -1444,7 +1506,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -1459,7 +1521,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -1469,7 +1531,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -1479,7 +1541,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -1489,7 +1551,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -1505,8 +1567,7 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -1520,3 +1581,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
index f29c5e325..56628ec16 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 28 2013 10:17:38
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 07:58:48
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2602778916500 because m5_exit instruction encountered
+Exiting @ tick 1104038330000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
index 0edabf3c5..1d3b3b539 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/stats.txt
@@ -4,13 +4,31 @@ sim_seconds                                  1.104038                       # Nu
 sim_ticks                                1104038330000                       # Number of ticks simulated
 final_tick                               1104038330000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  80920                       # Simulator instruction rate (inst/s)
-host_op_rate                                   104171                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             1450259542                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 402880                       # Number of bytes of host memory used
-host_seconds                                   761.27                       # Real time elapsed on the host
+host_inst_rate                                  67767                       # Simulator instruction rate (inst/s)
+host_op_rate                                    87238                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             1214516577                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 404472                       # Number of bytes of host memory used
+host_seconds                                   909.04                       # Real time elapsed on the host
 sim_insts                                    61602211                       # Number of instructions simulated
 sim_ops                                      79302243                       # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu0.inst           58                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::cpu1.inst          348                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total              406                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu0.inst           58                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu1.inst          348                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total          406                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu0.inst           58                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu1.inst          348                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total             406                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd     48758784                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker          768                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker          192                       # Number of bytes read from this memory
@@ -467,24 +485,6 @@ system.physmem.writeRowHits                     98940                       # Nu
 system.physmem.readRowHitRate                   99.71                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  12.01                       # Row buffer hit rate for writes
 system.physmem.avgGap                       155904.23                       # Average gap between requests
-system.realview.nvmem.bytes_read::cpu0.inst           64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::cpu1.inst          384                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total           448                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu0.inst           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu1.inst          384                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total          448                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu0.inst            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::cpu1.inst            6                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              7                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu0.inst           58                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::cpu1.inst          348                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total              406                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu0.inst           58                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu1.inst          348                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total          406                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu0.inst           58                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu1.inst          348                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total             406                       # Total bandwidth to/from this memory (bytes/s)
 system.membus.throughput                     62410733                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq             7306749                       # Transaction distribution
 system.membus.trans_dist::ReadResp            7306749                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
deleted file mode 100644
index e41fe50a6..000000000
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/status
+++ /dev/null
@@ -1 +0,0 @@
-build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual FAILED!
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
index 6ee273ff2..ff60c1de9 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/system.terminal
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
index 2b8b39c77..442f4520f 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/config.ini
@@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
+children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
@@ -24,7 +25,7 @@ load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 mem_ranges=0:134217727
-memories=system.physmem system.realview.nvmem
+memories=system.realview.nvmem system.physmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -70,6 +71,11 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer
@@ -84,7 +90,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -163,11 +169,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -175,10 +179,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -189,12 +193,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -203,7 +216,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -473,10 +486,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -487,12 +500,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -521,17 +543,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -542,16 +564,24 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -562,14 +592,18 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -578,10 +612,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -592,28 +626,36 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -631,19 +673,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -654,8 +701,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -668,16 +714,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -724,7 +770,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -742,7 +788,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -756,7 +802,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -765,7 +811,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -782,7 +828,7 @@ pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
-clock=1000
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -791,12 +837,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -806,7 +852,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -816,7 +862,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -826,7 +872,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -840,7 +886,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -853,7 +899,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -866,23 +912,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -892,19 +938,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -916,7 +961,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -929,7 +974,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -939,7 +984,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -949,7 +994,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -959,7 +1004,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -969,7 +1014,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -983,7 +1028,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -996,7 +1041,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -1011,7 +1056,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -1021,7 +1066,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -1031,7 +1076,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -1041,7 +1086,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -1061,3 +1106,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
index 450b5d1ef..67309d0d5 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 28 2013 10:15:55
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 07:59:33
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2533114761500 because m5_exit instruction encountered
+Exiting @ tick 2524309551500 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
index 6a97d3f47..d95619189 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/stats.txt
@@ -4,13 +4,25 @@ sim_seconds                                  2.524310                       # Nu
 sim_ticks                                2524309551500                       # Number of ticks simulated
 final_tick                               2524309551500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                  81082                       # Simulator instruction rate (inst/s)
-host_op_rate                                   104330                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             3394002800                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 397632                       # Number of bytes of host memory used
-host_seconds                                   743.76                       # Real time elapsed on the host
+host_inst_rate                                  66090                       # Simulator instruction rate (inst/s)
+host_op_rate                                    85039                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             2766442256                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 401396                       # Number of bytes of host memory used
+host_seconds                                   912.48                       # Real time elapsed on the host
 sim_insts                                    60305560                       # Number of instructions simulated
 sim_ops                                      77596391                       # Number of ops (including micro ops) simulated
+system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
+system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
+system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
+system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
+system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
+system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
+system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bytes_read::realview.clcd    119537664                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.dtb.walker         3264                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu.itb.walker          128                       # Number of bytes read from this memory
@@ -428,18 +440,6 @@ system.physmem.writeRowHits                     94229                       # Nu
 system.physmem.readRowHitRate                   99.83                       # Row buffer hit rate for reads
 system.physmem.writeRowHitRate                  11.59                       # Row buffer hit rate for writes
 system.physmem.avgGap                       158662.04                       # Average gap between requests
-system.realview.nvmem.bytes_read::cpu.inst           64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_read::total            64                       # Number of bytes read from this memory
-system.realview.nvmem.bytes_inst_read::cpu.inst           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.bytes_inst_read::total           64                       # Number of instructions bytes read from this memory
-system.realview.nvmem.num_reads::cpu.inst            1                       # Number of read requests responded to by this memory
-system.realview.nvmem.num_reads::total              1                       # Number of read requests responded to by this memory
-system.realview.nvmem.bw_read::cpu.inst            25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_read::total               25                       # Total read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::cpu.inst           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_inst_read::total           25                       # Instruction read bandwidth from this memory (bytes/s)
-system.realview.nvmem.bw_total::cpu.inst           25                       # Total bandwidth to/from this memory (bytes/s)
-system.realview.nvmem.bw_total::total              25                       # Total bandwidth to/from this memory (bytes/s)
 system.membus.throughput                     54917647                       # Throughput (bytes/s)
 system.membus.trans_dist::ReadReq            16149440                       # Transaction distribution
 system.membus.trans_dist::ReadResp           16149440                       # Transaction distribution
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
index e88d9e9c0..8f4cb76c4 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3/system.terminal
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
index 6dc26b748..843df146b 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/config.ini
@@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu0 cpu1 cpu2 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 clk_domain cpu0 cpu1 cpu2 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
@@ -24,7 +25,7 @@ load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
 mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -70,12 +71,16 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -110,10 +115,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -124,12 +129,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=ArmTLB
 children=walker
@@ -138,17 +152,17 @@ walker=system.cpu0.dtb.walker
 
 [system.cpu0.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -159,12 +173,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=ArmInterrupts
 
@@ -193,7 +216,7 @@ walker=system.cpu0.itb.walker
 
 [system.cpu0.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[2]
@@ -203,10 +226,9 @@ type=ExeTracer
 
 [system.cpu1]
 type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer
-branchPred=Null
+children=dtb isa itb tracer
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -214,7 +236,7 @@ do_statistics_insts=true
 dtb=system.cpu1.dtb
 function_trace=false
 function_trace_start=0
-interrupts=system.cpu1.interrupts
+interrupts=Null
 isa=system.cpu1.isa
 itb=system.cpu1.itb
 max_insts_all_threads=0
@@ -238,13 +260,10 @@ walker=system.cpu1.dtb.walker
 
 [system.cpu1.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
-[system.cpu1.interrupts]
-type=ArmInterrupts
-
 [system.cpu1.isa]
 type=ArmISA
 fpsid=1090793632
@@ -270,7 +289,7 @@ walker=system.cpu1.itb.walker
 
 [system.cpu1.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
@@ -279,7 +298,7 @@ type=ExeTracer
 
 [system.cpu2]
 type=DerivO3CPU
-children=branchPred dtb fuPool interrupts isa itb tracer
+children=branchPred dtb fuPool isa itb tracer
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
@@ -291,7 +310,7 @@ backComSize=5
 branchPred=system.cpu2.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -317,7 +336,7 @@ iewToCommitDelay=1
 iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
-interrupts=system.cpu2.interrupts
+interrupts=Null
 isa=system.cpu2.isa
 issueToExecuteDelay=1
 issueWidth=8
@@ -368,11 +387,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -386,7 +403,7 @@ walker=system.cpu2.dtb.walker
 
 [system.cpu2.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
@@ -653,9 +670,6 @@ issueLat=3
 opClass=IprAccess
 opLat=3
 
-[system.cpu2.interrupts]
-type=ArmInterrupts
-
 [system.cpu2.isa]
 type=ArmISA
 fpsid=1090793632
@@ -681,21 +695,25 @@ walker=system.cpu2.itb.walker
 
 [system.cpu2.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
 [system.cpu2.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -704,10 +722,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -718,18 +736,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -740,28 +767,36 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -779,19 +814,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -802,8 +842,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -816,16 +855,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -872,7 +911,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -890,7 +929,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -904,7 +943,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -913,7 +952,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -930,7 +969,7 @@ pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
-clock=1000
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -939,12 +978,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -954,7 +993,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -964,7 +1003,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -974,7 +1013,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -988,7 +1027,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -1001,7 +1040,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -1014,23 +1053,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -1040,19 +1079,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -1064,7 +1102,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -1077,7 +1115,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -1087,7 +1125,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -1097,7 +1135,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -1107,7 +1145,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -1117,7 +1155,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -1131,7 +1169,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -1144,7 +1182,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -1159,7 +1197,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -1169,7 +1207,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -1179,7 +1217,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -1189,7 +1227,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -1205,8 +1243,7 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -1220,3 +1257,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
index 9cf888f7d..d806d7d51 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 28 2013 10:14:28
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:26:23
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Switching CPUs...
@@ -19,4070 +19,4128 @@ Switching CPUs...
 Next CPU: DerivO3CPU
 info: Entering event queue @ 2000000000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2000001000.  Starting simulation...
+info: Entering event queue @ 2000002000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 3000001000.  Starting simulation...
+info: Entering event queue @ 3000002000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 3000004000.  Starting simulation...
+info: Entering event queue @ 3000005000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 4000004000.  Starting simulation...
+info: Entering event queue @ 4000005000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 5000004000.  Starting simulation...
-switching cpus
 info: Entering event queue @ 5000005000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5000005500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 6000005000.  Starting simulation...
+info: Entering event queue @ 6000005500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 6000010500.  Starting simulation...
+info: Entering event queue @ 6000011500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 7000010500.  Starting simulation...
+info: Entering event queue @ 7000011500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 8000010500.  Starting simulation...
+info: Entering event queue @ 8000011500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 8000121000.  Starting simulation...
+info: Entering event queue @ 8000193000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 9000121000.  Starting simulation...
+info: Entering event queue @ 9000193000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 9000131500.  Starting simulation...
+info: Entering event queue @ 9000195500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 10000131500.  Starting simulation...
+info: Entering event queue @ 10000195500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 11000131500.  Starting simulation...
+info: Entering event queue @ 11000195500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 11000132500.  Starting simulation...
+info: Entering event queue @ 11000203000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 12000132500.  Starting simulation...
+info: Entering event queue @ 12000203000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 12000140500.  Starting simulation...
+info: Entering event queue @ 12000210500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 13000140500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 13000141500.  Starting simulation...
+info: Entering event queue @ 13000210500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 14000141500.  Starting simulation...
+info: Entering event queue @ 14000210500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 14000161500.  Starting simulation...
+info: Entering event queue @ 14000218000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 15000161500.  Starting simulation...
+info: Entering event queue @ 15000218000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 15000173500.  Starting simulation...
+info: Entering event queue @ 15000660500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 16000173500.  Starting simulation...
+info: Entering event queue @ 16000660500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 17000173500.  Starting simulation...
+info: Entering event queue @ 17000660500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 17000181000.  Starting simulation...
+info: Entering event queue @ 17000668000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 18000181000.  Starting simulation...
-info: Entering event queue @ 26044694500.  Starting simulation...
-info: Entering event queue @ 26044701500.  Starting simulation...
+info: Entering event queue @ 18000668000.  Starting simulation...
+info: Entering event queue @ 26061002500.  Starting simulation...
+info: Entering event queue @ 26061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 26044706000.  Starting simulation...
+info: Entering event queue @ 26061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 27044706000.  Starting simulation...
+info: Entering event queue @ 27061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 28044706000.  Starting simulation...
+info: Entering event queue @ 28061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 29044706000.  Starting simulation...
-info: Entering event queue @ 36044694500.  Starting simulation...
-info: Entering event queue @ 36044701500.  Starting simulation...
+info: Entering event queue @ 29061009500.  Starting simulation...
+info: Entering event queue @ 36061002500.  Starting simulation...
+info: Entering event queue @ 36061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 36044706000.  Starting simulation...
+info: Entering event queue @ 36061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 37044706000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 37044706500.  Starting simulation...
+info: Entering event queue @ 37061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 38044706500.  Starting simulation...
-info: Entering event queue @ 38044722500.  Starting simulation...
+info: Entering event queue @ 38061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 38044806000.  Starting simulation...
+info: Entering event queue @ 38061018500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 39044806000.  Starting simulation...
+info: Entering event queue @ 39061018500.  Starting simulation...
+info: Entering event queue @ 39061063500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 39044813500.  Starting simulation...
+info: Entering event queue @ 39061151000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 40044813500.  Starting simulation...
+info: Entering event queue @ 40061151000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 41044813500.  Starting simulation...
+info: Entering event queue @ 41061151000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 41044821000.  Starting simulation...
+info: Entering event queue @ 41061158500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 42044821000.  Starting simulation...
+info: Entering event queue @ 42061158500.  Starting simulation...
+info: Entering event queue @ 42061194500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 42045002500.  Starting simulation...
+info: Entering event queue @ 42061214750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 43061214750.  Starting simulation...
 switching cpus
-info: Entering event queue @ 43045002500.  Starting simulation...
+info: Entering event queue @ 43061215000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 44045002500.  Starting simulation...
+info: Entering event queue @ 44061215000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 44045003500.  Starting simulation...
+info: Entering event queue @ 44061215500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 45045003500.  Starting simulation...
+info: Entering event queue @ 45061215500.  Starting simulation...
+info: Entering event queue @ 45061226000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 45045006000.  Starting simulation...
+info: Entering event queue @ 45061230500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 46045006000.  Starting simulation...
+info: Entering event queue @ 46061230500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 47045006000.  Starting simulation...
+info: Entering event queue @ 47061230500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 47045010000.  Starting simulation...
+info: Entering event queue @ 47061231000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 48045010000.  Starting simulation...
+info: Entering event queue @ 48061231000.  Starting simulation...
+info: Entering event queue @ 48061238500.  Starting simulation...
+info: Entering event queue @ 48061242500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 48045031000.  Starting simulation...
+info: Entering event queue @ 48061247000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 49045031000.  Starting simulation...
+info: Entering event queue @ 49061247000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 50045031000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 50045038500.  Starting simulation...
+info: Entering event queue @ 50061247000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 51045038500.  Starting simulation...
-info: Entering event queue @ 56044694500.  Starting simulation...
-info: Entering event queue @ 56044701500.  Starting simulation...
+info: Entering event queue @ 51061247000.  Starting simulation...
+info: Entering event queue @ 56061002500.  Starting simulation...
+info: Entering event queue @ 56061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 56044706000.  Starting simulation...
+info: Entering event queue @ 56061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 57044706000.  Starting simulation...
+info: Entering event queue @ 57061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 58044706000.  Starting simulation...
+info: Entering event queue @ 58061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 59044706000.  Starting simulation...
-info: Entering event queue @ 66044694500.  Starting simulation...
-info: Entering event queue @ 66044701500.  Starting simulation...
+info: Entering event queue @ 59061014000.  Starting simulation...
+info: Entering event queue @ 66061002500.  Starting simulation...
+info: Entering event queue @ 66061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 66044706000.  Starting simulation...
+info: Entering event queue @ 66061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 67044706000.  Starting simulation...
+info: Entering event queue @ 67061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 68044706000.  Starting simulation...
+info: Entering event queue @ 68061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 69044706000.  Starting simulation...
-info: Entering event queue @ 76044694500.  Starting simulation...
-info: Entering event queue @ 76044701500.  Starting simulation...
+info: Entering event queue @ 69061009500.  Starting simulation...
+info: Entering event queue @ 76061002500.  Starting simulation...
+info: Entering event queue @ 76061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 76044706000.  Starting simulation...
+info: Entering event queue @ 76061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 77044706000.  Starting simulation...
+info: Entering event queue @ 77061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 78044706000.  Starting simulation...
+info: Entering event queue @ 78061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 79044706000.  Starting simulation...
-info: Entering event queue @ 86044694500.  Starting simulation...
-info: Entering event queue @ 86044701000.  Starting simulation...
+info: Entering event queue @ 79061014000.  Starting simulation...
+info: Entering event queue @ 86061002500.  Starting simulation...
+info: Entering event queue @ 86061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 86044701500.  Starting simulation...
+info: Entering event queue @ 86061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 87044701500.  Starting simulation...
+info: Entering event queue @ 87061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 88044701500.  Starting simulation...
+info: Entering event queue @ 88061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 89044701500.  Starting simulation...
-info: Entering event queue @ 96044694500.  Starting simulation...
-info: Entering event queue @ 96044701500.  Starting simulation...
+info: Entering event queue @ 89061009500.  Starting simulation...
+info: Entering event queue @ 96061002500.  Starting simulation...
+info: Entering event queue @ 96061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 96044706000.  Starting simulation...
+info: Entering event queue @ 96061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 97044706000.  Starting simulation...
+info: Entering event queue @ 97061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 98044706000.  Starting simulation...
+info: Entering event queue @ 98061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 99044706000.  Starting simulation...
-info: Entering event queue @ 106044694500.  Starting simulation...
-info: Entering event queue @ 106044701500.  Starting simulation...
+info: Entering event queue @ 99061009500.  Starting simulation...
+info: Entering event queue @ 106061002500.  Starting simulation...
+info: Entering event queue @ 106061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 106044706000.  Starting simulation...
+info: Entering event queue @ 106061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 107044706000.  Starting simulation...
+info: Entering event queue @ 107061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 108044706000.  Starting simulation...
+info: Entering event queue @ 108061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 109044706000.  Starting simulation...
-info: Entering event queue @ 116044694500.  Starting simulation...
-info: Entering event queue @ 116044701500.  Starting simulation...
+info: Entering event queue @ 109061009500.  Starting simulation...
+info: Entering event queue @ 116061002500.  Starting simulation...
+info: Entering event queue @ 116061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 116044706000.  Starting simulation...
+info: Entering event queue @ 116061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 117044706000.  Starting simulation...
+info: Entering event queue @ 117061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 118044706000.  Starting simulation...
+info: Entering event queue @ 118061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 119044706000.  Starting simulation...
-info: Entering event queue @ 126044695500.  Starting simulation...
-info: Entering event queue @ 126044702000.  Starting simulation...
+info: Entering event queue @ 119061009500.  Starting simulation...
+info: Entering event queue @ 126061002500.  Starting simulation...
+info: Entering event queue @ 126061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 126044702500.  Starting simulation...
+info: Entering event queue @ 126061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 127044702500.  Starting simulation...
+info: Entering event queue @ 127061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 128044702500.  Starting simulation...
+info: Entering event queue @ 128061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 129044702500.  Starting simulation...
-info: Entering event queue @ 136044694500.  Starting simulation...
-info: Entering event queue @ 136044701000.  Starting simulation...
+info: Entering event queue @ 129061014000.  Starting simulation...
+info: Entering event queue @ 136061002500.  Starting simulation...
+info: Entering event queue @ 136206506250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 136044701500.  Starting simulation...
+info: Entering event queue @ 136206509000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 137044701500.  Starting simulation...
+info: Entering event queue @ 137206509000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 138044701500.  Starting simulation...
+info: Entering event queue @ 138206509000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 139044701500.  Starting simulation...
-info: Entering event queue @ 146044694500.  Starting simulation...
-info: Entering event queue @ 146044701500.  Starting simulation...
+info: Entering event queue @ 139206509000.  Starting simulation...
+info: Entering event queue @ 146061002500.  Starting simulation...
+info: Entering event queue @ 146061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 146044706000.  Starting simulation...
+info: Entering event queue @ 146061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 147044706000.  Starting simulation...
+info: Entering event queue @ 147061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 148044706000.  Starting simulation...
+info: Entering event queue @ 148061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 149044706000.  Starting simulation...
-info: Entering event queue @ 156044694500.  Starting simulation...
-info: Entering event queue @ 156044701500.  Starting simulation...
+info: Entering event queue @ 149061014000.  Starting simulation...
+info: Entering event queue @ 156061002500.  Starting simulation...
+info: Entering event queue @ 156061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 156044706000.  Starting simulation...
+info: Entering event queue @ 156061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 157044706000.  Starting simulation...
+info: Entering event queue @ 157061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 158044706000.  Starting simulation...
+info: Entering event queue @ 158061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 159044706000.  Starting simulation...
-info: Entering event queue @ 166044694500.  Starting simulation...
-info: Entering event queue @ 166044701500.  Starting simulation...
+info: Entering event queue @ 159061009500.  Starting simulation...
+info: Entering event queue @ 166061002500.  Starting simulation...
+info: Entering event queue @ 166061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 166044706000.  Starting simulation...
+info: Entering event queue @ 166061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 167044706000.  Starting simulation...
+info: Entering event queue @ 167061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
+info: Entering event queue @ 168061009500.  Starting simulation...
+info: Entering event queue @ 168904109250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 168044706000.  Starting simulation...
+info: Entering event queue @ 168904112000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 169044706000.  Starting simulation...
-info: Entering event queue @ 176044694500.  Starting simulation...
-info: Entering event queue @ 176044701500.  Starting simulation...
+info: Entering event queue @ 169904112000.  Starting simulation...
+info: Entering event queue @ 176061002500.  Starting simulation...
+info: Entering event queue @ 176061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 176044706000.  Starting simulation...
+info: Entering event queue @ 176061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 177044706000.  Starting simulation...
+info: Entering event queue @ 177061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 178044706000.  Starting simulation...
+info: Entering event queue @ 178061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 179044706000.  Starting simulation...
-info: Entering event queue @ 186044694500.  Starting simulation...
-info: Entering event queue @ 186044701500.  Starting simulation...
+info: Entering event queue @ 179061009500.  Starting simulation...
+info: Entering event queue @ 186061002500.  Starting simulation...
+info: Entering event queue @ 186061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 186044706000.  Starting simulation...
+info: Entering event queue @ 186061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 187044706000.  Starting simulation...
+info: Entering event queue @ 187061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 188044706000.  Starting simulation...
+info: Entering event queue @ 188061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 189044706000.  Starting simulation...
-info: Entering event queue @ 196044695500.  Starting simulation...
-info: Entering event queue @ 196044702500.  Starting simulation...
+info: Entering event queue @ 189061014000.  Starting simulation...
+info: Entering event queue @ 196061002500.  Starting simulation...
+info: Entering event queue @ 196061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 196044707000.  Starting simulation...
+info: Entering event queue @ 196061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 197044707000.  Starting simulation...
+info: Entering event queue @ 197061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 198044707000.  Starting simulation...
+info: Entering event queue @ 198061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 199044707000.  Starting simulation...
-info: Entering event queue @ 206044695500.  Starting simulation...
-info: Entering event queue @ 206044702500.  Starting simulation...
+info: Entering event queue @ 199061014000.  Starting simulation...
+info: Entering event queue @ 206061002500.  Starting simulation...
+info: Entering event queue @ 206061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 206044707000.  Starting simulation...
+info: Entering event queue @ 206061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 207044707000.  Starting simulation...
+info: Entering event queue @ 207061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 208044707000.  Starting simulation...
+info: Entering event queue @ 208061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 209044707000.  Starting simulation...
-info: Entering event queue @ 216044694500.  Starting simulation...
-info: Entering event queue @ 216044701500.  Starting simulation...
+info: Entering event queue @ 209061009500.  Starting simulation...
+info: Entering event queue @ 216061002500.  Starting simulation...
+info: Entering event queue @ 216061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 216044706000.  Starting simulation...
+info: Entering event queue @ 216061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 217044706000.  Starting simulation...
+info: Entering event queue @ 217061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 218044706000.  Starting simulation...
+info: Entering event queue @ 218061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 219044706000.  Starting simulation...
-info: Entering event queue @ 226044694500.  Starting simulation...
-info: Entering event queue @ 226044701500.  Starting simulation...
+info: Entering event queue @ 219061014000.  Starting simulation...
+info: Entering event queue @ 226061002500.  Starting simulation...
+info: Entering event queue @ 226061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 226044706000.  Starting simulation...
+info: Entering event queue @ 226061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 227044706000.  Starting simulation...
+info: Entering event queue @ 227061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 228044706000.  Starting simulation...
+info: Entering event queue @ 228061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 229044706000.  Starting simulation...
-info: Entering event queue @ 236044694500.  Starting simulation...
-info: Entering event queue @ 236044701500.  Starting simulation...
+info: Entering event queue @ 229061009500.  Starting simulation...
+info: Entering event queue @ 236061002500.  Starting simulation...
+info: Entering event queue @ 236061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 236044706000.  Starting simulation...
+info: Entering event queue @ 236061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 237044706000.  Starting simulation...
+info: Entering event queue @ 237061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 238044706000.  Starting simulation...
+info: Entering event queue @ 238061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 239044706000.  Starting simulation...
-info: Entering event queue @ 246044694500.  Starting simulation...
-info: Entering event queue @ 246044701000.  Starting simulation...
+info: Entering event queue @ 239061014000.  Starting simulation...
+info: Entering event queue @ 246061002500.  Starting simulation...
+info: Entering event queue @ 246061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 246044701500.  Starting simulation...
+info: Entering event queue @ 246061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 247044701500.  Starting simulation...
+info: Entering event queue @ 247061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 248044701500.  Starting simulation...
+info: Entering event queue @ 248061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 249044701500.  Starting simulation...
-info: Entering event queue @ 256044694500.  Starting simulation...
-info: Entering event queue @ 256044701500.  Starting simulation...
+info: Entering event queue @ 249061009500.  Starting simulation...
+info: Entering event queue @ 256061002500.  Starting simulation...
+info: Entering event queue @ 256061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 256044706000.  Starting simulation...
+info: Entering event queue @ 256061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 257044706000.  Starting simulation...
+info: Entering event queue @ 257061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 258044706000.  Starting simulation...
+info: Entering event queue @ 258061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 259044706000.  Starting simulation...
-info: Entering event queue @ 266044694500.  Starting simulation...
-info: Entering event queue @ 266911751000.  Starting simulation...
+info: Entering event queue @ 259061009500.  Starting simulation...
+info: Entering event queue @ 266061002500.  Starting simulation...
+info: Entering event queue @ 267151610250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 266911753000.  Starting simulation...
+info: Entering event queue @ 267151613000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 267911753000.  Starting simulation...
+info: Entering event queue @ 268151613000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 268911753000.  Starting simulation...
+info: Entering event queue @ 269151613000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 269911753000.  Starting simulation...
-info: Entering event queue @ 276044694500.  Starting simulation...
-info: Entering event queue @ 276044701500.  Starting simulation...
+info: Entering event queue @ 270151613000.  Starting simulation...
+info: Entering event queue @ 276061002500.  Starting simulation...
+info: Entering event queue @ 276061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 276044706000.  Starting simulation...
+info: Entering event queue @ 276061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 277044706000.  Starting simulation...
+info: Entering event queue @ 277061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 278044706000.  Starting simulation...
+info: Entering event queue @ 278061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 279044706000.  Starting simulation...
-info: Entering event queue @ 286044695500.  Starting simulation...
-info: Entering event queue @ 286044702500.  Starting simulation...
+info: Entering event queue @ 279061009500.  Starting simulation...
+info: Entering event queue @ 286061002500.  Starting simulation...
+info: Entering event queue @ 286061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 286044707000.  Starting simulation...
+info: Entering event queue @ 286061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 287044707000.  Starting simulation...
+info: Entering event queue @ 287061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 288044707000.  Starting simulation...
+info: Entering event queue @ 288061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 289044707000.  Starting simulation...
-info: Entering event queue @ 296044694500.  Starting simulation...
-info: Entering event queue @ 296044701000.  Starting simulation...
+info: Entering event queue @ 289061014000.  Starting simulation...
+info: Entering event queue @ 296061002500.  Starting simulation...
+info: Entering event queue @ 296061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 296044701500.  Starting simulation...
+info: Entering event queue @ 296061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 297044701500.  Starting simulation...
+info: Entering event queue @ 297061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 298044701500.  Starting simulation...
-info: Entering event queue @ 299648351000.  Starting simulation...
+info: Entering event queue @ 298061014000.  Starting simulation...
+info: Entering event queue @ 299887862250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 299648353000.  Starting simulation...
+info: Entering event queue @ 299887865000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 300648353000.  Starting simulation...
-info: Entering event queue @ 306044694500.  Starting simulation...
-info: Entering event queue @ 306044701500.  Starting simulation...
+info: Entering event queue @ 300887865000.  Starting simulation...
+info: Entering event queue @ 306061002500.  Starting simulation...
+info: Entering event queue @ 306061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 306044706000.  Starting simulation...
+info: Entering event queue @ 306061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 307044706000.  Starting simulation...
+info: Entering event queue @ 307061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 308044706000.  Starting simulation...
+info: Entering event queue @ 308061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 309044706000.  Starting simulation...
-info: Entering event queue @ 316044694500.  Starting simulation...
-info: Entering event queue @ 316044701500.  Starting simulation...
+info: Entering event queue @ 309061014000.  Starting simulation...
+info: Entering event queue @ 316061002500.  Starting simulation...
+info: Entering event queue @ 316061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 316044706000.  Starting simulation...
+info: Entering event queue @ 316061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 317044706000.  Starting simulation...
+info: Entering event queue @ 317061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 318044706000.  Starting simulation...
+info: Entering event queue @ 318061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 319044706000.  Starting simulation...
-info: Entering event queue @ 326044694500.  Starting simulation...
-info: Entering event queue @ 326044701500.  Starting simulation...
+info: Entering event queue @ 319061009500.  Starting simulation...
+info: Entering event queue @ 326061002500.  Starting simulation...
+info: Entering event queue @ 326061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 326044706000.  Starting simulation...
+info: Entering event queue @ 326061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 327044706000.  Starting simulation...
+info: Entering event queue @ 327061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 328044706000.  Starting simulation...
+info: Entering event queue @ 328061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 329044706000.  Starting simulation...
-info: Entering event queue @ 336044694500.  Starting simulation...
-info: Entering event queue @ 336044701500.  Starting simulation...
+info: Entering event queue @ 329061009500.  Starting simulation...
+info: Entering event queue @ 336061002500.  Starting simulation...
+info: Entering event queue @ 336061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 336044706000.  Starting simulation...
+info: Entering event queue @ 336061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 337044706000.  Starting simulation...
+info: Entering event queue @ 337061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 338044706000.  Starting simulation...
+info: Entering event queue @ 338061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 339044706000.  Starting simulation...
-info: Entering event queue @ 346044694500.  Starting simulation...
-info: Entering event queue @ 346044701500.  Starting simulation...
+info: Entering event queue @ 339061009500.  Starting simulation...
+info: Entering event queue @ 346061002500.  Starting simulation...
+info: Entering event queue @ 346061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 346044706000.  Starting simulation...
+info: Entering event queue @ 346061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 347044706000.  Starting simulation...
+info: Entering event queue @ 347061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 348044706000.  Starting simulation...
+info: Entering event queue @ 348061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 349044706000.  Starting simulation...
-info: Entering event queue @ 356044695500.  Starting simulation...
-info: Entering event queue @ 356044702500.  Starting simulation...
+info: Entering event queue @ 349061014000.  Starting simulation...
+info: Entering event queue @ 356061002500.  Starting simulation...
+info: Entering event queue @ 356061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 356044707000.  Starting simulation...
+info: Entering event queue @ 356061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 357044707000.  Starting simulation...
+info: Entering event queue @ 357061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 358044707000.  Starting simulation...
+info: Entering event queue @ 358061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 359044707000.  Starting simulation...
-info: Entering event queue @ 366044695500.  Starting simulation...
-info: Entering event queue @ 366044702500.  Starting simulation...
+info: Entering event queue @ 359061014000.  Starting simulation...
+info: Entering event queue @ 366061002500.  Starting simulation...
+info: Entering event queue @ 366061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 366044707000.  Starting simulation...
+info: Entering event queue @ 366061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 367044707000.  Starting simulation...
+info: Entering event queue @ 367061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 368044707000.  Starting simulation...
+info: Entering event queue @ 368061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 369044707000.  Starting simulation...
-info: Entering event queue @ 376044695500.  Starting simulation...
-info: Entering event queue @ 376044703500.  Starting simulation...
+info: Entering event queue @ 369061009500.  Starting simulation...
+info: Entering event queue @ 376061002500.  Starting simulation...
+info: Entering event queue @ 376061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 376044708000.  Starting simulation...
+info: Entering event queue @ 376061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 377044708000.  Starting simulation...
+info: Entering event queue @ 377061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 378044708000.  Starting simulation...
+info: Entering event queue @ 378061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 379044708000.  Starting simulation...
-info: Entering event queue @ 386044695500.  Starting simulation...
-info: Entering event queue @ 386044703500.  Starting simulation...
+info: Entering event queue @ 379061014000.  Starting simulation...
+info: Entering event queue @ 386061002500.  Starting simulation...
+info: Entering event queue @ 386061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 386044704000.  Starting simulation...
+info: Entering event queue @ 386061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 387044704000.  Starting simulation...
+info: Entering event queue @ 387061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 388044704000.  Starting simulation...
+info: Entering event queue @ 388061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 389044704000.  Starting simulation...
-info: Entering event queue @ 396044695500.  Starting simulation...
-info: Entering event queue @ 396044703500.  Starting simulation...
+info: Entering event queue @ 389061009500.  Starting simulation...
+info: Entering event queue @ 396061003500.  Starting simulation...
+info: Entering event queue @ 396061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 396044708000.  Starting simulation...
+info: Entering event queue @ 396061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 397044708000.  Starting simulation...
+info: Entering event queue @ 397061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 398044708000.  Starting simulation...
+info: Entering event queue @ 398061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 399044708000.  Starting simulation...
-info: Entering event queue @ 406044694500.  Starting simulation...
-info: Entering event queue @ 406044701000.  Starting simulation...
+info: Entering event queue @ 399061015500.  Starting simulation...
+info: Entering event queue @ 406061002500.  Starting simulation...
+info: Entering event queue @ 406061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 406044701500.  Starting simulation...
+info: Entering event queue @ 406061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 407044701500.  Starting simulation...
+info: Entering event queue @ 407061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 408044701500.  Starting simulation...
+info: Entering event queue @ 408061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 409044701500.  Starting simulation...
-info: Entering event queue @ 416044694500.  Starting simulation...
-info: Entering event queue @ 416044701500.  Starting simulation...
+info: Entering event queue @ 409061009500.  Starting simulation...
+info: Entering event queue @ 416061002500.  Starting simulation...
+info: Entering event queue @ 416061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 416044706000.  Starting simulation...
+info: Entering event queue @ 416061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 417044706000.  Starting simulation...
+info: Entering event queue @ 417061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 418044706000.  Starting simulation...
+info: Entering event queue @ 418061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 419044706000.  Starting simulation...
-info: Entering event queue @ 426044695500.  Starting simulation...
-info: Entering event queue @ 426044703500.  Starting simulation...
+info: Entering event queue @ 419061009500.  Starting simulation...
+info: Entering event queue @ 426061002500.  Starting simulation...
+info: Entering event queue @ 426061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 426044708000.  Starting simulation...
+info: Entering event queue @ 426061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 427044708000.  Starting simulation...
+info: Entering event queue @ 427061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 428044708000.  Starting simulation...
+info: Entering event queue @ 428061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 429044708000.  Starting simulation...
-info: Entering event queue @ 436044694500.  Starting simulation...
-info: Entering event queue @ 436044701500.  Starting simulation...
+info: Entering event queue @ 429061009500.  Starting simulation...
+info: Entering event queue @ 436061002500.  Starting simulation...
+info: Entering event queue @ 436061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 436044706000.  Starting simulation...
+info: Entering event queue @ 436061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 437044706000.  Starting simulation...
+info: Entering event queue @ 437061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 438044706000.  Starting simulation...
+info: Entering event queue @ 438061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 439044706000.  Starting simulation...
-info: Entering event queue @ 446044695500.  Starting simulation...
-info: Entering event queue @ 446044702500.  Starting simulation...
+info: Entering event queue @ 439061009500.  Starting simulation...
+info: Entering event queue @ 446061002500.  Starting simulation...
+info: Entering event queue @ 446061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 446044707000.  Starting simulation...
+info: Entering event queue @ 446061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 447044707000.  Starting simulation...
+info: Entering event queue @ 447061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 448044707000.  Starting simulation...
+info: Entering event queue @ 448061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 449044707000.  Starting simulation...
-info: Entering event queue @ 456044694500.  Starting simulation...
-info: Entering event queue @ 456044701000.  Starting simulation...
+info: Entering event queue @ 449061014000.  Starting simulation...
+info: Entering event queue @ 456061003500.  Starting simulation...
+info: Entering event queue @ 456061012000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 456044701500.  Starting simulation...
+info: Entering event queue @ 456061016500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 457044701500.  Starting simulation...
+info: Entering event queue @ 457061016500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 458044701500.  Starting simulation...
+info: Entering event queue @ 458061016500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 459044701500.  Starting simulation...
-info: Entering event queue @ 466044694500.  Starting simulation...
-info: Entering event queue @ 466044701500.  Starting simulation...
+info: Entering event queue @ 459061016500.  Starting simulation...
+info: Entering event queue @ 466061003500.  Starting simulation...
+info: Entering event queue @ 466061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 466044706000.  Starting simulation...
+info: Entering event queue @ 466061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 467044706000.  Starting simulation...
+info: Entering event queue @ 467061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 468044706000.  Starting simulation...
+info: Entering event queue @ 468061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 469044706000.  Starting simulation...
-info: Entering event queue @ 476044694500.  Starting simulation...
-info: Entering event queue @ 476044701500.  Starting simulation...
+info: Entering event queue @ 469061015500.  Starting simulation...
+info: Entering event queue @ 476061002500.  Starting simulation...
+info: Entering event queue @ 476061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 476044706000.  Starting simulation...
+info: Entering event queue @ 476061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 477044706000.  Starting simulation...
+info: Entering event queue @ 477061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 478044706000.  Starting simulation...
+info: Entering event queue @ 478061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 479044706000.  Starting simulation...
-info: Entering event queue @ 486044694500.  Starting simulation...
-info: Entering event queue @ 486044701500.  Starting simulation...
+info: Entering event queue @ 479061009500.  Starting simulation...
+info: Entering event queue @ 486061002500.  Starting simulation...
+info: Entering event queue @ 486061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 486044706000.  Starting simulation...
+info: Entering event queue @ 486061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 487044706000.  Starting simulation...
+info: Entering event queue @ 487061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 488044706000.  Starting simulation...
+info: Entering event queue @ 488061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 489044706000.  Starting simulation...
-info: Entering event queue @ 496044694500.  Starting simulation...
-info: Entering event queue @ 496065726000.  Starting simulation...
+info: Entering event queue @ 489061009500.  Starting simulation...
+info: Entering event queue @ 496061002500.  Starting simulation...
+info: Entering event queue @ 496305189250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 496065728000.  Starting simulation...
+info: Entering event queue @ 496305192000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 497065728000.  Starting simulation...
+info: Entering event queue @ 497305192000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 498065728000.  Starting simulation...
+info: Entering event queue @ 498305192000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 499065728000.  Starting simulation...
-info: Entering event queue @ 506044695500.  Starting simulation...
-info: Entering event queue @ 506044703500.  Starting simulation...
+info: Entering event queue @ 499305192000.  Starting simulation...
+info: Entering event queue @ 506061002500.  Starting simulation...
+info: Entering event queue @ 506061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 506044708000.  Starting simulation...
+info: Entering event queue @ 506061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 507044708000.  Starting simulation...
+info: Entering event queue @ 507061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 508044708000.  Starting simulation...
+info: Entering event queue @ 508061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 509044708000.  Starting simulation...
-info: Entering event queue @ 516044695500.  Starting simulation...
-info: Entering event queue @ 516044703000.  Starting simulation...
+info: Entering event queue @ 509061014000.  Starting simulation...
+info: Entering event queue @ 516061002500.  Starting simulation...
+info: Entering event queue @ 516061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 516044703500.  Starting simulation...
+info: Entering event queue @ 516061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 517044703500.  Starting simulation...
+info: Entering event queue @ 517061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 518044703500.  Starting simulation...
+info: Entering event queue @ 518061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 519044703500.  Starting simulation...
+info: Entering event queue @ 519061014000.  Starting simulation...
+info: Entering event queue @ 526061002500.  Starting simulation...
+info: Entering event queue @ 526061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 526044695500.  Starting simulation...
+info: Entering event queue @ 526061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 527044695500.  Starting simulation...
+info: Entering event queue @ 527061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 528044695500.  Starting simulation...
-info: Entering event queue @ 528802326000.  Starting simulation...
+info: Entering event queue @ 528061009500.  Starting simulation...
+info: Entering event queue @ 529041477250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 528802328000.  Starting simulation...
+info: Entering event queue @ 529041480000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 529802328000.  Starting simulation...
+info: Entering event queue @ 530041480000.  Starting simulation...
+info: Entering event queue @ 536061002500.  Starting simulation...
+info: Entering event queue @ 536061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 536044695500.  Starting simulation...
+info: Entering event queue @ 536061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 537044695500.  Starting simulation...
+info: Entering event queue @ 537061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 538044695500.  Starting simulation...
+info: Entering event queue @ 538061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 539044695500.  Starting simulation...
-info: Entering event queue @ 546044694500.  Starting simulation...
-info: Entering event queue @ 546044701500.  Starting simulation...
+info: Entering event queue @ 539061014000.  Starting simulation...
+info: Entering event queue @ 546061002500.  Starting simulation...
+info: Entering event queue @ 546061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 546044706000.  Starting simulation...
+info: Entering event queue @ 546061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 547044706000.  Starting simulation...
+info: Entering event queue @ 547061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 548044706000.  Starting simulation...
+info: Entering event queue @ 548061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 549044706000.  Starting simulation...
-info: Entering event queue @ 556044695500.  Starting simulation...
-info: Entering event queue @ 556044703500.  Starting simulation...
+info: Entering event queue @ 549061009500.  Starting simulation...
+info: Entering event queue @ 556061002500.  Starting simulation...
+info: Entering event queue @ 556061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 556044708000.  Starting simulation...
+info: Entering event queue @ 556061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 557044708000.  Starting simulation...
+info: Entering event queue @ 557061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 558044708000.  Starting simulation...
+info: Entering event queue @ 558061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 559044708000.  Starting simulation...
-info: Entering event queue @ 566044694500.  Starting simulation...
-info: Entering event queue @ 566044701000.  Starting simulation...
+info: Entering event queue @ 559061014000.  Starting simulation...
+info: Entering event queue @ 566061002500.  Starting simulation...
+info: Entering event queue @ 566061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 566044701500.  Starting simulation...
+info: Entering event queue @ 566061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 567044701500.  Starting simulation...
+info: Entering event queue @ 567061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 568044701500.  Starting simulation...
+info: Entering event queue @ 568061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 569044701500.  Starting simulation...
-info: Entering event queue @ 576044694500.  Starting simulation...
-info: Entering event queue @ 576044701500.  Starting simulation...
+info: Entering event queue @ 569061009500.  Starting simulation...
+info: Entering event queue @ 576061002500.  Starting simulation...
+info: Entering event queue @ 576061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 576044706000.  Starting simulation...
+info: Entering event queue @ 576061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 577044706000.  Starting simulation...
+info: Entering event queue @ 577061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 578044706000.  Starting simulation...
+info: Entering event queue @ 578061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 579044706000.  Starting simulation...
+info: Entering event queue @ 579061009500.  Starting simulation...
+info: Entering event queue @ 586061002500.  Starting simulation...
+info: Entering event queue @ 586061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 586044695500.  Starting simulation...
+info: Entering event queue @ 586061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 587044695500.  Starting simulation...
+info: Entering event queue @ 587061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 588044695500.  Starting simulation...
+info: Entering event queue @ 588061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 589044695500.  Starting simulation...
+info: Entering event queue @ 589061009500.  Starting simulation...
+info: Entering event queue @ 596061002500.  Starting simulation...
+info: Entering event queue @ 596061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 596044695500.  Starting simulation...
+info: Entering event queue @ 596061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 597044695500.  Starting simulation...
+info: Entering event queue @ 597061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 598044695500.  Starting simulation...
+info: Entering event queue @ 598061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 599044695500.  Starting simulation...
-info: Entering event queue @ 606044695500.  Starting simulation...
-info: Entering event queue @ 606044702500.  Starting simulation...
+info: Entering event queue @ 599061009500.  Starting simulation...
+info: Entering event queue @ 606061002500.  Starting simulation...
+info: Entering event queue @ 606061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 606044707000.  Starting simulation...
+info: Entering event queue @ 606061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 607044707000.  Starting simulation...
+info: Entering event queue @ 607061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 608044707000.  Starting simulation...
+info: Entering event queue @ 608061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 609044707000.  Starting simulation...
-info: Entering event queue @ 616044694500.  Starting simulation...
-info: Entering event queue @ 616044701500.  Starting simulation...
+info: Entering event queue @ 609061014000.  Starting simulation...
+info: Entering event queue @ 616061003500.  Starting simulation...
+info: Entering event queue @ 616061010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 616044706000.  Starting simulation...
+info: Entering event queue @ 616061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 617044706000.  Starting simulation...
+info: Entering event queue @ 617061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 618044706000.  Starting simulation...
+info: Entering event queue @ 618061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 619044706000.  Starting simulation...
-info: Entering event queue @ 626044694500.  Starting simulation...
-info: Entering event queue @ 627010955000.  Starting simulation...
+info: Entering event queue @ 619061015000.  Starting simulation...
+info: Entering event queue @ 626061003500.  Starting simulation...
+info: Entering event queue @ 627250298250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 627010957000.  Starting simulation...
+info: Entering event queue @ 627250301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 628010957000.  Starting simulation...
+info: Entering event queue @ 628250301000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 629010957000.  Starting simulation...
+info: Entering event queue @ 629250301000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 630010957000.  Starting simulation...
-info: Entering event queue @ 636044694500.  Starting simulation...
-info: Entering event queue @ 636044701500.  Starting simulation...
+info: Entering event queue @ 630250301000.  Starting simulation...
+info: Entering event queue @ 636061002500.  Starting simulation...
+info: Entering event queue @ 636061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 636044706000.  Starting simulation...
+info: Entering event queue @ 636061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 637044706000.  Starting simulation...
+info: Entering event queue @ 637061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 638044706000.  Starting simulation...
+info: Entering event queue @ 638061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 639044706000.  Starting simulation...
-info: Entering event queue @ 646044694500.  Starting simulation...
-info: Entering event queue @ 646044701500.  Starting simulation...
+info: Entering event queue @ 639061009500.  Starting simulation...
+info: Entering event queue @ 646061002500.  Starting simulation...
+info: Entering event queue @ 646061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 646044706000.  Starting simulation...
+info: Entering event queue @ 646061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 647044706000.  Starting simulation...
+info: Entering event queue @ 647061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 648044706000.  Starting simulation...
+info: Entering event queue @ 648061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 649044706000.  Starting simulation...
-info: Entering event queue @ 656044695500.  Starting simulation...
-info: Entering event queue @ 656044702500.  Starting simulation...
+info: Entering event queue @ 649061009500.  Starting simulation...
+info: Entering event queue @ 656061002500.  Starting simulation...
+info: Entering event queue @ 656061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 656044707000.  Starting simulation...
+info: Entering event queue @ 656061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 657044707000.  Starting simulation...
+info: Entering event queue @ 657061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 658044707000.  Starting simulation...
-info: Entering event queue @ 659746543000.  Starting simulation...
+info: Entering event queue @ 658061009500.  Starting simulation...
+info: Entering event queue @ 659986582250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 659746545000.  Starting simulation...
+info: Entering event queue @ 659986585000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 660746545000.  Starting simulation...
-info: Entering event queue @ 666044694500.  Starting simulation...
-info: Entering event queue @ 666044701500.  Starting simulation...
+info: Entering event queue @ 660986585000.  Starting simulation...
+info: Entering event queue @ 666061002500.  Starting simulation...
+info: Entering event queue @ 666061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 666044706000.  Starting simulation...
+info: Entering event queue @ 666061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 667044706000.  Starting simulation...
+info: Entering event queue @ 667061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 668044706000.  Starting simulation...
+info: Entering event queue @ 668061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 669044706000.  Starting simulation...
-info: Entering event queue @ 676044694500.  Starting simulation...
-info: Entering event queue @ 676044701500.  Starting simulation...
+info: Entering event queue @ 669061014000.  Starting simulation...
+info: Entering event queue @ 676061002500.  Starting simulation...
+info: Entering event queue @ 676061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 676044706000.  Starting simulation...
+info: Entering event queue @ 676061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 677044706000.  Starting simulation...
+info: Entering event queue @ 677061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 678044706000.  Starting simulation...
+info: Entering event queue @ 678061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 679044706000.  Starting simulation...
-info: Entering event queue @ 686044694500.  Starting simulation...
-info: Entering event queue @ 686044701500.  Starting simulation...
+info: Entering event queue @ 679061014000.  Starting simulation...
+info: Entering event queue @ 686061002500.  Starting simulation...
+info: Entering event queue @ 686061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 686044706000.  Starting simulation...
+info: Entering event queue @ 686061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 687044706000.  Starting simulation...
+info: Entering event queue @ 687061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 688044706000.  Starting simulation...
+info: Entering event queue @ 688061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 689044706000.  Starting simulation...
-info: Entering event queue @ 696044694500.  Starting simulation...
-info: Entering event queue @ 696044701500.  Starting simulation...
+info: Entering event queue @ 689061009500.  Starting simulation...
+info: Entering event queue @ 696061002500.  Starting simulation...
+info: Entering event queue @ 696061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 696044706000.  Starting simulation...
+info: Entering event queue @ 696061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 697044706000.  Starting simulation...
+info: Entering event queue @ 697061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 698044706000.  Starting simulation...
+info: Entering event queue @ 698061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 699044706000.  Starting simulation...
-info: Entering event queue @ 706044695500.  Starting simulation...
-info: Entering event queue @ 706044702500.  Starting simulation...
+info: Entering event queue @ 699061014000.  Starting simulation...
+info: Entering event queue @ 706061002500.  Starting simulation...
+info: Entering event queue @ 706061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 706044707000.  Starting simulation...
+info: Entering event queue @ 706061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 707044707000.  Starting simulation...
+info: Entering event queue @ 707061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 708044707000.  Starting simulation...
+info: Entering event queue @ 708061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 709044707000.  Starting simulation...
-info: Entering event queue @ 716044694500.  Starting simulation...
-info: Entering event queue @ 716044701500.  Starting simulation...
+info: Entering event queue @ 709061009500.  Starting simulation...
+info: Entering event queue @ 716061002500.  Starting simulation...
+info: Entering event queue @ 716061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 716044706000.  Starting simulation...
+info: Entering event queue @ 716061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 717044706000.  Starting simulation...
+info: Entering event queue @ 717061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 718044706000.  Starting simulation...
+info: Entering event queue @ 718061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 719044706000.  Starting simulation...
-info: Entering event queue @ 726044694500.  Starting simulation...
-info: Entering event queue @ 726044701500.  Starting simulation...
+info: Entering event queue @ 719061014000.  Starting simulation...
+info: Entering event queue @ 726061002500.  Starting simulation...
+info: Entering event queue @ 726061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 726044706000.  Starting simulation...
+info: Entering event queue @ 726061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 727044706000.  Starting simulation...
+info: Entering event queue @ 727061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 728044706000.  Starting simulation...
+info: Entering event queue @ 728061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 729044706000.  Starting simulation...
-info: Entering event queue @ 736044694500.  Starting simulation...
-info: Entering event queue @ 736044701000.  Starting simulation...
+info: Entering event queue @ 729061009500.  Starting simulation...
+info: Entering event queue @ 736061002500.  Starting simulation...
+info: Entering event queue @ 736061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 736044701500.  Starting simulation...
+info: Entering event queue @ 736061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 737044701500.  Starting simulation...
+info: Entering event queue @ 737061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 738044701500.  Starting simulation...
+info: Entering event queue @ 738061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 739044701500.  Starting simulation...
-info: Entering event queue @ 746044694500.  Starting simulation...
-info: Entering event queue @ 746044701500.  Starting simulation...
+info: Entering event queue @ 739061009500.  Starting simulation...
+info: Entering event queue @ 746061002500.  Starting simulation...
+info: Entering event queue @ 746061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 746044706000.  Starting simulation...
+info: Entering event queue @ 746061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 747044706000.  Starting simulation...
+info: Entering event queue @ 747061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 748044706000.  Starting simulation...
+info: Entering event queue @ 748061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 749044706000.  Starting simulation...
-info: Entering event queue @ 756044694500.  Starting simulation...
-info: Entering event queue @ 756044701500.  Starting simulation...
+info: Entering event queue @ 749061009500.  Starting simulation...
+info: Entering event queue @ 756061002500.  Starting simulation...
+info: Entering event queue @ 756061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 756044706000.  Starting simulation...
+info: Entering event queue @ 756061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 757044706000.  Starting simulation...
+info: Entering event queue @ 757061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 758044706000.  Starting simulation...
+info: Entering event queue @ 758061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 759044706000.  Starting simulation...
-info: Entering event queue @ 766044695500.  Starting simulation...
-info: Entering event queue @ 766044762000.  Starting simulation...
+info: Entering event queue @ 759061009500.  Starting simulation...
+info: Entering event queue @ 766061002500.  Starting simulation...
+info: Entering event queue @ 766061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 766044766500.  Starting simulation...
+info: Entering event queue @ 766061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 767044766500.  Starting simulation...
+info: Entering event queue @ 767061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 768044766500.  Starting simulation...
+info: Entering event queue @ 768061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 769044766500.  Starting simulation...
-info: Entering event queue @ 776044694500.  Starting simulation...
-info: Entering event queue @ 776044701500.  Starting simulation...
+info: Entering event queue @ 769061014000.  Starting simulation...
+info: Entering event queue @ 776061002500.  Starting simulation...
+info: Entering event queue @ 776061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 776044706000.  Starting simulation...
+info: Entering event queue @ 776061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 777044706000.  Starting simulation...
+info: Entering event queue @ 777061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 778044706000.  Starting simulation...
+info: Entering event queue @ 778061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 779044706000.  Starting simulation...
-info: Entering event queue @ 786044694500.  Starting simulation...
-info: Entering event queue @ 786044701000.  Starting simulation...
+info: Entering event queue @ 779061014000.  Starting simulation...
+info: Entering event queue @ 786061002500.  Starting simulation...
+info: Entering event queue @ 786061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 786044701500.  Starting simulation...
+info: Entering event queue @ 786061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 787044701500.  Starting simulation...
+info: Entering event queue @ 787061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 788044701500.  Starting simulation...
+info: Entering event queue @ 788061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 789044701500.  Starting simulation...
-info: Entering event queue @ 796044694500.  Starting simulation...
-info: Entering event queue @ 796044701500.  Starting simulation...
+info: Entering event queue @ 789061014000.  Starting simulation...
+info: Entering event queue @ 796061002500.  Starting simulation...
+info: Entering event queue @ 796061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 796044706000.  Starting simulation...
+info: Entering event queue @ 796061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 797044706000.  Starting simulation...
+info: Entering event queue @ 797061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 798044706000.  Starting simulation...
+info: Entering event queue @ 798061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 799044706000.  Starting simulation...
-info: Entering event queue @ 806044694500.  Starting simulation...
-info: Entering event queue @ 806044701500.  Starting simulation...
+info: Entering event queue @ 799061009500.  Starting simulation...
+info: Entering event queue @ 806061002500.  Starting simulation...
+info: Entering event queue @ 806061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 806044706000.  Starting simulation...
+info: Entering event queue @ 806061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 807044706000.  Starting simulation...
+info: Entering event queue @ 807061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 808044706000.  Starting simulation...
+info: Entering event queue @ 808061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 809044706000.  Starting simulation...
-info: Entering event queue @ 816044694500.  Starting simulation...
-info: Entering event queue @ 816044701500.  Starting simulation...
+info: Entering event queue @ 809061009500.  Starting simulation...
+info: Entering event queue @ 816061002500.  Starting simulation...
+info: Entering event queue @ 816061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 816044706000.  Starting simulation...
+info: Entering event queue @ 816061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 817044706000.  Starting simulation...
+info: Entering event queue @ 817061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 818044706000.  Starting simulation...
+info: Entering event queue @ 818061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 819044706000.  Starting simulation...
-info: Entering event queue @ 826044694500.  Starting simulation...
-info: Entering event queue @ 826044701500.  Starting simulation...
+info: Entering event queue @ 819061009500.  Starting simulation...
+info: Entering event queue @ 826061002500.  Starting simulation...
+info: Entering event queue @ 826061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 826044706000.  Starting simulation...
+info: Entering event queue @ 826061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 827044706000.  Starting simulation...
+info: Entering event queue @ 827061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 828044706000.  Starting simulation...
+info: Entering event queue @ 828061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 829044706000.  Starting simulation...
-info: Entering event queue @ 836044695500.  Starting simulation...
-info: Entering event queue @ 836044702500.  Starting simulation...
+info: Entering event queue @ 829061014000.  Starting simulation...
+info: Entering event queue @ 836061002500.  Starting simulation...
+info: Entering event queue @ 836061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 836044707000.  Starting simulation...
+info: Entering event queue @ 836061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 837044707000.  Starting simulation...
+info: Entering event queue @ 837061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 838044707000.  Starting simulation...
+info: Entering event queue @ 838061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 839044707000.  Starting simulation...
-info: Entering event queue @ 846044695500.  Starting simulation...
-info: Entering event queue @ 846044703000.  Starting simulation...
+info: Entering event queue @ 839061014000.  Starting simulation...
+info: Entering event queue @ 846061002500.  Starting simulation...
+info: Entering event queue @ 846061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 846044707500.  Starting simulation...
+info: Entering event queue @ 846061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 847044707500.  Starting simulation...
+info: Entering event queue @ 847061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 848044707500.  Starting simulation...
+info: Entering event queue @ 848061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 849044707500.  Starting simulation...
-info: Entering event queue @ 856044694500.  Starting simulation...
-info: Entering event queue @ 856163939000.  Starting simulation...
+info: Entering event queue @ 849061009500.  Starting simulation...
+info: Entering event queue @ 856061002500.  Starting simulation...
+info: Entering event queue @ 856404222250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 856163941000.  Starting simulation...
+info: Entering event queue @ 856404225000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 857163941000.  Starting simulation...
+info: Entering event queue @ 857404225000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 858163941000.  Starting simulation...
+info: Entering event queue @ 858404225000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 859163941000.  Starting simulation...
-info: Entering event queue @ 866044695500.  Starting simulation...
-info: Entering event queue @ 866044702500.  Starting simulation...
+info: Entering event queue @ 859404225000.  Starting simulation...
+info: Entering event queue @ 866061002500.  Starting simulation...
+info: Entering event queue @ 866061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 866044707000.  Starting simulation...
+info: Entering event queue @ 866061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 867044707000.  Starting simulation...
+info: Entering event queue @ 867061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 868044707000.  Starting simulation...
+info: Entering event queue @ 868061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 869044707000.  Starting simulation...
-info: Entering event queue @ 876044694500.  Starting simulation...
-info: Entering event queue @ 876044701500.  Starting simulation...
+info: Entering event queue @ 869061009500.  Starting simulation...
+info: Entering event queue @ 876061002500.  Starting simulation...
+info: Entering event queue @ 876061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 876044706000.  Starting simulation...
+info: Entering event queue @ 876061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 877044706000.  Starting simulation...
+info: Entering event queue @ 877061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 878044706000.  Starting simulation...
+info: Entering event queue @ 878061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 879044706000.  Starting simulation...
-info: Entering event queue @ 886044695500.  Starting simulation...
-info: Entering event queue @ 886044703500.  Starting simulation...
+info: Entering event queue @ 879061014000.  Starting simulation...
+info: Entering event queue @ 886061002500.  Starting simulation...
+info: Entering event queue @ 886061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 886044708000.  Starting simulation...
+info: Entering event queue @ 886061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 887044708000.  Starting simulation...
+info: Entering event queue @ 887061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 888044708000.  Starting simulation...
-info: Entering event queue @ 888900518000.  Starting simulation...
+info: Entering event queue @ 888061009500.  Starting simulation...
+info: Entering event queue @ 889140509250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 888900520000.  Starting simulation...
+info: Entering event queue @ 889140512000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 889900520000.  Starting simulation...
-info: Entering event queue @ 896044694500.  Starting simulation...
-info: Entering event queue @ 896044701000.  Starting simulation...
+info: Entering event queue @ 890140512000.  Starting simulation...
+info: Entering event queue @ 896061002500.  Starting simulation...
+info: Entering event queue @ 896061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 896044701500.  Starting simulation...
+info: Entering event queue @ 896061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 897044701500.  Starting simulation...
+info: Entering event queue @ 897061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 898044701500.  Starting simulation...
+info: Entering event queue @ 898061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 899044701500.  Starting simulation...
-info: Entering event queue @ 906044694500.  Starting simulation...
-info: Entering event queue @ 906044701500.  Starting simulation...
+info: Entering event queue @ 899061009500.  Starting simulation...
+info: Entering event queue @ 906061002500.  Starting simulation...
+info: Entering event queue @ 906061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 906044706000.  Starting simulation...
+info: Entering event queue @ 906061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 907044706000.  Starting simulation...
+info: Entering event queue @ 907061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 908044706000.  Starting simulation...
+info: Entering event queue @ 908061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 909044706000.  Starting simulation...
-info: Entering event queue @ 916044694500.  Starting simulation...
-info: Entering event queue @ 916044701500.  Starting simulation...
+info: Entering event queue @ 909061009500.  Starting simulation...
+info: Entering event queue @ 916061002500.  Starting simulation...
+info: Entering event queue @ 916061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 916044706000.  Starting simulation...
+info: Entering event queue @ 916061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 917044706000.  Starting simulation...
+info: Entering event queue @ 917061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 918044706000.  Starting simulation...
+info: Entering event queue @ 918061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 919044706000.  Starting simulation...
-info: Entering event queue @ 926044695500.  Starting simulation...
-info: Entering event queue @ 926044703500.  Starting simulation...
+info: Entering event queue @ 919061009500.  Starting simulation...
+info: Entering event queue @ 926061002500.  Starting simulation...
+info: Entering event queue @ 926061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 926044708000.  Starting simulation...
+info: Entering event queue @ 926061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 927044708000.  Starting simulation...
+info: Entering event queue @ 927061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 928044708000.  Starting simulation...
+info: Entering event queue @ 928061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 929044708000.  Starting simulation...
-info: Entering event queue @ 936044694500.  Starting simulation...
-info: Entering event queue @ 936044701500.  Starting simulation...
+info: Entering event queue @ 929061014000.  Starting simulation...
+info: Entering event queue @ 936061003500.  Starting simulation...
+info: Entering event queue @ 936061010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 936044706000.  Starting simulation...
+info: Entering event queue @ 936061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 937044706000.  Starting simulation...
+info: Entering event queue @ 937061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 938044706000.  Starting simulation...
+info: Entering event queue @ 938061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 939044706000.  Starting simulation...
-info: Entering event queue @ 946044694500.  Starting simulation...
-info: Entering event queue @ 946044701000.  Starting simulation...
+info: Entering event queue @ 939061015000.  Starting simulation...
+info: Entering event queue @ 946061003500.  Starting simulation...
+info: Entering event queue @ 946061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 946044701500.  Starting simulation...
+info: Entering event queue @ 946061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 947044701500.  Starting simulation...
+info: Entering event queue @ 947061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 948044701500.  Starting simulation...
+info: Entering event queue @ 948061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 949044701500.  Starting simulation...
-info: Entering event queue @ 956044694500.  Starting simulation...
-info: Entering event queue @ 956044701500.  Starting simulation...
+info: Entering event queue @ 949061015500.  Starting simulation...
+info: Entering event queue @ 956061002500.  Starting simulation...
+info: Entering event queue @ 956061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 956044706000.  Starting simulation...
+info: Entering event queue @ 956061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 957044706000.  Starting simulation...
+info: Entering event queue @ 957061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 958044706000.  Starting simulation...
+info: Entering event queue @ 958061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 959044706000.  Starting simulation...
-info: Entering event queue @ 966044695500.  Starting simulation...
-info: Entering event queue @ 966044703500.  Starting simulation...
+info: Entering event queue @ 959061009500.  Starting simulation...
+info: Entering event queue @ 966061002500.  Starting simulation...
+info: Entering event queue @ 966061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 966044704000.  Starting simulation...
+info: Entering event queue @ 966061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 967044704000.  Starting simulation...
+info: Entering event queue @ 967061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 968044704000.  Starting simulation...
+info: Entering event queue @ 968061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 969044704000.  Starting simulation...
-info: Entering event queue @ 976044695500.  Starting simulation...
-info: Entering event queue @ 976044703500.  Starting simulation...
+info: Entering event queue @ 969061009500.  Starting simulation...
+info: Entering event queue @ 976061002500.  Starting simulation...
+info: Entering event queue @ 976061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 976044704000.  Starting simulation...
+info: Entering event queue @ 976061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 977044704000.  Starting simulation...
+info: Entering event queue @ 977061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 978044704000.  Starting simulation...
+info: Entering event queue @ 978061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 979044704000.  Starting simulation...
-info: Entering event queue @ 986044694500.  Starting simulation...
-info: Entering event queue @ 987109151000.  Starting simulation...
+info: Entering event queue @ 979061009500.  Starting simulation...
+info: Entering event queue @ 986061003500.  Starting simulation...
+info: Entering event queue @ 987349326250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 987109153000.  Starting simulation...
+info: Entering event queue @ 987349329000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 988109153000.  Starting simulation...
+info: Entering event queue @ 988349329000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 989109153000.  Starting simulation...
+info: Entering event queue @ 989349329000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 990109153000.  Starting simulation...
-info: Entering event queue @ 996044695500.  Starting simulation...
-info: Entering event queue @ 996044702500.  Starting simulation...
+info: Entering event queue @ 990349329000.  Starting simulation...
+info: Entering event queue @ 996061002500.  Starting simulation...
+info: Entering event queue @ 996061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 996044707000.  Starting simulation...
+info: Entering event queue @ 996061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 997044707000.  Starting simulation...
+info: Entering event queue @ 997061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 998044707000.  Starting simulation...
+info: Entering event queue @ 998061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 999044707000.  Starting simulation...
+info: Entering event queue @ 999061014000.  Starting simulation...
+info: Entering event queue @ 1006061002500.  Starting simulation...
+info: Entering event queue @ 1006061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1006044695500.  Starting simulation...
+info: Entering event queue @ 1006061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1007044695500.  Starting simulation...
+info: Entering event queue @ 1007061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1008044695500.  Starting simulation...
+info: Entering event queue @ 1008061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1009044695500.  Starting simulation...
-info: Entering event queue @ 1016044694500.  Starting simulation...
-info: Entering event queue @ 1016044701500.  Starting simulation...
+info: Entering event queue @ 1009061009500.  Starting simulation...
+info: Entering event queue @ 1016061002500.  Starting simulation...
+info: Entering event queue @ 1016061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1016044706000.  Starting simulation...
+info: Entering event queue @ 1016061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1017044706000.  Starting simulation...
+info: Entering event queue @ 1017061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1018044706000.  Starting simulation...
+info: Entering event queue @ 1018061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1019044706000.  Starting simulation...
-info: Entering event queue @ 1026044695500.  Starting simulation...
-info: Entering event queue @ 1026044703500.  Starting simulation...
+info: Entering event queue @ 1019061014000.  Starting simulation...
+info: Entering event queue @ 1026061002500.  Starting simulation...
+info: Entering event queue @ 1026061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1026044708000.  Starting simulation...
+info: Entering event queue @ 1026061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1027044708000.  Starting simulation...
+info: Entering event queue @ 1027061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1028044708000.  Starting simulation...
+info: Entering event queue @ 1028061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1029044708000.  Starting simulation...
+info: Entering event queue @ 1029061009500.  Starting simulation...
+info: Entering event queue @ 1036061002500.  Starting simulation...
+info: Entering event queue @ 1036061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1036044695500.  Starting simulation...
+info: Entering event queue @ 1036061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1037044695500.  Starting simulation...
+info: Entering event queue @ 1037061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1038044695500.  Starting simulation...
+info: Entering event queue @ 1038061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1039044695500.  Starting simulation...
-info: Entering event queue @ 1046044694500.  Starting simulation...
-info: Entering event queue @ 1046044701500.  Starting simulation...
+info: Entering event queue @ 1039061014000.  Starting simulation...
+info: Entering event queue @ 1046061002500.  Starting simulation...
+info: Entering event queue @ 1046061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1046044706000.  Starting simulation...
+info: Entering event queue @ 1046061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1047044706000.  Starting simulation...
+info: Entering event queue @ 1047061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1048044706000.  Starting simulation...
+info: Entering event queue @ 1048061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1049044706000.  Starting simulation...
-info: Entering event queue @ 1056044694500.  Starting simulation...
-info: Entering event queue @ 1056044701500.  Starting simulation...
+info: Entering event queue @ 1049061009500.  Starting simulation...
+info: Entering event queue @ 1056061002500.  Starting simulation...
+info: Entering event queue @ 1056061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1056044706000.  Starting simulation...
+info: Entering event queue @ 1056061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1057044706000.  Starting simulation...
+info: Entering event queue @ 1057061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1058044706000.  Starting simulation...
+info: Entering event queue @ 1058061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1059044706000.  Starting simulation...
-info: Entering event queue @ 1066044694500.  Starting simulation...
-info: Entering event queue @ 1066044701000.  Starting simulation...
+info: Entering event queue @ 1059061009500.  Starting simulation...
+info: Entering event queue @ 1066061002500.  Starting simulation...
+info: Entering event queue @ 1066061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1066044701500.  Starting simulation...
+info: Entering event queue @ 1066061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1067044701500.  Starting simulation...
+info: Entering event queue @ 1067061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1068044701500.  Starting simulation...
+info: Entering event queue @ 1068061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1069044701500.  Starting simulation...
-info: Entering event queue @ 1076044694500.  Starting simulation...
-info: Entering event queue @ 1076044701500.  Starting simulation...
+info: Entering event queue @ 1069061009500.  Starting simulation...
+info: Entering event queue @ 1076061002500.  Starting simulation...
+info: Entering event queue @ 1076061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1076044706000.  Starting simulation...
+info: Entering event queue @ 1076061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1077044706000.  Starting simulation...
+info: Entering event queue @ 1077061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1078044706000.  Starting simulation...
+info: Entering event queue @ 1078061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1079044706000.  Starting simulation...
-info: Entering event queue @ 1086044694500.  Starting simulation...
-info: Entering event queue @ 1086044701500.  Starting simulation...
+info: Entering event queue @ 1079061009500.  Starting simulation...
+info: Entering event queue @ 1086061002500.  Starting simulation...
+info: Entering event queue @ 1086061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1086044706000.  Starting simulation...
+info: Entering event queue @ 1086061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1087044706000.  Starting simulation...
+info: Entering event queue @ 1087061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1088044706000.  Starting simulation...
+info: Entering event queue @ 1088061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1089044706000.  Starting simulation...
-info: Entering event queue @ 1096044695500.  Starting simulation...
-info: Entering event queue @ 1096044703500.  Starting simulation...
+info: Entering event queue @ 1089061014000.  Starting simulation...
+info: Entering event queue @ 1096061003500.  Starting simulation...
+info: Entering event queue @ 1096061010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1096044708000.  Starting simulation...
+info: Entering event queue @ 1096061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1097044708000.  Starting simulation...
+info: Entering event queue @ 1097061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1098044708000.  Starting simulation...
+info: Entering event queue @ 1098061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1099044708000.  Starting simulation...
-info: Entering event queue @ 1106044694500.  Starting simulation...
-info: Entering event queue @ 1106044701500.  Starting simulation...
+info: Entering event queue @ 1099061015000.  Starting simulation...
+info: Entering event queue @ 1106061003500.  Starting simulation...
+info: Entering event queue @ 1106061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1106044706000.  Starting simulation...
+info: Entering event queue @ 1106061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1107044706000.  Starting simulation...
+info: Entering event queue @ 1107061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1108044706000.  Starting simulation...
+info: Entering event queue @ 1108061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1109044706000.  Starting simulation...
-info: Entering event queue @ 1116044694500.  Starting simulation...
-info: Entering event queue @ 1116044701000.  Starting simulation...
+info: Entering event queue @ 1109061015500.  Starting simulation...
+info: Entering event queue @ 1116061002500.  Starting simulation...
+info: Entering event queue @ 1116061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1116044701500.  Starting simulation...
+info: Entering event queue @ 1116061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1117044701500.  Starting simulation...
+info: Entering event queue @ 1117061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1118044701500.  Starting simulation...
+info: Entering event queue @ 1118061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1119044701500.  Starting simulation...
-info: Entering event queue @ 1126044694500.  Starting simulation...
-info: Entering event queue @ 1126044701500.  Starting simulation...
+info: Entering event queue @ 1119061009500.  Starting simulation...
+info: Entering event queue @ 1126061002500.  Starting simulation...
+info: Entering event queue @ 1126061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1126044706000.  Starting simulation...
+info: Entering event queue @ 1126061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1127044706000.  Starting simulation...
+info: Entering event queue @ 1127061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1128044706000.  Starting simulation...
+info: Entering event queue @ 1128061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1129044706000.  Starting simulation...
-info: Entering event queue @ 1136044695500.  Starting simulation...
-info: Entering event queue @ 1136044702500.  Starting simulation...
+info: Entering event queue @ 1129061009500.  Starting simulation...
+info: Entering event queue @ 1136061002500.  Starting simulation...
+info: Entering event queue @ 1136061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1136044707000.  Starting simulation...
+info: Entering event queue @ 1136061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1137044707000.  Starting simulation...
+info: Entering event queue @ 1137061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1138044707000.  Starting simulation...
+info: Entering event queue @ 1138061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1139044707000.  Starting simulation...
-info: Entering event queue @ 1146044694500.  Starting simulation...
-info: Entering event queue @ 1146044701500.  Starting simulation...
+info: Entering event queue @ 1139061009500.  Starting simulation...
+info: Entering event queue @ 1146061002500.  Starting simulation...
+info: Entering event queue @ 1146061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1146044706000.  Starting simulation...
+info: Entering event queue @ 1146061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1147044706000.  Starting simulation...
+info: Entering event queue @ 1147061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1148044706000.  Starting simulation...
+info: Entering event queue @ 1148061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1149044706000.  Starting simulation...
-info: Entering event queue @ 1156044694500.  Starting simulation...
-info: Entering event queue @ 1156044701500.  Starting simulation...
+info: Entering event queue @ 1149061014000.  Starting simulation...
+info: Entering event queue @ 1156061002500.  Starting simulation...
+info: Entering event queue @ 1156061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1156044706000.  Starting simulation...
+info: Entering event queue @ 1156061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1157044706000.  Starting simulation...
+info: Entering event queue @ 1157061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1158044706000.  Starting simulation...
+info: Entering event queue @ 1158061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1159044706000.  Starting simulation...
-info: Entering event queue @ 1166044695500.  Starting simulation...
-info: Entering event queue @ 1166044704000.  Starting simulation...
+info: Entering event queue @ 1159061014000.  Starting simulation...
+info: Entering event queue @ 1166061002500.  Starting simulation...
+info: Entering event queue @ 1166061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1166044708500.  Starting simulation...
+info: Entering event queue @ 1166061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1167044708500.  Starting simulation...
+info: Entering event queue @ 1167061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1168044708500.  Starting simulation...
+info: Entering event queue @ 1168061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1169044708500.  Starting simulation...
+info: Entering event queue @ 1169061009500.  Starting simulation...
+info: Entering event queue @ 1176061002500.  Starting simulation...
+info: Entering event queue @ 1176061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1176044695500.  Starting simulation...
+info: Entering event queue @ 1176061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1177044695500.  Starting simulation...
+info: Entering event queue @ 1177061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1178044695500.  Starting simulation...
+info: Entering event queue @ 1178061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1179044695500.  Starting simulation...
+info: Entering event queue @ 1179061014000.  Starting simulation...
+info: Entering event queue @ 1186061002500.  Starting simulation...
+info: Entering event queue @ 1186061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1186044695500.  Starting simulation...
+info: Entering event queue @ 1186061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1187044695500.  Starting simulation...
+info: Entering event queue @ 1187061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1188044695500.  Starting simulation...
+info: Entering event queue @ 1188061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1189044695500.  Starting simulation...
+info: Entering event queue @ 1189061009500.  Starting simulation...
+info: Entering event queue @ 1196061003500.  Starting simulation...
+info: Entering event queue @ 1196061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1196044695500.  Starting simulation...
+info: Entering event queue @ 1196061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1197044695500.  Starting simulation...
+info: Entering event queue @ 1197061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1198044695500.  Starting simulation...
+info: Entering event queue @ 1198061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1199044695500.  Starting simulation...
-info: Entering event queue @ 1206044694500.  Starting simulation...
-info: Entering event queue @ 1206044701500.  Starting simulation...
+info: Entering event queue @ 1199061015500.  Starting simulation...
+info: Entering event queue @ 1206061002500.  Starting simulation...
+info: Entering event queue @ 1206061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1206044706000.  Starting simulation...
+info: Entering event queue @ 1206061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1207044706000.  Starting simulation...
+info: Entering event queue @ 1207061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1208044706000.  Starting simulation...
+info: Entering event queue @ 1208061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1209044706000.  Starting simulation...
-info: Entering event queue @ 1216044695500.  Starting simulation...
-info: Entering event queue @ 1216263126000.  Starting simulation...
+info: Entering event queue @ 1209061009500.  Starting simulation...
+info: Entering event queue @ 1216061002500.  Starting simulation...
+info: Entering event queue @ 1216502945250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1216263128000.  Starting simulation...
+info: Entering event queue @ 1216502948000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1217263128000.  Starting simulation...
+info: Entering event queue @ 1217502948000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1218263128000.  Starting simulation...
+info: Entering event queue @ 1218502948000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1219263128000.  Starting simulation...
-info: Entering event queue @ 1226044694500.  Starting simulation...
-info: Entering event queue @ 1226044701000.  Starting simulation...
+info: Entering event queue @ 1219502948000.  Starting simulation...
+info: Entering event queue @ 1226061002500.  Starting simulation...
+info: Entering event queue @ 1226061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1226044701500.  Starting simulation...
+info: Entering event queue @ 1226061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1227044701500.  Starting simulation...
+info: Entering event queue @ 1227061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1228044701500.  Starting simulation...
+info: Entering event queue @ 1228061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1229044701500.  Starting simulation...
-info: Entering event queue @ 1236044694500.  Starting simulation...
-info: Entering event queue @ 1236044701500.  Starting simulation...
+info: Entering event queue @ 1229061009500.  Starting simulation...
+info: Entering event queue @ 1236061002500.  Starting simulation...
+info: Entering event queue @ 1236061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1236044706000.  Starting simulation...
+info: Entering event queue @ 1236061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1237044706000.  Starting simulation...
+info: Entering event queue @ 1237061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1238044706000.  Starting simulation...
+info: Entering event queue @ 1238061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1239044706000.  Starting simulation...
-info: Entering event queue @ 1246044694500.  Starting simulation...
-info: Entering event queue @ 1246044701500.  Starting simulation...
+info: Entering event queue @ 1239061009500.  Starting simulation...
+info: Entering event queue @ 1246061002500.  Starting simulation...
+info: Entering event queue @ 1246061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1246044706000.  Starting simulation...
+info: Entering event queue @ 1246061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1247044706000.  Starting simulation...
+info: Entering event queue @ 1247061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1248044706000.  Starting simulation...
-info: Entering event queue @ 1248999726000.  Starting simulation...
+info: Entering event queue @ 1248061014000.  Starting simulation...
+info: Entering event queue @ 1249239189250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1248999728000.  Starting simulation...
+info: Entering event queue @ 1249239192000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1249999728000.  Starting simulation...
-info: Entering event queue @ 1256044695500.  Starting simulation...
-info: Entering event queue @ 1256044703500.  Starting simulation...
+info: Entering event queue @ 1250239192000.  Starting simulation...
+info: Entering event queue @ 1256061003500.  Starting simulation...
+info: Entering event queue @ 1256061010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1256044708000.  Starting simulation...
+info: Entering event queue @ 1256061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1257044708000.  Starting simulation...
+info: Entering event queue @ 1257061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1258044708000.  Starting simulation...
+info: Entering event queue @ 1258061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1259044708000.  Starting simulation...
-info: Entering event queue @ 1266044694500.  Starting simulation...
-info: Entering event queue @ 1266044701500.  Starting simulation...
+info: Entering event queue @ 1259061015000.  Starting simulation...
+info: Entering event queue @ 1266061003500.  Starting simulation...
+info: Entering event queue @ 1266061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1266044706000.  Starting simulation...
+info: Entering event queue @ 1266061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1267044706000.  Starting simulation...
+info: Entering event queue @ 1267061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1268044706000.  Starting simulation...
+info: Entering event queue @ 1268061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1269044706000.  Starting simulation...
-info: Entering event queue @ 1276044694500.  Starting simulation...
-info: Entering event queue @ 1276044701000.  Starting simulation...
+info: Entering event queue @ 1269061015500.  Starting simulation...
+info: Entering event queue @ 1276061002500.  Starting simulation...
+info: Entering event queue @ 1276061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1276044701500.  Starting simulation...
+info: Entering event queue @ 1276061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1277044701500.  Starting simulation...
+info: Entering event queue @ 1277061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1278044701500.  Starting simulation...
+info: Entering event queue @ 1278061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1279044701500.  Starting simulation...
-info: Entering event queue @ 1286044694500.  Starting simulation...
-info: Entering event queue @ 1286044701500.  Starting simulation...
+info: Entering event queue @ 1279061009500.  Starting simulation...
+info: Entering event queue @ 1286061002500.  Starting simulation...
+info: Entering event queue @ 1286061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1286044706000.  Starting simulation...
+info: Entering event queue @ 1286061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1287044706000.  Starting simulation...
+info: Entering event queue @ 1287061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1288044706000.  Starting simulation...
+info: Entering event queue @ 1288061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1289044706000.  Starting simulation...
-info: Entering event queue @ 1296044695500.  Starting simulation...
-info: Entering event queue @ 1296044702500.  Starting simulation...
+info: Entering event queue @ 1289061009500.  Starting simulation...
+info: Entering event queue @ 1296061002500.  Starting simulation...
+info: Entering event queue @ 1296061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1296044707000.  Starting simulation...
+info: Entering event queue @ 1296061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1297044707000.  Starting simulation...
+info: Entering event queue @ 1297061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1298044707000.  Starting simulation...
+info: Entering event queue @ 1298061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1299044707000.  Starting simulation...
-info: Entering event queue @ 1306044694500.  Starting simulation...
-info: Entering event queue @ 1306044701500.  Starting simulation...
+info: Entering event queue @ 1299061009500.  Starting simulation...
+info: Entering event queue @ 1306061002500.  Starting simulation...
+info: Entering event queue @ 1306061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1306044706000.  Starting simulation...
+info: Entering event queue @ 1306061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1307044706000.  Starting simulation...
+info: Entering event queue @ 1307061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1308044706000.  Starting simulation...
+info: Entering event queue @ 1308061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1309044706000.  Starting simulation...
-info: Entering event queue @ 1316044694500.  Starting simulation...
-info: Entering event queue @ 1316044701500.  Starting simulation...
+info: Entering event queue @ 1309061014000.  Starting simulation...
+info: Entering event queue @ 1316061002500.  Starting simulation...
+info: Entering event queue @ 1316061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1316044706000.  Starting simulation...
+info: Entering event queue @ 1316061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1317044706000.  Starting simulation...
+info: Entering event queue @ 1317061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1318044706000.  Starting simulation...
+info: Entering event queue @ 1318061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1319044706000.  Starting simulation...
-info: Entering event queue @ 1326044695500.  Starting simulation...
-info: Entering event queue @ 1326044702500.  Starting simulation...
+info: Entering event queue @ 1319061014000.  Starting simulation...
+info: Entering event queue @ 1326061002500.  Starting simulation...
+info: Entering event queue @ 1326061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1326044707000.  Starting simulation...
+info: Entering event queue @ 1326061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1327044707000.  Starting simulation...
+info: Entering event queue @ 1327061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1328044707000.  Starting simulation...
+info: Entering event queue @ 1328061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1329044707000.  Starting simulation...
-info: Entering event queue @ 1336044695500.  Starting simulation...
-info: Entering event queue @ 1336044702500.  Starting simulation...
+info: Entering event queue @ 1329061009500.  Starting simulation...
+info: Entering event queue @ 1336061002500.  Starting simulation...
+info: Entering event queue @ 1336061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1336044707000.  Starting simulation...
+info: Entering event queue @ 1336061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1337044707000.  Starting simulation...
+info: Entering event queue @ 1337061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1338044707000.  Starting simulation...
+info: Entering event queue @ 1338061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1339044707000.  Starting simulation...
-info: Entering event queue @ 1346044695500.  Starting simulation...
-info: Entering event queue @ 1347208355000.  Starting simulation...
+info: Entering event queue @ 1339061014000.  Starting simulation...
+info: Entering event queue @ 1346061002500.  Starting simulation...
+info: Entering event queue @ 1347448013250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1347208357000.  Starting simulation...
+info: Entering event queue @ 1347448016000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1348208357000.  Starting simulation...
+info: Entering event queue @ 1348448016000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1349208357000.  Starting simulation...
+info: Entering event queue @ 1349448016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1350208357000.  Starting simulation...
+info: Entering event queue @ 1350448016000.  Starting simulation...
+info: Entering event queue @ 1356061002500.  Starting simulation...
+info: Entering event queue @ 1356061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1356044695500.  Starting simulation...
+info: Entering event queue @ 1356061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1357044695500.  Starting simulation...
+info: Entering event queue @ 1357061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1358044695500.  Starting simulation...
+info: Entering event queue @ 1358061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1359044695500.  Starting simulation...
-info: Entering event queue @ 1366044694500.  Starting simulation...
-info: Entering event queue @ 1366044701500.  Starting simulation...
+info: Entering event queue @ 1359061014000.  Starting simulation...
+info: Entering event queue @ 1366061002500.  Starting simulation...
+info: Entering event queue @ 1366061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1366044706000.  Starting simulation...
+info: Entering event queue @ 1366061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1367044706000.  Starting simulation...
+info: Entering event queue @ 1367061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1368044706000.  Starting simulation...
+info: Entering event queue @ 1368061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1369044706000.  Starting simulation...
-info: Entering event queue @ 1376044695500.  Starting simulation...
-info: Entering event queue @ 1376044703500.  Starting simulation...
+info: Entering event queue @ 1369061009500.  Starting simulation...
+info: Entering event queue @ 1376061002500.  Starting simulation...
+info: Entering event queue @ 1376061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1376044708000.  Starting simulation...
+info: Entering event queue @ 1376061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1377044708000.  Starting simulation...
+info: Entering event queue @ 1377061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1378044708000.  Starting simulation...
+info: Entering event queue @ 1378061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1379044708000.  Starting simulation...
-info: Entering event queue @ 1386044694500.  Starting simulation...
-info: Entering event queue @ 1386044701000.  Starting simulation...
+info: Entering event queue @ 1379061009500.  Starting simulation...
+info: Entering event queue @ 1386061002500.  Starting simulation...
+info: Entering event queue @ 1386061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1386044701500.  Starting simulation...
+info: Entering event queue @ 1386061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1387044701500.  Starting simulation...
+info: Entering event queue @ 1387061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1388044701500.  Starting simulation...
+info: Entering event queue @ 1388061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1389044701500.  Starting simulation...
-info: Entering event queue @ 1396044694500.  Starting simulation...
-info: Entering event queue @ 1396044701500.  Starting simulation...
+info: Entering event queue @ 1389061009500.  Starting simulation...
+info: Entering event queue @ 1396061002500.  Starting simulation...
+info: Entering event queue @ 1396061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1396044706000.  Starting simulation...
+info: Entering event queue @ 1396061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1397044706000.  Starting simulation...
+info: Entering event queue @ 1397061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1398044706000.  Starting simulation...
+info: Entering event queue @ 1398061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1399044706000.  Starting simulation...
+info: Entering event queue @ 1399061009500.  Starting simulation...
+info: Entering event queue @ 1406061002500.  Starting simulation...
+info: Entering event queue @ 1406061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1406044695500.  Starting simulation...
+info: Entering event queue @ 1406061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1407044695500.  Starting simulation...
+info: Entering event queue @ 1407061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1408044695500.  Starting simulation...
+info: Entering event queue @ 1408061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1409044695500.  Starting simulation...
-info: Entering event queue @ 1416044694500.  Starting simulation...
-info: Entering event queue @ 1416044701500.  Starting simulation...
+info: Entering event queue @ 1409061014000.  Starting simulation...
+info: Entering event queue @ 1416061003500.  Starting simulation...
+info: Entering event queue @ 1416061010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1416044706000.  Starting simulation...
+info: Entering event queue @ 1416061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1417044706000.  Starting simulation...
+info: Entering event queue @ 1417061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1418044706000.  Starting simulation...
+info: Entering event queue @ 1418061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1419044706000.  Starting simulation...
-info: Entering event queue @ 1426044694500.  Starting simulation...
-info: Entering event queue @ 1426044701500.  Starting simulation...
+info: Entering event queue @ 1419061015000.  Starting simulation...
+info: Entering event queue @ 1426061003500.  Starting simulation...
+info: Entering event queue @ 1426061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1426044706000.  Starting simulation...
+info: Entering event queue @ 1426061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1427044706000.  Starting simulation...
+info: Entering event queue @ 1427061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1428044706000.  Starting simulation...
+info: Entering event queue @ 1428061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1429044706000.  Starting simulation...
-info: Entering event queue @ 1436044694500.  Starting simulation...
-info: Entering event queue @ 1436044701000.  Starting simulation...
+info: Entering event queue @ 1429061015500.  Starting simulation...
+info: Entering event queue @ 1436061002500.  Starting simulation...
+info: Entering event queue @ 1436061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1436044701500.  Starting simulation...
+info: Entering event queue @ 1436061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1437044701500.  Starting simulation...
+info: Entering event queue @ 1437061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1438044701500.  Starting simulation...
+info: Entering event queue @ 1438061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1439044701500.  Starting simulation...
-info: Entering event queue @ 1446044694500.  Starting simulation...
-info: Entering event queue @ 1446044701500.  Starting simulation...
+info: Entering event queue @ 1439061009500.  Starting simulation...
+info: Entering event queue @ 1446061002500.  Starting simulation...
+info: Entering event queue @ 1446061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1446044706000.  Starting simulation...
+info: Entering event queue @ 1446061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1447044706000.  Starting simulation...
+info: Entering event queue @ 1447061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1448044706000.  Starting simulation...
+info: Entering event queue @ 1448061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1449044706000.  Starting simulation...
-info: Entering event queue @ 1456044695500.  Starting simulation...
-info: Entering event queue @ 1456044702500.  Starting simulation...
+info: Entering event queue @ 1449061009500.  Starting simulation...
+info: Entering event queue @ 1456061002500.  Starting simulation...
+info: Entering event queue @ 1456061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1456044707000.  Starting simulation...
+info: Entering event queue @ 1456061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1457044707000.  Starting simulation...
+info: Entering event queue @ 1457061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1458044707000.  Starting simulation...
+info: Entering event queue @ 1458061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1459044707000.  Starting simulation...
-info: Entering event queue @ 1466044694500.  Starting simulation...
-info: Entering event queue @ 1466044701500.  Starting simulation...
+info: Entering event queue @ 1459061009500.  Starting simulation...
+info: Entering event queue @ 1466061002500.  Starting simulation...
+info: Entering event queue @ 1466061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1466044706000.  Starting simulation...
+info: Entering event queue @ 1466061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1467044706000.  Starting simulation...
+info: Entering event queue @ 1467061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1468044706000.  Starting simulation...
+info: Entering event queue @ 1468061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1469044706000.  Starting simulation...
-info: Entering event queue @ 1476044694500.  Starting simulation...
-info: Entering event queue @ 1476044701500.  Starting simulation...
+info: Entering event queue @ 1469061014000.  Starting simulation...
+info: Entering event queue @ 1476061002500.  Starting simulation...
+info: Entering event queue @ 1476061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1476044706000.  Starting simulation...
+info: Entering event queue @ 1476061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1477044706000.  Starting simulation...
+info: Entering event queue @ 1477061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1478044706000.  Starting simulation...
+info: Entering event queue @ 1478061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1479044706000.  Starting simulation...
-info: Entering event queue @ 1486044695500.  Starting simulation...
-info: Entering event queue @ 1486044702500.  Starting simulation...
+info: Entering event queue @ 1479061014000.  Starting simulation...
+info: Entering event queue @ 1486061002500.  Starting simulation...
+info: Entering event queue @ 1486061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1486044707000.  Starting simulation...
+info: Entering event queue @ 1486061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1487044707000.  Starting simulation...
+info: Entering event queue @ 1487061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1488044707000.  Starting simulation...
+info: Entering event queue @ 1488061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1489044707000.  Starting simulation...
-info: Entering event queue @ 1496044695500.  Starting simulation...
-info: Entering event queue @ 1496044702500.  Starting simulation...
+info: Entering event queue @ 1489061009500.  Starting simulation...
+info: Entering event queue @ 1496061002500.  Starting simulation...
+info: Entering event queue @ 1496061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1496044707000.  Starting simulation...
+info: Entering event queue @ 1496061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1497044707000.  Starting simulation...
+info: Entering event queue @ 1497061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1498044707000.  Starting simulation...
+info: Entering event queue @ 1498061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1499044707000.  Starting simulation...
+info: Entering event queue @ 1499061014000.  Starting simulation...
+info: Entering event queue @ 1506061002500.  Starting simulation...
+info: Entering event queue @ 1506061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1506044695500.  Starting simulation...
+info: Entering event queue @ 1506061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1507044695500.  Starting simulation...
+info: Entering event queue @ 1507061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1508044695500.  Starting simulation...
+info: Entering event queue @ 1508061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1509044695500.  Starting simulation...
+info: Entering event queue @ 1509061009500.  Starting simulation...
+info: Entering event queue @ 1516061002500.  Starting simulation...
+info: Entering event queue @ 1516061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1516044695500.  Starting simulation...
+info: Entering event queue @ 1516061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1517044695500.  Starting simulation...
+info: Entering event queue @ 1517061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1518044695500.  Starting simulation...
+info: Entering event queue @ 1518061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1519044695500.  Starting simulation...
-info: Entering event queue @ 1526044694500.  Starting simulation...
-info: Entering event queue @ 1526044701500.  Starting simulation...
+info: Entering event queue @ 1519061014000.  Starting simulation...
+info: Entering event queue @ 1526061002500.  Starting simulation...
+info: Entering event queue @ 1526061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1526044706000.  Starting simulation...
+info: Entering event queue @ 1526061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1527044706000.  Starting simulation...
+info: Entering event queue @ 1527061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1528044706000.  Starting simulation...
+info: Entering event queue @ 1528061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1529044706000.  Starting simulation...
-info: Entering event queue @ 1536044695500.  Starting simulation...
-info: Entering event queue @ 1536044703500.  Starting simulation...
+info: Entering event queue @ 1529061009500.  Starting simulation...
+info: Entering event queue @ 1536061002500.  Starting simulation...
+info: Entering event queue @ 1536061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1536044708000.  Starting simulation...
+info: Entering event queue @ 1536061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1537044708000.  Starting simulation...
+info: Entering event queue @ 1537061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1538044708000.  Starting simulation...
+info: Entering event queue @ 1538061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1539044708000.  Starting simulation...
-info: Entering event queue @ 1546044694500.  Starting simulation...
-info: Entering event queue @ 1546044701000.  Starting simulation...
+info: Entering event queue @ 1539061009500.  Starting simulation...
+info: Entering event queue @ 1546061002500.  Starting simulation...
+info: Entering event queue @ 1546061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1546044701500.  Starting simulation...
+info: Entering event queue @ 1546061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1547044701500.  Starting simulation...
+info: Entering event queue @ 1547061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1548044701500.  Starting simulation...
+info: Entering event queue @ 1548061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1549044701500.  Starting simulation...
-info: Entering event queue @ 1556044694500.  Starting simulation...
-info: Entering event queue @ 1556044701500.  Starting simulation...
+info: Entering event queue @ 1549061009500.  Starting simulation...
+info: Entering event queue @ 1556061002500.  Starting simulation...
+info: Entering event queue @ 1556061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1556044706000.  Starting simulation...
+info: Entering event queue @ 1556061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1557044706000.  Starting simulation...
+info: Entering event queue @ 1557061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1558044706000.  Starting simulation...
+info: Entering event queue @ 1558061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1559044706000.  Starting simulation...
-info: Entering event queue @ 1566044695500.  Starting simulation...
-info: Entering event queue @ 1566044703500.  Starting simulation...
+info: Entering event queue @ 1559061009500.  Starting simulation...
+info: Entering event queue @ 1566061002500.  Starting simulation...
+info: Entering event queue @ 1566061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1566044708000.  Starting simulation...
+info: Entering event queue @ 1566061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1567044708000.  Starting simulation...
+info: Entering event queue @ 1567061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1568044708000.  Starting simulation...
+info: Entering event queue @ 1568061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1569044708000.  Starting simulation...
-info: Entering event queue @ 1576044695500.  Starting simulation...
-info: Entering event queue @ 1576362334000.  Starting simulation...
+info: Entering event queue @ 1569061014000.  Starting simulation...
+info: Entering event queue @ 1576061003500.  Starting simulation...
+info: Entering event queue @ 1576601934250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1576362336000.  Starting simulation...
+info: Entering event queue @ 1576601937000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1577362336000.  Starting simulation...
+info: Entering event queue @ 1577601937000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1578362336000.  Starting simulation...
+info: Entering event queue @ 1578601937000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1579362336000.  Starting simulation...
-info: Entering event queue @ 1586044695500.  Starting simulation...
-info: Entering event queue @ 1586044703500.  Starting simulation...
+info: Entering event queue @ 1579601937000.  Starting simulation...
+info: Entering event queue @ 1586061003500.  Starting simulation...
+info: Entering event queue @ 1586061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1586044708000.  Starting simulation...
+info: Entering event queue @ 1586061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1587044708000.  Starting simulation...
+info: Entering event queue @ 1587061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1588044708000.  Starting simulation...
+info: Entering event queue @ 1588061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1589044708000.  Starting simulation...
-info: Entering event queue @ 1596044694500.  Starting simulation...
-info: Entering event queue @ 1596044701000.  Starting simulation...
+info: Entering event queue @ 1589061015500.  Starting simulation...
+info: Entering event queue @ 1596061002500.  Starting simulation...
+info: Entering event queue @ 1596061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1596044701500.  Starting simulation...
+info: Entering event queue @ 1596061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1597044701500.  Starting simulation...
+info: Entering event queue @ 1597061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1598044701500.  Starting simulation...
+info: Entering event queue @ 1598061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1599044701500.  Starting simulation...
-info: Entering event queue @ 1606044695500.  Starting simulation...
-info: Entering event queue @ 1606044703000.  Starting simulation...
+info: Entering event queue @ 1599061009500.  Starting simulation...
+info: Entering event queue @ 1606061002500.  Starting simulation...
+info: Entering event queue @ 1606061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1606044703500.  Starting simulation...
+info: Entering event queue @ 1606061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1607044703500.  Starting simulation...
+info: Entering event queue @ 1607061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1608044703500.  Starting simulation...
-info: Entering event queue @ 1609097918000.  Starting simulation...
+info: Entering event queue @ 1608061009500.  Starting simulation...
+info: Entering event queue @ 1609338221250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1609097920000.  Starting simulation...
+info: Entering event queue @ 1609338224000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1610097920000.  Starting simulation...
-info: Entering event queue @ 1616044694500.  Starting simulation...
-info: Entering event queue @ 1616044701500.  Starting simulation...
+info: Entering event queue @ 1610338224000.  Starting simulation...
+info: Entering event queue @ 1616061002500.  Starting simulation...
+info: Entering event queue @ 1616061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1616044706000.  Starting simulation...
+info: Entering event queue @ 1616061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1617044706000.  Starting simulation...
+info: Entering event queue @ 1617061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1618044706000.  Starting simulation...
+info: Entering event queue @ 1618061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1619044706000.  Starting simulation...
-info: Entering event queue @ 1626044694500.  Starting simulation...
-info: Entering event queue @ 1626044701500.  Starting simulation...
+info: Entering event queue @ 1619061009500.  Starting simulation...
+info: Entering event queue @ 1626061002500.  Starting simulation...
+info: Entering event queue @ 1626061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1626044706000.  Starting simulation...
+info: Entering event queue @ 1626061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1627044706000.  Starting simulation...
+info: Entering event queue @ 1627061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1628044706000.  Starting simulation...
+info: Entering event queue @ 1628061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1629044706000.  Starting simulation...
-info: Entering event queue @ 1636044694500.  Starting simulation...
-info: Entering event queue @ 1636044701500.  Starting simulation...
+info: Entering event queue @ 1629061014000.  Starting simulation...
+info: Entering event queue @ 1636061002500.  Starting simulation...
+info: Entering event queue @ 1636061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1636044706000.  Starting simulation...
+info: Entering event queue @ 1636061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1637044706000.  Starting simulation...
+info: Entering event queue @ 1637061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1638044706000.  Starting simulation...
+info: Entering event queue @ 1638061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1639044706000.  Starting simulation...
-info: Entering event queue @ 1646044695500.  Starting simulation...
-info: Entering event queue @ 1646044702500.  Starting simulation...
+info: Entering event queue @ 1639061014000.  Starting simulation...
+info: Entering event queue @ 1646061002500.  Starting simulation...
+info: Entering event queue @ 1646061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1646044707000.  Starting simulation...
+info: Entering event queue @ 1646061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1647044707000.  Starting simulation...
+info: Entering event queue @ 1647061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1648044707000.  Starting simulation...
+info: Entering event queue @ 1648061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1649044707000.  Starting simulation...
-info: Entering event queue @ 1656044695500.  Starting simulation...
-info: Entering event queue @ 1656044702500.  Starting simulation...
+info: Entering event queue @ 1649061009500.  Starting simulation...
+info: Entering event queue @ 1656061002500.  Starting simulation...
+info: Entering event queue @ 1656061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1656044707000.  Starting simulation...
+info: Entering event queue @ 1656061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1657044707000.  Starting simulation...
+info: Entering event queue @ 1657061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1658044707000.  Starting simulation...
+info: Entering event queue @ 1658061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1659044707000.  Starting simulation...
+info: Entering event queue @ 1659061014000.  Starting simulation...
+info: Entering event queue @ 1666061002500.  Starting simulation...
+info: Entering event queue @ 1666061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1666044695500.  Starting simulation...
+info: Entering event queue @ 1666061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1667044695500.  Starting simulation...
+info: Entering event queue @ 1667061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1668044695500.  Starting simulation...
+info: Entering event queue @ 1668061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1669044695500.  Starting simulation...
+info: Entering event queue @ 1669061009500.  Starting simulation...
+info: Entering event queue @ 1676061002500.  Starting simulation...
+info: Entering event queue @ 1676061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1676044695500.  Starting simulation...
+info: Entering event queue @ 1676061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1677044695500.  Starting simulation...
+info: Entering event queue @ 1677061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1678044695500.  Starting simulation...
+info: Entering event queue @ 1678061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1679044695500.  Starting simulation...
-info: Entering event queue @ 1686044694500.  Starting simulation...
-info: Entering event queue @ 1686044701500.  Starting simulation...
+info: Entering event queue @ 1679061014000.  Starting simulation...
+info: Entering event queue @ 1686061002500.  Starting simulation...
+info: Entering event queue @ 1686061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1686044706000.  Starting simulation...
+info: Entering event queue @ 1686061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1687044706000.  Starting simulation...
+info: Entering event queue @ 1687061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1688044706000.  Starting simulation...
+info: Entering event queue @ 1688061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1689044706000.  Starting simulation...
-info: Entering event queue @ 1696044695500.  Starting simulation...
-info: Entering event queue @ 1696044703500.  Starting simulation...
+info: Entering event queue @ 1689061009500.  Starting simulation...
+info: Entering event queue @ 1696061002500.  Starting simulation...
+info: Entering event queue @ 1696061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1696044708000.  Starting simulation...
+info: Entering event queue @ 1696061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1697044708000.  Starting simulation...
+info: Entering event queue @ 1697061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1698044708000.  Starting simulation...
+info: Entering event queue @ 1698061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1699044708000.  Starting simulation...
-info: Entering event queue @ 1706044694500.  Starting simulation...
-info: Entering event queue @ 1707307739000.  Starting simulation...
+info: Entering event queue @ 1699061009500.  Starting simulation...
+info: Entering event queue @ 1706061002500.  Starting simulation...
+info: Entering event queue @ 1707547042250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1707307741000.  Starting simulation...
+info: Entering event queue @ 1707547045000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1708307741000.  Starting simulation...
+info: Entering event queue @ 1708547045000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1709307741000.  Starting simulation...
+info: Entering event queue @ 1709547045000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1710307741000.  Starting simulation...
-info: Entering event queue @ 1716044694500.  Starting simulation...
-info: Entering event queue @ 1716044701500.  Starting simulation...
+info: Entering event queue @ 1710547045000.  Starting simulation...
+info: Entering event queue @ 1716061002500.  Starting simulation...
+info: Entering event queue @ 1716061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1716044706000.  Starting simulation...
+info: Entering event queue @ 1716061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1717044706000.  Starting simulation...
+info: Entering event queue @ 1717061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1718044706000.  Starting simulation...
+info: Entering event queue @ 1718061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1719044706000.  Starting simulation...
-info: Entering event queue @ 1726044694500.  Starting simulation...
-info: Entering event queue @ 1726044701500.  Starting simulation...
+info: Entering event queue @ 1719061009500.  Starting simulation...
+info: Entering event queue @ 1726061002500.  Starting simulation...
+info: Entering event queue @ 1726061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1726044706000.  Starting simulation...
+info: Entering event queue @ 1726061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1727044706000.  Starting simulation...
+info: Entering event queue @ 1727061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1728044706000.  Starting simulation...
+info: Entering event queue @ 1728061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1729044706000.  Starting simulation...
-info: Entering event queue @ 1736044695500.  Starting simulation...
-info: Entering event queue @ 1736044703500.  Starting simulation...
+info: Entering event queue @ 1729061014000.  Starting simulation...
+info: Entering event queue @ 1736061003500.  Starting simulation...
+info: Entering event queue @ 1736061010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1736044708000.  Starting simulation...
+info: Entering event queue @ 1736061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1737044708000.  Starting simulation...
+info: Entering event queue @ 1737061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1738044708000.  Starting simulation...
+info: Entering event queue @ 1738061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1739044708000.  Starting simulation...
-info: Entering event queue @ 1746044695500.  Starting simulation...
-info: Entering event queue @ 1746044702500.  Starting simulation...
+info: Entering event queue @ 1739061015000.  Starting simulation...
+info: Entering event queue @ 1746061003500.  Starting simulation...
+info: Entering event queue @ 1746061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1746044707000.  Starting simulation...
+info: Entering event queue @ 1746061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1747044707000.  Starting simulation...
+info: Entering event queue @ 1747061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1748044707000.  Starting simulation...
+info: Entering event queue @ 1748061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1749044707000.  Starting simulation...
-info: Entering event queue @ 1756044694500.  Starting simulation...
-info: Entering event queue @ 1756044701000.  Starting simulation...
+info: Entering event queue @ 1749061015500.  Starting simulation...
+info: Entering event queue @ 1756061002500.  Starting simulation...
+info: Entering event queue @ 1756061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1756044701500.  Starting simulation...
+info: Entering event queue @ 1756061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1757044701500.  Starting simulation...
+info: Entering event queue @ 1757061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1758044701500.  Starting simulation...
+info: Entering event queue @ 1758061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1759044701500.  Starting simulation...
-info: Entering event queue @ 1766044694500.  Starting simulation...
-info: Entering event queue @ 1766044701500.  Starting simulation...
+info: Entering event queue @ 1759061009500.  Starting simulation...
+info: Entering event queue @ 1766061002500.  Starting simulation...
+info: Entering event queue @ 1766061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1766044706000.  Starting simulation...
+info: Entering event queue @ 1766061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1767044706000.  Starting simulation...
+info: Entering event queue @ 1767061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1768044706000.  Starting simulation...
+info: Entering event queue @ 1768061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1769044706000.  Starting simulation...
-info: Entering event queue @ 1776044695500.  Starting simulation...
-info: Entering event queue @ 1776044703000.  Starting simulation...
+info: Entering event queue @ 1769061009500.  Starting simulation...
+info: Entering event queue @ 1776061002500.  Starting simulation...
+info: Entering event queue @ 1776061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1776044703500.  Starting simulation...
+info: Entering event queue @ 1776061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1777044703500.  Starting simulation...
+info: Entering event queue @ 1777061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1778044703500.  Starting simulation...
+info: Entering event queue @ 1778061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1779044703500.  Starting simulation...
-info: Entering event queue @ 1786044694500.  Starting simulation...
-info: Entering event queue @ 1786044701500.  Starting simulation...
+info: Entering event queue @ 1779061009500.  Starting simulation...
+info: Entering event queue @ 1786061003500.  Starting simulation...
+info: Entering event queue @ 1786061011500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1786044706000.  Starting simulation...
+info: Entering event queue @ 1786061016000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1787044706000.  Starting simulation...
+info: Entering event queue @ 1787061016000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1788044706000.  Starting simulation...
+info: Entering event queue @ 1788061016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1789044706000.  Starting simulation...
-info: Entering event queue @ 1796044694500.  Starting simulation...
-info: Entering event queue @ 1796044701500.  Starting simulation...
+info: Entering event queue @ 1789061016000.  Starting simulation...
+info: Entering event queue @ 1796061002500.  Starting simulation...
+info: Entering event queue @ 1796061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1796044706000.  Starting simulation...
+info: Entering event queue @ 1796061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1797044706000.  Starting simulation...
+info: Entering event queue @ 1797061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1798044706000.  Starting simulation...
+info: Entering event queue @ 1798061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1799044706000.  Starting simulation...
-info: Entering event queue @ 1806044695500.  Starting simulation...
-info: Entering event queue @ 1806044704000.  Starting simulation...
+info: Entering event queue @ 1799061014000.  Starting simulation...
+info: Entering event queue @ 1806061002500.  Starting simulation...
+info: Entering event queue @ 1806061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1806044704500.  Starting simulation...
+info: Entering event queue @ 1806061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1807044704500.  Starting simulation...
+info: Entering event queue @ 1807061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1808044704500.  Starting simulation...
+info: Entering event queue @ 1808061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1809044704500.  Starting simulation...
-info: Entering event queue @ 1816044694500.  Starting simulation...
-info: Entering event queue @ 1816044701500.  Starting simulation...
+info: Entering event queue @ 1809061009500.  Starting simulation...
+info: Entering event queue @ 1816061002500.  Starting simulation...
+info: Entering event queue @ 1816061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1816044706000.  Starting simulation...
+info: Entering event queue @ 1816061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1817044706000.  Starting simulation...
+info: Entering event queue @ 1817061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1818044706000.  Starting simulation...
+info: Entering event queue @ 1818061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1819044706000.  Starting simulation...
+info: Entering event queue @ 1819061014000.  Starting simulation...
+info: Entering event queue @ 1826061002500.  Starting simulation...
+info: Entering event queue @ 1826061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1826044695500.  Starting simulation...
+info: Entering event queue @ 1826061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1827044695500.  Starting simulation...
+info: Entering event queue @ 1827061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1828044695500.  Starting simulation...
+info: Entering event queue @ 1828061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1829044695500.  Starting simulation...
+info: Entering event queue @ 1829061009500.  Starting simulation...
+info: Entering event queue @ 1836061002500.  Starting simulation...
+info: Entering event queue @ 1836061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1836044695500.  Starting simulation...
+info: Entering event queue @ 1836061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1837044695500.  Starting simulation...
+info: Entering event queue @ 1837061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
+info: Entering event queue @ 1838061014000.  Starting simulation...
+info: Entering event queue @ 1838124570250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1838044695500.  Starting simulation...
+info: Entering event queue @ 1838124573000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1839044695500.  Starting simulation...
-info: Entering event queue @ 1846044694500.  Starting simulation...
-info: Entering event queue @ 1846044701500.  Starting simulation...
+info: Entering event queue @ 1839124573000.  Starting simulation...
+info: Entering event queue @ 1846061002500.  Starting simulation...
+info: Entering event queue @ 1846061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1846044706000.  Starting simulation...
+info: Entering event queue @ 1846061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1847044706000.  Starting simulation...
+info: Entering event queue @ 1847061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1848044706000.  Starting simulation...
+info: Entering event queue @ 1848061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1849044706000.  Starting simulation...
-info: Entering event queue @ 1856044695500.  Starting simulation...
-info: Entering event queue @ 1856044703500.  Starting simulation...
+info: Entering event queue @ 1849061009500.  Starting simulation...
+info: Entering event queue @ 1856061002500.  Starting simulation...
+info: Entering event queue @ 1856061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1856044708000.  Starting simulation...
+info: Entering event queue @ 1856061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1857044708000.  Starting simulation...
+info: Entering event queue @ 1857061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1858044708000.  Starting simulation...
+info: Entering event queue @ 1858061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1859044708000.  Starting simulation...
-info: Entering event queue @ 1866044694500.  Starting simulation...
-info: Entering event queue @ 1866044701000.  Starting simulation...
+info: Entering event queue @ 1859061009500.  Starting simulation...
+info: Entering event queue @ 1866061002500.  Starting simulation...
+info: Entering event queue @ 1866061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1866044701500.  Starting simulation...
+info: Entering event queue @ 1866061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1867044701500.  Starting simulation...
+info: Entering event queue @ 1867061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1868044701500.  Starting simulation...
+info: Entering event queue @ 1868061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1869044701500.  Starting simulation...
-info: Entering event queue @ 1876044694500.  Starting simulation...
-info: Entering event queue @ 1876044701500.  Starting simulation...
+info: Entering event queue @ 1869061009500.  Starting simulation...
+info: Entering event queue @ 1876061002500.  Starting simulation...
+info: Entering event queue @ 1876061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1876044706000.  Starting simulation...
+info: Entering event queue @ 1876061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1877044706000.  Starting simulation...
+info: Entering event queue @ 1877061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1878044706000.  Starting simulation...
+info: Entering event queue @ 1878061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1879044706000.  Starting simulation...
-info: Entering event queue @ 1886044694500.  Starting simulation...
-info: Entering event queue @ 1886044701500.  Starting simulation...
+info: Entering event queue @ 1879061009500.  Starting simulation...
+info: Entering event queue @ 1886061002500.  Starting simulation...
+info: Entering event queue @ 1886061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1886044706000.  Starting simulation...
+info: Entering event queue @ 1886061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1887044706000.  Starting simulation...
+info: Entering event queue @ 1887061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1888044706000.  Starting simulation...
+info: Entering event queue @ 1888061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1889044706000.  Starting simulation...
-info: Entering event queue @ 1896044695500.  Starting simulation...
-info: Entering event queue @ 1896044703500.  Starting simulation...
+info: Entering event queue @ 1889061014000.  Starting simulation...
+info: Entering event queue @ 1896061003500.  Starting simulation...
+info: Entering event queue @ 1896061010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1896044708000.  Starting simulation...
+info: Entering event queue @ 1896061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1897044708000.  Starting simulation...
+info: Entering event queue @ 1897061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1898044708000.  Starting simulation...
+info: Entering event queue @ 1898061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1899044708000.  Starting simulation...
+info: Entering event queue @ 1899061015000.  Starting simulation...
+info: Entering event queue @ 1906061003500.  Starting simulation...
+info: Entering event queue @ 1906061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1906044695500.  Starting simulation...
+info: Entering event queue @ 1906061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1907044695500.  Starting simulation...
+info: Entering event queue @ 1907061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1908044695500.  Starting simulation...
+info: Entering event queue @ 1908061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1909044695500.  Starting simulation...
-info: Entering event queue @ 1916044694500.  Starting simulation...
-info: Entering event queue @ 1916044701000.  Starting simulation...
+info: Entering event queue @ 1909061015500.  Starting simulation...
+info: Entering event queue @ 1916061002500.  Starting simulation...
+info: Entering event queue @ 1916061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1916044701500.  Starting simulation...
+info: Entering event queue @ 1916061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1917044701500.  Starting simulation...
+info: Entering event queue @ 1917061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1918044701500.  Starting simulation...
+info: Entering event queue @ 1918061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1919044701500.  Starting simulation...
-info: Entering event queue @ 1926044694500.  Starting simulation...
-info: Entering event queue @ 1926044701500.  Starting simulation...
+info: Entering event queue @ 1919061009500.  Starting simulation...
+info: Entering event queue @ 1926061002500.  Starting simulation...
+info: Entering event queue @ 1926061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1926044706000.  Starting simulation...
+info: Entering event queue @ 1926061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1927044706000.  Starting simulation...
+info: Entering event queue @ 1927061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1928044706000.  Starting simulation...
+info: Entering event queue @ 1928061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1929044706000.  Starting simulation...
-info: Entering event queue @ 1936044695500.  Starting simulation...
-info: Entering event queue @ 1936460526000.  Starting simulation...
+info: Entering event queue @ 1929061009500.  Starting simulation...
+info: Entering event queue @ 1936061002500.  Starting simulation...
+info: Entering event queue @ 1936700970250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1936460528000.  Starting simulation...
+info: Entering event queue @ 1936700973000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1937460528000.  Starting simulation...
+info: Entering event queue @ 1937700973000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1938460528000.  Starting simulation...
+info: Entering event queue @ 1938700973000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1939460528000.  Starting simulation...
-info: Entering event queue @ 1946044694500.  Starting simulation...
-info: Entering event queue @ 1946044701500.  Starting simulation...
+info: Entering event queue @ 1939700973000.  Starting simulation...
+info: Entering event queue @ 1946061002500.  Starting simulation...
+info: Entering event queue @ 1946061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1946044706000.  Starting simulation...
+info: Entering event queue @ 1946061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1947044706000.  Starting simulation...
+info: Entering event queue @ 1947061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1948044706000.  Starting simulation...
+info: Entering event queue @ 1948061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1949044706000.  Starting simulation...
-info: Entering event queue @ 1956044694500.  Starting simulation...
-info: Entering event queue @ 1956044701500.  Starting simulation...
+info: Entering event queue @ 1949061014000.  Starting simulation...
+info: Entering event queue @ 1956061002500.  Starting simulation...
+info: Entering event queue @ 1956061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1956044706000.  Starting simulation...
+info: Entering event queue @ 1956061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1957044706000.  Starting simulation...
+info: Entering event queue @ 1957061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1958044706000.  Starting simulation...
+info: Entering event queue @ 1958061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1959044706000.  Starting simulation...
-info: Entering event queue @ 1966044695500.  Starting simulation...
-info: Entering event queue @ 1966044704000.  Starting simulation...
+info: Entering event queue @ 1959061014000.  Starting simulation...
+info: Entering event queue @ 1966061002500.  Starting simulation...
+info: Entering event queue @ 1966061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1966044704500.  Starting simulation...
+info: Entering event queue @ 1966061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1967044704500.  Starting simulation...
+info: Entering event queue @ 1967061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1968044704500.  Starting simulation...
-info: Entering event queue @ 1969197126000.  Starting simulation...
+info: Entering event queue @ 1968061009500.  Starting simulation...
+info: Entering event queue @ 1969436945250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1969197128000.  Starting simulation...
+info: Entering event queue @ 1969436948000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1970197128000.  Starting simulation...
-info: Entering event queue @ 1976044695500.  Starting simulation...
-info: Entering event queue @ 1976044703000.  Starting simulation...
+info: Entering event queue @ 1970436948000.  Starting simulation...
+info: Entering event queue @ 1976061002500.  Starting simulation...
+info: Entering event queue @ 1976061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1976044703500.  Starting simulation...
+info: Entering event queue @ 1976061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1977044703500.  Starting simulation...
+info: Entering event queue @ 1977061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1978044703500.  Starting simulation...
+info: Entering event queue @ 1978061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1979044703500.  Starting simulation...
+info: Entering event queue @ 1979061014000.  Starting simulation...
+info: Entering event queue @ 1986061002500.  Starting simulation...
+info: Entering event queue @ 1986061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1986044695500.  Starting simulation...
+info: Entering event queue @ 1986061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1987044695500.  Starting simulation...
+info: Entering event queue @ 1987061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1988044695500.  Starting simulation...
+info: Entering event queue @ 1988061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1989044695500.  Starting simulation...
+info: Entering event queue @ 1989061009500.  Starting simulation...
+info: Entering event queue @ 1996061003500.  Starting simulation...
+info: Entering event queue @ 1996061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1996044695500.  Starting simulation...
+info: Entering event queue @ 1996061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1997044695500.  Starting simulation...
+info: Entering event queue @ 1997061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 1998044695500.  Starting simulation...
+info: Entering event queue @ 1998061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 1999044695500.  Starting simulation...
-info: Entering event queue @ 2006044695500.  Starting simulation...
-info: Entering event queue @ 2006044703500.  Starting simulation...
+info: Entering event queue @ 1999061015500.  Starting simulation...
+info: Entering event queue @ 2006061002500.  Starting simulation...
+info: Entering event queue @ 2006061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2006044704000.  Starting simulation...
+info: Entering event queue @ 2006061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2007044704000.  Starting simulation...
+info: Entering event queue @ 2007061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2008044704000.  Starting simulation...
+info: Entering event queue @ 2008061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2009044704000.  Starting simulation...
-info: Entering event queue @ 2016044695500.  Starting simulation...
-info: Entering event queue @ 2016044702000.  Starting simulation...
+info: Entering event queue @ 2009061009500.  Starting simulation...
+info: Entering event queue @ 2016061002500.  Starting simulation...
+info: Entering event queue @ 2016061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2016044702500.  Starting simulation...
+info: Entering event queue @ 2016061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2017044702500.  Starting simulation...
+info: Entering event queue @ 2017061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2018044702500.  Starting simulation...
+info: Entering event queue @ 2018061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2019044702500.  Starting simulation...
-info: Entering event queue @ 2026044694500.  Starting simulation...
-info: Entering event queue @ 2026044701000.  Starting simulation...
+info: Entering event queue @ 2019061009500.  Starting simulation...
+info: Entering event queue @ 2026061002500.  Starting simulation...
+info: Entering event queue @ 2026061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2026044701500.  Starting simulation...
+info: Entering event queue @ 2026061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2027044701500.  Starting simulation...
+info: Entering event queue @ 2027061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2028044701500.  Starting simulation...
+info: Entering event queue @ 2028061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2029044701500.  Starting simulation...
-info: Entering event queue @ 2036044694500.  Starting simulation...
-info: Entering event queue @ 2036044701500.  Starting simulation...
+info: Entering event queue @ 2029061009500.  Starting simulation...
+info: Entering event queue @ 2036061002500.  Starting simulation...
+info: Entering event queue @ 2036061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2036044706000.  Starting simulation...
+info: Entering event queue @ 2036061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2037044706000.  Starting simulation...
+info: Entering event queue @ 2037061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2038044706000.  Starting simulation...
+info: Entering event queue @ 2038061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2039044706000.  Starting simulation...
-info: Entering event queue @ 2046044694500.  Starting simulation...
-info: Entering event queue @ 2046044701500.  Starting simulation...
+info: Entering event queue @ 2039061009500.  Starting simulation...
+info: Entering event queue @ 2046061002500.  Starting simulation...
+info: Entering event queue @ 2046061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2046044706000.  Starting simulation...
+info: Entering event queue @ 2046061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2047044706000.  Starting simulation...
+info: Entering event queue @ 2047061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2048044706000.  Starting simulation...
+info: Entering event queue @ 2048061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2049044706000.  Starting simulation...
-info: Entering event queue @ 2056044695500.  Starting simulation...
-info: Entering event queue @ 2056044703500.  Starting simulation...
+info: Entering event queue @ 2049061014000.  Starting simulation...
+info: Entering event queue @ 2056061003500.  Starting simulation...
+info: Entering event queue @ 2056061010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2056044708000.  Starting simulation...
+info: Entering event queue @ 2056061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2057044708000.  Starting simulation...
+info: Entering event queue @ 2057061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2058044708000.  Starting simulation...
+info: Entering event queue @ 2058061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2059044708000.  Starting simulation...
-info: Entering event queue @ 2066044695500.  Starting simulation...
-info: Entering event queue @ 2067405755000.  Starting simulation...
+info: Entering event queue @ 2059061015000.  Starting simulation...
+info: Entering event queue @ 2066061003500.  Starting simulation...
+info: Entering event queue @ 2067645765250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2067405757000.  Starting simulation...
+info: Entering event queue @ 2067645768000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2068405757000.  Starting simulation...
+info: Entering event queue @ 2068645768000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2069405757000.  Starting simulation...
+info: Entering event queue @ 2069645768000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2070405757000.  Starting simulation...
-info: Entering event queue @ 2076044694500.  Starting simulation...
-info: Entering event queue @ 2076044701000.  Starting simulation...
+info: Entering event queue @ 2070645768000.  Starting simulation...
+info: Entering event queue @ 2076061002500.  Starting simulation...
+info: Entering event queue @ 2076061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2076044701500.  Starting simulation...
+info: Entering event queue @ 2076061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2077044701500.  Starting simulation...
+info: Entering event queue @ 2077061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2078044701500.  Starting simulation...
+info: Entering event queue @ 2078061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2079044701500.  Starting simulation...
-info: Entering event queue @ 2086044694500.  Starting simulation...
-info: Entering event queue @ 2086044701500.  Starting simulation...
+info: Entering event queue @ 2079061009500.  Starting simulation...
+info: Entering event queue @ 2086061002500.  Starting simulation...
+info: Entering event queue @ 2086061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2086044706000.  Starting simulation...
+info: Entering event queue @ 2086061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2087044706000.  Starting simulation...
+info: Entering event queue @ 2087061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2088044706000.  Starting simulation...
+info: Entering event queue @ 2088061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2089044706000.  Starting simulation...
-info: Entering event queue @ 2096044695500.  Starting simulation...
-info: Entering event queue @ 2096044702500.  Starting simulation...
+info: Entering event queue @ 2089061009500.  Starting simulation...
+info: Entering event queue @ 2096061002500.  Starting simulation...
+info: Entering event queue @ 2096061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2096044707000.  Starting simulation...
+info: Entering event queue @ 2096061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2097044707000.  Starting simulation...
+info: Entering event queue @ 2097061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2098044707000.  Starting simulation...
+info: Entering event queue @ 2098061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2099044707000.  Starting simulation...
-info: Entering event queue @ 2106044694500.  Starting simulation...
-info: Entering event queue @ 2106044701500.  Starting simulation...
+info: Entering event queue @ 2099061009500.  Starting simulation...
+info: Entering event queue @ 2106061002500.  Starting simulation...
+info: Entering event queue @ 2106061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2106044706000.  Starting simulation...
+info: Entering event queue @ 2106061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2107044706000.  Starting simulation...
+info: Entering event queue @ 2107061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2108044706000.  Starting simulation...
+info: Entering event queue @ 2108061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2109044706000.  Starting simulation...
-info: Entering event queue @ 2116044694500.  Starting simulation...
-info: Entering event queue @ 2116044701500.  Starting simulation...
+info: Entering event queue @ 2109061014000.  Starting simulation...
+info: Entering event queue @ 2116061002500.  Starting simulation...
+info: Entering event queue @ 2116061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2116044706000.  Starting simulation...
+info: Entering event queue @ 2116061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2117044706000.  Starting simulation...
+info: Entering event queue @ 2117061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2118044706000.  Starting simulation...
+info: Entering event queue @ 2118061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2119044706000.  Starting simulation...
-info: Entering event queue @ 2126044695500.  Starting simulation...
-info: Entering event queue @ 2126044704000.  Starting simulation...
+info: Entering event queue @ 2119061014000.  Starting simulation...
+info: Entering event queue @ 2126061002500.  Starting simulation...
+info: Entering event queue @ 2126061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2126044708500.  Starting simulation...
+info: Entering event queue @ 2126061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2127044708500.  Starting simulation...
+info: Entering event queue @ 2127061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2128044708500.  Starting simulation...
+info: Entering event queue @ 2128061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2129044708500.  Starting simulation...
+info: Entering event queue @ 2129061009500.  Starting simulation...
+info: Entering event queue @ 2136061002500.  Starting simulation...
+info: Entering event queue @ 2136061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2136044695500.  Starting simulation...
+info: Entering event queue @ 2136061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2137044695500.  Starting simulation...
+info: Entering event queue @ 2137061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2138044695500.  Starting simulation...
+info: Entering event queue @ 2138061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2139044695500.  Starting simulation...
+info: Entering event queue @ 2139061014000.  Starting simulation...
+info: Entering event queue @ 2146061002500.  Starting simulation...
+info: Entering event queue @ 2146061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2146044695500.  Starting simulation...
+info: Entering event queue @ 2146061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2147044695500.  Starting simulation...
+info: Entering event queue @ 2147061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2148044695500.  Starting simulation...
+info: Entering event queue @ 2148061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2149044695500.  Starting simulation...
+info: Entering event queue @ 2149061009500.  Starting simulation...
+info: Entering event queue @ 2156061002500.  Starting simulation...
+info: Entering event queue @ 2156061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2156044695500.  Starting simulation...
+info: Entering event queue @ 2156061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2157044695500.  Starting simulation...
+info: Entering event queue @ 2157061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2158044695500.  Starting simulation...
+info: Entering event queue @ 2158061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2159044695500.  Starting simulation...
-info: Entering event queue @ 2166044694500.  Starting simulation...
-info: Entering event queue @ 2166044701500.  Starting simulation...
+info: Entering event queue @ 2159061014000.  Starting simulation...
+info: Entering event queue @ 2166061002500.  Starting simulation...
+info: Entering event queue @ 2166061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2166044706000.  Starting simulation...
+info: Entering event queue @ 2166061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2167044706000.  Starting simulation...
+info: Entering event queue @ 2167061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2168044706000.  Starting simulation...
+info: Entering event queue @ 2168061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2169044706000.  Starting simulation...
-info: Entering event queue @ 2176044694500.  Starting simulation...
-info: Entering event queue @ 2176044701500.  Starting simulation...
+info: Entering event queue @ 2169061009500.  Starting simulation...
+info: Entering event queue @ 2176061002500.  Starting simulation...
+info: Entering event queue @ 2176061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2176044706000.  Starting simulation...
+info: Entering event queue @ 2176061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2177044706000.  Starting simulation...
+info: Entering event queue @ 2177061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2178044706000.  Starting simulation...
+info: Entering event queue @ 2178061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2179044706000.  Starting simulation...
-info: Entering event queue @ 2186044694500.  Starting simulation...
-info: Entering event queue @ 2186044701000.  Starting simulation...
+info: Entering event queue @ 2179061009500.  Starting simulation...
+info: Entering event queue @ 2186061002500.  Starting simulation...
+info: Entering event queue @ 2186061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2186044701500.  Starting simulation...
+info: Entering event queue @ 2186061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2187044701500.  Starting simulation...
+info: Entering event queue @ 2187061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2188044701500.  Starting simulation...
+info: Entering event queue @ 2188061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2189044701500.  Starting simulation...
-info: Entering event queue @ 2196044694500.  Starting simulation...
-info: Entering event queue @ 2196044701500.  Starting simulation...
+info: Entering event queue @ 2189061009500.  Starting simulation...
+info: Entering event queue @ 2196061002500.  Starting simulation...
+info: Entering event queue @ 2196061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2196044706000.  Starting simulation...
+info: Entering event queue @ 2196061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2197044706000.  Starting simulation...
+info: Entering event queue @ 2197061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
+info: Entering event queue @ 2198061009500.  Starting simulation...
+info: Entering event queue @ 2198295410250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2198044706000.  Starting simulation...
+info: Entering event queue @ 2198295413000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2199044706000.  Starting simulation...
+info: Entering event queue @ 2199295413000.  Starting simulation...
+info: Entering event queue @ 2206061002500.  Starting simulation...
+info: Entering event queue @ 2206061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2206044695500.  Starting simulation...
+info: Entering event queue @ 2206061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2207044695500.  Starting simulation...
+info: Entering event queue @ 2207061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2208044695500.  Starting simulation...
+info: Entering event queue @ 2208061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2209044695500.  Starting simulation...
-info: Entering event queue @ 2216044694500.  Starting simulation...
-info: Entering event queue @ 2216044701500.  Starting simulation...
+info: Entering event queue @ 2209061014000.  Starting simulation...
+info: Entering event queue @ 2216061003500.  Starting simulation...
+info: Entering event queue @ 2216061010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2216044706000.  Starting simulation...
+info: Entering event queue @ 2216061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2217044706000.  Starting simulation...
+info: Entering event queue @ 2217061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2218044706000.  Starting simulation...
+info: Entering event queue @ 2218061015000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2219044706000.  Starting simulation...
-info: Entering event queue @ 2226044695500.  Starting simulation...
-info: Entering event queue @ 2226044703500.  Starting simulation...
+info: Entering event queue @ 2219061015000.  Starting simulation...
+info: Entering event queue @ 2226061003500.  Starting simulation...
+info: Entering event queue @ 2226061011000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2226044708000.  Starting simulation...
+info: Entering event queue @ 2226061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2227044708000.  Starting simulation...
+info: Entering event queue @ 2227061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2228044708000.  Starting simulation...
+info: Entering event queue @ 2228061015500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2229044708000.  Starting simulation...
-info: Entering event queue @ 2236044694500.  Starting simulation...
-info: Entering event queue @ 2236044701000.  Starting simulation...
+info: Entering event queue @ 2229061015500.  Starting simulation...
+info: Entering event queue @ 2236061002500.  Starting simulation...
+info: Entering event queue @ 2236061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2236044701500.  Starting simulation...
+info: Entering event queue @ 2236061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2237044701500.  Starting simulation...
+info: Entering event queue @ 2237061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2238044701500.  Starting simulation...
+info: Entering event queue @ 2238061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2239044701500.  Starting simulation...
-info: Entering event queue @ 2246044694500.  Starting simulation...
-info: Entering event queue @ 2246044701500.  Starting simulation...
+info: Entering event queue @ 2239061009500.  Starting simulation...
+info: Entering event queue @ 2246061002500.  Starting simulation...
+info: Entering event queue @ 2246061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2246044706000.  Starting simulation...
+info: Entering event queue @ 2246061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2247044706000.  Starting simulation...
+info: Entering event queue @ 2247061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2248044706000.  Starting simulation...
+info: Entering event queue @ 2248061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2249044706000.  Starting simulation...
-info: Entering event queue @ 2256044694500.  Starting simulation...
-info: Entering event queue @ 2256044701500.  Starting simulation...
+info: Entering event queue @ 2249061009500.  Starting simulation...
+info: Entering event queue @ 2256061002500.  Starting simulation...
+info: Entering event queue @ 2256061009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2256044706000.  Starting simulation...
+info: Entering event queue @ 2256061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2257044706000.  Starting simulation...
+info: Entering event queue @ 2257061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
 switching cpus
-info: Entering event queue @ 2258044706000.  Starting simulation...
+info: Entering event queue @ 2258061009500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2259044706000.  Starting simulation...
-info: Entering event queue @ 2266044694500.  Starting simulation...
-info: Entering event queue @ 2266044701500.  Starting simulation...
+info: Entering event queue @ 2259061009500.  Starting simulation...
+info: Entering event queue @ 2266061002500.  Starting simulation...
+info: Entering event queue @ 2266061009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2266044706000.  Starting simulation...
+info: Entering event queue @ 2266061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2267044706000.  Starting simulation...
+info: Entering event queue @ 2267061014000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2268044706000.  Starting simulation...
+info: Entering event queue @ 2268061014000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2268044713500.  Starting simulation...
+info: Entering event queue @ 2268061021500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2269044713500.  Starting simulation...
+info: Entering event queue @ 2269061021500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2269044786000.  Starting simulation...
+info: Entering event queue @ 2269061148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2270044786000.  Starting simulation...
+info: Entering event queue @ 2270061148000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2271044786000.  Starting simulation...
+info: Entering event queue @ 2271061148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2271044847000.  Starting simulation...
+info: Entering event queue @ 2271061155500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2272044847000.  Starting simulation...
+info: Entering event queue @ 2272061155500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2272044909000.  Starting simulation...
+info: Entering event queue @ 2272061191000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2273044909000.  Starting simulation...
+info: Entering event queue @ 2273061191000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2274044909000.  Starting simulation...
+info: Entering event queue @ 2274061191000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2274045051000.  Starting simulation...
+info: Entering event queue @ 2274061278000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2275045051000.  Starting simulation...
+info: Entering event queue @ 2275061278000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2275045114000.  Starting simulation...
+info: Entering event queue @ 2275061305000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2276045114000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2276045117500.  Starting simulation...
+info: Entering event queue @ 2276061305000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2277045117500.  Starting simulation...
+info: Entering event queue @ 2277061305000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2277045208000.  Starting simulation...
+info: Entering event queue @ 2277061449000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2278045208000.  Starting simulation...
+info: Entering event queue @ 2278061449000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2278045280000.  Starting simulation...
+info: Entering event queue @ 2278061476000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2279045280000.  Starting simulation...
+info: Entering event queue @ 2279061476000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2280045280000.  Starting simulation...
+info: Entering event queue @ 2280061476000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2280045384000.  Starting simulation...
+info: Entering event queue @ 2280061529000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2281045384000.  Starting simulation...
+info: Entering event queue @ 2281061529000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2281048528000.  Starting simulation...
+info: Entering event queue @ 2281070598000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2282048528000.  Starting simulation...
+info: Entering event queue @ 2282070598000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2283048528000.  Starting simulation...
+info: Entering event queue @ 2283070598000.  Starting simulation...
+info: Entering event queue @ 2283070605500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2283048535500.  Starting simulation...
+info: Entering event queue @ 2283070607500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2284048535500.  Starting simulation...
+info: Entering event queue @ 2284070607500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2284048596000.  Starting simulation...
+info: Entering event queue @ 2284072321000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2285048596000.  Starting simulation...
+info: Entering event queue @ 2285072321000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2286048596000.  Starting simulation...
+info: Entering event queue @ 2286072321000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2286048638000.  Starting simulation...
+info: Entering event queue @ 2286072412000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2287048638000.  Starting simulation...
+info: Entering event queue @ 2287072412000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2287048678500.  Starting simulation...
+info: Entering event queue @ 2287072517000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2288048678500.  Starting simulation...
+info: Entering event queue @ 2288072517000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2289048678500.  Starting simulation...
+info: Entering event queue @ 2289072517000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2289048766000.  Starting simulation...
+info: Entering event queue @ 2289072627000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2290048766000.  Starting simulation...
+info: Entering event queue @ 2290072627000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2290048836000.  Starting simulation...
+info: Entering event queue @ 2290072768000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2291048836000.  Starting simulation...
+info: Entering event queue @ 2291072768000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2292048836000.  Starting simulation...
+info: Entering event queue @ 2292072768000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2292048927000.  Starting simulation...
+info: Entering event queue @ 2292072780000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2293048927000.  Starting simulation...
+info: Entering event queue @ 2293072780000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2293049027000.  Starting simulation...
+info: Entering event queue @ 2293072888000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2294049027000.  Starting simulation...
+info: Entering event queue @ 2294072888000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2295049027000.  Starting simulation...
-info: Entering event queue @ 2296559734000.  Starting simulation...
+info: Entering event queue @ 2295072888000.  Starting simulation...
+info: Entering event queue @ 2296800002250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2296559736000.  Starting simulation...
+info: Entering event queue @ 2296800005000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2297559736000.  Starting simulation...
+info: Entering event queue @ 2297800005000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2297559885000.  Starting simulation...
+info: Entering event queue @ 2297800079000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2298559885000.  Starting simulation...
+info: Entering event queue @ 2298800079000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2299559885000.  Starting simulation...
+info: Entering event queue @ 2299800079000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2299559978000.  Starting simulation...
+info: Entering event queue @ 2299800134000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2300559978000.  Starting simulation...
+info: Entering event queue @ 2300800134000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2300560079000.  Starting simulation...
+info: Entering event queue @ 2300800209000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2301560079000.  Starting simulation...
+info: Entering event queue @ 2301800209000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2302560079000.  Starting simulation...
+info: Entering event queue @ 2302800209000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2302560132000.  Starting simulation...
+info: Entering event queue @ 2302800293000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2303560132000.  Starting simulation...
+info: Entering event queue @ 2303800293000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2303560241000.  Starting simulation...
+info: Entering event queue @ 2303800354000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2304560241000.  Starting simulation...
+info: Entering event queue @ 2304800354000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2305560241000.  Starting simulation...
+info: Entering event queue @ 2305800354000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2305560280000.  Starting simulation...
+info: Entering event queue @ 2305800437000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2306560280000.  Starting simulation...
+info: Entering event queue @ 2306800437000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2306560431000.  Starting simulation...
+info: Entering event queue @ 2306800538000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2307560431000.  Starting simulation...
+info: Entering event queue @ 2307800538000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2308560431000.  Starting simulation...
+info: Entering event queue @ 2308800538000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2308560560000.  Starting simulation...
+info: Entering event queue @ 2308800680000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2309560560000.  Starting simulation...
+info: Entering event queue @ 2309800680000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2309560642000.  Starting simulation...
+info: Entering event queue @ 2309800703000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2310560642000.  Starting simulation...
+info: Entering event queue @ 2310800703000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2311560642000.  Starting simulation...
+info: Entering event queue @ 2311800703000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2311560786000.  Starting simulation...
+info: Entering event queue @ 2311800722000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2312560786000.  Starting simulation...
+info: Entering event queue @ 2312800722000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2312560905000.  Starting simulation...
+info: Entering event queue @ 2312800881000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2313560905000.  Starting simulation...
+info: Entering event queue @ 2313800881000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2314560905000.  Starting simulation...
+info: Entering event queue @ 2314800881000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2314561028000.  Starting simulation...
+info: Entering event queue @ 2314800888500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2315561028000.  Starting simulation...
+info: Entering event queue @ 2315800888500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2315561054000.  Starting simulation...
+info: Entering event queue @ 2315801041000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2316561054000.  Starting simulation...
+info: Entering event queue @ 2316801041000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2317561054000.  Starting simulation...
+info: Entering event queue @ 2317801041000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2317561176000.  Starting simulation...
+info: Entering event queue @ 2317801187000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2318561176000.  Starting simulation...
+info: Entering event queue @ 2318801187000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2318561200000.  Starting simulation...
+info: Entering event queue @ 2318801316000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2319561200000.  Starting simulation...
+info: Entering event queue @ 2319801316000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2320561200000.  Starting simulation...
+info: Entering event queue @ 2320801316000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2320561287000.  Starting simulation...
+info: Entering event queue @ 2320801362000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2321561287000.  Starting simulation...
+info: Entering event queue @ 2321801362000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2321561319000.  Starting simulation...
+info: Entering event queue @ 2321801451000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2322561319000.  Starting simulation...
+info: Entering event queue @ 2322801451000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2323561319000.  Starting simulation...
+info: Entering event queue @ 2323801451000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2323561362000.  Starting simulation...
+info: Entering event queue @ 2323801593000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2324561362000.  Starting simulation...
+info: Entering event queue @ 2324801593000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2324561408000.  Starting simulation...
+info: Entering event queue @ 2324801757000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2325561408000.  Starting simulation...
+info: Entering event queue @ 2325801757000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2326561408000.  Starting simulation...
+info: Entering event queue @ 2326801757000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2326561540000.  Starting simulation...
+info: Entering event queue @ 2326801907000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2327561540000.  Starting simulation...
+info: Entering event queue @ 2327801907000.  Starting simulation...
+info: Entering event queue @ 2329536286250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2327561579000.  Starting simulation...
+info: Entering event queue @ 2329536289000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2328561579000.  Starting simulation...
+info: Entering event queue @ 2330536289000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2329561579000.  Starting simulation...
+info: Entering event queue @ 2331536289000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2329561703000.  Starting simulation...
+info: Entering event queue @ 2331536409000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2330561703000.  Starting simulation...
+info: Entering event queue @ 2332536409000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2330561718000.  Starting simulation...
+info: Entering event queue @ 2332536496000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2331561718000.  Starting simulation...
+info: Entering event queue @ 2333536496000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2332561718000.  Starting simulation...
+info: Entering event queue @ 2334536496000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2332561741000.  Starting simulation...
+info: Entering event queue @ 2334536578000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2333561741000.  Starting simulation...
+info: Entering event queue @ 2335536578000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2333561793000.  Starting simulation...
+info: Entering event queue @ 2335536696000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2334561793000.  Starting simulation...
+info: Entering event queue @ 2336536696000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2335561793000.  Starting simulation...
+info: Entering event queue @ 2337536696000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2335561883000.  Starting simulation...
+info: Entering event queue @ 2337536812000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2336561883000.  Starting simulation...
+info: Entering event queue @ 2338536812000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2336561949000.  Starting simulation...
+info: Entering event queue @ 2338536969000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2337561949000.  Starting simulation...
+info: Entering event queue @ 2339536969000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2338561949000.  Starting simulation...
+info: Entering event queue @ 2340536969000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2338562083000.  Starting simulation...
+info: Entering event queue @ 2340536997000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2339562083000.  Starting simulation...
+info: Entering event queue @ 2341536997000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2339562223000.  Starting simulation...
+info: Entering event queue @ 2341537098500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2340562223000.  Starting simulation...
+info: Entering event queue @ 2342537098500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2341562223000.  Starting simulation...
+info: Entering event queue @ 2343537098500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2341562231000.  Starting simulation...
+info: Entering event queue @ 2343537168000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2342562231000.  Starting simulation...
+info: Entering event queue @ 2344537168000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2342562288000.  Starting simulation...
+info: Entering event queue @ 2344537177500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2343562288000.  Starting simulation...
+info: Entering event queue @ 2345537177500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2344562288000.  Starting simulation...
+info: Entering event queue @ 2346537177500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2344562311000.  Starting simulation...
+info: Entering event queue @ 2346537288000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2345562311000.  Starting simulation...
+info: Entering event queue @ 2347537288000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2345562459000.  Starting simulation...
+info: Entering event queue @ 2347537394000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2346562459000.  Starting simulation...
+info: Entering event queue @ 2348537394000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2347562459000.  Starting simulation...
+info: Entering event queue @ 2349537394000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2347562517000.  Starting simulation...
+info: Entering event queue @ 2349537514000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2348562517000.  Starting simulation...
+info: Entering event queue @ 2350537514000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2348562659000.  Starting simulation...
+info: Entering event queue @ 2350537663000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2349562659000.  Starting simulation...
+info: Entering event queue @ 2351537663000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2350562659000.  Starting simulation...
+info: Entering event queue @ 2352537663000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2350562734000.  Starting simulation...
+info: Entering event queue @ 2352537779000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2351562734000.  Starting simulation...
+info: Entering event queue @ 2353537779000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2351562890000.  Starting simulation...
+info: Entering event queue @ 2353537905000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2352562890000.  Starting simulation...
+info: Entering event queue @ 2354537905000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2353562890000.  Starting simulation...
+info: Entering event queue @ 2355537905000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2353562986000.  Starting simulation...
+info: Entering event queue @ 2355538017000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2354562986000.  Starting simulation...
+info: Entering event queue @ 2356538017000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2354563105000.  Starting simulation...
+info: Entering event queue @ 2356538152000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2355563105000.  Starting simulation...
+info: Entering event queue @ 2357538152000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2356563105000.  Starting simulation...
+info: Entering event queue @ 2358538152000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2356563162000.  Starting simulation...
+info: Entering event queue @ 2358538294000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2357563162000.  Starting simulation...
+info: Entering event queue @ 2359538294000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2357568596000.  Starting simulation...
+info: Entering event queue @ 2359542534000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2358568596000.  Starting simulation...
+info: Entering event queue @ 2360542534000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2359568596000.  Starting simulation...
+info: Entering event queue @ 2361542534000.  Starting simulation...
+info: Entering event queue @ 2362129237250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2359568661000.  Starting simulation...
+info: Entering event queue @ 2362129240000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2360568661000.  Starting simulation...
-info: Entering event queue @ 2362032934000.  Starting simulation...
+info: Entering event queue @ 2363129240000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2362032936000.  Starting simulation...
+info: Entering event queue @ 2363133658000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2363032936000.  Starting simulation...
+info: Entering event queue @ 2364133658000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2364032936000.  Starting simulation...
+info: Entering event queue @ 2365133658000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2364033051000.  Starting simulation...
+info: Entering event queue @ 2365133769000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2365033051000.  Starting simulation...
+info: Entering event queue @ 2366133769000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2365033171000.  Starting simulation...
+info: Entering event queue @ 2366133837000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2366033171000.  Starting simulation...
+info: Entering event queue @ 2367133837000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2367033171000.  Starting simulation...
+info: Entering event queue @ 2368133837000.  Starting simulation...
+info: Entering event queue @ 2368133844500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2367033178500.  Starting simulation...
+info: Entering event queue @ 2368133845000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2368033178500.  Starting simulation...
+info: Entering event queue @ 2369133845000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2368033187500.  Starting simulation...
+info: Entering event queue @ 2369133852500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2369033187500.  Starting simulation...
+info: Entering event queue @ 2370133852500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2370033187500.  Starting simulation...
+info: Entering event queue @ 2371133852500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2370033205000.  Starting simulation...
+info: Entering event queue @ 2371134001000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2371033205000.  Starting simulation...
+info: Entering event queue @ 2372134001000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2371033365500.  Starting simulation...
+info: Entering event queue @ 2372143233000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2372033365500.  Starting simulation...
+info: Entering event queue @ 2373143233000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2373033365500.  Starting simulation...
-info: Entering event queue @ 2373033604000.  Starting simulation...
+info: Entering event queue @ 2374143233000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2373033611500.  Starting simulation...
+info: Entering event queue @ 2374143240500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2374033611500.  Starting simulation...
+info: Entering event queue @ 2375143240500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2374033619000.  Starting simulation...
+info: Entering event queue @ 2375145136500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2375033619000.  Starting simulation...
+info: Entering event queue @ 2376145136500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2376033619000.  Starting simulation...
+info: Entering event queue @ 2377145136500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2376033645000.  Starting simulation...
+info: Entering event queue @ 2377145199000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2377033645000.  Starting simulation...
+info: Entering event queue @ 2378145199000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2377043485500.  Starting simulation...
+info: Entering event queue @ 2378149152000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2379149152000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2378043485500.  Starting simulation...
+info: Entering event queue @ 2379149152500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2379043485500.  Starting simulation...
+info: Entering event queue @ 2380149152500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2379043518000.  Starting simulation...
+info: Entering event queue @ 2380149276000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2380043518000.  Starting simulation...
+info: Entering event queue @ 2381149276000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2380043682500.  Starting simulation...
+info: Entering event queue @ 2381149328000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2381043682500.  Starting simulation...
+info: Entering event queue @ 2382149328000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2382043682500.  Starting simulation...
+info: Entering event queue @ 2383149328000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2382043698000.  Starting simulation...
+info: Entering event queue @ 2383149380000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2383043698000.  Starting simulation...
+info: Entering event queue @ 2384149380000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2383051750000.  Starting simulation...
+info: Entering event queue @ 2384149451500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2384051750000.  Starting simulation...
+info: Entering event queue @ 2385149451500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2385051750000.  Starting simulation...
+info: Entering event queue @ 2386149451500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2385051891000.  Starting simulation...
+info: Entering event queue @ 2386149459000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2386051891000.  Starting simulation...
-info: Entering event queue @ 2386051935000.  Starting simulation...
+info: Entering event queue @ 2387149459000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2386052242750.  Starting simulation...
+info: Entering event queue @ 2387152521500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2387052242750.  Starting simulation...
+info: Entering event queue @ 2388152521500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2388052242750.  Starting simulation...
+info: Entering event queue @ 2389152521500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2388052250250.  Starting simulation...
+info: Entering event queue @ 2389152529000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2389052250250.  Starting simulation...
+info: Entering event queue @ 2390152529000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2389052257750.  Starting simulation...
+info: Entering event queue @ 2390152536500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2390052257750.  Starting simulation...
+info: Entering event queue @ 2391152536500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2391052257750.  Starting simulation...
+info: Entering event queue @ 2392152536500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2391052265250.  Starting simulation...
+info: Entering event queue @ 2392152544000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2392052265250.  Starting simulation...
+info: Entering event queue @ 2393152544000.  Starting simulation...
+info: Entering event queue @ 2395010782250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2392062139500.  Starting simulation...
+info: Entering event queue @ 2395010785000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2393062139500.  Starting simulation...
+info: Entering event queue @ 2396010785000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2393062140000.  Starting simulation...
+info: Entering event queue @ 2396010785500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2394062140000.  Starting simulation...
-info: Entering event queue @ 2394135530000.  Starting simulation...
+info: Entering event queue @ 2397010785500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2394135532000.  Starting simulation...
+info: Entering event queue @ 2397010793000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2395135532000.  Starting simulation...
+info: Entering event queue @ 2398010793000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2395135538000.  Starting simulation...
+info: Entering event queue @ 2398010844000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2399010844000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2396135538000.  Starting simulation...
+info: Entering event queue @ 2399010844500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2397135538000.  Starting simulation...
+info: Entering event queue @ 2400010844500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2397135545500.  Starting simulation...
+info: Entering event queue @ 2400010852000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2398135545500.  Starting simulation...
+info: Entering event queue @ 2401010852000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2398135611000.  Starting simulation...
+info: Entering event queue @ 2401010917000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2399135611000.  Starting simulation...
+info: Entering event queue @ 2402010917000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2400135611000.  Starting simulation...
+info: Entering event queue @ 2403010917000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2400135618500.  Starting simulation...
+info: Entering event queue @ 2403010924500.  Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal
index fa29081ad..aaf6d88fc 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/system.terminal
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
index 4b0166894..7b9011e3a 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/config.ini
@@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
@@ -24,7 +25,7 @@ load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -70,6 +71,11 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb tracer
@@ -84,7 +90,7 @@ backComSize=5
 branchPred=system.cpu0.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -163,11 +169,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -175,10 +179,10 @@ predType=tournament
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -189,12 +193,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=ArmTLB
 children=walker
@@ -203,7 +216,7 @@ walker=system.cpu0.dtb.walker
 
 [system.cpu0.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[3]
@@ -473,10 +486,10 @@ opLat=3
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -487,12 +500,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=ArmInterrupts
 
@@ -521,7 +543,7 @@ walker=system.cpu0.itb.walker
 
 [system.cpu0.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[2]
@@ -531,7 +553,7 @@ type=ExeTracer
 
 [system.cpu1]
 type=DerivO3CPU
-children=branchPred dtb fuPool interrupts isa itb tracer
+children=branchPred dtb fuPool isa itb tracer
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
@@ -543,7 +565,7 @@ backComSize=5
 branchPred=system.cpu1.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -569,7 +591,7 @@ iewToCommitDelay=1
 iewToDecodeDelay=1
 iewToFetchDelay=1
 iewToRenameDelay=1
-interrupts=system.cpu1.interrupts
+interrupts=Null
 isa=system.cpu1.isa
 issueToExecuteDelay=1
 issueWidth=8
@@ -620,11 +642,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -638,7 +658,7 @@ walker=system.cpu1.dtb.walker
 
 [system.cpu1.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
@@ -905,9 +925,6 @@ issueLat=3
 opClass=IprAccess
 opLat=3
 
-[system.cpu1.interrupts]
-type=ArmInterrupts
-
 [system.cpu1.isa]
 type=ArmISA
 fpsid=1090793632
@@ -933,21 +950,25 @@ walker=system.cpu1.itb.walker
 
 [system.cpu1.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
 [system.cpu1.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -956,10 +977,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -970,18 +991,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -992,28 +1022,36 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -1031,19 +1069,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -1054,8 +1097,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -1068,16 +1110,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -1124,7 +1166,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -1142,7 +1184,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -1156,7 +1198,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -1165,7 +1207,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -1182,7 +1224,7 @@ pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
-clock=1000
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -1191,12 +1233,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -1206,7 +1248,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -1216,7 +1258,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -1226,7 +1268,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -1240,7 +1282,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -1253,7 +1295,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -1266,23 +1308,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -1292,19 +1334,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -1316,7 +1357,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -1329,7 +1370,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -1339,7 +1380,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -1349,7 +1390,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -1359,7 +1400,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -1369,7 +1410,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -1383,7 +1424,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -1396,7 +1437,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -1411,7 +1452,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -1421,7 +1462,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -1431,7 +1472,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -1441,7 +1482,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -1457,8 +1498,7 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -1472,3 +1512,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
index 42bd5914c..c194b7193 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simerr
@@ -21,3 +21,5 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
index 3a7e6d4a4..5ab09214a 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 28 2013 10:14:03
-gem5 started Mar 28 2013 10:14:28
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:05:36
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Switching CPUs...
@@ -20,2605 +20,2605 @@ Switching CPUs...
 Next CPU: DerivO3CPU
 info: Entering event queue @ 2000007500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2000059000.  Starting simulation...
+info: Entering event queue @ 2000060000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 3000059000.  Starting simulation...
+info: Entering event queue @ 3000060000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 3000062500.  Starting simulation...
+info: Entering event queue @ 3000063500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 4000062500.  Starting simulation...
+info: Entering event queue @ 4000063500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 4000382000.  Starting simulation...
+info: Entering event queue @ 4000079500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 5000382000.  Starting simulation...
-info: Entering event queue @ 5000388500.  Starting simulation...
+info: Entering event queue @ 5000079500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 5000393500.  Starting simulation...
+info: Entering event queue @ 5000082000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 6000393500.  Starting simulation...
+info: Entering event queue @ 6000082000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 6000471000.  Starting simulation...
+info: Entering event queue @ 6000085000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 7000471000.  Starting simulation...
-info: Entering event queue @ 7000479500.  Starting simulation...
+info: Entering event queue @ 7000085000.  Starting simulation...
+info: Entering event queue @ 7000092500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 7000484000.  Starting simulation...
+info: Entering event queue @ 7000096500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 8000484000.  Starting simulation...
+info: Entering event queue @ 8000096500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 8000798500.  Starting simulation...
+info: Entering event queue @ 8000104000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 9000798500.  Starting simulation...
-info: Entering event queue @ 9000819500.  Starting simulation...
-info: Entering event queue @ 9000821500.  Starting simulation...
+info: Entering event queue @ 9000104000.  Starting simulation...
+info: Entering event queue @ 9000125000.  Starting simulation...
+info: Entering event queue @ 9000130000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 9000826000.  Starting simulation...
+info: Entering event queue @ 9000134500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 10000826000.  Starting simulation...
+info: Entering event queue @ 10000134500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 10000828500.  Starting simulation...
+info: Entering event queue @ 10000250000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 11000828500.  Starting simulation...
+info: Entering event queue @ 11000250000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 11000860500.  Starting simulation...
+info: Entering event queue @ 11000557000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 12000860500.  Starting simulation...
+info: Entering event queue @ 12000557000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 12000871500.  Starting simulation...
+info: Entering event queue @ 12000567000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 13000871500.  Starting simulation...
+info: Entering event queue @ 13000567000.  Starting simulation...
+info: Entering event queue @ 13000584000.  Starting simulation...
+info: Entering event queue @ 13000589000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 13000879000.  Starting simulation...
+info: Entering event queue @ 13000593500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 14000879000.  Starting simulation...
-info: Entering event queue @ 14000902000.  Starting simulation...
-info: Entering event queue @ 14000911000.  Starting simulation...
+info: Entering event queue @ 14000593500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 14000916504.  Starting simulation...
+info: Entering event queue @ 14000684000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 15000916504.  Starting simulation...
-info: Entering event queue @ 15000925500.  Starting simulation...
-info: Entering event queue @ 15000931500.  Starting simulation...
+info: Entering event queue @ 15000684000.  Starting simulation...
+info: Entering event queue @ 15000698000.  Starting simulation...
+info: Entering event queue @ 15000703000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 15000936000.  Starting simulation...
+info: Entering event queue @ 15000707500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 16000936000.  Starting simulation...
+info: Entering event queue @ 16000707500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 16001197000.  Starting simulation...
+info: Entering event queue @ 16000715000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 17001197000.  Starting simulation...
+info: Entering event queue @ 17000715000.  Starting simulation...
+info: Entering event queue @ 17000770000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 26026543000.  Starting simulation...
+info: Entering event queue @ 17000896000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 27026543000.  Starting simulation...
+info: Entering event queue @ 18000896000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 36026543000.  Starting simulation...
+info: Entering event queue @ 26407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 37026543000.  Starting simulation...
+info: Entering event queue @ 27407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 46026543000.  Starting simulation...
+info: Entering event queue @ 36407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 47026543000.  Starting simulation...
-info: Entering event queue @ 48597551000.  Starting simulation...
+info: Entering event queue @ 37407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 48597553000.  Starting simulation...
+info: Entering event queue @ 46407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 49597553000.  Starting simulation...
+info: Entering event queue @ 47407630000.  Starting simulation...
+info: Entering event queue @ 48415862250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 49597756250.  Starting simulation...
+info: Entering event queue @ 48415869750.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 50597756250.  Starting simulation...
+info: Entering event queue @ 49415869750.  Starting simulation...
+info: Entering event queue @ 49415893500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 50597763750.  Starting simulation...
+info: Entering event queue @ 49415994500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 51597763750.  Starting simulation...
+info: Entering event queue @ 50415994500.  Starting simulation...
+info: Entering event queue @ 50416030500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 51597906750.  Starting simulation...
+info: Entering event queue @ 50416112000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 52597906750.  Starting simulation...
-info: Entering event queue @ 52597914250.  Starting simulation...
-info: Entering event queue @ 52597920000.  Starting simulation...
+info: Entering event queue @ 51416112000.  Starting simulation...
+info: Entering event queue @ 51416127500.  Starting simulation...
+info: Entering event queue @ 51416132000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 52597924500.  Starting simulation...
+info: Entering event queue @ 51416136500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 53597924500.  Starting simulation...
-info: Entering event queue @ 53597946500.  Starting simulation...
+info: Entering event queue @ 52416136500.  Starting simulation...
+info: Entering event queue @ 52416144500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 53597952000.  Starting simulation...
+info: Entering event queue @ 52416149000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 54597952000.  Starting simulation...
+info: Entering event queue @ 53416149000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 54597974500.  Starting simulation...
+info: Entering event queue @ 53416152000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 55597974500.  Starting simulation...
-info: Entering event queue @ 55597991000.  Starting simulation...
-info: Entering event queue @ 55597997500.  Starting simulation...
+info: Entering event queue @ 54416152000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 55598002000.  Starting simulation...
+info: Entering event queue @ 54416158000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 56598002000.  Starting simulation...
+info: Entering event queue @ 55416158000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 56598009500.  Starting simulation...
+info: Entering event queue @ 55416494500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 57598009500.  Starting simulation...
-info: Entering event queue @ 57598017000.  Starting simulation...
-info: Entering event queue @ 57598021000.  Starting simulation...
+info: Entering event queue @ 56416494500.  Starting simulation...
+info: Entering event queue @ 56416502000.  Starting simulation...
+info: Entering event queue @ 56416506500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 57598025500.  Starting simulation...
+info: Entering event queue @ 56416511000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 58598025500.  Starting simulation...
+info: Entering event queue @ 57416511000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 66026543000.  Starting simulation...
+info: Entering event queue @ 66407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 67026543000.  Starting simulation...
+info: Entering event queue @ 67407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 76026543000.  Starting simulation...
+info: Entering event queue @ 76407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 77026543000.  Starting simulation...
+info: Entering event queue @ 77407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 86026543000.  Starting simulation...
+info: Entering event queue @ 86407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 87026543000.  Starting simulation...
+info: Entering event queue @ 87407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 96026543000.  Starting simulation...
+info: Entering event queue @ 96407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 97026543000.  Starting simulation...
+info: Entering event queue @ 97407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 106026543000.  Starting simulation...
+info: Entering event queue @ 106407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 107026543000.  Starting simulation...
+info: Entering event queue @ 107407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 116026543000.  Starting simulation...
+info: Entering event queue @ 116407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 117026543000.  Starting simulation...
+info: Entering event queue @ 117407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 126026543000.  Starting simulation...
+info: Entering event queue @ 126407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 127026543000.  Starting simulation...
+info: Entering event queue @ 127407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 136026543000.  Starting simulation...
+info: Entering event queue @ 136407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 137026543000.  Starting simulation...
+info: Entering event queue @ 137407630000.  Starting simulation...
+info: Entering event queue @ 146407630000.  Starting simulation...
+info: Entering event queue @ 146556126250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 146026543000.  Starting simulation...
+info: Entering event queue @ 146556129000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 147026543000.  Starting simulation...
+info: Entering event queue @ 147556129000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 156026543000.  Starting simulation...
+info: Entering event queue @ 156407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 157026543000.  Starting simulation...
+info: Entering event queue @ 157407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 166026543000.  Starting simulation...
+info: Entering event queue @ 166407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 167026543000.  Starting simulation...
+info: Entering event queue @ 167407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 176026543000.  Starting simulation...
+info: Entering event queue @ 176407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 177026543000.  Starting simulation...
+info: Entering event queue @ 177407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 186026543000.  Starting simulation...
+info: Entering event queue @ 186407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 187026543000.  Starting simulation...
+info: Entering event queue @ 187407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 196026543000.  Starting simulation...
+info: Entering event queue @ 196407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 197026543000.  Starting simulation...
+info: Entering event queue @ 197407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 206026543000.  Starting simulation...
+info: Entering event queue @ 206407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 207026543000.  Starting simulation...
+info: Entering event queue @ 207407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 216026543000.  Starting simulation...
+info: Entering event queue @ 207407637500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 217026543000.  Starting simulation...
+info: Entering event queue @ 208407637500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 217026554500.  Starting simulation...
+info: Entering event queue @ 216407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 218026554500.  Starting simulation...
+info: Entering event queue @ 217407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 226026543000.  Starting simulation...
+info: Entering event queue @ 226407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 227026543000.  Starting simulation...
+info: Entering event queue @ 227407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 236026543000.  Starting simulation...
+info: Entering event queue @ 236407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 237026543000.  Starting simulation...
+info: Entering event queue @ 237407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 246026543000.  Starting simulation...
+info: Entering event queue @ 246407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 247026543000.  Starting simulation...
+info: Entering event queue @ 247407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 256026543000.  Starting simulation...
+info: Entering event queue @ 256407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 257026543000.  Starting simulation...
+info: Entering event queue @ 257407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 266026543000.  Starting simulation...
+info: Entering event queue @ 266407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 267026543000.  Starting simulation...
-info: Entering event queue @ 276026543000.  Starting simulation...
-info: Entering event queue @ 276896939000.  Starting simulation...
+info: Entering event queue @ 267407630000.  Starting simulation...
+info: Entering event queue @ 276407630000.  Starting simulation...
+info: Entering event queue @ 277500885250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 276896941000.  Starting simulation...
+info: Entering event queue @ 277500888000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 277896941000.  Starting simulation...
+info: Entering event queue @ 278500888000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 286026543000.  Starting simulation...
+info: Entering event queue @ 286407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 287026543000.  Starting simulation...
+info: Entering event queue @ 287407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 296026543000.  Starting simulation...
+info: Entering event queue @ 296407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 297026543000.  Starting simulation...
+info: Entering event queue @ 297407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 306026543000.  Starting simulation...
+info: Entering event queue @ 306407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 307026543000.  Starting simulation...
+info: Entering event queue @ 307407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 316026543000.  Starting simulation...
+info: Entering event queue @ 316407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 317026543000.  Starting simulation...
+info: Entering event queue @ 317407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 326026543000.  Starting simulation...
+info: Entering event queue @ 326407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 327026543000.  Starting simulation...
+info: Entering event queue @ 327407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 336026543000.  Starting simulation...
+info: Entering event queue @ 336407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 337026543000.  Starting simulation...
+info: Entering event queue @ 337407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 346026543000.  Starting simulation...
+info: Entering event queue @ 346407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 347026543000.  Starting simulation...
+info: Entering event queue @ 347407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 356026543000.  Starting simulation...
+info: Entering event queue @ 356407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 357026543000.  Starting simulation...
+info: Entering event queue @ 357407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 366026543000.  Starting simulation...
+info: Entering event queue @ 366407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 367026543000.  Starting simulation...
+info: Entering event queue @ 367407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 376026543000.  Starting simulation...
+info: Entering event queue @ 376407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 377026543000.  Starting simulation...
+info: Entering event queue @ 377407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 386026543000.  Starting simulation...
+info: Entering event queue @ 386407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 387026543000.  Starting simulation...
+info: Entering event queue @ 387407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 396026543000.  Starting simulation...
+info: Entering event queue @ 396407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 397026543000.  Starting simulation...
+info: Entering event queue @ 397407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 406026543000.  Starting simulation...
+info: Entering event queue @ 406407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 407026543000.  Starting simulation...
+info: Entering event queue @ 407407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 416026543000.  Starting simulation...
+info: Entering event queue @ 416407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 417026543000.  Starting simulation...
+info: Entering event queue @ 417407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 426026543000.  Starting simulation...
+info: Entering event queue @ 426407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 427026543000.  Starting simulation...
+info: Entering event queue @ 427407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 436026543000.  Starting simulation...
+info: Entering event queue @ 436407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 437026543000.  Starting simulation...
+info: Entering event queue @ 437407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 446026543000.  Starting simulation...
+info: Entering event queue @ 446407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 447026543000.  Starting simulation...
+info: Entering event queue @ 447407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 456026543000.  Starting simulation...
+info: Entering event queue @ 456407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 457026543000.  Starting simulation...
+info: Entering event queue @ 457407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 466026543000.  Starting simulation...
+info: Entering event queue @ 466407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 467026543000.  Starting simulation...
+info: Entering event queue @ 467407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 476026543000.  Starting simulation...
+info: Entering event queue @ 476407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 477026543000.  Starting simulation...
+info: Entering event queue @ 477407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 486026543000.  Starting simulation...
+info: Entering event queue @ 486407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 487026543000.  Starting simulation...
+info: Entering event queue @ 487407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 496026543000.  Starting simulation...
+info: Entering event queue @ 496407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 497026543000.  Starting simulation...
-info: Entering event queue @ 506026543000.  Starting simulation...
-info: Entering event queue @ 506050935000.  Starting simulation...
+info: Entering event queue @ 497407630000.  Starting simulation...
+info: Entering event queue @ 506407630000.  Starting simulation...
+info: Entering event queue @ 506654813250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 506050937000.  Starting simulation...
+info: Entering event queue @ 506654816000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 507050937000.  Starting simulation...
+info: Entering event queue @ 507654816000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 516026543000.  Starting simulation...
+info: Entering event queue @ 516407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 517026543000.  Starting simulation...
+info: Entering event queue @ 517407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 526026543000.  Starting simulation...
+info: Entering event queue @ 526407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 527026543000.  Starting simulation...
+info: Entering event queue @ 527407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 536026543000.  Starting simulation...
+info: Entering event queue @ 536407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 537026543000.  Starting simulation...
+info: Entering event queue @ 537407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 546026543000.  Starting simulation...
+info: Entering event queue @ 546407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 547026543000.  Starting simulation...
+info: Entering event queue @ 547407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 556026543000.  Starting simulation...
+info: Entering event queue @ 556407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 557026543000.  Starting simulation...
+info: Entering event queue @ 557407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 566026543000.  Starting simulation...
+info: Entering event queue @ 566407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 567026543000.  Starting simulation...
+info: Entering event queue @ 567407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 576026543000.  Starting simulation...
+info: Entering event queue @ 576407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 577026543000.  Starting simulation...
+info: Entering event queue @ 577407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 586026543000.  Starting simulation...
+info: Entering event queue @ 586407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 587026543000.  Starting simulation...
+info: Entering event queue @ 587407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 596026543000.  Starting simulation...
+info: Entering event queue @ 596407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 597026543000.  Starting simulation...
+info: Entering event queue @ 597407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 606026543000.  Starting simulation...
+info: Entering event queue @ 606407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 607026543000.  Starting simulation...
+info: Entering event queue @ 607407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 616026543000.  Starting simulation...
+info: Entering event queue @ 616407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 617026543000.  Starting simulation...
+info: Entering event queue @ 617407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 626026543000.  Starting simulation...
+info: Entering event queue @ 626407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 627026543000.  Starting simulation...
-info: Entering event queue @ 636026543000.  Starting simulation...
-info: Entering event queue @ 636994938000.  Starting simulation...
+info: Entering event queue @ 627407630000.  Starting simulation...
+info: Entering event queue @ 636407630000.  Starting simulation...
+info: Entering event queue @ 637599918250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 636994940000.  Starting simulation...
+info: Entering event queue @ 637599921000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 637994940000.  Starting simulation...
+info: Entering event queue @ 638599921000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 646026543000.  Starting simulation...
+info: Entering event queue @ 646407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 647026543000.  Starting simulation...
+info: Entering event queue @ 647407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 656026543000.  Starting simulation...
+info: Entering event queue @ 656407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 657026543000.  Starting simulation...
+info: Entering event queue @ 657407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 666026543000.  Starting simulation...
+info: Entering event queue @ 666407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 667026543000.  Starting simulation...
+info: Entering event queue @ 667407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 676026543000.  Starting simulation...
+info: Entering event queue @ 676407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 677026543000.  Starting simulation...
+info: Entering event queue @ 677407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 686026543000.  Starting simulation...
+info: Entering event queue @ 686407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 687026543000.  Starting simulation...
+info: Entering event queue @ 687407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 696026543000.  Starting simulation...
+info: Entering event queue @ 696407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 697026543000.  Starting simulation...
+info: Entering event queue @ 697407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 706026543000.  Starting simulation...
+info: Entering event queue @ 706407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 707026543000.  Starting simulation...
+info: Entering event queue @ 707407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 716026543000.  Starting simulation...
+info: Entering event queue @ 716407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 717026543000.  Starting simulation...
+info: Entering event queue @ 717407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 726026543000.  Starting simulation...
+info: Entering event queue @ 726407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 727026543000.  Starting simulation...
+info: Entering event queue @ 727407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 736026543000.  Starting simulation...
+info: Entering event queue @ 736407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 737026543000.  Starting simulation...
+info: Entering event queue @ 737407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 746026543000.  Starting simulation...
+info: Entering event queue @ 746407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 747026543000.  Starting simulation...
+info: Entering event queue @ 747407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 756026543000.  Starting simulation...
+info: Entering event queue @ 756407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 757026543000.  Starting simulation...
+info: Entering event queue @ 757407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 766026543000.  Starting simulation...
+info: Entering event queue @ 766407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 767026543000.  Starting simulation...
+info: Entering event queue @ 767407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 776026543000.  Starting simulation...
+info: Entering event queue @ 776407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 777026543000.  Starting simulation...
+info: Entering event queue @ 777407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 786026543000.  Starting simulation...
+info: Entering event queue @ 786407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 787026543000.  Starting simulation...
+info: Entering event queue @ 787407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 796026543000.  Starting simulation...
+info: Entering event queue @ 796407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 797026543000.  Starting simulation...
+info: Entering event queue @ 797407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 806026543000.  Starting simulation...
+info: Entering event queue @ 806407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 807026543000.  Starting simulation...
+info: Entering event queue @ 807407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 816026543000.  Starting simulation...
+info: Entering event queue @ 816407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 817026543000.  Starting simulation...
+info: Entering event queue @ 817407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 826026543000.  Starting simulation...
+info: Entering event queue @ 826407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 827026543000.  Starting simulation...
+info: Entering event queue @ 827407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 836026543000.  Starting simulation...
+info: Entering event queue @ 836407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 837026543000.  Starting simulation...
+info: Entering event queue @ 837407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 846026543000.  Starting simulation...
+info: Entering event queue @ 846407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 847026543000.  Starting simulation...
+info: Entering event queue @ 847407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 856026543000.  Starting simulation...
+info: Entering event queue @ 856407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 857026543000.  Starting simulation...
-info: Entering event queue @ 866026543000.  Starting simulation...
-info: Entering event queue @ 866148955000.  Starting simulation...
+info: Entering event queue @ 857407630000.  Starting simulation...
+info: Entering event queue @ 866407630000.  Starting simulation...
+info: Entering event queue @ 866753842250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 866148957000.  Starting simulation...
+info: Entering event queue @ 866753845000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 867148957000.  Starting simulation...
+info: Entering event queue @ 867753845000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 876026543000.  Starting simulation...
+info: Entering event queue @ 876407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 877026543000.  Starting simulation...
+info: Entering event queue @ 877407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 886026543000.  Starting simulation...
+info: Entering event queue @ 886407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 887026543000.  Starting simulation...
+info: Entering event queue @ 887407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 896026543000.  Starting simulation...
+info: Entering event queue @ 896407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 897026543000.  Starting simulation...
+info: Entering event queue @ 897407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 906026543000.  Starting simulation...
+info: Entering event queue @ 906407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 907026543000.  Starting simulation...
+info: Entering event queue @ 907407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 916026543000.  Starting simulation...
+info: Entering event queue @ 916407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 917026543000.  Starting simulation...
+info: Entering event queue @ 917407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 926026543000.  Starting simulation...
+info: Entering event queue @ 926407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 927026543000.  Starting simulation...
+info: Entering event queue @ 927407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 936026543000.  Starting simulation...
+info: Entering event queue @ 936407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 937026543000.  Starting simulation...
+info: Entering event queue @ 937407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 946026543000.  Starting simulation...
+info: Entering event queue @ 946407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 947026543000.  Starting simulation...
+info: Entering event queue @ 947407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 956026543000.  Starting simulation...
+info: Entering event queue @ 956407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 957026543000.  Starting simulation...
+info: Entering event queue @ 957407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 966026543000.  Starting simulation...
+info: Entering event queue @ 966407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 967026543000.  Starting simulation...
+info: Entering event queue @ 967407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 976026543000.  Starting simulation...
+info: Entering event queue @ 976407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 977026543000.  Starting simulation...
+info: Entering event queue @ 977407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 986026543000.  Starting simulation...
+info: Entering event queue @ 986407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 987026543000.  Starting simulation...
-info: Entering event queue @ 996026543000.  Starting simulation...
-info: Entering event queue @ 997094339000.  Starting simulation...
+info: Entering event queue @ 987407630000.  Starting simulation...
+info: Entering event queue @ 996407630000.  Starting simulation...
+info: Entering event queue @ 997698950250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 997094341000.  Starting simulation...
+info: Entering event queue @ 997698953000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 998094341000.  Starting simulation...
+info: Entering event queue @ 998698953000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1006026543000.  Starting simulation...
+info: Entering event queue @ 1006407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1007026543000.  Starting simulation...
+info: Entering event queue @ 1007407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1016026543000.  Starting simulation...
+info: Entering event queue @ 1016407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1017026543000.  Starting simulation...
+info: Entering event queue @ 1017407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1026026543000.  Starting simulation...
+info: Entering event queue @ 1026407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1027026543000.  Starting simulation...
+info: Entering event queue @ 1027407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1036026543000.  Starting simulation...
+info: Entering event queue @ 1036407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1037026543000.  Starting simulation...
+info: Entering event queue @ 1037407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1046026543000.  Starting simulation...
+info: Entering event queue @ 1046407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1047026543000.  Starting simulation...
+info: Entering event queue @ 1047407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1056026543000.  Starting simulation...
+info: Entering event queue @ 1056407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1057026543000.  Starting simulation...
+info: Entering event queue @ 1057407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1066026543000.  Starting simulation...
+info: Entering event queue @ 1066407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1067026543000.  Starting simulation...
+info: Entering event queue @ 1067407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1076026543000.  Starting simulation...
+info: Entering event queue @ 1076407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1077026543000.  Starting simulation...
+info: Entering event queue @ 1077407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1086026543000.  Starting simulation...
+info: Entering event queue @ 1086407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1087026543000.  Starting simulation...
+info: Entering event queue @ 1087407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1096026543000.  Starting simulation...
+info: Entering event queue @ 1096407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1097026543000.  Starting simulation...
+info: Entering event queue @ 1097407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1106026543000.  Starting simulation...
+info: Entering event queue @ 1106407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1107026543000.  Starting simulation...
+info: Entering event queue @ 1107407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1116026543000.  Starting simulation...
+info: Entering event queue @ 1116407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1117026543000.  Starting simulation...
+info: Entering event queue @ 1117407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1126026543000.  Starting simulation...
+info: Entering event queue @ 1126407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1127026543000.  Starting simulation...
+info: Entering event queue @ 1127407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1136026543000.  Starting simulation...
+info: Entering event queue @ 1136407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1137026543000.  Starting simulation...
+info: Entering event queue @ 1137407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1146026543000.  Starting simulation...
+info: Entering event queue @ 1146407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1147026543000.  Starting simulation...
+info: Entering event queue @ 1147407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1156026543000.  Starting simulation...
+info: Entering event queue @ 1156407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1157026543000.  Starting simulation...
+info: Entering event queue @ 1157407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1166026543000.  Starting simulation...
+info: Entering event queue @ 1166407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1167026543000.  Starting simulation...
+info: Entering event queue @ 1167407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1176026543000.  Starting simulation...
+info: Entering event queue @ 1176407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1177026543000.  Starting simulation...
+info: Entering event queue @ 1177407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1186026543000.  Starting simulation...
+info: Entering event queue @ 1186407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1187026543000.  Starting simulation...
+info: Entering event queue @ 1187407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1196026543000.  Starting simulation...
+info: Entering event queue @ 1196407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1197026543000.  Starting simulation...
+info: Entering event queue @ 1197407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1206026543000.  Starting simulation...
+info: Entering event queue @ 1206407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1207026543000.  Starting simulation...
+info: Entering event queue @ 1207407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1216026543000.  Starting simulation...
+info: Entering event queue @ 1216407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1217026543000.  Starting simulation...
-info: Entering event queue @ 1226026543000.  Starting simulation...
-info: Entering event queue @ 1226248314000.  Starting simulation...
+info: Entering event queue @ 1217407630000.  Starting simulation...
+info: Entering event queue @ 1226407630000.  Starting simulation...
+info: Entering event queue @ 1226852565250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1226248316000.  Starting simulation...
+info: Entering event queue @ 1226852568000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1227248316000.  Starting simulation...
+info: Entering event queue @ 1227852568000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1236026543000.  Starting simulation...
+info: Entering event queue @ 1236407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1237026543000.  Starting simulation...
+info: Entering event queue @ 1237407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1246026543000.  Starting simulation...
+info: Entering event queue @ 1246407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1247026543000.  Starting simulation...
+info: Entering event queue @ 1247407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1256026543000.  Starting simulation...
+info: Entering event queue @ 1256407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1257026543000.  Starting simulation...
+info: Entering event queue @ 1257407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1266026543000.  Starting simulation...
+info: Entering event queue @ 1266407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1267026543000.  Starting simulation...
+info: Entering event queue @ 1267407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1276026543000.  Starting simulation...
+info: Entering event queue @ 1276407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1277026543000.  Starting simulation...
+info: Entering event queue @ 1277407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1286026543000.  Starting simulation...
+info: Entering event queue @ 1286407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1287026543000.  Starting simulation...
+info: Entering event queue @ 1287407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1296026543000.  Starting simulation...
+info: Entering event queue @ 1296407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1297026543000.  Starting simulation...
+info: Entering event queue @ 1297407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1306026543000.  Starting simulation...
+info: Entering event queue @ 1306407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1307026543000.  Starting simulation...
+info: Entering event queue @ 1307407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1316026543000.  Starting simulation...
+info: Entering event queue @ 1316407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1317026543000.  Starting simulation...
+info: Entering event queue @ 1317407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1326026543000.  Starting simulation...
+info: Entering event queue @ 1326407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1327026543000.  Starting simulation...
+info: Entering event queue @ 1327407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1336026543000.  Starting simulation...
+info: Entering event queue @ 1336407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1337026543000.  Starting simulation...
+info: Entering event queue @ 1337407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1346026543000.  Starting simulation...
+info: Entering event queue @ 1346407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1347026543000.  Starting simulation...
-info: Entering event queue @ 1356026543000.  Starting simulation...
-info: Entering event queue @ 1357193547000.  Starting simulation...
+info: Entering event queue @ 1347407630000.  Starting simulation...
+info: Entering event queue @ 1356407630000.  Starting simulation...
+info: Entering event queue @ 1357797666250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1357193549000.  Starting simulation...
+info: Entering event queue @ 1357797669000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1358193549000.  Starting simulation...
+info: Entering event queue @ 1358797669000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1366026543000.  Starting simulation...
+info: Entering event queue @ 1366407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1367026543000.  Starting simulation...
+info: Entering event queue @ 1367407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1376026543000.  Starting simulation...
+info: Entering event queue @ 1376407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1377026543000.  Starting simulation...
+info: Entering event queue @ 1377407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1386026543000.  Starting simulation...
+info: Entering event queue @ 1386407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1387026543000.  Starting simulation...
+info: Entering event queue @ 1387407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1396026543000.  Starting simulation...
+info: Entering event queue @ 1396407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1397026543000.  Starting simulation...
+info: Entering event queue @ 1397407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1406026543000.  Starting simulation...
+info: Entering event queue @ 1406407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1407026543000.  Starting simulation...
+info: Entering event queue @ 1407407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1416026543000.  Starting simulation...
+info: Entering event queue @ 1416407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1417026543000.  Starting simulation...
+info: Entering event queue @ 1417407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1426026543000.  Starting simulation...
+info: Entering event queue @ 1426407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1427026543000.  Starting simulation...
+info: Entering event queue @ 1427407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1436026543000.  Starting simulation...
+info: Entering event queue @ 1436407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1437026543000.  Starting simulation...
+info: Entering event queue @ 1437407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1446026543000.  Starting simulation...
+info: Entering event queue @ 1446407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1447026543000.  Starting simulation...
+info: Entering event queue @ 1447407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1456026543000.  Starting simulation...
+info: Entering event queue @ 1456407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1457026543000.  Starting simulation...
+info: Entering event queue @ 1457407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1466026543000.  Starting simulation...
+info: Entering event queue @ 1466407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1467026543000.  Starting simulation...
+info: Entering event queue @ 1467407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1476026543000.  Starting simulation...
+info: Entering event queue @ 1476407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1477026543000.  Starting simulation...
+info: Entering event queue @ 1477407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1486026543000.  Starting simulation...
+info: Entering event queue @ 1486407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1487026543000.  Starting simulation...
+info: Entering event queue @ 1487407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1496026543000.  Starting simulation...
+info: Entering event queue @ 1496407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1497026543000.  Starting simulation...
+info: Entering event queue @ 1497407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1506026543000.  Starting simulation...
+info: Entering event queue @ 1506407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1507026543000.  Starting simulation...
+info: Entering event queue @ 1507407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1516026543000.  Starting simulation...
+info: Entering event queue @ 1516407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1517026543000.  Starting simulation...
+info: Entering event queue @ 1517407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1526026543000.  Starting simulation...
+info: Entering event queue @ 1526407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1527026543000.  Starting simulation...
+info: Entering event queue @ 1527407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1536026543000.  Starting simulation...
+info: Entering event queue @ 1536407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1537026543000.  Starting simulation...
+info: Entering event queue @ 1537407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1546026543000.  Starting simulation...
+info: Entering event queue @ 1546407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1547026543000.  Starting simulation...
+info: Entering event queue @ 1547407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1556026543000.  Starting simulation...
+info: Entering event queue @ 1556407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1557026543000.  Starting simulation...
+info: Entering event queue @ 1557407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1566026543000.  Starting simulation...
+info: Entering event queue @ 1566407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1567026543000.  Starting simulation...
+info: Entering event queue @ 1567407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1576026543000.  Starting simulation...
+info: Entering event queue @ 1576407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1577026543000.  Starting simulation...
-info: Entering event queue @ 1586026543000.  Starting simulation...
-info: Entering event queue @ 1586347543000.  Starting simulation...
+info: Entering event queue @ 1577407630000.  Starting simulation...
+info: Entering event queue @ 1586407630000.  Starting simulation...
+info: Entering event queue @ 1586951590250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1586347545000.  Starting simulation...
+info: Entering event queue @ 1586951593000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1587347545000.  Starting simulation...
+info: Entering event queue @ 1587951593000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1596026543000.  Starting simulation...
+info: Entering event queue @ 1596407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1597026543000.  Starting simulation...
+info: Entering event queue @ 1597407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1606026543000.  Starting simulation...
+info: Entering event queue @ 1606407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1607026543000.  Starting simulation...
+info: Entering event queue @ 1607407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1616026543000.  Starting simulation...
+info: Entering event queue @ 1616407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1617026543000.  Starting simulation...
+info: Entering event queue @ 1617407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1626026543000.  Starting simulation...
+info: Entering event queue @ 1626407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1627026543000.  Starting simulation...
+info: Entering event queue @ 1627407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1636026543000.  Starting simulation...
+info: Entering event queue @ 1636407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1637026543000.  Starting simulation...
+info: Entering event queue @ 1637407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1646026543000.  Starting simulation...
+info: Entering event queue @ 1646407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1647026543000.  Starting simulation...
+info: Entering event queue @ 1647407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1656026543000.  Starting simulation...
+info: Entering event queue @ 1656407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1657026543000.  Starting simulation...
+info: Entering event queue @ 1657407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1666026543000.  Starting simulation...
+info: Entering event queue @ 1666407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1667026543000.  Starting simulation...
+info: Entering event queue @ 1667407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1676026543000.  Starting simulation...
+info: Entering event queue @ 1676407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1677026543000.  Starting simulation...
+info: Entering event queue @ 1677407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1686026543000.  Starting simulation...
+info: Entering event queue @ 1686407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1687026543000.  Starting simulation...
+info: Entering event queue @ 1687407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1696026543000.  Starting simulation...
+info: Entering event queue @ 1696407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1697026543000.  Starting simulation...
+info: Entering event queue @ 1697407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1706026543000.  Starting simulation...
+info: Entering event queue @ 1706407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1707026543000.  Starting simulation...
-info: Entering event queue @ 1716026543000.  Starting simulation...
-info: Entering event queue @ 1717291739000.  Starting simulation...
+info: Entering event queue @ 1707407630000.  Starting simulation...
+info: Entering event queue @ 1716407630000.  Starting simulation...
+info: Entering event queue @ 1717896662250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1717291741000.  Starting simulation...
+info: Entering event queue @ 1717896665000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1718291741000.  Starting simulation...
+info: Entering event queue @ 1718896665000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1726026543000.  Starting simulation...
+info: Entering event queue @ 1726407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1727026543000.  Starting simulation...
+info: Entering event queue @ 1727407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1736026543000.  Starting simulation...
+info: Entering event queue @ 1736407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1737026543000.  Starting simulation...
+info: Entering event queue @ 1737407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1746026543000.  Starting simulation...
+info: Entering event queue @ 1746407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1747026543000.  Starting simulation...
+info: Entering event queue @ 1747407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1756026543000.  Starting simulation...
+info: Entering event queue @ 1756407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1757026543000.  Starting simulation...
+info: Entering event queue @ 1757407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1766026543000.  Starting simulation...
+info: Entering event queue @ 1766407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1767026543000.  Starting simulation...
+info: Entering event queue @ 1767407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1776026543000.  Starting simulation...
+info: Entering event queue @ 1776407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1777026543000.  Starting simulation...
+info: Entering event queue @ 1777407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1786026543000.  Starting simulation...
+info: Entering event queue @ 1786407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1787026543000.  Starting simulation...
+info: Entering event queue @ 1787407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1796026543000.  Starting simulation...
+info: Entering event queue @ 1796407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1797026543000.  Starting simulation...
+info: Entering event queue @ 1797407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1806026543000.  Starting simulation...
+info: Entering event queue @ 1806407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1807026543000.  Starting simulation...
+info: Entering event queue @ 1807407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1816026543000.  Starting simulation...
+info: Entering event queue @ 1816407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1817026543000.  Starting simulation...
+info: Entering event queue @ 1817407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1826026543000.  Starting simulation...
+info: Entering event queue @ 1826407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1827026543000.  Starting simulation...
+info: Entering event queue @ 1827407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1836026543000.  Starting simulation...
+info: Entering event queue @ 1836407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1837026543000.  Starting simulation...
+info: Entering event queue @ 1837407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1846026543000.  Starting simulation...
+info: Entering event queue @ 1846407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1847026543000.  Starting simulation...
+info: Entering event queue @ 1847407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1856026543000.  Starting simulation...
+info: Entering event queue @ 1856407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1857026543000.  Starting simulation...
+info: Entering event queue @ 1857407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1866026543000.  Starting simulation...
+info: Entering event queue @ 1866407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1867026543000.  Starting simulation...
+info: Entering event queue @ 1867407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1876026543000.  Starting simulation...
+info: Entering event queue @ 1876407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1877026543000.  Starting simulation...
+info: Entering event queue @ 1877407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1886026543000.  Starting simulation...
+info: Entering event queue @ 1886407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1887026543000.  Starting simulation...
+info: Entering event queue @ 1887407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1896026543000.  Starting simulation...
+info: Entering event queue @ 1896407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1897026543000.  Starting simulation...
+info: Entering event queue @ 1897407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1906026543000.  Starting simulation...
+info: Entering event queue @ 1906407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1907026543000.  Starting simulation...
+info: Entering event queue @ 1907407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1916026543000.  Starting simulation...
+info: Entering event queue @ 1916407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1917026543000.  Starting simulation...
+info: Entering event queue @ 1917407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1926026543000.  Starting simulation...
+info: Entering event queue @ 1926407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1927026543000.  Starting simulation...
+info: Entering event queue @ 1927407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1936026543000.  Starting simulation...
+info: Entering event queue @ 1936407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1937026543000.  Starting simulation...
-info: Entering event queue @ 1946026543000.  Starting simulation...
-info: Entering event queue @ 1946445714000.  Starting simulation...
+info: Entering event queue @ 1937407630000.  Starting simulation...
+info: Entering event queue @ 1946407630000.  Starting simulation...
+info: Entering event queue @ 1947050277250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1946445716000.  Starting simulation...
+info: Entering event queue @ 1947050280000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1947445716000.  Starting simulation...
+info: Entering event queue @ 1948050280000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1956026543000.  Starting simulation...
+info: Entering event queue @ 1956407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1957026543000.  Starting simulation...
+info: Entering event queue @ 1957407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1966026543000.  Starting simulation...
+info: Entering event queue @ 1966407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1967026543000.  Starting simulation...
+info: Entering event queue @ 1967407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1976026543000.  Starting simulation...
+info: Entering event queue @ 1976407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1977026543000.  Starting simulation...
+info: Entering event queue @ 1977407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1986026543000.  Starting simulation...
+info: Entering event queue @ 1986407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1987026543000.  Starting simulation...
+info: Entering event queue @ 1987407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1996026543000.  Starting simulation...
+info: Entering event queue @ 1996407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 1997026543000.  Starting simulation...
+info: Entering event queue @ 1997407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2006026543000.  Starting simulation...
+info: Entering event queue @ 2006407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2007026543000.  Starting simulation...
+info: Entering event queue @ 2007407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2016026543000.  Starting simulation...
+info: Entering event queue @ 2016407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2017026543000.  Starting simulation...
+info: Entering event queue @ 2017407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2026026543000.  Starting simulation...
+info: Entering event queue @ 2026407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2027026543000.  Starting simulation...
+info: Entering event queue @ 2027407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2036026543000.  Starting simulation...
+info: Entering event queue @ 2036407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2037026543000.  Starting simulation...
+info: Entering event queue @ 2037407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2046026543000.  Starting simulation...
+info: Entering event queue @ 2046407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2047026543000.  Starting simulation...
+info: Entering event queue @ 2047407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2056026543000.  Starting simulation...
+info: Entering event queue @ 2056407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2057026543000.  Starting simulation...
+info: Entering event queue @ 2057407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2066026543000.  Starting simulation...
+info: Entering event queue @ 2066407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2067026543000.  Starting simulation...
-info: Entering event queue @ 2076026543000.  Starting simulation...
-info: Entering event queue @ 2077390947000.  Starting simulation...
+info: Entering event queue @ 2067407630000.  Starting simulation...
+info: Entering event queue @ 2076407630000.  Starting simulation...
+info: Entering event queue @ 2077995385250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2077390949000.  Starting simulation...
+info: Entering event queue @ 2077995388000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2078390949000.  Starting simulation...
+info: Entering event queue @ 2078995388000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2086026543000.  Starting simulation...
+info: Entering event queue @ 2086407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2087026543000.  Starting simulation...
+info: Entering event queue @ 2087407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2096026543000.  Starting simulation...
+info: Entering event queue @ 2096407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2097026543000.  Starting simulation...
+info: Entering event queue @ 2097407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2106026543000.  Starting simulation...
+info: Entering event queue @ 2106407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2107026543000.  Starting simulation...
+info: Entering event queue @ 2107407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2116026543000.  Starting simulation...
+info: Entering event queue @ 2116407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2117026543000.  Starting simulation...
+info: Entering event queue @ 2117407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2126026543000.  Starting simulation...
+info: Entering event queue @ 2126407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2127026543000.  Starting simulation...
+info: Entering event queue @ 2127407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2136026543000.  Starting simulation...
+info: Entering event queue @ 2136407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2137026543000.  Starting simulation...
+info: Entering event queue @ 2137407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2146026543000.  Starting simulation...
+info: Entering event queue @ 2146407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2147026543000.  Starting simulation...
+info: Entering event queue @ 2147407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2156026543000.  Starting simulation...
+info: Entering event queue @ 2156407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2157026543000.  Starting simulation...
+info: Entering event queue @ 2157407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2166026543000.  Starting simulation...
+info: Entering event queue @ 2166407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2167026543000.  Starting simulation...
+info: Entering event queue @ 2167407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2176026543000.  Starting simulation...
+info: Entering event queue @ 2176407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2177026543000.  Starting simulation...
+info: Entering event queue @ 2177407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2186026543000.  Starting simulation...
+info: Entering event queue @ 2186407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2187026543000.  Starting simulation...
+info: Entering event queue @ 2187407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2196026543000.  Starting simulation...
+info: Entering event queue @ 2196407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2197026543000.  Starting simulation...
+info: Entering event queue @ 2197407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2206026543000.  Starting simulation...
+info: Entering event queue @ 2206407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2207026543000.  Starting simulation...
+info: Entering event queue @ 2207407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2216026543000.  Starting simulation...
+info: Entering event queue @ 2216407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2217026543000.  Starting simulation...
+info: Entering event queue @ 2217407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2226026543000.  Starting simulation...
+info: Entering event queue @ 2226407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2227026543000.  Starting simulation...
+info: Entering event queue @ 2227407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2236026543000.  Starting simulation...
+info: Entering event queue @ 2236407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2237026543000.  Starting simulation...
+info: Entering event queue @ 2237407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2246026543000.  Starting simulation...
+info: Entering event queue @ 2246407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2247026543000.  Starting simulation...
+info: Entering event queue @ 2247407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2256026543000.  Starting simulation...
+info: Entering event queue @ 2256407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2257026543000.  Starting simulation...
+info: Entering event queue @ 2257407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2266026543000.  Starting simulation...
+info: Entering event queue @ 2266407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2267026543000.  Starting simulation...
+info: Entering event queue @ 2267407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2276026543000.  Starting simulation...
+info: Entering event queue @ 2276407630000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2277026543000.  Starting simulation...
+info: Entering event queue @ 2277407630000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2277026550500.  Starting simulation...
+info: Entering event queue @ 2277409537500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2278026550500.  Starting simulation...
+info: Entering event queue @ 2278409537500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2278026844500.  Starting simulation...
+info: Entering event queue @ 2278414867500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2279026844500.  Starting simulation...
+info: Entering event queue @ 2279414867500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2279028634000.  Starting simulation...
+info: Entering event queue @ 2279419426000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2280028634000.  Starting simulation...
+info: Entering event queue @ 2280419426000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2280028792000.  Starting simulation...
+info: Entering event queue @ 2280419476000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2281028792000.  Starting simulation...
+info: Entering event queue @ 2281419476000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2281031728500.  Starting simulation...
+info: Entering event queue @ 2281429116500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2282031728500.  Starting simulation...
+info: Entering event queue @ 2282429116500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2282031872000.  Starting simulation...
+info: Entering event queue @ 2282429246000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2283031872000.  Starting simulation...
+info: Entering event queue @ 2283429246000.  Starting simulation...
+info: Entering event queue @ 2283429488500.  Starting simulation...
+info: Entering event queue @ 2283429494500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2283037827500.  Starting simulation...
+info: Entering event queue @ 2283429499000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2284037827500.  Starting simulation...
+info: Entering event queue @ 2284429499000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2284037973000.  Starting simulation...
+info: Entering event queue @ 2284429592000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2285037973000.  Starting simulation...
+info: Entering event queue @ 2285429592000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2285038127500.  Starting simulation...
+info: Entering event queue @ 2285429739000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2286038127500.  Starting simulation...
+info: Entering event queue @ 2286429739000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2286038281000.  Starting simulation...
+info: Entering event queue @ 2286429753500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2287038281000.  Starting simulation...
+info: Entering event queue @ 2287429753500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2287038326000.  Starting simulation...
+info: Entering event queue @ 2287429870500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2288038326000.  Starting simulation...
+info: Entering event queue @ 2288429870500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2288038395000.  Starting simulation...
+info: Entering event queue @ 2288429988500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2289038395000.  Starting simulation...
+info: Entering event queue @ 2289429988500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2289038454000.  Starting simulation...
+info: Entering event queue @ 2289430124000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2290038454000.  Starting simulation...
+info: Entering event queue @ 2290430124000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2290043867000.  Starting simulation...
+info: Entering event queue @ 2290430180500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2291043867000.  Starting simulation...
+info: Entering event queue @ 2291430180500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2291044009000.  Starting simulation...
+info: Entering event queue @ 2291430236000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2292044009000.  Starting simulation...
+info: Entering event queue @ 2292430236000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2292044100000.  Starting simulation...
+info: Entering event queue @ 2292430259000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2293044100000.  Starting simulation...
+info: Entering event queue @ 2293430259000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2293044163000.  Starting simulation...
+info: Entering event queue @ 2293433076000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2294044163000.  Starting simulation...
+info: Entering event queue @ 2294433076000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2294044227000.  Starting simulation...
+info: Entering event queue @ 2294433155000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2295044227000.  Starting simulation...
+info: Entering event queue @ 2295433155000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2295044273000.  Starting simulation...
+info: Entering event queue @ 2295433172000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2296044273000.  Starting simulation...
+info: Entering event queue @ 2296433172000.  Starting simulation...
+info: Entering event queue @ 2296433181500.  Starting simulation...
+info: Entering event queue @ 2296433186000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2296044353500.  Starting simulation...
+info: Entering event queue @ 2296433190500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2297044353500.  Starting simulation...
+info: Entering event queue @ 2297433190500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2297044376000.  Starting simulation...
+info: Entering event queue @ 2297433312000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2298044376000.  Starting simulation...
+info: Entering event queue @ 2298433312000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2298044505000.  Starting simulation...
+info: Entering event queue @ 2298433344000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2299044505000.  Starting simulation...
+info: Entering event queue @ 2299433344000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2299044591000.  Starting simulation...
+info: Entering event queue @ 2299433455000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2300044591000.  Starting simulation...
-info: Entering event queue @ 2300054074500.  Starting simulation...
-info: Entering event queue @ 2300054079500.  Starting simulation...
+info: Entering event queue @ 2300433455000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2300054084000.  Starting simulation...
+info: Entering event queue @ 2300433479000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2301054084000.  Starting simulation...
+info: Entering event queue @ 2301433479000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2301054216000.  Starting simulation...
+info: Entering event queue @ 2301433503000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2302054216000.  Starting simulation...
+info: Entering event queue @ 2302433503000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2302054252000.  Starting simulation...
+info: Entering event queue @ 2302440698000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2303054252000.  Starting simulation...
+info: Entering event queue @ 2303440698000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2303064199000.  Starting simulation...
+info: Entering event queue @ 2303440805000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2304064199000.  Starting simulation...
+info: Entering event queue @ 2304440805000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2304064238000.  Starting simulation...
+info: Entering event queue @ 2304440909000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2305064238000.  Starting simulation...
-info: Entering event queue @ 2306544922000.  Starting simulation...
+info: Entering event queue @ 2305440909000.  Starting simulation...
+info: Entering event queue @ 2307149622250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2306544924000.  Starting simulation...
+info: Entering event queue @ 2307149625000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2307544924000.  Starting simulation...
+info: Entering event queue @ 2308149625000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2307554441000.  Starting simulation...
+info: Entering event queue @ 2308149782000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2308554441000.  Starting simulation...
+info: Entering event queue @ 2309149782000.  Starting simulation...
+info: Entering event queue @ 2309152871000.  Starting simulation...
+info: Entering event queue @ 2309152877000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2308554462000.  Starting simulation...
+info: Entering event queue @ 2309152881500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2309554462000.  Starting simulation...
+info: Entering event queue @ 2310152881500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2309561672000.  Starting simulation...
+info: Entering event queue @ 2310153091000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2310561672000.  Starting simulation...
-info: Entering event queue @ 2310570028500.  Starting simulation...
-info: Entering event queue @ 2310570035000.  Starting simulation...
+info: Entering event queue @ 2311153091000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2310570039500.  Starting simulation...
+info: Entering event queue @ 2311153129000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2311570039500.  Starting simulation...
+info: Entering event queue @ 2312153129000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2311570139000.  Starting simulation...
+info: Entering event queue @ 2312162803000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2312570139000.  Starting simulation...
+info: Entering event queue @ 2313162803000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2312570195000.  Starting simulation...
+info: Entering event queue @ 2313162841000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2313570195000.  Starting simulation...
+info: Entering event queue @ 2314162841000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2313570285000.  Starting simulation...
+info: Entering event queue @ 2314162969000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2314570285000.  Starting simulation...
+info: Entering event queue @ 2315162969000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2314570324500.  Starting simulation...
+info: Entering event queue @ 2315169643000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2315570324500.  Starting simulation...
+info: Entering event queue @ 2316169643000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2315570361000.  Starting simulation...
+info: Entering event queue @ 2316169714000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2316570361000.  Starting simulation...
+info: Entering event queue @ 2317169714000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2316570403500.  Starting simulation...
+info: Entering event queue @ 2317169776000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2317570403500.  Starting simulation...
+info: Entering event queue @ 2318169776000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2317570429000.  Starting simulation...
+info: Entering event queue @ 2318175119000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2318570429000.  Starting simulation...
+info: Entering event queue @ 2319175119000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2318570448000.  Starting simulation...
+info: Entering event queue @ 2319175239000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2319570448000.  Starting simulation...
+info: Entering event queue @ 2320175239000.  Starting simulation...
+info: Entering event queue @ 2320175450500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2319570560000.  Starting simulation...
+info: Entering event queue @ 2320175458000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2320570560000.  Starting simulation...
+info: Entering event queue @ 2321175458000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2320570567500.  Starting simulation...
+info: Entering event queue @ 2321175591500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2321570567500.  Starting simulation...
+info: Entering event queue @ 2322175591500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2321570700000.  Starting simulation...
+info: Entering event queue @ 2322175626000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2322570700000.  Starting simulation...
+info: Entering event queue @ 2323175626000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2322570838000.  Starting simulation...
+info: Entering event queue @ 2323175647000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2323570838000.  Starting simulation...
+info: Entering event queue @ 2324175647000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2323570953000.  Starting simulation...
+info: Entering event queue @ 2324175714000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2324570953000.  Starting simulation...
+info: Entering event queue @ 2325175714000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2324571046000.  Starting simulation...
+info: Entering event queue @ 2325175854000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2325571046000.  Starting simulation...
+info: Entering event queue @ 2326175854000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2325571075000.  Starting simulation...
+info: Entering event queue @ 2326180829000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2326571075000.  Starting simulation...
+info: Entering event queue @ 2327180829000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2326571130000.  Starting simulation...
+info: Entering event queue @ 2327180923000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2327571130000.  Starting simulation...
+info: Entering event queue @ 2328180923000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2327571202000.  Starting simulation...
+info: Entering event queue @ 2328180942000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2328571202000.  Starting simulation...
+info: Entering event queue @ 2329180942000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2328571330000.  Starting simulation...
+info: Entering event queue @ 2329181056000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2329571330000.  Starting simulation...
+info: Entering event queue @ 2330181056000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2329571413000.  Starting simulation...
+info: Entering event queue @ 2330181099000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2330571413000.  Starting simulation...
+info: Entering event queue @ 2331181099000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2330571445000.  Starting simulation...
+info: Entering event queue @ 2331181224000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2331571445000.  Starting simulation...
+info: Entering event queue @ 2332181224000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2331571479000.  Starting simulation...
+info: Entering event queue @ 2332181371000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2332571479000.  Starting simulation...
+info: Entering event queue @ 2333181371000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2332581124000.  Starting simulation...
+info: Entering event queue @ 2333183918000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2333581124000.  Starting simulation...
+info: Entering event queue @ 2334183918000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2333581247000.  Starting simulation...
+info: Entering event queue @ 2334184003000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2334581247000.  Starting simulation...
-info: Entering event queue @ 2334581254500.  Starting simulation...
+info: Entering event queue @ 2335184003000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2334581257000.  Starting simulation...
+info: Entering event queue @ 2335184065500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2335581257000.  Starting simulation...
+info: Entering event queue @ 2336184065500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2335581419000.  Starting simulation...
+info: Entering event queue @ 2336184220000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2336581419000.  Starting simulation...
+info: Entering event queue @ 2337184220000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2336590347000.  Starting simulation...
+info: Entering event queue @ 2337184247000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2337590347000.  Starting simulation...
-info: Entering event queue @ 2339281522000.  Starting simulation...
+info: Entering event queue @ 2338184247000.  Starting simulation...
+info: Entering event queue @ 2339885909250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2339281524000.  Starting simulation...
+info: Entering event queue @ 2339885912000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2340281524000.  Starting simulation...
+info: Entering event queue @ 2340885912000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2340281630500.  Starting simulation...
+info: Entering event queue @ 2340885975000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2341281630500.  Starting simulation...
+info: Entering event queue @ 2341885975000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2341281710000.  Starting simulation...
+info: Entering event queue @ 2341885983000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2342281710000.  Starting simulation...
+info: Entering event queue @ 2342885983000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2342281728000.  Starting simulation...
+info: Entering event queue @ 2342893450000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2343281728000.  Starting simulation...
+info: Entering event queue @ 2343893450000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2343281745500.  Starting simulation...
+info: Entering event queue @ 2343893492000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2344281745500.  Starting simulation...
+info: Entering event queue @ 2344893492000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2344281816000.  Starting simulation...
+info: Entering event queue @ 2344893590000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2345281816000.  Starting simulation...
+info: Entering event queue @ 2345893590000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2345281843000.  Starting simulation...
+info: Entering event queue @ 2345900652000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2346281843000.  Starting simulation...
+info: Entering event queue @ 2346900652000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2346281957000.  Starting simulation...
+info: Entering event queue @ 2346900696000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2347281957000.  Starting simulation...
+info: Entering event queue @ 2347900696000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2347282029000.  Starting simulation...
+info: Entering event queue @ 2347900767000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2348282029000.  Starting simulation...
+info: Entering event queue @ 2348900767000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2348282128000.  Starting simulation...
+info: Entering event queue @ 2348900774500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2349282128000.  Starting simulation...
+info: Entering event queue @ 2349900774500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2349282215000.  Starting simulation...
+info: Entering event queue @ 2349900793000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2350282215000.  Starting simulation...
+info: Entering event queue @ 2350900793000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2350282373000.  Starting simulation...
+info: Entering event queue @ 2350900953500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2351282373000.  Starting simulation...
+info: Entering event queue @ 2351900953500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2351282490000.  Starting simulation...
+info: Entering event queue @ 2351901376000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2352282490000.  Starting simulation...
+info: Entering event queue @ 2352901376000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2352282616000.  Starting simulation...
+info: Entering event queue @ 2352901383500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2353282616000.  Starting simulation...
+info: Entering event queue @ 2353901383500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2353282704000.  Starting simulation...
+info: Entering event queue @ 2353901423000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2354282704000.  Starting simulation...
+info: Entering event queue @ 2354901423000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2354292637000.  Starting simulation...
+info: Entering event queue @ 2354908569000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2355292637000.  Starting simulation...
+info: Entering event queue @ 2355908569000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2355292752000.  Starting simulation...
+info: Entering event queue @ 2355908584000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2356292752000.  Starting simulation...
+info: Entering event queue @ 2356908584000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2356292829000.  Starting simulation...
+info: Entering event queue @ 2356908737000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2357292829000.  Starting simulation...
+info: Entering event queue @ 2357908737000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2357295010000.  Starting simulation...
+info: Entering event queue @ 2357915083000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2358295010000.  Starting simulation...
+info: Entering event queue @ 2358915083000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2358295060000.  Starting simulation...
+info: Entering event queue @ 2358915112000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2359295060000.  Starting simulation...
+info: Entering event queue @ 2359915112000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2359295117000.  Starting simulation...
+info: Entering event queue @ 2359915187000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2360295117000.  Starting simulation...
+info: Entering event queue @ 2360915187000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2360295201000.  Starting simulation...
+info: Entering event queue @ 2360922523000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2361295201000.  Starting simulation...
+info: Entering event queue @ 2361922523000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2361295232000.  Starting simulation...
+info: Entering event queue @ 2361922658000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2362295232000.  Starting simulation...
+info: Entering event queue @ 2362922658000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2362295364500.  Starting simulation...
+info: Entering event queue @ 2362922750500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2363295364500.  Starting simulation...
+info: Entering event queue @ 2363922750500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2363295520000.  Starting simulation...
+info: Entering event queue @ 2363922762000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2364295520000.  Starting simulation...
+info: Entering event queue @ 2364922762000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2364301747000.  Starting simulation...
+info: Entering event queue @ 2364922771000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2365301747000.  Starting simulation...
+info: Entering event queue @ 2365922771000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2365301807000.  Starting simulation...
+info: Entering event queue @ 2365927824000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2366301807000.  Starting simulation...
+info: Entering event queue @ 2366927824000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2366301912000.  Starting simulation...
+info: Entering event queue @ 2366927896000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2367301912000.  Starting simulation...
+info: Entering event queue @ 2367927896000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2367304066000.  Starting simulation...
+info: Entering event queue @ 2367927978000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2368304066000.  Starting simulation...
+info: Entering event queue @ 2368927978000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2368304184000.  Starting simulation...
+info: Entering event queue @ 2368928076000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2369304184000.  Starting simulation...
+info: Entering event queue @ 2369928076000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2369304297000.  Starting simulation...
+info: Entering event queue @ 2369928159000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2370304297000.  Starting simulation...
+info: Entering event queue @ 2370928159000.  Starting simulation...
+info: Entering event queue @ 2372622506250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2370304370000.  Starting simulation...
+info: Entering event queue @ 2372622509000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2371304370000.  Starting simulation...
-info: Entering event queue @ 2372016955000.  Starting simulation...
+info: Entering event queue @ 2373622509000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2372016957000.  Starting simulation...
+info: Entering event queue @ 2373622667000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2373016957000.  Starting simulation...
+info: Entering event queue @ 2374622667000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2373017069000.  Starting simulation...
+info: Entering event queue @ 2374625947000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2374017069000.  Starting simulation...
+info: Entering event queue @ 2375625947000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2374019359000.  Starting simulation...
+info: Entering event queue @ 2375625991000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2375019359000.  Starting simulation...
+info: Entering event queue @ 2376625991000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2375019391000.  Starting simulation...
+info: Entering event queue @ 2376626046000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2376019391000.  Starting simulation...
+info: Entering event queue @ 2377626046000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2376019468000.  Starting simulation...
+info: Entering event queue @ 2377626053500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2377019468000.  Starting simulation...
+info: Entering event queue @ 2378626053500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2377019493500.  Starting simulation...
+info: Entering event queue @ 2378626119000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2378019493500.  Starting simulation...
+info: Entering event queue @ 2379626119000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2378019501000.  Starting simulation...
+info: Entering event queue @ 2379633260000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2379019501000.  Starting simulation...
+info: Entering event queue @ 2380633260000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2379019576000.  Starting simulation...
+info: Entering event queue @ 2380633388000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2380019576000.  Starting simulation...
+info: Entering event queue @ 2381633388000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2380019732000.  Starting simulation...
+info: Entering event queue @ 2381633484000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2381019732000.  Starting simulation...
+info: Entering event queue @ 2382633484000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2381028816000.  Starting simulation...
+info: Entering event queue @ 2382639954000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2382028816000.  Starting simulation...
+info: Entering event queue @ 2383639954000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2382028916000.  Starting simulation...
+info: Entering event queue @ 2383640101000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2383028916000.  Starting simulation...
+info: Entering event queue @ 2384640101000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2383028989000.  Starting simulation...
+info: Entering event queue @ 2384640241000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2384028989000.  Starting simulation...
+info: Entering event queue @ 2385640241000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2384029150000.  Starting simulation...
+info: Entering event queue @ 2385646694000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2385029150000.  Starting simulation...
+info: Entering event queue @ 2386646694000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2385029168000.  Starting simulation...
+info: Entering event queue @ 2386646793000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2386029168000.  Starting simulation...
+info: Entering event queue @ 2387646793000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2386029178000.  Starting simulation...
+info: Entering event queue @ 2387646908500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2387029178000.  Starting simulation...
+info: Entering event queue @ 2388646908500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2387029238000.  Starting simulation...
+info: Entering event queue @ 2388646947500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2388029238000.  Starting simulation...
+info: Entering event queue @ 2389646947500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2388029333000.  Starting simulation...
+info: Entering event queue @ 2389647000500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2389029333000.  Starting simulation...
+info: Entering event queue @ 2390647000500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2389029370000.  Starting simulation...
+info: Entering event queue @ 2390647107000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2390029370000.  Starting simulation...
+info: Entering event queue @ 2391647107000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2390029405000.  Starting simulation...
+info: Entering event queue @ 2391647193000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2391029405000.  Starting simulation...
+info: Entering event queue @ 2392647193000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2391029529500.  Starting simulation...
+info: Entering event queue @ 2392647232000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2392029529500.  Starting simulation...
+info: Entering event queue @ 2393647232000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2392029617500.  Starting simulation...
+info: Entering event queue @ 2393655582000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2393029617500.  Starting simulation...
+info: Entering event queue @ 2394655582000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2393029685500.  Starting simulation...
+info: Entering event queue @ 2394655705000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2394029685500.  Starting simulation...
+info: Entering event queue @ 2395655705000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2394029788000.  Starting simulation...
+info: Entering event queue @ 2395655800000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2395029788000.  Starting simulation...
+info: Entering event queue @ 2396655800000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2395029853000.  Starting simulation...
+info: Entering event queue @ 2396655896000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2396029853000.  Starting simulation...
+info: Entering event queue @ 2397655896000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2396029864500.  Starting simulation...
+info: Entering event queue @ 2397656000000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2397029864500.  Starting simulation...
+info: Entering event queue @ 2398656000000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2397029943500.  Starting simulation...
+info: Entering event queue @ 2398656109000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2398029943500.  Starting simulation...
+info: Entering event queue @ 2399656109000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2398030031500.  Starting simulation...
+info: Entering event queue @ 2399656252000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2399030031500.  Starting simulation...
+info: Entering event queue @ 2400656252000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2399030085500.  Starting simulation...
+info: Entering event queue @ 2400658939000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2400030085500.  Starting simulation...
+info: Entering event queue @ 2401658939000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2400030175000.  Starting simulation...
+info: Entering event queue @ 2401659076000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2401030175000.  Starting simulation...
+info: Entering event queue @ 2402659076000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2401030308000.  Starting simulation...
+info: Entering event queue @ 2402659185500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2402030308000.  Starting simulation...
+info: Entering event queue @ 2403659185500.  Starting simulation...
+info: Entering event queue @ 2405358441250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2402030463000.  Starting simulation...
+info: Entering event queue @ 2405358444000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2403030463000.  Starting simulation...
-info: Entering event queue @ 2403036923000.  Starting simulation...
-info: Entering event queue @ 2403036924000.  Starting simulation...
+info: Entering event queue @ 2406358444000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2403036928500.  Starting simulation...
+info: Entering event queue @ 2406358469000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2404036928500.  Starting simulation...
-info: Entering event queue @ 2404753534000.  Starting simulation...
+info: Entering event queue @ 2407358469000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2404753536000.  Starting simulation...
+info: Entering event queue @ 2407367356000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2405753536000.  Starting simulation...
+info: Entering event queue @ 2408367356000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2405753688000.  Starting simulation...
+info: Entering event queue @ 2408367376000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2406753688000.  Starting simulation...
+info: Entering event queue @ 2409367376000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2406753797500.  Starting simulation...
+info: Entering event queue @ 2409367470000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2407753797500.  Starting simulation...
+info: Entering event queue @ 2410367470000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2407753845500.  Starting simulation...
+info: Entering event queue @ 2410374541000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2408753845500.  Starting simulation...
+info: Entering event queue @ 2411374541000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2408753915000.  Starting simulation...
+info: Entering event queue @ 2411374671000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2409753915000.  Starting simulation...
+info: Entering event queue @ 2412374671000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2409754052000.  Starting simulation...
+info: Entering event queue @ 2412374731500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2410754052000.  Starting simulation...
+info: Entering event queue @ 2413374731500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2410754121000.  Starting simulation...
+info: Entering event queue @ 2413381673000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2411754121000.  Starting simulation...
+info: Entering event queue @ 2414381673000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2411754241000.  Starting simulation...
+info: Entering event queue @ 2414381740000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2412754241000.  Starting simulation...
+info: Entering event queue @ 2415381740000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2412754335000.  Starting simulation...
+info: Entering event queue @ 2415381765000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2413754335000.  Starting simulation...
+info: Entering event queue @ 2416381765000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2413754496000.  Starting simulation...
+info: Entering event queue @ 2416388872000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2414754496000.  Starting simulation...
+info: Entering event queue @ 2417388872000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2414754503500.  Starting simulation...
+info: Entering event queue @ 2417388890000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2415754503500.  Starting simulation...
+info: Entering event queue @ 2418388890000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2415754548000.  Starting simulation...
+info: Entering event queue @ 2418388899500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2416754548000.  Starting simulation...
+info: Entering event queue @ 2419388899500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2416754666000.  Starting simulation...
+info: Entering event queue @ 2419388941000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2417754666000.  Starting simulation...
+info: Entering event queue @ 2420388941000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2417754746500.  Starting simulation...
+info: Entering event queue @ 2420389055000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2418754746500.  Starting simulation...
+info: Entering event queue @ 2421389055000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2418754759000.  Starting simulation...
+info: Entering event queue @ 2421389132000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2419754759000.  Starting simulation...
+info: Entering event queue @ 2422389132000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2419754791000.  Starting simulation...
+info: Entering event queue @ 2422389169500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2420754791000.  Starting simulation...
+info: Entering event queue @ 2423389169500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2420763573000.  Starting simulation...
+info: Entering event queue @ 2423389212000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2421763573000.  Starting simulation...
+info: Entering event queue @ 2424389212000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2421763627000.  Starting simulation...
+info: Entering event queue @ 2424392828000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2422763627000.  Starting simulation...
+info: Entering event queue @ 2425392828000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2422763683000.  Starting simulation...
+info: Entering event queue @ 2425392965000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2423763683000.  Starting simulation...
+info: Entering event queue @ 2426392965000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2423763816000.  Starting simulation...
+info: Entering event queue @ 2426393102000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2424763816000.  Starting simulation...
+info: Entering event queue @ 2427393102000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2424763896000.  Starting simulation...
+info: Entering event queue @ 2427396556000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2425763896000.  Starting simulation...
+info: Entering event queue @ 2428396556000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2425764024500.  Starting simulation...
+info: Entering event queue @ 2428396645000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2426764024500.  Starting simulation...
+info: Entering event queue @ 2429396645000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2426764049000.  Starting simulation...
+info: Entering event queue @ 2429396754000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2427764049000.  Starting simulation...
+info: Entering event queue @ 2430396754000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2427764185000.  Starting simulation...
+info: Entering event queue @ 2430403859000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2428764185000.  Starting simulation...
+info: Entering event queue @ 2431403859000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2428770274000.  Starting simulation...
+info: Entering event queue @ 2431403964000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2429770274000.  Starting simulation...
+info: Entering event queue @ 2432403964000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2429770406000.  Starting simulation...
+info: Entering event queue @ 2432404100500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2430770406000.  Starting simulation...
+info: Entering event queue @ 2433404100500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2430770512000.  Starting simulation...
+info: Entering event queue @ 2433404250000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2431770512000.  Starting simulation...
+info: Entering event queue @ 2434404250000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2431770631000.  Starting simulation...
+info: Entering event queue @ 2434410611000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2432770631000.  Starting simulation...
+info: Entering event queue @ 2435410611000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2432770756000.  Starting simulation...
+info: Entering event queue @ 2435410707000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2433770756000.  Starting simulation...
+info: Entering event queue @ 2436410707000.  Starting simulation...
+info: Entering event queue @ 2438094729250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2433771542000.  Starting simulation...
+info: Entering event queue @ 2438094732000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2434771542000.  Starting simulation...
+info: Entering event queue @ 2439094732000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2434771640000.  Starting simulation...
+info: Entering event queue @ 2439094850000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2435771640000.  Starting simulation...
+info: Entering event queue @ 2440094850000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2435771648000.  Starting simulation...
+info: Entering event queue @ 2440094895000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2436771648000.  Starting simulation...
-info: Entering event queue @ 2437490134000.  Starting simulation...
+info: Entering event queue @ 2441094895000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2437490136000.  Starting simulation...
+info: Entering event queue @ 2441099330000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2438490136000.  Starting simulation...
+info: Entering event queue @ 2442099330000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2438490158000.  Starting simulation...
+info: Entering event queue @ 2442099486000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2439490158000.  Starting simulation...
+info: Entering event queue @ 2443099486000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2439490217000.  Starting simulation...
+info: Entering event queue @ 2443099600500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2440490217000.  Starting simulation...
+info: Entering event queue @ 2444099600500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2440490335500.  Starting simulation...
+info: Entering event queue @ 2444106551000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2441490335500.  Starting simulation...
+info: Entering event queue @ 2445106551000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2441490449000.  Starting simulation...
+info: Entering event queue @ 2445106624000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2442490449000.  Starting simulation...
+info: Entering event queue @ 2446106624000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2442490551000.  Starting simulation...
+info: Entering event queue @ 2446106663000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2443490551000.  Starting simulation...
+info: Entering event queue @ 2447106663000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2443490670000.  Starting simulation...
+info: Entering event queue @ 2447106677500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2444490670000.  Starting simulation...
+info: Entering event queue @ 2448106677500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2444490744000.  Starting simulation...
+info: Entering event queue @ 2448106732000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2445490744000.  Starting simulation...
+info: Entering event queue @ 2449106732000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2445499008000.  Starting simulation...
+info: Entering event queue @ 2449106788500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2446499008000.  Starting simulation...
+info: Entering event queue @ 2450106788500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2446499143000.  Starting simulation...
+info: Entering event queue @ 2450106864000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2447499143000.  Starting simulation...
+info: Entering event queue @ 2451106864000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2447499251000.  Starting simulation...
+info: Entering event queue @ 2451106954500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2448499251000.  Starting simulation...
+info: Entering event queue @ 2452106954500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2448501472000.  Starting simulation...
+info: Entering event queue @ 2452107027000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2449501472000.  Starting simulation...
+info: Entering event queue @ 2453107027000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2449501552000.  Starting simulation...
+info: Entering event queue @ 2453107165000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2450501552000.  Starting simulation...
+info: Entering event queue @ 2454107165000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2450501708000.  Starting simulation...
+info: Entering event queue @ 2454112628000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2451501708000.  Starting simulation...
+info: Entering event queue @ 2455112628000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2451501752500.  Starting simulation...
+info: Entering event queue @ 2455112711000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2452501752500.  Starting simulation...
+info: Entering event queue @ 2456112711000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2452501854000.  Starting simulation...
+info: Entering event queue @ 2456112857000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2453501854000.  Starting simulation...
+info: Entering event queue @ 2457112857000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2453501960000.  Starting simulation...
+info: Entering event queue @ 2457112869000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2454501960000.  Starting simulation...
+info: Entering event queue @ 2458112869000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2454502105000.  Starting simulation...
+info: Entering event queue @ 2458113021000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2455502105000.  Starting simulation...
+info: Entering event queue @ 2459113021000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2455502233000.  Starting simulation...
+info: Entering event queue @ 2459113070000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2456502233000.  Starting simulation...
+info: Entering event queue @ 2460113070000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2456502345000.  Starting simulation...
+info: Entering event queue @ 2460113176000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2457502345000.  Starting simulation...
+info: Entering event queue @ 2461113176000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2457502439000.  Starting simulation...
+info: Entering event queue @ 2461114992000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2458502439000.  Starting simulation...
+info: Entering event queue @ 2462114992000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2458502524000.  Starting simulation...
+info: Entering event queue @ 2462115142000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2459502524000.  Starting simulation...
+info: Entering event queue @ 2463115142000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2459502597500.  Starting simulation...
+info: Entering event queue @ 2463115302000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2460502597500.  Starting simulation...
+info: Entering event queue @ 2464115302000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2460502627000.  Starting simulation...
+info: Entering event queue @ 2464122382000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2461502627000.  Starting simulation...
+info: Entering event queue @ 2465122382000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2461502675000.  Starting simulation...
+info: Entering event queue @ 2465122453000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2462502675000.  Starting simulation...
+info: Entering event queue @ 2466122453000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2462502774500.  Starting simulation...
+info: Entering event queue @ 2466122567000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2463502774500.  Starting simulation...
+info: Entering event queue @ 2467122567000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2463502818000.  Starting simulation...
+info: Entering event queue @ 2467122667000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2464502818000.  Starting simulation...
+info: Entering event queue @ 2468122667000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2464502945000.  Starting simulation...
+info: Entering event queue @ 2468122726000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2465502945000.  Starting simulation...
+info: Entering event queue @ 2469122726000.  Starting simulation...
+info: Entering event queue @ 2470831329250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2465511849000.  Starting simulation...
+info: Entering event queue @ 2470831332000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2466511849000.  Starting simulation...
+info: Entering event queue @ 2471831332000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2466511856500.  Starting simulation...
+info: Entering event queue @ 2471831399000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2467511856500.  Starting simulation...
+info: Entering event queue @ 2472831399000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2467512001000.  Starting simulation...
+info: Entering event queue @ 2472831434000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2468512001000.  Starting simulation...
+info: Entering event queue @ 2473831434000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2468512063000.  Starting simulation...
+info: Entering event queue @ 2473831443000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2469512063000.  Starting simulation...
-info: Entering event queue @ 2470225739000.  Starting simulation...
+info: Entering event queue @ 2474831443000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2470225741000.  Starting simulation...
+info: Entering event queue @ 2474831496500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2471225741000.  Starting simulation...
+info: Entering event queue @ 2475831496500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2471226221500.  Starting simulation...
+info: Entering event queue @ 2475831610000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2472226221500.  Starting simulation...
+info: Entering event queue @ 2476831610000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2472226357000.  Starting simulation...
+info: Entering event queue @ 2476831728000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2473226357000.  Starting simulation...
+info: Entering event queue @ 2477831728000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2473226411000.  Starting simulation...
+info: Entering event queue @ 2477831824000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2474226411000.  Starting simulation...
+info: Entering event queue @ 2478831824000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2474226515000.  Starting simulation...
+info: Entering event queue @ 2478833712000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2475226515000.  Starting simulation...
+info: Entering event queue @ 2479833712000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2475226537000.  Starting simulation...
+info: Entering event queue @ 2479833747000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2476226537000.  Starting simulation...
+info: Entering event queue @ 2480833747000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2476226570000.  Starting simulation...
+info: Entering event queue @ 2480833839000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2477226570000.  Starting simulation...
+info: Entering event queue @ 2481833839000.  Starting simulation...
+info: Entering event queue @ 2481835884000.  Starting simulation...
+info: Entering event queue @ 2481835889000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2477230887000.  Starting simulation...
+info: Entering event queue @ 2481835893500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2478230887000.  Starting simulation...
-info: Entering event queue @ 2478231272000.  Starting simulation...
+info: Entering event queue @ 2482835893500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2478231279500.  Starting simulation...
+info: Entering event queue @ 2482837674000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2479231279500.  Starting simulation...
+info: Entering event queue @ 2483837674000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2479231321000.  Starting simulation...
+info: Entering event queue @ 2483837738000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2480231321000.  Starting simulation...
+info: Entering event queue @ 2484837738000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2480231467000.  Starting simulation...
+info: Entering event queue @ 2484841149000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2481231467000.  Starting simulation...
+info: Entering event queue @ 2485841149000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2481237971000.  Starting simulation...
+info: Entering event queue @ 2485841199000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2482237971000.  Starting simulation...
+info: Entering event queue @ 2486841199000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2482238135000.  Starting simulation...
+info: Entering event queue @ 2486841323500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2483238135000.  Starting simulation...
+info: Entering event queue @ 2487841323500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2483238269000.  Starting simulation...
+info: Entering event queue @ 2487841419000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2484238269000.  Starting simulation...
+info: Entering event queue @ 2488841419000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2484238311000.  Starting simulation...
+info: Entering event queue @ 2488841557500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2485238311000.  Starting simulation...
+info: Entering event queue @ 2489841557500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2485238411000.  Starting simulation...
+info: Entering event queue @ 2489841714000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2486238411000.  Starting simulation...
+info: Entering event queue @ 2490841714000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2486238487000.  Starting simulation...
+info: Entering event queue @ 2490841815000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2487238487000.  Starting simulation...
+info: Entering event queue @ 2491841815000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2487239689000.  Starting simulation...
+info: Entering event queue @ 2491846012000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2488239689000.  Starting simulation...
+info: Entering event queue @ 2492846012000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2488239724000.  Starting simulation...
+info: Entering event queue @ 2492846092000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2489239724000.  Starting simulation...
+info: Entering event queue @ 2493846092000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2489244495500.  Starting simulation...
+info: Entering event queue @ 2493846192000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2490244495500.  Starting simulation...
-info: Entering event queue @ 2490244503000.  Starting simulation...
+info: Entering event queue @ 2494846192000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2490244507500.  Starting simulation...
+info: Entering event queue @ 2494846274000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2491244507500.  Starting simulation...
+info: Entering event queue @ 2495846274000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2491244516000.  Starting simulation...
+info: Entering event queue @ 2495846428000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2492244516000.  Starting simulation...
+info: Entering event queue @ 2496846428000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2492244536000.  Starting simulation...
+info: Entering event queue @ 2496846578500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2493244536000.  Starting simulation...
+info: Entering event queue @ 2497846578500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2493251837000.  Starting simulation...
+info: Entering event queue @ 2497846655000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2494251837000.  Starting simulation...
+info: Entering event queue @ 2498846655000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2494251954000.  Starting simulation...
+info: Entering event queue @ 2498846726000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2495251954000.  Starting simulation...
+info: Entering event queue @ 2499846726000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2495252012000.  Starting simulation...
+info: Entering event queue @ 2499846861000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2496252012000.  Starting simulation...
+info: Entering event queue @ 2500846861000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2496255849000.  Starting simulation...
+info: Entering event queue @ 2500851435000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2497255849000.  Starting simulation...
+info: Entering event queue @ 2501851435000.  Starting simulation...
+info: Entering event queue @ 2503567610250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2497255860000.  Starting simulation...
+info: Entering event queue @ 2503567613000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2498255860000.  Starting simulation...
+info: Entering event queue @ 2504567613000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2498256024000.  Starting simulation...
+info: Entering event queue @ 2504567726000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2499256024000.  Starting simulation...
+info: Entering event queue @ 2505567726000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2499256176000.  Starting simulation...
+info: Entering event queue @ 2505574981000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2500256176000.  Starting simulation...
+info: Entering event queue @ 2506574981000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2500256276000.  Starting simulation...
+info: Entering event queue @ 2506575012000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2501256276000.  Starting simulation...
-info: Entering event queue @ 2502962318000.  Starting simulation...
+info: Entering event queue @ 2507575012000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2502962320000.  Starting simulation...
+info: Entering event queue @ 2507575052000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2503962320000.  Starting simulation...
+info: Entering event queue @ 2508575052000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2503962362000.  Starting simulation...
+info: Entering event queue @ 2508575160000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2504962362000.  Starting simulation...
+info: Entering event queue @ 2509575160000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2504962512000.  Starting simulation...
+info: Entering event queue @ 2509575287000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2505962512000.  Starting simulation...
-info: Entering event queue @ 2505962525000.  Starting simulation...
-info: Entering event queue @ 2505962534000.  Starting simulation...
-info: Entering event queue @ 2505962538500.  Starting simulation...
+info: Entering event queue @ 2510575287000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2505962539500.  Starting simulation...
+info: Entering event queue @ 2510575294500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2506962539500.  Starting simulation...
+info: Entering event queue @ 2511575294500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2506962568500.  Starting simulation...
+info: Entering event queue @ 2511575312000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2507962568500.  Starting simulation...
+info: Entering event queue @ 2512575312000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2507970193000.  Starting simulation...
+info: Entering event queue @ 2512575405000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2508970193000.  Starting simulation...
+info: Entering event queue @ 2513575405000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2508970326000.  Starting simulation...
+info: Entering event queue @ 2513575444000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2509970326000.  Starting simulation...
+info: Entering event queue @ 2514575444000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2509970419000.  Starting simulation...
+info: Entering event queue @ 2514575602000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2510970419000.  Starting simulation...
+info: Entering event queue @ 2515575602000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2510970429000.  Starting simulation...
+info: Entering event queue @ 2515575628500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2511970429000.  Starting simulation...
+info: Entering event queue @ 2516575628500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2511974054000.  Starting simulation...
+info: Entering event queue @ 2516575659000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2512974054000.  Starting simulation...
+info: Entering event queue @ 2517575659000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2512974121500.  Starting simulation...
+info: Entering event queue @ 2517575698000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2513974121500.  Starting simulation...
+info: Entering event queue @ 2518575698000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2513974129000.  Starting simulation...
+info: Entering event queue @ 2518577085000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2514974129000.  Starting simulation...
+info: Entering event queue @ 2519577085000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2514975356000.  Starting simulation...
+info: Entering event queue @ 2519577132000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2515975356000.  Starting simulation...
+info: Entering event queue @ 2520577132000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2515975454000.  Starting simulation...
+info: Entering event queue @ 2520577256500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2516975454000.  Starting simulation...
+info: Entering event queue @ 2521577256500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2516975552000.  Starting simulation...
+info: Entering event queue @ 2521584198000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2517975552000.  Starting simulation...
+info: Entering event queue @ 2522584198000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2517982622000.  Starting simulation...
+info: Entering event queue @ 2522584259000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2518982622000.  Starting simulation...
+info: Entering event queue @ 2523584259000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2518982687000.  Starting simulation...
+info: Entering event queue @ 2523584372000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2519982687000.  Starting simulation...
+info: Entering event queue @ 2524584372000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2519982786000.  Starting simulation...
+info: Entering event queue @ 2524584455500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2520982786000.  Starting simulation...
-info: Entering event queue @ 2520988988500.  Starting simulation...
-info: Entering event queue @ 2520988994500.  Starting simulation...
+info: Entering event queue @ 2525584455500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2520988999000.  Starting simulation...
+info: Entering event queue @ 2525591164000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2521988999000.  Starting simulation...
+info: Entering event queue @ 2526591164000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2521989071000.  Starting simulation...
+info: Entering event queue @ 2526591230000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2522989071000.  Starting simulation...
+info: Entering event queue @ 2527591230000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2522989085500.  Starting simulation...
+info: Entering event queue @ 2527591238000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2523989085500.  Starting simulation...
+info: Entering event queue @ 2528591238000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2523989143000.  Starting simulation...
+info: Entering event queue @ 2528597259000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2524989143000.  Starting simulation...
+info: Entering event queue @ 2529597259000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2524989219000.  Starting simulation...
+info: Entering event queue @ 2529597411000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2525989219000.  Starting simulation...
+info: Entering event queue @ 2530597411000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2525998131000.  Starting simulation...
+info: Entering event queue @ 2530597561500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2526998131000.  Starting simulation...
+info: Entering event queue @ 2531597561500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2527002132000.  Starting simulation...
+info: Entering event queue @ 2531597646000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2528002132000.  Starting simulation...
+info: Entering event queue @ 2532597646000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2528002139500.  Starting simulation...
+info: Entering event queue @ 2532597765000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2529002139500.  Starting simulation...
+info: Entering event queue @ 2533597765000.  Starting simulation...
+info: Entering event queue @ 2533597774500.  Starting simulation...
+info: Entering event queue @ 2533597779000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2529002278000.  Starting simulation...
+info: Entering event queue @ 2533597780000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2530002278000.  Starting simulation...
-info: Entering event queue @ 2530002328000.  Starting simulation...
+info: Entering event queue @ 2534597780000.  Starting simulation...
+info: Entering event queue @ 2536303549250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2530002335500.  Starting simulation...
+info: Entering event queue @ 2536303552000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2531002335500.  Starting simulation...
+info: Entering event queue @ 2537303552000.  Starting simulation...
+info: Entering event queue @ 2537303556000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2531002354000.  Starting simulation...
+info: Entering event queue @ 2537303560500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2532002354000.  Starting simulation...
+info: Entering event queue @ 2538303560500.  Starting simulation...
+info: Entering event queue @ 2538303568500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2532006673000.  Starting simulation...
+info: Entering event queue @ 2538303573000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2533006673000.  Starting simulation...
+info: Entering event queue @ 2539303573000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2533015860500.  Starting simulation...
+info: Entering event queue @ 2539303580500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2534015860500.  Starting simulation...
-info: Entering event queue @ 2535698918000.  Starting simulation...
+info: Entering event queue @ 2540303580500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2535698920000.  Starting simulation...
+info: Entering event queue @ 2540303606000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2536698920000.  Starting simulation...
+info: Entering event queue @ 2541303606000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2536698927500.  Starting simulation...
+info: Entering event queue @ 2541303613500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2537698927500.  Starting simulation...
+info: Entering event queue @ 2542303613500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2537698997000.  Starting simulation...
+info: Entering event queue @ 2542303621000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2538698997000.  Starting simulation...
-info: Entering event queue @ 2538699007500.  Starting simulation...
-info: Entering event queue @ 2538699018000.  Starting simulation...
+info: Entering event queue @ 2543303621000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2538699018500.  Starting simulation...
+info: Entering event queue @ 2543303628500.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2539699018500.  Starting simulation...
-info: Entering event queue @ 2539704793500.  Starting simulation...
-info: Entering event queue @ 2539704800000.  Starting simulation...
+info: Entering event queue @ 2544303628500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2539704804500.  Starting simulation...
+info: Entering event queue @ 2544303636000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2540704804500.  Starting simulation...
+info: Entering event queue @ 2545303636000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2540704925000.  Starting simulation...
+info: Entering event queue @ 2545303749000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2541704925000.  Starting simulation...
-info: Entering event queue @ 2541705319000.  Starting simulation...
+info: Entering event queue @ 2546303749000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2541705326500.  Starting simulation...
+info: Entering event queue @ 2546303779000.  Starting simulation...
 Switching CPUs...
 Next CPU: DerivO3CPU
-info: Entering event queue @ 2542705326500.  Starting simulation...
+info: Entering event queue @ 2547303779000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2542705334000.  Starting simulation...
+info: Entering event queue @ 2547303786500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2548303786500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2548303794000.  Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal
index f6a311dd6..973d0288c 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-o3/system.terminal
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
index 0095c8976..78712e3a3 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/config.ini
@@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
@@ -24,7 +25,7 @@ load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
 mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -70,12 +71,16 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -103,10 +108,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -117,12 +122,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=ArmTLB
 children=walker
@@ -131,17 +145,17 @@ walker=system.cpu0.dtb.walker
 
 [system.cpu0.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -152,12 +166,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=ArmInterrupts
 
@@ -186,7 +209,7 @@ walker=system.cpu0.itb.walker
 
 [system.cpu0.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[2]
@@ -196,10 +219,9 @@ type=ExeTracer
 
 [system.cpu1]
 type=TimingSimpleCPU
-children=dtb interrupts isa itb tracer
-branchPred=Null
+children=dtb isa itb tracer
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -207,7 +229,7 @@ do_statistics_insts=true
 dtb=system.cpu1.dtb
 function_trace=false
 function_trace_start=0
-interrupts=system.cpu1.interrupts
+interrupts=Null
 isa=system.cpu1.isa
 itb=system.cpu1.itb
 max_insts_all_threads=0
@@ -231,13 +253,10 @@ walker=system.cpu1.dtb.walker
 
 [system.cpu1.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
-[system.cpu1.interrupts]
-type=ArmInterrupts
-
 [system.cpu1.isa]
 type=ArmISA
 fpsid=1090793632
@@ -263,21 +282,25 @@ walker=system.cpu1.itb.walker
 
 [system.cpu1.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
 [system.cpu1.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -286,10 +309,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -300,18 +323,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -322,28 +354,36 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -361,19 +401,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -384,8 +429,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -398,16 +442,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -454,7 +498,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -472,7 +516,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -486,7 +530,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -495,7 +539,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -512,7 +556,7 @@ pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
-clock=1000
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -521,12 +565,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -536,7 +580,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -546,7 +590,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -556,7 +600,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -570,7 +614,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -583,7 +627,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -596,23 +640,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -622,19 +666,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -646,7 +689,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -659,7 +702,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -669,7 +712,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -679,7 +722,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -689,7 +732,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -699,7 +742,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -713,7 +756,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -726,7 +769,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -741,7 +784,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -751,7 +794,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -761,7 +804,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -771,7 +814,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -787,8 +830,7 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -802,3 +844,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
index c5c33b0cf..e2fadf975 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simerr
@@ -31,3 +31,5 @@ warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
 warn: User mode does not have SPSR
+warn: User mode does not have SPSR
+warn: User mode does not have SPSR
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
index bcd78ce1e..6d8b9163b 100755
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/simout
@@ -3,10763 +3,10534 @@ Redirecting stderr to build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realvi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 02:56:16
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:46:41
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 info: Entering event queue @ 1000000000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1000020000.  Starting simulation...
+info: Entering event queue @ 1000007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2000020000.  Starting simulation...
+info: Entering event queue @ 2000007500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2000027500.  Starting simulation...
+info: Entering event queue @ 2000015000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 3000027500.  Starting simulation...
+info: Entering event queue @ 3000015000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 3000051500.  Starting simulation...
+info: Entering event queue @ 3000081000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 4000051500.  Starting simulation...
+info: Entering event queue @ 4000081000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 4000072500.  Starting simulation...
+info: Entering event queue @ 4000151000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 5000072500.  Starting simulation...
+info: Entering event queue @ 5000151000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 5000073000.  Starting simulation...
+info: Entering event queue @ 5000197000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 6000073000.  Starting simulation...
+info: Entering event queue @ 6000197000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 6000074000.  Starting simulation...
+info: Entering event queue @ 6000198000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 7000074000.  Starting simulation...
+info: Entering event queue @ 7000198000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 7000075000.  Starting simulation...
+info: Entering event queue @ 7000198500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 8000075000.  Starting simulation...
+info: Entering event queue @ 8000198500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 8000075500.  Starting simulation...
+info: Entering event queue @ 8000199000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 9000075500.  Starting simulation...
+info: Entering event queue @ 9000199000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 9000211000.  Starting simulation...
+info: Entering event queue @ 9000200000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 10000211000.  Starting simulation...
+info: Entering event queue @ 10000200000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 10000212000.  Starting simulation...
+info: Entering event queue @ 10000269500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 11000212000.  Starting simulation...
+info: Entering event queue @ 11000269500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 11000212500.  Starting simulation...
+info: Entering event queue @ 11000272000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 12000212500.  Starting simulation...
+info: Entering event queue @ 12000272000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 12000213500.  Starting simulation...
+info: Entering event queue @ 12000273000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 13000213500.  Starting simulation...
+info: Entering event queue @ 13000273000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 13000214500.  Starting simulation...
+info: Entering event queue @ 13000274000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 14000214500.  Starting simulation...
-info: Entering event queue @ 14000227000.  Starting simulation...
+info: Entering event queue @ 14000274000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 14000228500.  Starting simulation...
+info: Entering event queue @ 14000275000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 15000228500.  Starting simulation...
+info: Entering event queue @ 15000275000.  Starting simulation...
+info: Entering event queue @ 15000288500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 15000236000.  Starting simulation...
+info: Entering event queue @ 15000290000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 16000236000.  Starting simulation...
-info: Entering event queue @ 16000253000.  Starting simulation...
+info: Entering event queue @ 16000290000.  Starting simulation...
+info: Entering event queue @ 16000302500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 16000256500.  Starting simulation...
+info: Entering event queue @ 16000306000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 17000256500.  Starting simulation...
+info: Entering event queue @ 17000306000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 17000257000.  Starting simulation...
+info: Entering event queue @ 17000313500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 18000257000.  Starting simulation...
+info: Entering event queue @ 18000313500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 18000264500.  Starting simulation...
+info: Entering event queue @ 18000314500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 19000264500.  Starting simulation...
-info: Entering event queue @ 19000274500.  Starting simulation...
+info: Entering event queue @ 19000314500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 19000277000.  Starting simulation...
+info: Entering event queue @ 19000322000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 20000277000.  Starting simulation...
+info: Entering event queue @ 20000322000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 20000284500.  Starting simulation...
+info: Entering event queue @ 20000329500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 21000284500.  Starting simulation...
+info: Entering event queue @ 21000329500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 21000285500.  Starting simulation...
+info: Entering event queue @ 21000337000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 22000285500.  Starting simulation...
+info: Entering event queue @ 22000337000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 22000293000.  Starting simulation...
+info: Entering event queue @ 22000344500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 23000293000.  Starting simulation...
-info: Entering event queue @ 23000303000.  Starting simulation...
+info: Entering event queue @ 23000344500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 23000304500.  Starting simulation...
+info: Entering event queue @ 23000395000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 24000304500.  Starting simulation...
+info: Entering event queue @ 24000395000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 24000312000.  Starting simulation...
+info: Entering event queue @ 24000402500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 25000312000.  Starting simulation...
+info: Entering event queue @ 25000402500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 25000319500.  Starting simulation...
+info: Entering event queue @ 25000410000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 26000319500.  Starting simulation...
+info: Entering event queue @ 26000410000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 26000327000.  Starting simulation...
+info: Entering event queue @ 26000417500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 27000327000.  Starting simulation...
+info: Entering event queue @ 27000417500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 27000334500.  Starting simulation...
+info: Entering event queue @ 27000425000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 28000334500.  Starting simulation...
+info: Entering event queue @ 28000425000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 28000342000.  Starting simulation...
+info: Entering event queue @ 28000432500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 29000342000.  Starting simulation...
-info: Entering event queue @ 29000349500.  Starting simulation...
+info: Entering event queue @ 29000432500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 29000351500.  Starting simulation...
+info: Entering event queue @ 29000440000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 30000351500.  Starting simulation...
+info: Entering event queue @ 30000440000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 30000359000.  Starting simulation...
+info: Entering event queue @ 30000447500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 31000359000.  Starting simulation...
+info: Entering event queue @ 31000447500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 31000366500.  Starting simulation...
+info: Entering event queue @ 31000455000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 32000366500.  Starting simulation...
+info: Entering event queue @ 32000455000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 32000374000.  Starting simulation...
+info: Entering event queue @ 32000462500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 33000374000.  Starting simulation...
+info: Entering event queue @ 33000462500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 33000406500.  Starting simulation...
+info: Entering event queue @ 33000470000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 34000406500.  Starting simulation...
+info: Entering event queue @ 34000470000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 34000414000.  Starting simulation...
+info: Entering event queue @ 34000694000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 35000414000.  Starting simulation...
-info: Entering event queue @ 35000437500.  Starting simulation...
+info: Entering event queue @ 35000694000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 35000654750.  Starting simulation...
+info: Entering event queue @ 35000701500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 36000654750.  Starting simulation...
+info: Entering event queue @ 36000701500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 36000663500.  Starting simulation...
+info: Entering event queue @ 36000709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 37000663500.  Starting simulation...
+info: Entering event queue @ 37000709000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 37000671000.  Starting simulation...
+info: Entering event queue @ 37000716500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 38000671000.  Starting simulation...
+info: Entering event queue @ 38000716500.  Starting simulation...
+info: Entering event queue @ 38000736000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 38000678500.  Starting simulation...
+info: Entering event queue @ 38000832750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 39000832750.  Starting simulation...
 switching cpus
-info: Entering event queue @ 39000678500.  Starting simulation...
+info: Entering event queue @ 39000840250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 40000840250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 40000678500.  Starting simulation...
+info: Entering event queue @ 40000847750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 41000678500.  Starting simulation...
+info: Entering event queue @ 41000847750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 42000678500.  Starting simulation...
+info: Entering event queue @ 42000847750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 43000678500.  Starting simulation...
+info: Entering event queue @ 43000847750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 44000678500.  Starting simulation...
+info: Entering event queue @ 44000847750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 45000678500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 45000686000.  Starting simulation...
+info: Entering event queue @ 45000847750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 46000847750.  Starting simulation...
 switching cpus
-info: Entering event queue @ 46000686000.  Starting simulation...
+info: Entering event queue @ 46000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 47000686000.  Starting simulation...
+info: Entering event queue @ 47000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 48000686000.  Starting simulation...
+info: Entering event queue @ 48000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 49000686000.  Starting simulation...
+info: Entering event queue @ 49000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 50000686000.  Starting simulation...
+info: Entering event queue @ 50000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 51000686000.  Starting simulation...
+info: Entering event queue @ 51000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 52000686000.  Starting simulation...
+info: Entering event queue @ 52000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 53000686000.  Starting simulation...
+info: Entering event queue @ 53000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 54000686000.  Starting simulation...
+info: Entering event queue @ 54000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 55000686000.  Starting simulation...
+info: Entering event queue @ 55000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 56000686000.  Starting simulation...
+info: Entering event queue @ 56000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 57000686000.  Starting simulation...
+info: Entering event queue @ 57000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 58000686000.  Starting simulation...
+info: Entering event queue @ 58000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 59000686000.  Starting simulation...
+info: Entering event queue @ 59000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 60000686000.  Starting simulation...
+info: Entering event queue @ 60000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 61000686000.  Starting simulation...
+info: Entering event queue @ 61000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 62000686000.  Starting simulation...
+info: Entering event queue @ 62000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 63000686000.  Starting simulation...
+info: Entering event queue @ 63000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 64000686000.  Starting simulation...
+info: Entering event queue @ 64000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 65000686000.  Starting simulation...
-info: Entering event queue @ 66499718000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 66499720000.  Starting simulation...
+info: Entering event queue @ 65000855250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 67499720000.  Starting simulation...
+info: Entering event queue @ 66000855250.  Starting simulation...
+info: Entering event queue @ 67631497250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 67499727500.  Starting simulation...
+info: Entering event queue @ 67631500000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 68499727500.  Starting simulation...
+info: Entering event queue @ 68631500000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 68499737500.  Starting simulation...
+info: Entering event queue @ 68631519500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 69499737500.  Starting simulation...
+info: Entering event queue @ 69631519500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 69499745000.  Starting simulation...
+info: Entering event queue @ 69631527000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 70499745000.  Starting simulation...
+info: Entering event queue @ 70631527000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 70499751500.  Starting simulation...
+info: Entering event queue @ 70631534500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 71499751500.  Starting simulation...
-info: Entering event queue @ 71499768500.  Starting simulation...
+info: Entering event queue @ 71631534500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 71499859000.  Starting simulation...
+info: Entering event queue @ 71631554500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 72499859000.  Starting simulation...
-info: Entering event queue @ 72499881500.  Starting simulation...
+info: Entering event queue @ 72631554500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 72499991500.  Starting simulation...
+info: Entering event queue @ 72631563500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 73499991500.  Starting simulation...
+info: Entering event queue @ 73631563500.  Starting simulation...
+info: Entering event queue @ 73631597500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 73500001500.  Starting simulation...
+info: Entering event queue @ 73631689750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 74500001500.  Starting simulation...
-info: Entering event queue @ 74500025500.  Starting simulation...
+info: Entering event queue @ 74631689750.  Starting simulation...
 switching cpus
-info: Entering event queue @ 74500109000.  Starting simulation...
+info: Entering event queue @ 74631697250.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 75500109000.  Starting simulation...
+info: Entering event queue @ 75631697250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 75500119500.  Starting simulation...
+info: Entering event queue @ 75631727500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 76500119500.  Starting simulation...
+info: Entering event queue @ 76631727500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 76500120500.  Starting simulation...
+info: Entering event queue @ 76631736500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 77500120500.  Starting simulation...
+info: Entering event queue @ 77631736500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 77500128000.  Starting simulation...
+info: Entering event queue @ 77631744000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 78500128000.  Starting simulation...
+info: Entering event queue @ 78631744000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 78500135500.  Starting simulation...
+info: Entering event queue @ 78631751500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 79500135500.  Starting simulation...
+info: Entering event queue @ 79631751500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 79500143000.  Starting simulation...
+info: Entering event queue @ 79631773500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 80500143000.  Starting simulation...
+info: Entering event queue @ 80631773500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 80500143500.  Starting simulation...
+info: Entering event queue @ 80631802500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 81500143500.  Starting simulation...
+info: Entering event queue @ 81631802500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 81500151000.  Starting simulation...
+info: Entering event queue @ 81631810000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 82500151000.  Starting simulation...
+info: Entering event queue @ 82631810000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 82500158500.  Starting simulation...
+info: Entering event queue @ 82631817500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 83500158500.  Starting simulation...
+info: Entering event queue @ 83631817500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 83500166000.  Starting simulation...
+info: Entering event queue @ 83631834500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 84500166000.  Starting simulation...
+info: Entering event queue @ 84631834500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 84500180500.  Starting simulation...
+info: Entering event queue @ 84631842000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 85500180500.  Starting simulation...
+info: Entering event queue @ 85631842000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 85500229000.  Starting simulation...
+info: Entering event queue @ 85631849500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 86500229000.  Starting simulation...
+info: Entering event queue @ 86631849500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 86500236500.  Starting simulation...
+info: Entering event queue @ 86631857000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 87500236500.  Starting simulation...
+info: Entering event queue @ 87631857000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 87500244000.  Starting simulation...
+info: Entering event queue @ 87631864500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 88500244000.  Starting simulation...
+info: Entering event queue @ 88631864500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 88500251500.  Starting simulation...
+info: Entering event queue @ 88631872000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 89500251500.  Starting simulation...
+info: Entering event queue @ 89631872000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 89500259000.  Starting simulation...
+info: Entering event queue @ 89631879500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 90500259000.  Starting simulation...
+info: Entering event queue @ 90631879500.  Starting simulation...
+info: Entering event queue @ 90631913500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 90500266500.  Starting simulation...
+info: Entering event queue @ 90631921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 91500266500.  Starting simulation...
+info: Entering event queue @ 91631921000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 91500274000.  Starting simulation...
+info: Entering event queue @ 91631938500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 92500274000.  Starting simulation...
+info: Entering event queue @ 92631938500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 92500281500.  Starting simulation...
+info: Entering event queue @ 92631957500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 93500281500.  Starting simulation...
+info: Entering event queue @ 93631957500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 93500292500.  Starting simulation...
+info: Entering event queue @ 93631965000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 94500292500.  Starting simulation...
-info: Entering event queue @ 94500313500.  Starting simulation...
+info: Entering event queue @ 94631965000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 94500420000.  Starting simulation...
+info: Entering event queue @ 94631983500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 95500420000.  Starting simulation...
+info: Entering event queue @ 95631983500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 95500427500.  Starting simulation...
+info: Entering event queue @ 95632005500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 96500427500.  Starting simulation...
+info: Entering event queue @ 96632005500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 96500441500.  Starting simulation...
+info: Entering event queue @ 96632013000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 97500441500.  Starting simulation...
-info: Entering event queue @ 97500449000.  Starting simulation...
+info: Entering event queue @ 97632013000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 97500450000.  Starting simulation...
+info: Entering event queue @ 97632020500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 98500450000.  Starting simulation...
-info: Entering event queue @ 99219551000.  Starting simulation...
+info: Entering event queue @ 98632020500.  Starting simulation...
+info: Entering event queue @ 100364210250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 99219553000.  Starting simulation...
+info: Entering event queue @ 100364213000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 100219553000.  Starting simulation...
+info: Entering event queue @ 101364213000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 100219553500.  Starting simulation...
+info: Entering event queue @ 101364220500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 101219553500.  Starting simulation...
+info: Entering event queue @ 102364220500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 101219554000.  Starting simulation...
+info: Entering event queue @ 102364228000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 102219554000.  Starting simulation...
+info: Entering event queue @ 103364228000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 102219560000.  Starting simulation...
+info: Entering event queue @ 103364235500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 103219560000.  Starting simulation...
+info: Entering event queue @ 104364235500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 103219562000.  Starting simulation...
+info: Entering event queue @ 104364260500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 104219562000.  Starting simulation...
+info: Entering event queue @ 105364260500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 104219563000.  Starting simulation...
+info: Entering event queue @ 105364274500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 105219563000.  Starting simulation...
+info: Entering event queue @ 106364274500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 105219565000.  Starting simulation...
+info: Entering event queue @ 106364300500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 106219565000.  Starting simulation...
+info: Entering event queue @ 107364300500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 106219567000.  Starting simulation...
+info: Entering event queue @ 107364308000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 107219567000.  Starting simulation...
+info: Entering event queue @ 108364308000.  Starting simulation...
+info: Entering event queue @ 108364322500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 107219568000.  Starting simulation...
+info: Entering event queue @ 108364326000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 108219568000.  Starting simulation...
+info: Entering event queue @ 109364326000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 108219614500.  Starting simulation...
+info: Entering event queue @ 109364326500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 109219614500.  Starting simulation...
+info: Entering event queue @ 110364326500.  Starting simulation...
+info: Entering event queue @ 110364339000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 109219615500.  Starting simulation...
+info: Entering event queue @ 110364342500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 110219615500.  Starting simulation...
-info: Entering event queue @ 110219625000.  Starting simulation...
+info: Entering event queue @ 111364342500.  Starting simulation...
+info: Entering event queue @ 111364349500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 110219627500.  Starting simulation...
+info: Entering event queue @ 111364351000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 111219627500.  Starting simulation...
+info: Entering event queue @ 112364351000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 111219635000.  Starting simulation...
+info: Entering event queue @ 112364355500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 112219635000.  Starting simulation...
+info: Entering event queue @ 113364355500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 112219642500.  Starting simulation...
+info: Entering event queue @ 113364357000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 114364357000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 113219642500.  Starting simulation...
+info: Entering event queue @ 114364358000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 115364358000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 114219642500.  Starting simulation...
+info: Entering event queue @ 115364361500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 116364361500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 115219642500.  Starting simulation...
+info: Entering event queue @ 116364363000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 117364363000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 116219642500.  Starting simulation...
+info: Entering event queue @ 117364363500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 118364363500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 117219642500.  Starting simulation...
+info: Entering event queue @ 118364371000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 119364371000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 118219642500.  Starting simulation...
+info: Entering event queue @ 119364374000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 120364374000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 119219642500.  Starting simulation...
+info: Entering event queue @ 120364381500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 121364381500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 120219642500.  Starting simulation...
+info: Entering event queue @ 121364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 121219642500.  Starting simulation...
+info: Entering event queue @ 122364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 122219642500.  Starting simulation...
+info: Entering event queue @ 123364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 123219642500.  Starting simulation...
+info: Entering event queue @ 124364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 124219642500.  Starting simulation...
+info: Entering event queue @ 125364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 125219642500.  Starting simulation...
+info: Entering event queue @ 126364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 126219642500.  Starting simulation...
+info: Entering event queue @ 127364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 127219642500.  Starting simulation...
+info: Entering event queue @ 128364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 128219642500.  Starting simulation...
+info: Entering event queue @ 129364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 129219642500.  Starting simulation...
+info: Entering event queue @ 130364389000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 131364389000.  Starting simulation...
+info: Entering event queue @ 133099170250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 130219642500.  Starting simulation...
+info: Entering event queue @ 133099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 131219642500.  Starting simulation...
-info: Entering event queue @ 131956130000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 131956132000.  Starting simulation...
+info: Entering event queue @ 134099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 132956132000.  Starting simulation...
+info: Entering event queue @ 135099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 133956132000.  Starting simulation...
+info: Entering event queue @ 136099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 134956132000.  Starting simulation...
+info: Entering event queue @ 137099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 135956132000.  Starting simulation...
+info: Entering event queue @ 138099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 136956132000.  Starting simulation...
+info: Entering event queue @ 139099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 137956132000.  Starting simulation...
+info: Entering event queue @ 140099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 138956132000.  Starting simulation...
+info: Entering event queue @ 141099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 139956132000.  Starting simulation...
+info: Entering event queue @ 142099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 140956132000.  Starting simulation...
+info: Entering event queue @ 143099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 141956132000.  Starting simulation...
+info: Entering event queue @ 144099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 142956132000.  Starting simulation...
+info: Entering event queue @ 145099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 143956132000.  Starting simulation...
+info: Entering event queue @ 146099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 144956132000.  Starting simulation...
+info: Entering event queue @ 147099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 145956132000.  Starting simulation...
+info: Entering event queue @ 148099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 146956132000.  Starting simulation...
+info: Entering event queue @ 149099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 147956132000.  Starting simulation...
+info: Entering event queue @ 150099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 148956132000.  Starting simulation...
+info: Entering event queue @ 151099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 149956132000.  Starting simulation...
+info: Entering event queue @ 152099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 150956132000.  Starting simulation...
+info: Entering event queue @ 153099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 151956132000.  Starting simulation...
+info: Entering event queue @ 154099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 152956132000.  Starting simulation...
+info: Entering event queue @ 155099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 153956132000.  Starting simulation...
+info: Entering event queue @ 156099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 154956132000.  Starting simulation...
+info: Entering event queue @ 157099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 155956132000.  Starting simulation...
+info: Entering event queue @ 158099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 156956132000.  Starting simulation...
+info: Entering event queue @ 159099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 157956132000.  Starting simulation...
+info: Entering event queue @ 160099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 158956132000.  Starting simulation...
+info: Entering event queue @ 161099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 159956132000.  Starting simulation...
+info: Entering event queue @ 162099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 160956132000.  Starting simulation...
+info: Entering event queue @ 163099173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 164099173000.  Starting simulation...
+info: Entering event queue @ 165835457250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 161956132000.  Starting simulation...
+info: Entering event queue @ 165835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 162956132000.  Starting simulation...
+info: Entering event queue @ 166835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 163956132000.  Starting simulation...
-info: Entering event queue @ 164692730000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 164692732000.  Starting simulation...
+info: Entering event queue @ 167835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 165692732000.  Starting simulation...
+info: Entering event queue @ 168835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 166692732000.  Starting simulation...
+info: Entering event queue @ 169835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 167692732000.  Starting simulation...
+info: Entering event queue @ 170835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 168692732000.  Starting simulation...
+info: Entering event queue @ 171835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 169692732000.  Starting simulation...
+info: Entering event queue @ 172835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 170692732000.  Starting simulation...
+info: Entering event queue @ 173835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 171692732000.  Starting simulation...
+info: Entering event queue @ 174835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 172692732000.  Starting simulation...
+info: Entering event queue @ 175835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 173692732000.  Starting simulation...
+info: Entering event queue @ 176835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 174692732000.  Starting simulation...
+info: Entering event queue @ 177835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 175692732000.  Starting simulation...
+info: Entering event queue @ 178835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 176692732000.  Starting simulation...
+info: Entering event queue @ 179835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 177692732000.  Starting simulation...
+info: Entering event queue @ 180835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 178692732000.  Starting simulation...
+info: Entering event queue @ 181835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 179692732000.  Starting simulation...
+info: Entering event queue @ 182835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 180692732000.  Starting simulation...
+info: Entering event queue @ 183835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 181692732000.  Starting simulation...
+info: Entering event queue @ 184835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 182692732000.  Starting simulation...
+info: Entering event queue @ 185835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 183692732000.  Starting simulation...
+info: Entering event queue @ 186835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 184692732000.  Starting simulation...
+info: Entering event queue @ 187835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 185692732000.  Starting simulation...
+info: Entering event queue @ 188835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 186692732000.  Starting simulation...
+info: Entering event queue @ 189835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 187692732000.  Starting simulation...
+info: Entering event queue @ 190835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 188692732000.  Starting simulation...
+info: Entering event queue @ 191835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 189692732000.  Starting simulation...
+info: Entering event queue @ 192835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 190692732000.  Starting simulation...
+info: Entering event queue @ 193835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 191692732000.  Starting simulation...
+info: Entering event queue @ 194835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 192692732000.  Starting simulation...
+info: Entering event queue @ 195835460000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 196835460000.  Starting simulation...
+info: Entering event queue @ 198571738250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 193692732000.  Starting simulation...
+info: Entering event queue @ 198571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 194692732000.  Starting simulation...
+info: Entering event queue @ 199571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 195692732000.  Starting simulation...
+info: Entering event queue @ 200571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 196692732000.  Starting simulation...
-info: Entering event queue @ 197429351000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 197429353000.  Starting simulation...
+info: Entering event queue @ 201571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 198429353000.  Starting simulation...
+info: Entering event queue @ 202571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 199429353000.  Starting simulation...
+info: Entering event queue @ 203571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 200429353000.  Starting simulation...
+info: Entering event queue @ 204571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 201429353000.  Starting simulation...
+info: Entering event queue @ 205571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 202429353000.  Starting simulation...
+info: Entering event queue @ 206571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 203429353000.  Starting simulation...
+info: Entering event queue @ 207571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 204429353000.  Starting simulation...
+info: Entering event queue @ 208571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 205429353000.  Starting simulation...
+info: Entering event queue @ 209571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 206429353000.  Starting simulation...
+info: Entering event queue @ 210571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 207429353000.  Starting simulation...
+info: Entering event queue @ 211571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 208429353000.  Starting simulation...
+info: Entering event queue @ 212571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 209429353000.  Starting simulation...
+info: Entering event queue @ 213571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 210429353000.  Starting simulation...
+info: Entering event queue @ 214571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 211429353000.  Starting simulation...
+info: Entering event queue @ 215571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 212429353000.  Starting simulation...
+info: Entering event queue @ 216571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 213429353000.  Starting simulation...
+info: Entering event queue @ 217571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 214429353000.  Starting simulation...
+info: Entering event queue @ 218571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 215429353000.  Starting simulation...
+info: Entering event queue @ 219571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 216429353000.  Starting simulation...
+info: Entering event queue @ 220571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 217429353000.  Starting simulation...
+info: Entering event queue @ 221571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 218429353000.  Starting simulation...
+info: Entering event queue @ 222571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 219429353000.  Starting simulation...
+info: Entering event queue @ 223571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 220429353000.  Starting simulation...
+info: Entering event queue @ 224571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 221429353000.  Starting simulation...
+info: Entering event queue @ 225571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 222429353000.  Starting simulation...
+info: Entering event queue @ 226571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 223429353000.  Starting simulation...
+info: Entering event queue @ 227571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 224429353000.  Starting simulation...
+info: Entering event queue @ 228571741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 229571741000.  Starting simulation...
+info: Entering event queue @ 231307990250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 225429353000.  Starting simulation...
+info: Entering event queue @ 231307993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 226429353000.  Starting simulation...
+info: Entering event queue @ 232307993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 227429353000.  Starting simulation...
+info: Entering event queue @ 233307993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 228429353000.  Starting simulation...
+info: Entering event queue @ 234307993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 229429353000.  Starting simulation...
-info: Entering event queue @ 230164914000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 230164916000.  Starting simulation...
+info: Entering event queue @ 235307993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 236307993000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 231164916000.  Starting simulation...
+info: Entering event queue @ 236308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 232164916000.  Starting simulation...
+info: Entering event queue @ 237308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 233164916000.  Starting simulation...
+info: Entering event queue @ 238308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 234164916000.  Starting simulation...
+info: Entering event queue @ 239308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 235164916000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 235164923500.  Starting simulation...
+info: Entering event queue @ 240308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 236164923500.  Starting simulation...
+info: Entering event queue @ 241308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 237164923500.  Starting simulation...
+info: Entering event queue @ 242308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 238164923500.  Starting simulation...
+info: Entering event queue @ 243308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 239164923500.  Starting simulation...
+info: Entering event queue @ 244308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 240164923500.  Starting simulation...
+info: Entering event queue @ 245308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 241164923500.  Starting simulation...
+info: Entering event queue @ 246308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 242164923500.  Starting simulation...
+info: Entering event queue @ 247308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 243164923500.  Starting simulation...
+info: Entering event queue @ 248308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 244164923500.  Starting simulation...
+info: Entering event queue @ 249308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 245164923500.  Starting simulation...
+info: Entering event queue @ 250308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 246164923500.  Starting simulation...
+info: Entering event queue @ 251308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 247164923500.  Starting simulation...
+info: Entering event queue @ 252308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 248164923500.  Starting simulation...
+info: Entering event queue @ 253308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 249164923500.  Starting simulation...
+info: Entering event queue @ 254308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 250164923500.  Starting simulation...
+info: Entering event queue @ 255308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 251164923500.  Starting simulation...
+info: Entering event queue @ 256308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 252164923500.  Starting simulation...
+info: Entering event queue @ 257308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 253164923500.  Starting simulation...
+info: Entering event queue @ 258308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 254164923500.  Starting simulation...
+info: Entering event queue @ 259308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 255164923500.  Starting simulation...
+info: Entering event queue @ 260308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 256164923500.  Starting simulation...
+info: Entering event queue @ 261308000500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 262308000500.  Starting simulation...
+info: Entering event queue @ 264044274250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 257164923500.  Starting simulation...
+info: Entering event queue @ 264044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 258164923500.  Starting simulation...
+info: Entering event queue @ 265044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 259164923500.  Starting simulation...
+info: Entering event queue @ 266044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 260164923500.  Starting simulation...
+info: Entering event queue @ 267044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 261164923500.  Starting simulation...
+info: Entering event queue @ 268044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 262164923500.  Starting simulation...
-info: Entering event queue @ 262901514000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 262901516000.  Starting simulation...
+info: Entering event queue @ 269044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 263901516000.  Starting simulation...
+info: Entering event queue @ 270044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 264901516000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 264901593000.  Starting simulation...
+info: Entering event queue @ 271044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 265901593000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 265901798500.  Starting simulation...
+info: Entering event queue @ 272044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 266901798500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 266901833000.  Starting simulation...
+info: Entering event queue @ 273044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 267901833000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 267901840500.  Starting simulation...
+info: Entering event queue @ 274044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 268901840500.  Starting simulation...
+info: Entering event queue @ 275044277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 276044277000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 269901840500.  Starting simulation...
+info: Entering event queue @ 276044278500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 277044278500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 270901840500.  Starting simulation...
+info: Entering event queue @ 277044286000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 278044286000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 271901840500.  Starting simulation...
+info: Entering event queue @ 278044293500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 279044293500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 272901840500.  Starting simulation...
+info: Entering event queue @ 279044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 273901840500.  Starting simulation...
+info: Entering event queue @ 280044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 274901840500.  Starting simulation...
+info: Entering event queue @ 281044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 275901840500.  Starting simulation...
+info: Entering event queue @ 282044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 276901840500.  Starting simulation...
+info: Entering event queue @ 283044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 277901840500.  Starting simulation...
+info: Entering event queue @ 284044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 278901840500.  Starting simulation...
+info: Entering event queue @ 285044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 279901840500.  Starting simulation...
+info: Entering event queue @ 286044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 280901840500.  Starting simulation...
+info: Entering event queue @ 287044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 281901840500.  Starting simulation...
+info: Entering event queue @ 288044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 282901840500.  Starting simulation...
+info: Entering event queue @ 289044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 283901840500.  Starting simulation...
+info: Entering event queue @ 290044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 284901840500.  Starting simulation...
+info: Entering event queue @ 291044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 285901840500.  Starting simulation...
+info: Entering event queue @ 292044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 286901840500.  Starting simulation...
+info: Entering event queue @ 293044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 287901840500.  Starting simulation...
+info: Entering event queue @ 294044301000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 295044301000.  Starting simulation...
+info: Entering event queue @ 296780565250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 288901840500.  Starting simulation...
+info: Entering event queue @ 296780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 289901840500.  Starting simulation...
+info: Entering event queue @ 297780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 290901840500.  Starting simulation...
+info: Entering event queue @ 298780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 291901840500.  Starting simulation...
+info: Entering event queue @ 299780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 292901840500.  Starting simulation...
+info: Entering event queue @ 300780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 293901840500.  Starting simulation...
+info: Entering event queue @ 301780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 294901840500.  Starting simulation...
-info: Entering event queue @ 295638135000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 295638137000.  Starting simulation...
+info: Entering event queue @ 302780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 296638137000.  Starting simulation...
+info: Entering event queue @ 303780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 297638137000.  Starting simulation...
+info: Entering event queue @ 304780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 298638137000.  Starting simulation...
+info: Entering event queue @ 305780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 299638137000.  Starting simulation...
+info: Entering event queue @ 306780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 300638137000.  Starting simulation...
+info: Entering event queue @ 307780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 301638137000.  Starting simulation...
+info: Entering event queue @ 308780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 302638137000.  Starting simulation...
+info: Entering event queue @ 309780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 303638137000.  Starting simulation...
+info: Entering event queue @ 310780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 304638137000.  Starting simulation...
+info: Entering event queue @ 311780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 305638137000.  Starting simulation...
+info: Entering event queue @ 312780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 306638137000.  Starting simulation...
+info: Entering event queue @ 313780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 307638137000.  Starting simulation...
+info: Entering event queue @ 314780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 308638137000.  Starting simulation...
+info: Entering event queue @ 315780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 309638137000.  Starting simulation...
+info: Entering event queue @ 316780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 310638137000.  Starting simulation...
+info: Entering event queue @ 317780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 311638137000.  Starting simulation...
+info: Entering event queue @ 318780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 312638137000.  Starting simulation...
+info: Entering event queue @ 319780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 313638137000.  Starting simulation...
+info: Entering event queue @ 320780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 314638137000.  Starting simulation...
+info: Entering event queue @ 321780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 315638137000.  Starting simulation...
+info: Entering event queue @ 322780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 316638137000.  Starting simulation...
+info: Entering event queue @ 323780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 317638137000.  Starting simulation...
+info: Entering event queue @ 324780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 318638137000.  Starting simulation...
+info: Entering event queue @ 325780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 319638137000.  Starting simulation...
+info: Entering event queue @ 326780568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 327780568000.  Starting simulation...
+info: Entering event queue @ 329516810250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 320638137000.  Starting simulation...
+info: Entering event queue @ 329516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 321638137000.  Starting simulation...
+info: Entering event queue @ 330516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 322638137000.  Starting simulation...
+info: Entering event queue @ 331516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 323638137000.  Starting simulation...
+info: Entering event queue @ 332516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 324638137000.  Starting simulation...
+info: Entering event queue @ 333516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 325638137000.  Starting simulation...
+info: Entering event queue @ 334516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 326638137000.  Starting simulation...
+info: Entering event queue @ 335516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 327638137000.  Starting simulation...
-info: Entering event queue @ 328373547000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 328373549000.  Starting simulation...
+info: Entering event queue @ 336516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 329373549000.  Starting simulation...
+info: Entering event queue @ 337516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 330373549000.  Starting simulation...
+info: Entering event queue @ 338516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 331373549000.  Starting simulation...
+info: Entering event queue @ 339516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 332373549000.  Starting simulation...
+info: Entering event queue @ 340516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 333373549000.  Starting simulation...
+info: Entering event queue @ 341516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 334373549000.  Starting simulation...
+info: Entering event queue @ 342516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 335373549000.  Starting simulation...
+info: Entering event queue @ 343516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 336373549000.  Starting simulation...
+info: Entering event queue @ 344516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 337373549000.  Starting simulation...
+info: Entering event queue @ 345516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 338373549000.  Starting simulation...
+info: Entering event queue @ 346516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 339373549000.  Starting simulation...
+info: Entering event queue @ 347516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 340373549000.  Starting simulation...
+info: Entering event queue @ 348516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 341373549000.  Starting simulation...
+info: Entering event queue @ 349516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 342373549000.  Starting simulation...
+info: Entering event queue @ 350516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 343373549000.  Starting simulation...
+info: Entering event queue @ 351516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 344373549000.  Starting simulation...
+info: Entering event queue @ 352516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 345373549000.  Starting simulation...
+info: Entering event queue @ 353516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 346373549000.  Starting simulation...
+info: Entering event queue @ 354516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 347373549000.  Starting simulation...
+info: Entering event queue @ 355516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 348373549000.  Starting simulation...
+info: Entering event queue @ 356516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 349373549000.  Starting simulation...
+info: Entering event queue @ 357516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 350373549000.  Starting simulation...
+info: Entering event queue @ 358516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 351373549000.  Starting simulation...
+info: Entering event queue @ 359516813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 360516813000.  Starting simulation...
+info: Entering event queue @ 362253097250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 352373549000.  Starting simulation...
+info: Entering event queue @ 362253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 353373549000.  Starting simulation...
+info: Entering event queue @ 363253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 354373549000.  Starting simulation...
+info: Entering event queue @ 364253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 355373549000.  Starting simulation...
+info: Entering event queue @ 365253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 356373549000.  Starting simulation...
+info: Entering event queue @ 366253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 357373549000.  Starting simulation...
+info: Entering event queue @ 367253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 358373549000.  Starting simulation...
+info: Entering event queue @ 368253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 359373549000.  Starting simulation...
+info: Entering event queue @ 369253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 360373549000.  Starting simulation...
-info: Entering event queue @ 361110147000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 361110149000.  Starting simulation...
+info: Entering event queue @ 370253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 362110149000.  Starting simulation...
+info: Entering event queue @ 371253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 363110149000.  Starting simulation...
+info: Entering event queue @ 372253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 364110149000.  Starting simulation...
+info: Entering event queue @ 373253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 365110149000.  Starting simulation...
+info: Entering event queue @ 374253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 366110149000.  Starting simulation...
+info: Entering event queue @ 375253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 367110149000.  Starting simulation...
+info: Entering event queue @ 376253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 368110149000.  Starting simulation...
+info: Entering event queue @ 377253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 369110149000.  Starting simulation...
+info: Entering event queue @ 378253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 370110149000.  Starting simulation...
+info: Entering event queue @ 379253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 371110149000.  Starting simulation...
+info: Entering event queue @ 380253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 372110149000.  Starting simulation...
+info: Entering event queue @ 381253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 373110149000.  Starting simulation...
+info: Entering event queue @ 382253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 374110149000.  Starting simulation...
+info: Entering event queue @ 383253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 375110149000.  Starting simulation...
+info: Entering event queue @ 384253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 376110149000.  Starting simulation...
+info: Entering event queue @ 385253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 377110149000.  Starting simulation...
+info: Entering event queue @ 386253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 378110149000.  Starting simulation...
+info: Entering event queue @ 387253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 379110149000.  Starting simulation...
+info: Entering event queue @ 388253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 380110149000.  Starting simulation...
+info: Entering event queue @ 389253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 381110149000.  Starting simulation...
+info: Entering event queue @ 390253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 382110149000.  Starting simulation...
+info: Entering event queue @ 391253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 383110149000.  Starting simulation...
+info: Entering event queue @ 392253100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 393253100000.  Starting simulation...
+info: Entering event queue @ 394989382250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 384110149000.  Starting simulation...
+info: Entering event queue @ 394989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 385110149000.  Starting simulation...
+info: Entering event queue @ 395989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 386110149000.  Starting simulation...
+info: Entering event queue @ 396989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 387110149000.  Starting simulation...
+info: Entering event queue @ 397989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 388110149000.  Starting simulation...
+info: Entering event queue @ 398989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 389110149000.  Starting simulation...
+info: Entering event queue @ 399989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 390110149000.  Starting simulation...
+info: Entering event queue @ 400989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 391110149000.  Starting simulation...
+info: Entering event queue @ 401989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 392110149000.  Starting simulation...
+info: Entering event queue @ 402989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 393110149000.  Starting simulation...
-info: Entering event queue @ 393846726000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 393846728000.  Starting simulation...
+info: Entering event queue @ 403989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 394846728000.  Starting simulation...
+info: Entering event queue @ 404989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 395846728000.  Starting simulation...
+info: Entering event queue @ 405989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 396846728000.  Starting simulation...
+info: Entering event queue @ 406989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 397846728000.  Starting simulation...
+info: Entering event queue @ 407989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 398846728000.  Starting simulation...
+info: Entering event queue @ 408989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 399846728000.  Starting simulation...
+info: Entering event queue @ 409989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 400846728000.  Starting simulation...
+info: Entering event queue @ 410989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 401846728000.  Starting simulation...
+info: Entering event queue @ 411989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 402846728000.  Starting simulation...
+info: Entering event queue @ 412989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 403846728000.  Starting simulation...
+info: Entering event queue @ 413989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 404846728000.  Starting simulation...
+info: Entering event queue @ 414989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 405846728000.  Starting simulation...
+info: Entering event queue @ 415989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 406846728000.  Starting simulation...
+info: Entering event queue @ 416989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 407846728000.  Starting simulation...
+info: Entering event queue @ 417989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 408846728000.  Starting simulation...
+info: Entering event queue @ 418989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 409846728000.  Starting simulation...
+info: Entering event queue @ 419989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 410846728000.  Starting simulation...
+info: Entering event queue @ 420989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 411846728000.  Starting simulation...
+info: Entering event queue @ 421989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 412846728000.  Starting simulation...
+info: Entering event queue @ 422989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 413846728000.  Starting simulation...
+info: Entering event queue @ 423989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 414846728000.  Starting simulation...
+info: Entering event queue @ 424989385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 425989385000.  Starting simulation...
+info: Entering event queue @ 427725666250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 415846728000.  Starting simulation...
+info: Entering event queue @ 427725669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 416846728000.  Starting simulation...
+info: Entering event queue @ 428725669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 417846728000.  Starting simulation...
+info: Entering event queue @ 429725669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 418846728000.  Starting simulation...
+info: Entering event queue @ 430725669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 419846728000.  Starting simulation...
+info: Entering event queue @ 431725669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 420846728000.  Starting simulation...
+info: Entering event queue @ 432725669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 421846728000.  Starting simulation...
+info: Entering event queue @ 433725669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 422846728000.  Starting simulation...
+info: Entering event queue @ 434725669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 435725669000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 423846728000.  Starting simulation...
+info: Entering event queue @ 435725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 424846728000.  Starting simulation...
+info: Entering event queue @ 436725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 425846728000.  Starting simulation...
-info: Entering event queue @ 426582138000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 426582140000.  Starting simulation...
+info: Entering event queue @ 437725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 427582140000.  Starting simulation...
+info: Entering event queue @ 438725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 428582140000.  Starting simulation...
+info: Entering event queue @ 439725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 429582140000.  Starting simulation...
+info: Entering event queue @ 440725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 430582140000.  Starting simulation...
+info: Entering event queue @ 441725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 431582140000.  Starting simulation...
+info: Entering event queue @ 442725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 432582140000.  Starting simulation...
+info: Entering event queue @ 443725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 433582140000.  Starting simulation...
+info: Entering event queue @ 444725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 434582140000.  Starting simulation...
+info: Entering event queue @ 445725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 435582140000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 435582147500.  Starting simulation...
+info: Entering event queue @ 446725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 436582147500.  Starting simulation...
+info: Entering event queue @ 447725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 437582147500.  Starting simulation...
+info: Entering event queue @ 448725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 438582147500.  Starting simulation...
+info: Entering event queue @ 449725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 439582147500.  Starting simulation...
+info: Entering event queue @ 450725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 440582147500.  Starting simulation...
+info: Entering event queue @ 451725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 441582147500.  Starting simulation...
+info: Entering event queue @ 452725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 442582147500.  Starting simulation...
+info: Entering event queue @ 453725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 443582147500.  Starting simulation...
+info: Entering event queue @ 454725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 444582147500.  Starting simulation...
+info: Entering event queue @ 455725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 445582147500.  Starting simulation...
+info: Entering event queue @ 456725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 446582147500.  Starting simulation...
+info: Entering event queue @ 457725676500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 458725676500.  Starting simulation...
+info: Entering event queue @ 460461918250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 447582147500.  Starting simulation...
+info: Entering event queue @ 460461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 448582147500.  Starting simulation...
+info: Entering event queue @ 461461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 449582147500.  Starting simulation...
+info: Entering event queue @ 462461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 450582147500.  Starting simulation...
+info: Entering event queue @ 463461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 451582147500.  Starting simulation...
+info: Entering event queue @ 464461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 452582147500.  Starting simulation...
+info: Entering event queue @ 465461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 453582147500.  Starting simulation...
+info: Entering event queue @ 466461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 454582147500.  Starting simulation...
+info: Entering event queue @ 467461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 455582147500.  Starting simulation...
+info: Entering event queue @ 468461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 456582147500.  Starting simulation...
+info: Entering event queue @ 469461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 457582147500.  Starting simulation...
+info: Entering event queue @ 470461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 458582147500.  Starting simulation...
-info: Entering event queue @ 459318738000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 459318740000.  Starting simulation...
+info: Entering event queue @ 471461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 460318740000.  Starting simulation...
+info: Entering event queue @ 472461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 461318740000.  Starting simulation...
+info: Entering event queue @ 473461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 462318740000.  Starting simulation...
+info: Entering event queue @ 474461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 463318740000.  Starting simulation...
+info: Entering event queue @ 475461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 464318740000.  Starting simulation...
+info: Entering event queue @ 476461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 465318740000.  Starting simulation...
+info: Entering event queue @ 477461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 466318740000.  Starting simulation...
+info: Entering event queue @ 478461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 467318740000.  Starting simulation...
+info: Entering event queue @ 479461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 468318740000.  Starting simulation...
+info: Entering event queue @ 480461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 469318740000.  Starting simulation...
+info: Entering event queue @ 481461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 470318740000.  Starting simulation...
+info: Entering event queue @ 482461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 471318740000.  Starting simulation...
+info: Entering event queue @ 483461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 472318740000.  Starting simulation...
+info: Entering event queue @ 484461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 473318740000.  Starting simulation...
+info: Entering event queue @ 485461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 474318740000.  Starting simulation...
+info: Entering event queue @ 486461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 475318740000.  Starting simulation...
+info: Entering event queue @ 487461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 476318740000.  Starting simulation...
+info: Entering event queue @ 488461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 477318740000.  Starting simulation...
+info: Entering event queue @ 489461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 478318740000.  Starting simulation...
+info: Entering event queue @ 490461921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 491461921000.  Starting simulation...
+info: Entering event queue @ 493198202250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 479318740000.  Starting simulation...
+info: Entering event queue @ 493198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 480318740000.  Starting simulation...
+info: Entering event queue @ 494198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 481318740000.  Starting simulation...
+info: Entering event queue @ 495198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 482318740000.  Starting simulation...
+info: Entering event queue @ 496198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 483318740000.  Starting simulation...
+info: Entering event queue @ 497198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 484318740000.  Starting simulation...
+info: Entering event queue @ 498198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 485318740000.  Starting simulation...
+info: Entering event queue @ 499198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 486318740000.  Starting simulation...
+info: Entering event queue @ 500198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 487318740000.  Starting simulation...
+info: Entering event queue @ 501198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 488318740000.  Starting simulation...
+info: Entering event queue @ 502198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 489318740000.  Starting simulation...
+info: Entering event queue @ 503198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 490318740000.  Starting simulation...
+info: Entering event queue @ 504198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 491318740000.  Starting simulation...
-info: Entering event queue @ 492055355000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 492055357000.  Starting simulation...
+info: Entering event queue @ 505198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 493055357000.  Starting simulation...
+info: Entering event queue @ 506198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 494055357000.  Starting simulation...
+info: Entering event queue @ 507198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 495055357000.  Starting simulation...
+info: Entering event queue @ 508198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 496055357000.  Starting simulation...
+info: Entering event queue @ 509198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 497055357000.  Starting simulation...
+info: Entering event queue @ 510198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 498055357000.  Starting simulation...
+info: Entering event queue @ 511198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 499055357000.  Starting simulation...
+info: Entering event queue @ 512198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 500055357000.  Starting simulation...
+info: Entering event queue @ 513198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 501055357000.  Starting simulation...
+info: Entering event queue @ 514198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 502055357000.  Starting simulation...
+info: Entering event queue @ 515198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 503055357000.  Starting simulation...
+info: Entering event queue @ 516198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 504055357000.  Starting simulation...
+info: Entering event queue @ 517198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 505055357000.  Starting simulation...
+info: Entering event queue @ 518198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 506055357000.  Starting simulation...
+info: Entering event queue @ 519198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 507055357000.  Starting simulation...
+info: Entering event queue @ 520198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 508055357000.  Starting simulation...
+info: Entering event queue @ 521198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 509055357000.  Starting simulation...
+info: Entering event queue @ 522198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 510055357000.  Starting simulation...
+info: Entering event queue @ 523198205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 524198205000.  Starting simulation...
+info: Entering event queue @ 525934134250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 511055357000.  Starting simulation...
+info: Entering event queue @ 525934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 512055357000.  Starting simulation...
+info: Entering event queue @ 526934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 513055357000.  Starting simulation...
+info: Entering event queue @ 527934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 514055357000.  Starting simulation...
+info: Entering event queue @ 528934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 515055357000.  Starting simulation...
+info: Entering event queue @ 529934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 516055357000.  Starting simulation...
+info: Entering event queue @ 530934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 517055357000.  Starting simulation...
+info: Entering event queue @ 531934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 518055357000.  Starting simulation...
+info: Entering event queue @ 532934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 519055357000.  Starting simulation...
+info: Entering event queue @ 533934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 520055357000.  Starting simulation...
+info: Entering event queue @ 534934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 521055357000.  Starting simulation...
+info: Entering event queue @ 535934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 522055357000.  Starting simulation...
+info: Entering event queue @ 536934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 523055357000.  Starting simulation...
+info: Entering event queue @ 537934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 524055357000.  Starting simulation...
-info: Entering event queue @ 524790922000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 524790924000.  Starting simulation...
+info: Entering event queue @ 538934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 525790924000.  Starting simulation...
+info: Entering event queue @ 539934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 526790924000.  Starting simulation...
+info: Entering event queue @ 540934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 527790924000.  Starting simulation...
+info: Entering event queue @ 541934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 528790924000.  Starting simulation...
+info: Entering event queue @ 542934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 529790924000.  Starting simulation...
+info: Entering event queue @ 543934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 530790924000.  Starting simulation...
+info: Entering event queue @ 544934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 531790924000.  Starting simulation...
+info: Entering event queue @ 545934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 532790924000.  Starting simulation...
+info: Entering event queue @ 546934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 533790924000.  Starting simulation...
+info: Entering event queue @ 547934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 534790924000.  Starting simulation...
+info: Entering event queue @ 548934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 535790924000.  Starting simulation...
+info: Entering event queue @ 549934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 536790924000.  Starting simulation...
+info: Entering event queue @ 550934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 537790924000.  Starting simulation...
+info: Entering event queue @ 551934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 538790924000.  Starting simulation...
+info: Entering event queue @ 552934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 539790924000.  Starting simulation...
+info: Entering event queue @ 553934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 540790924000.  Starting simulation...
+info: Entering event queue @ 554934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 541790924000.  Starting simulation...
+info: Entering event queue @ 555934137000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 556934137000.  Starting simulation...
+info: Entering event queue @ 558670734250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 542790924000.  Starting simulation...
+info: Entering event queue @ 558670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 543790924000.  Starting simulation...
+info: Entering event queue @ 559670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 544790924000.  Starting simulation...
+info: Entering event queue @ 560670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 545790924000.  Starting simulation...
+info: Entering event queue @ 561670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 546790924000.  Starting simulation...
+info: Entering event queue @ 562670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 547790924000.  Starting simulation...
+info: Entering event queue @ 563670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 548790924000.  Starting simulation...
+info: Entering event queue @ 564670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 549790924000.  Starting simulation...
+info: Entering event queue @ 565670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 550790924000.  Starting simulation...
+info: Entering event queue @ 566670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 551790924000.  Starting simulation...
+info: Entering event queue @ 567670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 552790924000.  Starting simulation...
+info: Entering event queue @ 568670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 553790924000.  Starting simulation...
+info: Entering event queue @ 569670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 554790924000.  Starting simulation...
+info: Entering event queue @ 570670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 555790924000.  Starting simulation...
+info: Entering event queue @ 571670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 556790924000.  Starting simulation...
-info: Entering event queue @ 557527522000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 557527524000.  Starting simulation...
+info: Entering event queue @ 572670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 558527524000.  Starting simulation...
+info: Entering event queue @ 573670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 559527524000.  Starting simulation...
+info: Entering event queue @ 574670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 560527524000.  Starting simulation...
+info: Entering event queue @ 575670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 561527524000.  Starting simulation...
+info: Entering event queue @ 576670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 562527524000.  Starting simulation...
+info: Entering event queue @ 577670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 563527524000.  Starting simulation...
+info: Entering event queue @ 578670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 564527524000.  Starting simulation...
+info: Entering event queue @ 579670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 565527524000.  Starting simulation...
+info: Entering event queue @ 580670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 566527524000.  Starting simulation...
+info: Entering event queue @ 581670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 567527524000.  Starting simulation...
+info: Entering event queue @ 582670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 568527524000.  Starting simulation...
+info: Entering event queue @ 583670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 569527524000.  Starting simulation...
+info: Entering event queue @ 584670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 570527524000.  Starting simulation...
+info: Entering event queue @ 585670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 571527524000.  Starting simulation...
+info: Entering event queue @ 586670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 572527524000.  Starting simulation...
+info: Entering event queue @ 587670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 573527524000.  Starting simulation...
+info: Entering event queue @ 588670737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 589670737000.  Starting simulation...
+info: Entering event queue @ 591406706250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 574527524000.  Starting simulation...
+info: Entering event queue @ 591406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 575527524000.  Starting simulation...
+info: Entering event queue @ 592406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 576527524000.  Starting simulation...
+info: Entering event queue @ 593406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 577527524000.  Starting simulation...
+info: Entering event queue @ 594406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 578527524000.  Starting simulation...
+info: Entering event queue @ 595406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 579527524000.  Starting simulation...
+info: Entering event queue @ 596406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 580527524000.  Starting simulation...
+info: Entering event queue @ 597406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 581527524000.  Starting simulation...
+info: Entering event queue @ 598406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 582527524000.  Starting simulation...
+info: Entering event queue @ 599406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 583527524000.  Starting simulation...
+info: Entering event queue @ 600406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 584527524000.  Starting simulation...
+info: Entering event queue @ 601406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 585527524000.  Starting simulation...
+info: Entering event queue @ 602406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 586527524000.  Starting simulation...
+info: Entering event queue @ 603406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 587527524000.  Starting simulation...
+info: Entering event queue @ 604406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 588527524000.  Starting simulation...
+info: Entering event queue @ 605406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 589527524000.  Starting simulation...
-info: Entering event queue @ 590264122000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 590264124000.  Starting simulation...
+info: Entering event queue @ 606406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 591264124000.  Starting simulation...
+info: Entering event queue @ 607406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 592264124000.  Starting simulation...
+info: Entering event queue @ 608406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 593264124000.  Starting simulation...
+info: Entering event queue @ 609406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 594264124000.  Starting simulation...
+info: Entering event queue @ 610406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 595264124000.  Starting simulation...
+info: Entering event queue @ 611406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 596264124000.  Starting simulation...
+info: Entering event queue @ 612406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 597264124000.  Starting simulation...
+info: Entering event queue @ 613406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 598264124000.  Starting simulation...
+info: Entering event queue @ 614406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 599264124000.  Starting simulation...
+info: Entering event queue @ 615406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 600264124000.  Starting simulation...
+info: Entering event queue @ 616406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 601264124000.  Starting simulation...
+info: Entering event queue @ 617406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 602264124000.  Starting simulation...
+info: Entering event queue @ 618406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 603264124000.  Starting simulation...
+info: Entering event queue @ 619406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 604264124000.  Starting simulation...
+info: Entering event queue @ 620406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 605264124000.  Starting simulation...
+info: Entering event queue @ 621406709000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 622406709000.  Starting simulation...
+info: Entering event queue @ 624142997250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 606264124000.  Starting simulation...
+info: Entering event queue @ 624143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 607264124000.  Starting simulation...
+info: Entering event queue @ 625143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 608264124000.  Starting simulation...
+info: Entering event queue @ 626143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 609264124000.  Starting simulation...
+info: Entering event queue @ 627143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 610264124000.  Starting simulation...
+info: Entering event queue @ 628143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 611264124000.  Starting simulation...
+info: Entering event queue @ 629143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 612264124000.  Starting simulation...
+info: Entering event queue @ 630143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 613264124000.  Starting simulation...
+info: Entering event queue @ 631143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 614264124000.  Starting simulation...
+info: Entering event queue @ 632143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 615264124000.  Starting simulation...
+info: Entering event queue @ 633143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 616264124000.  Starting simulation...
+info: Entering event queue @ 634143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 617264124000.  Starting simulation...
+info: Entering event queue @ 635143000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 636143000000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 618264124000.  Starting simulation...
+info: Entering event queue @ 636143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 619264124000.  Starting simulation...
+info: Entering event queue @ 637143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 620264124000.  Starting simulation...
+info: Entering event queue @ 638143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 621264124000.  Starting simulation...
+info: Entering event queue @ 639143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 622264124000.  Starting simulation...
-info: Entering event queue @ 623000743000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 623000745000.  Starting simulation...
+info: Entering event queue @ 640143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 624000745000.  Starting simulation...
+info: Entering event queue @ 641143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 625000745000.  Starting simulation...
+info: Entering event queue @ 642143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 626000745000.  Starting simulation...
+info: Entering event queue @ 643143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 627000745000.  Starting simulation...
+info: Entering event queue @ 644143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 628000745000.  Starting simulation...
+info: Entering event queue @ 645143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 629000745000.  Starting simulation...
+info: Entering event queue @ 646143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 630000745000.  Starting simulation...
+info: Entering event queue @ 647143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 631000745000.  Starting simulation...
+info: Entering event queue @ 648143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 632000745000.  Starting simulation...
+info: Entering event queue @ 649143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 633000745000.  Starting simulation...
+info: Entering event queue @ 650143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 634000745000.  Starting simulation...
+info: Entering event queue @ 651143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 635000745000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 635000752500.  Starting simulation...
+info: Entering event queue @ 652143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 636000752500.  Starting simulation...
+info: Entering event queue @ 653143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 637000752500.  Starting simulation...
+info: Entering event queue @ 654143007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 655143007500.  Starting simulation...
+info: Entering event queue @ 656879241250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 638000752500.  Starting simulation...
+info: Entering event queue @ 656879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 639000752500.  Starting simulation...
+info: Entering event queue @ 657879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 640000752500.  Starting simulation...
+info: Entering event queue @ 658879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 641000752500.  Starting simulation...
+info: Entering event queue @ 659879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 642000752500.  Starting simulation...
+info: Entering event queue @ 660879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 643000752500.  Starting simulation...
+info: Entering event queue @ 661879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 644000752500.  Starting simulation...
+info: Entering event queue @ 662879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 645000752500.  Starting simulation...
+info: Entering event queue @ 663879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 646000752500.  Starting simulation...
+info: Entering event queue @ 664879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 647000752500.  Starting simulation...
+info: Entering event queue @ 665879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 648000752500.  Starting simulation...
+info: Entering event queue @ 666879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 649000752500.  Starting simulation...
+info: Entering event queue @ 667879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 650000752500.  Starting simulation...
+info: Entering event queue @ 668879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 651000752500.  Starting simulation...
+info: Entering event queue @ 669879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 652000752500.  Starting simulation...
+info: Entering event queue @ 670879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 653000752500.  Starting simulation...
+info: Entering event queue @ 671879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 654000752500.  Starting simulation...
+info: Entering event queue @ 672879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 655000752500.  Starting simulation...
-info: Entering event queue @ 655736155000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 655736157000.  Starting simulation...
+info: Entering event queue @ 673879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 656736157000.  Starting simulation...
+info: Entering event queue @ 674879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 657736157000.  Starting simulation...
+info: Entering event queue @ 675879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 658736157000.  Starting simulation...
+info: Entering event queue @ 676879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 659736157000.  Starting simulation...
+info: Entering event queue @ 677879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 660736157000.  Starting simulation...
+info: Entering event queue @ 678879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 661736157000.  Starting simulation...
+info: Entering event queue @ 679879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 662736157000.  Starting simulation...
+info: Entering event queue @ 680879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 663736157000.  Starting simulation...
+info: Entering event queue @ 681879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 664736157000.  Starting simulation...
+info: Entering event queue @ 682879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 665736157000.  Starting simulation...
+info: Entering event queue @ 683879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 666736157000.  Starting simulation...
+info: Entering event queue @ 684879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 667736157000.  Starting simulation...
+info: Entering event queue @ 685879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 668736157000.  Starting simulation...
+info: Entering event queue @ 686879244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 687879244000.  Starting simulation...
+info: Entering event queue @ 689615526250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 669736157000.  Starting simulation...
+info: Entering event queue @ 689615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 670736157000.  Starting simulation...
+info: Entering event queue @ 690615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 671736157000.  Starting simulation...
+info: Entering event queue @ 691615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 672736157000.  Starting simulation...
+info: Entering event queue @ 692615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 673736157000.  Starting simulation...
+info: Entering event queue @ 693615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 674736157000.  Starting simulation...
+info: Entering event queue @ 694615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 675736157000.  Starting simulation...
+info: Entering event queue @ 695615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 676736157000.  Starting simulation...
+info: Entering event queue @ 696615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 677736157000.  Starting simulation...
+info: Entering event queue @ 697615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 678736157000.  Starting simulation...
+info: Entering event queue @ 698615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 679736157000.  Starting simulation...
+info: Entering event queue @ 699615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 680736157000.  Starting simulation...
+info: Entering event queue @ 700615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 681736157000.  Starting simulation...
+info: Entering event queue @ 701615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 682736157000.  Starting simulation...
+info: Entering event queue @ 702615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 683736157000.  Starting simulation...
+info: Entering event queue @ 703615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 684736157000.  Starting simulation...
+info: Entering event queue @ 704615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 685736157000.  Starting simulation...
+info: Entering event queue @ 705615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 686736157000.  Starting simulation...
+info: Entering event queue @ 706615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 687736157000.  Starting simulation...
-info: Entering event queue @ 688472755000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 688472757000.  Starting simulation...
+info: Entering event queue @ 707615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 689472757000.  Starting simulation...
+info: Entering event queue @ 708615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 690472757000.  Starting simulation...
+info: Entering event queue @ 709615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 691472757000.  Starting simulation...
+info: Entering event queue @ 710615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 692472757000.  Starting simulation...
+info: Entering event queue @ 711615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 693472757000.  Starting simulation...
+info: Entering event queue @ 712615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 694472757000.  Starting simulation...
+info: Entering event queue @ 713615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 695472757000.  Starting simulation...
+info: Entering event queue @ 714615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 696472757000.  Starting simulation...
+info: Entering event queue @ 715615529000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 716615529000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 697472757000.  Starting simulation...
+info: Entering event queue @ 716615536500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 698472757000.  Starting simulation...
+info: Entering event queue @ 717615536500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 699472757000.  Starting simulation...
+info: Entering event queue @ 718615536500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 700472757000.  Starting simulation...
+info: Entering event queue @ 719615536500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 720615536500.  Starting simulation...
+info: Entering event queue @ 722351817250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 701472757000.  Starting simulation...
+info: Entering event queue @ 722351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 702472757000.  Starting simulation...
+info: Entering event queue @ 723351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 703472757000.  Starting simulation...
+info: Entering event queue @ 724351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 704472757000.  Starting simulation...
+info: Entering event queue @ 725351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 705472757000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 705472764500.  Starting simulation...
+info: Entering event queue @ 726351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 706472764500.  Starting simulation...
+info: Entering event queue @ 727351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 707472764500.  Starting simulation...
+info: Entering event queue @ 728351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 708472764500.  Starting simulation...
+info: Entering event queue @ 729351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 709472764500.  Starting simulation...
+info: Entering event queue @ 730351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 710472764500.  Starting simulation...
+info: Entering event queue @ 731351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 711472764500.  Starting simulation...
+info: Entering event queue @ 732351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 712472764500.  Starting simulation...
+info: Entering event queue @ 733351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 713472764500.  Starting simulation...
+info: Entering event queue @ 734351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 714472764500.  Starting simulation...
+info: Entering event queue @ 735351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 715472764500.  Starting simulation...
+info: Entering event queue @ 736351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 716472764500.  Starting simulation...
+info: Entering event queue @ 737351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 717472764500.  Starting simulation...
+info: Entering event queue @ 738351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 718472764500.  Starting simulation...
+info: Entering event queue @ 739351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 719472764500.  Starting simulation...
+info: Entering event queue @ 740351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 720472764500.  Starting simulation...
-info: Entering event queue @ 721209334000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 721209336000.  Starting simulation...
+info: Entering event queue @ 741351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 722209336000.  Starting simulation...
+info: Entering event queue @ 742351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 723209336000.  Starting simulation...
+info: Entering event queue @ 743351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 724209336000.  Starting simulation...
+info: Entering event queue @ 744351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 725209336000.  Starting simulation...
+info: Entering event queue @ 745351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 726209336000.  Starting simulation...
+info: Entering event queue @ 746351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 727209336000.  Starting simulation...
+info: Entering event queue @ 747351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 728209336000.  Starting simulation...
+info: Entering event queue @ 748351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 729209336000.  Starting simulation...
+info: Entering event queue @ 749351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 730209336000.  Starting simulation...
+info: Entering event queue @ 750351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 731209336000.  Starting simulation...
+info: Entering event queue @ 751351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 732209336000.  Starting simulation...
+info: Entering event queue @ 752351820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 753351820000.  Starting simulation...
+info: Entering event queue @ 755088065250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 733209336000.  Starting simulation...
+info: Entering event queue @ 755088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 734209336000.  Starting simulation...
+info: Entering event queue @ 756088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 735209336000.  Starting simulation...
+info: Entering event queue @ 757088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 736209336000.  Starting simulation...
+info: Entering event queue @ 758088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 737209336000.  Starting simulation...
+info: Entering event queue @ 759088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 738209336000.  Starting simulation...
+info: Entering event queue @ 760088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 739209336000.  Starting simulation...
+info: Entering event queue @ 761088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 740209336000.  Starting simulation...
+info: Entering event queue @ 762088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 741209336000.  Starting simulation...
+info: Entering event queue @ 763088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 742209336000.  Starting simulation...
+info: Entering event queue @ 764088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 743209336000.  Starting simulation...
+info: Entering event queue @ 765088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 744209336000.  Starting simulation...
+info: Entering event queue @ 766088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 745209336000.  Starting simulation...
+info: Entering event queue @ 767088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 746209336000.  Starting simulation...
+info: Entering event queue @ 768088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 747209336000.  Starting simulation...
+info: Entering event queue @ 769088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 748209336000.  Starting simulation...
+info: Entering event queue @ 770088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 749209336000.  Starting simulation...
+info: Entering event queue @ 771088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 750209336000.  Starting simulation...
+info: Entering event queue @ 772088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 751209336000.  Starting simulation...
+info: Entering event queue @ 773088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 752209336000.  Starting simulation...
+info: Entering event queue @ 774088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 753209336000.  Starting simulation...
-info: Entering event queue @ 753944939000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 753944941000.  Starting simulation...
+info: Entering event queue @ 775088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 754944941000.  Starting simulation...
+info: Entering event queue @ 776088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 755944941000.  Starting simulation...
+info: Entering event queue @ 777088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 756944941000.  Starting simulation...
+info: Entering event queue @ 778088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 757944941000.  Starting simulation...
+info: Entering event queue @ 779088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 758944941000.  Starting simulation...
+info: Entering event queue @ 780088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 759944941000.  Starting simulation...
+info: Entering event queue @ 781088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 760944941000.  Starting simulation...
+info: Entering event queue @ 782088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 761944941000.  Starting simulation...
+info: Entering event queue @ 783088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 762944941000.  Starting simulation...
+info: Entering event queue @ 784088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 763944941000.  Starting simulation...
+info: Entering event queue @ 785088068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 786088068000.  Starting simulation...
+info: Entering event queue @ 787824349250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 764944941000.  Starting simulation...
+info: Entering event queue @ 787824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 765944941000.  Starting simulation...
+info: Entering event queue @ 788824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 766944941000.  Starting simulation...
+info: Entering event queue @ 789824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 767944941000.  Starting simulation...
+info: Entering event queue @ 790824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 768944941000.  Starting simulation...
+info: Entering event queue @ 791824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 769944941000.  Starting simulation...
+info: Entering event queue @ 792824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 770944941000.  Starting simulation...
+info: Entering event queue @ 793824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 771944941000.  Starting simulation...
+info: Entering event queue @ 794824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 772944941000.  Starting simulation...
+info: Entering event queue @ 795824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 773944941000.  Starting simulation...
+info: Entering event queue @ 796824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 774944941000.  Starting simulation...
+info: Entering event queue @ 797824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 775944941000.  Starting simulation...
+info: Entering event queue @ 798824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 776944941000.  Starting simulation...
+info: Entering event queue @ 799824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 777944941000.  Starting simulation...
+info: Entering event queue @ 800824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 778944941000.  Starting simulation...
+info: Entering event queue @ 801824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 779944941000.  Starting simulation...
+info: Entering event queue @ 802824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 780944941000.  Starting simulation...
+info: Entering event queue @ 803824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 781944941000.  Starting simulation...
+info: Entering event queue @ 804824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 782944941000.  Starting simulation...
+info: Entering event queue @ 805824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 783944941000.  Starting simulation...
+info: Entering event queue @ 806824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 784944941000.  Starting simulation...
+info: Entering event queue @ 807824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 785944941000.  Starting simulation...
-info: Entering event queue @ 786681539000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 786681541000.  Starting simulation...
+info: Entering event queue @ 808824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 787681541000.  Starting simulation...
+info: Entering event queue @ 809824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 788681541000.  Starting simulation...
+info: Entering event queue @ 810824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 789681541000.  Starting simulation...
+info: Entering event queue @ 811824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 790681541000.  Starting simulation...
+info: Entering event queue @ 812824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 791681541000.  Starting simulation...
+info: Entering event queue @ 813824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 792681541000.  Starting simulation...
+info: Entering event queue @ 814824352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 815824352000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 793681541000.  Starting simulation...
+info: Entering event queue @ 815824359500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 794681541000.  Starting simulation...
+info: Entering event queue @ 816824359500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 795681541000.  Starting simulation...
+info: Entering event queue @ 817824359500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 818824359500.  Starting simulation...
+info: Entering event queue @ 820560634250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 796681541000.  Starting simulation...
+info: Entering event queue @ 820560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 797681541000.  Starting simulation...
+info: Entering event queue @ 821560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 798681541000.  Starting simulation...
+info: Entering event queue @ 822560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 799681541000.  Starting simulation...
+info: Entering event queue @ 823560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 800681541000.  Starting simulation...
+info: Entering event queue @ 824560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 801681541000.  Starting simulation...
+info: Entering event queue @ 825560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 802681541000.  Starting simulation...
+info: Entering event queue @ 826560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 803681541000.  Starting simulation...
+info: Entering event queue @ 827560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 804681541000.  Starting simulation...
+info: Entering event queue @ 828560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 805681541000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 805681548500.  Starting simulation...
+info: Entering event queue @ 829560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 806681548500.  Starting simulation...
+info: Entering event queue @ 830560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 807681548500.  Starting simulation...
+info: Entering event queue @ 831560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 808681548500.  Starting simulation...
+info: Entering event queue @ 832560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 809681548500.  Starting simulation...
+info: Entering event queue @ 833560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 810681548500.  Starting simulation...
+info: Entering event queue @ 834560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 811681548500.  Starting simulation...
+info: Entering event queue @ 835560637000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 836560637000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 812681548500.  Starting simulation...
+info: Entering event queue @ 836560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 813681548500.  Starting simulation...
+info: Entering event queue @ 837560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 814681548500.  Starting simulation...
+info: Entering event queue @ 838560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 815681548500.  Starting simulation...
+info: Entering event queue @ 839560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 816681548500.  Starting simulation...
+info: Entering event queue @ 840560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 817681548500.  Starting simulation...
+info: Entering event queue @ 841560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 818681548500.  Starting simulation...
-info: Entering event queue @ 819418118000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 819418120000.  Starting simulation...
+info: Entering event queue @ 842560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 820418120000.  Starting simulation...
+info: Entering event queue @ 843560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 821418120000.  Starting simulation...
+info: Entering event queue @ 844560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 822418120000.  Starting simulation...
+info: Entering event queue @ 845560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 823418120000.  Starting simulation...
+info: Entering event queue @ 846560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 824418120000.  Starting simulation...
+info: Entering event queue @ 847560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 825418120000.  Starting simulation...
+info: Entering event queue @ 848560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 826418120000.  Starting simulation...
+info: Entering event queue @ 849560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 827418120000.  Starting simulation...
+info: Entering event queue @ 850560644500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 851560644500.  Starting simulation...
+info: Entering event queue @ 853296882250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 828418120000.  Starting simulation...
+info: Entering event queue @ 853296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 829418120000.  Starting simulation...
+info: Entering event queue @ 854296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 830418120000.  Starting simulation...
+info: Entering event queue @ 855296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 831418120000.  Starting simulation...
+info: Entering event queue @ 856296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 832418120000.  Starting simulation...
+info: Entering event queue @ 857296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 833418120000.  Starting simulation...
+info: Entering event queue @ 858296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 834418120000.  Starting simulation...
+info: Entering event queue @ 859296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 835418120000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 835418127500.  Starting simulation...
+info: Entering event queue @ 860296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 836418127500.  Starting simulation...
+info: Entering event queue @ 861296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 837418127500.  Starting simulation...
+info: Entering event queue @ 862296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 838418127500.  Starting simulation...
+info: Entering event queue @ 863296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 839418127500.  Starting simulation...
+info: Entering event queue @ 864296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 840418127500.  Starting simulation...
+info: Entering event queue @ 865296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 841418127500.  Starting simulation...
+info: Entering event queue @ 866296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 842418127500.  Starting simulation...
+info: Entering event queue @ 867296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 843418127500.  Starting simulation...
+info: Entering event queue @ 868296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 844418127500.  Starting simulation...
+info: Entering event queue @ 869296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 845418127500.  Starting simulation...
+info: Entering event queue @ 870296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 846418127500.  Starting simulation...
+info: Entering event queue @ 871296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 847418127500.  Starting simulation...
+info: Entering event queue @ 872296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 848418127500.  Starting simulation...
+info: Entering event queue @ 873296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 849418127500.  Starting simulation...
+info: Entering event queue @ 874296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 850418127500.  Starting simulation...
+info: Entering event queue @ 875296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 851418127500.  Starting simulation...
-info: Entering event queue @ 852153530000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 852153532000.  Starting simulation...
+info: Entering event queue @ 876296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 853153532000.  Starting simulation...
+info: Entering event queue @ 877296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 854153532000.  Starting simulation...
+info: Entering event queue @ 878296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 855153532000.  Starting simulation...
+info: Entering event queue @ 879296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 856153532000.  Starting simulation...
+info: Entering event queue @ 880296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 857153532000.  Starting simulation...
+info: Entering event queue @ 881296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 858153532000.  Starting simulation...
+info: Entering event queue @ 882296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 859153532000.  Starting simulation...
+info: Entering event queue @ 883296885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 884296885000.  Starting simulation...
+info: Entering event queue @ 886033170250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 860153532000.  Starting simulation...
+info: Entering event queue @ 886033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 861153532000.  Starting simulation...
+info: Entering event queue @ 887033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 862153532000.  Starting simulation...
+info: Entering event queue @ 888033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 863153532000.  Starting simulation...
+info: Entering event queue @ 889033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 864153532000.  Starting simulation...
+info: Entering event queue @ 890033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 865153532000.  Starting simulation...
+info: Entering event queue @ 891033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 866153532000.  Starting simulation...
+info: Entering event queue @ 892033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 867153532000.  Starting simulation...
+info: Entering event queue @ 893033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 868153532000.  Starting simulation...
+info: Entering event queue @ 894033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 869153532000.  Starting simulation...
+info: Entering event queue @ 895033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 870153532000.  Starting simulation...
+info: Entering event queue @ 896033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 871153532000.  Starting simulation...
+info: Entering event queue @ 897033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 872153532000.  Starting simulation...
+info: Entering event queue @ 898033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 873153532000.  Starting simulation...
+info: Entering event queue @ 899033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 874153532000.  Starting simulation...
+info: Entering event queue @ 900033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 875153532000.  Starting simulation...
+info: Entering event queue @ 901033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 876153532000.  Starting simulation...
+info: Entering event queue @ 902033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 877153532000.  Starting simulation...
+info: Entering event queue @ 903033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 878153532000.  Starting simulation...
+info: Entering event queue @ 904033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 879153532000.  Starting simulation...
+info: Entering event queue @ 905033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 880153532000.  Starting simulation...
+info: Entering event queue @ 906033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 881153532000.  Starting simulation...
+info: Entering event queue @ 907033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 882153532000.  Starting simulation...
+info: Entering event queue @ 908033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 883153532000.  Starting simulation...
+info: Entering event queue @ 909033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 884153532000.  Starting simulation...
-info: Entering event queue @ 884890130000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 884890132000.  Starting simulation...
+info: Entering event queue @ 910033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 885890132000.  Starting simulation...
+info: Entering event queue @ 911033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 886890132000.  Starting simulation...
+info: Entering event queue @ 912033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 887890132000.  Starting simulation...
+info: Entering event queue @ 913033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 888890132000.  Starting simulation...
+info: Entering event queue @ 914033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 889890132000.  Starting simulation...
+info: Entering event queue @ 915033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 890890132000.  Starting simulation...
+info: Entering event queue @ 916033173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 917033173000.  Starting simulation...
+info: Entering event queue @ 918769454250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 891890132000.  Starting simulation...
+info: Entering event queue @ 918769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 892890132000.  Starting simulation...
+info: Entering event queue @ 919769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 893890132000.  Starting simulation...
+info: Entering event queue @ 920769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 894890132000.  Starting simulation...
+info: Entering event queue @ 921769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 895890132000.  Starting simulation...
+info: Entering event queue @ 922769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 896890132000.  Starting simulation...
+info: Entering event queue @ 923769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 897890132000.  Starting simulation...
+info: Entering event queue @ 924769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 898890132000.  Starting simulation...
+info: Entering event queue @ 925769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 899890132000.  Starting simulation...
+info: Entering event queue @ 926769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 900890132000.  Starting simulation...
+info: Entering event queue @ 927769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 901890132000.  Starting simulation...
+info: Entering event queue @ 928769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 902890132000.  Starting simulation...
+info: Entering event queue @ 929769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 903890132000.  Starting simulation...
+info: Entering event queue @ 930769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 904890132000.  Starting simulation...
+info: Entering event queue @ 931769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 905890132000.  Starting simulation...
+info: Entering event queue @ 932769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 906890132000.  Starting simulation...
+info: Entering event queue @ 933769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 907890132000.  Starting simulation...
+info: Entering event queue @ 934769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 908890132000.  Starting simulation...
+info: Entering event queue @ 935769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 909890132000.  Starting simulation...
+info: Entering event queue @ 936769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 910890132000.  Starting simulation...
+info: Entering event queue @ 937769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 911890132000.  Starting simulation...
+info: Entering event queue @ 938769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 912890132000.  Starting simulation...
+info: Entering event queue @ 939769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 913890132000.  Starting simulation...
+info: Entering event queue @ 940769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 914890132000.  Starting simulation...
+info: Entering event queue @ 941769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 915890132000.  Starting simulation...
+info: Entering event queue @ 942769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 916890132000.  Starting simulation...
-info: Entering event queue @ 917626751000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 917626753000.  Starting simulation...
+info: Entering event queue @ 943769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 918626753000.  Starting simulation...
+info: Entering event queue @ 944769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 919626753000.  Starting simulation...
+info: Entering event queue @ 945769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 920626753000.  Starting simulation...
+info: Entering event queue @ 946769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 921626753000.  Starting simulation...
+info: Entering event queue @ 947769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 922626753000.  Starting simulation...
+info: Entering event queue @ 948769457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 949769457000.  Starting simulation...
+info: Entering event queue @ 951505745250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 923626753000.  Starting simulation...
+info: Entering event queue @ 951505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 924626753000.  Starting simulation...
+info: Entering event queue @ 952505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 925626753000.  Starting simulation...
+info: Entering event queue @ 953505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 926626753000.  Starting simulation...
+info: Entering event queue @ 954505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 927626753000.  Starting simulation...
+info: Entering event queue @ 955505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 928626753000.  Starting simulation...
+info: Entering event queue @ 956505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 929626753000.  Starting simulation...
+info: Entering event queue @ 957505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 930626753000.  Starting simulation...
+info: Entering event queue @ 958505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 931626753000.  Starting simulation...
+info: Entering event queue @ 959505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 932626753000.  Starting simulation...
+info: Entering event queue @ 960505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 933626753000.  Starting simulation...
+info: Entering event queue @ 961505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 934626753000.  Starting simulation...
+info: Entering event queue @ 962505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 935626753000.  Starting simulation...
+info: Entering event queue @ 963505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 936626753000.  Starting simulation...
+info: Entering event queue @ 964505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 937626753000.  Starting simulation...
+info: Entering event queue @ 965505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 938626753000.  Starting simulation...
+info: Entering event queue @ 966505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 939626753000.  Starting simulation...
+info: Entering event queue @ 967505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 940626753000.  Starting simulation...
+info: Entering event queue @ 968505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 941626753000.  Starting simulation...
+info: Entering event queue @ 969505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 942626753000.  Starting simulation...
+info: Entering event queue @ 970505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 943626753000.  Starting simulation...
+info: Entering event queue @ 971505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 944626753000.  Starting simulation...
+info: Entering event queue @ 972505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 945626753000.  Starting simulation...
+info: Entering event queue @ 973505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 946626753000.  Starting simulation...
+info: Entering event queue @ 974505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 947626753000.  Starting simulation...
+info: Entering event queue @ 975505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 948626753000.  Starting simulation...
+info: Entering event queue @ 976505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 949626753000.  Starting simulation...
-info: Entering event queue @ 950363351000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 950363353000.  Starting simulation...
+info: Entering event queue @ 977505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 951363353000.  Starting simulation...
+info: Entering event queue @ 978505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 952363353000.  Starting simulation...
+info: Entering event queue @ 979505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 953363353000.  Starting simulation...
+info: Entering event queue @ 980505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 954363353000.  Starting simulation...
+info: Entering event queue @ 981505748000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 982505748000.  Starting simulation...
+info: Entering event queue @ 984241990250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 955363353000.  Starting simulation...
+info: Entering event queue @ 984241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 956363353000.  Starting simulation...
+info: Entering event queue @ 985241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 957363353000.  Starting simulation...
+info: Entering event queue @ 986241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 958363353000.  Starting simulation...
+info: Entering event queue @ 987241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 959363353000.  Starting simulation...
+info: Entering event queue @ 988241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 960363353000.  Starting simulation...
+info: Entering event queue @ 989241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 961363353000.  Starting simulation...
+info: Entering event queue @ 990241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 962363353000.  Starting simulation...
+info: Entering event queue @ 991241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 963363353000.  Starting simulation...
+info: Entering event queue @ 992241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 964363353000.  Starting simulation...
+info: Entering event queue @ 993241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 965363353000.  Starting simulation...
+info: Entering event queue @ 994241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 966363353000.  Starting simulation...
+info: Entering event queue @ 995241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 967363353000.  Starting simulation...
+info: Entering event queue @ 996241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 968363353000.  Starting simulation...
+info: Entering event queue @ 997241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 969363353000.  Starting simulation...
+info: Entering event queue @ 998241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 970363353000.  Starting simulation...
+info: Entering event queue @ 999241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 971363353000.  Starting simulation...
+info: Entering event queue @ 1000241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 972363353000.  Starting simulation...
+info: Entering event queue @ 1001241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 973363353000.  Starting simulation...
+info: Entering event queue @ 1002241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 974363353000.  Starting simulation...
+info: Entering event queue @ 1003241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 975363353000.  Starting simulation...
+info: Entering event queue @ 1004241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 976363353000.  Starting simulation...
+info: Entering event queue @ 1005241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 977363353000.  Starting simulation...
+info: Entering event queue @ 1006241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 978363353000.  Starting simulation...
+info: Entering event queue @ 1007241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 979363353000.  Starting simulation...
+info: Entering event queue @ 1008241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 980363353000.  Starting simulation...
+info: Entering event queue @ 1009241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 981363353000.  Starting simulation...
+info: Entering event queue @ 1010241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 982363353000.  Starting simulation...
-info: Entering event queue @ 983098914000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 983098916000.  Starting simulation...
+info: Entering event queue @ 1011241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 984098916000.  Starting simulation...
+info: Entering event queue @ 1012241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 985098916000.  Starting simulation...
+info: Entering event queue @ 1013241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 986098916000.  Starting simulation...
+info: Entering event queue @ 1014241993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1015241993000.  Starting simulation...
+info: Entering event queue @ 1016978277250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 987098916000.  Starting simulation...
+info: Entering event queue @ 1016978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 988098916000.  Starting simulation...
+info: Entering event queue @ 1017978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 989098916000.  Starting simulation...
+info: Entering event queue @ 1018978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 990098916000.  Starting simulation...
+info: Entering event queue @ 1019978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 991098916000.  Starting simulation...
+info: Entering event queue @ 1020978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 992098916000.  Starting simulation...
+info: Entering event queue @ 1021978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 993098916000.  Starting simulation...
+info: Entering event queue @ 1022978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 994098916000.  Starting simulation...
+info: Entering event queue @ 1023978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 995098916000.  Starting simulation...
+info: Entering event queue @ 1024978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 996098916000.  Starting simulation...
+info: Entering event queue @ 1025978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 997098916000.  Starting simulation...
+info: Entering event queue @ 1026978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 998098916000.  Starting simulation...
+info: Entering event queue @ 1027978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 999098916000.  Starting simulation...
+info: Entering event queue @ 1028978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1000098916000.  Starting simulation...
+info: Entering event queue @ 1029978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1001098916000.  Starting simulation...
+info: Entering event queue @ 1030978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1002098916000.  Starting simulation...
+info: Entering event queue @ 1031978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1003098916000.  Starting simulation...
+info: Entering event queue @ 1032978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1004098916000.  Starting simulation...
+info: Entering event queue @ 1033978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1005098916000.  Starting simulation...
+info: Entering event queue @ 1034978280000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1035978280000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1006098916000.  Starting simulation...
+info: Entering event queue @ 1035978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1007098916000.  Starting simulation...
+info: Entering event queue @ 1036978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1008098916000.  Starting simulation...
+info: Entering event queue @ 1037978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1009098916000.  Starting simulation...
+info: Entering event queue @ 1038978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1010098916000.  Starting simulation...
+info: Entering event queue @ 1039978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1011098916000.  Starting simulation...
+info: Entering event queue @ 1040978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1012098916000.  Starting simulation...
+info: Entering event queue @ 1041978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1013098916000.  Starting simulation...
+info: Entering event queue @ 1042978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1014098916000.  Starting simulation...
+info: Entering event queue @ 1043978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1015098916000.  Starting simulation...
-info: Entering event queue @ 1015835514000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1015835516000.  Starting simulation...
+info: Entering event queue @ 1044978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1016835516000.  Starting simulation...
+info: Entering event queue @ 1045978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1017835516000.  Starting simulation...
+info: Entering event queue @ 1046978287500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1047978287500.  Starting simulation...
+info: Entering event queue @ 1049714558250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1018835516000.  Starting simulation...
+info: Entering event queue @ 1049714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1019835516000.  Starting simulation...
+info: Entering event queue @ 1050714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1020835516000.  Starting simulation...
+info: Entering event queue @ 1051714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1021835516000.  Starting simulation...
+info: Entering event queue @ 1052714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1022835516000.  Starting simulation...
+info: Entering event queue @ 1053714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1023835516000.  Starting simulation...
+info: Entering event queue @ 1054714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1024835516000.  Starting simulation...
+info: Entering event queue @ 1055714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1025835516000.  Starting simulation...
+info: Entering event queue @ 1056714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1026835516000.  Starting simulation...
+info: Entering event queue @ 1057714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1027835516000.  Starting simulation...
+info: Entering event queue @ 1058714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1028835516000.  Starting simulation...
+info: Entering event queue @ 1059714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1029835516000.  Starting simulation...
+info: Entering event queue @ 1060714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1030835516000.  Starting simulation...
+info: Entering event queue @ 1061714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1031835516000.  Starting simulation...
+info: Entering event queue @ 1062714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1032835516000.  Starting simulation...
+info: Entering event queue @ 1063714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1033835516000.  Starting simulation...
+info: Entering event queue @ 1064714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1034835516000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1034835523500.  Starting simulation...
+info: Entering event queue @ 1065714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1035835523500.  Starting simulation...
+info: Entering event queue @ 1066714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1036835523500.  Starting simulation...
+info: Entering event queue @ 1067714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1037835523500.  Starting simulation...
+info: Entering event queue @ 1068714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1038835523500.  Starting simulation...
+info: Entering event queue @ 1069714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1039835523500.  Starting simulation...
+info: Entering event queue @ 1070714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1040835523500.  Starting simulation...
+info: Entering event queue @ 1071714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1041835523500.  Starting simulation...
+info: Entering event queue @ 1072714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1042835523500.  Starting simulation...
+info: Entering event queue @ 1073714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1043835523500.  Starting simulation...
+info: Entering event queue @ 1074714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1044835523500.  Starting simulation...
+info: Entering event queue @ 1075714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1045835523500.  Starting simulation...
+info: Entering event queue @ 1076714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1046835523500.  Starting simulation...
+info: Entering event queue @ 1077714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1047835523500.  Starting simulation...
-info: Entering event queue @ 1048572135000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1048572137000.  Starting simulation...
+info: Entering event queue @ 1078714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1049572137000.  Starting simulation...
+info: Entering event queue @ 1079714561000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1080714561000.  Starting simulation...
+info: Entering event queue @ 1082450813250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1050572137000.  Starting simulation...
+info: Entering event queue @ 1082450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1051572137000.  Starting simulation...
+info: Entering event queue @ 1083450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1052572137000.  Starting simulation...
+info: Entering event queue @ 1084450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1053572137000.  Starting simulation...
+info: Entering event queue @ 1085450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1054572137000.  Starting simulation...
+info: Entering event queue @ 1086450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1055572137000.  Starting simulation...
+info: Entering event queue @ 1087450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1056572137000.  Starting simulation...
+info: Entering event queue @ 1088450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1057572137000.  Starting simulation...
+info: Entering event queue @ 1089450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1058572137000.  Starting simulation...
+info: Entering event queue @ 1090450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1059572137000.  Starting simulation...
+info: Entering event queue @ 1091450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1060572137000.  Starting simulation...
+info: Entering event queue @ 1092450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1061572137000.  Starting simulation...
+info: Entering event queue @ 1093450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1062572137000.  Starting simulation...
+info: Entering event queue @ 1094450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1063572137000.  Starting simulation...
+info: Entering event queue @ 1095450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1064572137000.  Starting simulation...
+info: Entering event queue @ 1096450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1065572137000.  Starting simulation...
+info: Entering event queue @ 1097450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1066572137000.  Starting simulation...
+info: Entering event queue @ 1098450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1067572137000.  Starting simulation...
+info: Entering event queue @ 1099450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1068572137000.  Starting simulation...
+info: Entering event queue @ 1100450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1069572137000.  Starting simulation...
+info: Entering event queue @ 1101450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1070572137000.  Starting simulation...
+info: Entering event queue @ 1102450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1071572137000.  Starting simulation...
+info: Entering event queue @ 1103450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1072572137000.  Starting simulation...
+info: Entering event queue @ 1104450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1073572137000.  Starting simulation...
+info: Entering event queue @ 1105450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1074572137000.  Starting simulation...
+info: Entering event queue @ 1106450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1075572137000.  Starting simulation...
+info: Entering event queue @ 1107450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1076572137000.  Starting simulation...
+info: Entering event queue @ 1108450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1077572137000.  Starting simulation...
+info: Entering event queue @ 1109450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1078572137000.  Starting simulation...
+info: Entering event queue @ 1110450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1079572137000.  Starting simulation...
+info: Entering event queue @ 1111450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1080572137000.  Starting simulation...
-info: Entering event queue @ 1081307547000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1081307549000.  Starting simulation...
+info: Entering event queue @ 1112450816000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1113450816000.  Starting simulation...
+info: Entering event queue @ 1115187098250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1082307549000.  Starting simulation...
+info: Entering event queue @ 1115187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1083307549000.  Starting simulation...
+info: Entering event queue @ 1116187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1084307549000.  Starting simulation...
+info: Entering event queue @ 1117187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1085307549000.  Starting simulation...
+info: Entering event queue @ 1118187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1086307549000.  Starting simulation...
+info: Entering event queue @ 1119187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1087307549000.  Starting simulation...
+info: Entering event queue @ 1120187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1088307549000.  Starting simulation...
+info: Entering event queue @ 1121187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1089307549000.  Starting simulation...
+info: Entering event queue @ 1122187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1090307549000.  Starting simulation...
+info: Entering event queue @ 1123187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1091307549000.  Starting simulation...
+info: Entering event queue @ 1124187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1092307549000.  Starting simulation...
+info: Entering event queue @ 1125187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1093307549000.  Starting simulation...
+info: Entering event queue @ 1126187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1094307549000.  Starting simulation...
+info: Entering event queue @ 1127187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1095307549000.  Starting simulation...
+info: Entering event queue @ 1128187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1096307549000.  Starting simulation...
+info: Entering event queue @ 1129187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1097307549000.  Starting simulation...
+info: Entering event queue @ 1130187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1098307549000.  Starting simulation...
+info: Entering event queue @ 1131187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1099307549000.  Starting simulation...
+info: Entering event queue @ 1132187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1100307549000.  Starting simulation...
+info: Entering event queue @ 1133187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1101307549000.  Starting simulation...
+info: Entering event queue @ 1134187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1102307549000.  Starting simulation...
+info: Entering event queue @ 1135187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1103307549000.  Starting simulation...
+info: Entering event queue @ 1136187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1104307549000.  Starting simulation...
+info: Entering event queue @ 1137187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1105307549000.  Starting simulation...
+info: Entering event queue @ 1138187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1106307549000.  Starting simulation...
+info: Entering event queue @ 1139187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1107307549000.  Starting simulation...
+info: Entering event queue @ 1140187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1108307549000.  Starting simulation...
+info: Entering event queue @ 1141187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1109307549000.  Starting simulation...
+info: Entering event queue @ 1142187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1110307549000.  Starting simulation...
+info: Entering event queue @ 1143187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1111307549000.  Starting simulation...
+info: Entering event queue @ 1144187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1112307549000.  Starting simulation...
+info: Entering event queue @ 1145187101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1113307549000.  Starting simulation...
-info: Entering event queue @ 1114044147000.  Starting simulation...
+info: Entering event queue @ 1146187101000.  Starting simulation...
+info: Entering event queue @ 1147923385250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1114044149000.  Starting simulation...
+info: Entering event queue @ 1147923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1115044149000.  Starting simulation...
+info: Entering event queue @ 1148923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1116044149000.  Starting simulation...
+info: Entering event queue @ 1149923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1117044149000.  Starting simulation...
+info: Entering event queue @ 1150923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1118044149000.  Starting simulation...
+info: Entering event queue @ 1151923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1119044149000.  Starting simulation...
+info: Entering event queue @ 1152923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1120044149000.  Starting simulation...
+info: Entering event queue @ 1153923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1121044149000.  Starting simulation...
+info: Entering event queue @ 1154923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1122044149000.  Starting simulation...
+info: Entering event queue @ 1155923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1123044149000.  Starting simulation...
+info: Entering event queue @ 1156923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1124044149000.  Starting simulation...
+info: Entering event queue @ 1157923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1125044149000.  Starting simulation...
+info: Entering event queue @ 1158923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1126044149000.  Starting simulation...
+info: Entering event queue @ 1159923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1127044149000.  Starting simulation...
+info: Entering event queue @ 1160923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1128044149000.  Starting simulation...
+info: Entering event queue @ 1161923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1129044149000.  Starting simulation...
+info: Entering event queue @ 1162923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1130044149000.  Starting simulation...
+info: Entering event queue @ 1163923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1131044149000.  Starting simulation...
+info: Entering event queue @ 1164923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1132044149000.  Starting simulation...
+info: Entering event queue @ 1165923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1133044149000.  Starting simulation...
+info: Entering event queue @ 1166923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1134044149000.  Starting simulation...
+info: Entering event queue @ 1167923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1135044149000.  Starting simulation...
+info: Entering event queue @ 1168923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1136044149000.  Starting simulation...
+info: Entering event queue @ 1169923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1137044149000.  Starting simulation...
+info: Entering event queue @ 1170923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1138044149000.  Starting simulation...
+info: Entering event queue @ 1171923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1139044149000.  Starting simulation...
+info: Entering event queue @ 1172923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1140044149000.  Starting simulation...
+info: Entering event queue @ 1173923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1141044149000.  Starting simulation...
+info: Entering event queue @ 1174923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1142044149000.  Starting simulation...
+info: Entering event queue @ 1175923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1143044149000.  Starting simulation...
+info: Entering event queue @ 1176923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1144044149000.  Starting simulation...
+info: Entering event queue @ 1177923388000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1178923388000.  Starting simulation...
+info: Entering event queue @ 1180659666250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1145044149000.  Starting simulation...
+info: Entering event queue @ 1180659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1146044149000.  Starting simulation...
-info: Entering event queue @ 1146780726000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1146780728000.  Starting simulation...
+info: Entering event queue @ 1181659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1147780728000.  Starting simulation...
+info: Entering event queue @ 1182659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1148780728000.  Starting simulation...
+info: Entering event queue @ 1183659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1149780728000.  Starting simulation...
+info: Entering event queue @ 1184659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1150780728000.  Starting simulation...
+info: Entering event queue @ 1185659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1151780728000.  Starting simulation...
+info: Entering event queue @ 1186659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1152780728000.  Starting simulation...
+info: Entering event queue @ 1187659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1153780728000.  Starting simulation...
+info: Entering event queue @ 1188659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1154780728000.  Starting simulation...
+info: Entering event queue @ 1189659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1155780728000.  Starting simulation...
+info: Entering event queue @ 1190659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1156780728000.  Starting simulation...
+info: Entering event queue @ 1191659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1157780728000.  Starting simulation...
+info: Entering event queue @ 1192659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1158780728000.  Starting simulation...
+info: Entering event queue @ 1193659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1159780728000.  Starting simulation...
+info: Entering event queue @ 1194659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1160780728000.  Starting simulation...
+info: Entering event queue @ 1195659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1161780728000.  Starting simulation...
+info: Entering event queue @ 1196659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1162780728000.  Starting simulation...
+info: Entering event queue @ 1197659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1163780728000.  Starting simulation...
+info: Entering event queue @ 1198659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1164780728000.  Starting simulation...
+info: Entering event queue @ 1199659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1165780728000.  Starting simulation...
+info: Entering event queue @ 1200659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1166780728000.  Starting simulation...
+info: Entering event queue @ 1201659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1167780728000.  Starting simulation...
+info: Entering event queue @ 1202659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1168780728000.  Starting simulation...
+info: Entering event queue @ 1203659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1169780728000.  Starting simulation...
+info: Entering event queue @ 1204659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1170780728000.  Starting simulation...
+info: Entering event queue @ 1205659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1171780728000.  Starting simulation...
+info: Entering event queue @ 1206659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1172780728000.  Starting simulation...
+info: Entering event queue @ 1207659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1173780728000.  Starting simulation...
+info: Entering event queue @ 1208659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1174780728000.  Starting simulation...
+info: Entering event queue @ 1209659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1175780728000.  Starting simulation...
+info: Entering event queue @ 1210659669000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1211659669000.  Starting simulation...
+info: Entering event queue @ 1213395918250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1176780728000.  Starting simulation...
+info: Entering event queue @ 1213395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1177780728000.  Starting simulation...
+info: Entering event queue @ 1214395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1178780728000.  Starting simulation...
-info: Entering event queue @ 1179516138000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1179516140000.  Starting simulation...
+info: Entering event queue @ 1215395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1180516140000.  Starting simulation...
+info: Entering event queue @ 1216395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1181516140000.  Starting simulation...
+info: Entering event queue @ 1217395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1182516140000.  Starting simulation...
+info: Entering event queue @ 1218395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1183516140000.  Starting simulation...
+info: Entering event queue @ 1219395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1184516140000.  Starting simulation...
+info: Entering event queue @ 1220395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1185516140000.  Starting simulation...
+info: Entering event queue @ 1221395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1186516140000.  Starting simulation...
+info: Entering event queue @ 1222395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1187516140000.  Starting simulation...
+info: Entering event queue @ 1223395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1188516140000.  Starting simulation...
+info: Entering event queue @ 1224395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1189516140000.  Starting simulation...
+info: Entering event queue @ 1225395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1190516140000.  Starting simulation...
+info: Entering event queue @ 1226395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1191516140000.  Starting simulation...
+info: Entering event queue @ 1227395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1192516140000.  Starting simulation...
+info: Entering event queue @ 1228395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1193516140000.  Starting simulation...
+info: Entering event queue @ 1229395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1194516140000.  Starting simulation...
+info: Entering event queue @ 1230395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1195516140000.  Starting simulation...
+info: Entering event queue @ 1231395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1196516140000.  Starting simulation...
+info: Entering event queue @ 1232395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1197516140000.  Starting simulation...
+info: Entering event queue @ 1233395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1198516140000.  Starting simulation...
+info: Entering event queue @ 1234395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1199516140000.  Starting simulation...
+info: Entering event queue @ 1235395921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1236395921000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1200516140000.  Starting simulation...
+info: Entering event queue @ 1236395928500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1201516140000.  Starting simulation...
+info: Entering event queue @ 1237395928500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1202516140000.  Starting simulation...
+info: Entering event queue @ 1238395928500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1203516140000.  Starting simulation...
+info: Entering event queue @ 1239395928500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1204516140000.  Starting simulation...
+info: Entering event queue @ 1240395928500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1205516140000.  Starting simulation...
+info: Entering event queue @ 1241395928500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1206516140000.  Starting simulation...
+info: Entering event queue @ 1242395928500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1207516140000.  Starting simulation...
+info: Entering event queue @ 1243395928500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1244395928500.  Starting simulation...
+info: Entering event queue @ 1246132202250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1208516140000.  Starting simulation...
+info: Entering event queue @ 1246132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1209516140000.  Starting simulation...
+info: Entering event queue @ 1247132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1210516140000.  Starting simulation...
+info: Entering event queue @ 1248132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1211516140000.  Starting simulation...
-info: Entering event queue @ 1212252738000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1212252740000.  Starting simulation...
+info: Entering event queue @ 1249132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1213252740000.  Starting simulation...
+info: Entering event queue @ 1250132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1214252740000.  Starting simulation...
+info: Entering event queue @ 1251132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1215252740000.  Starting simulation...
+info: Entering event queue @ 1252132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1216252740000.  Starting simulation...
+info: Entering event queue @ 1253132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1217252740000.  Starting simulation...
+info: Entering event queue @ 1254132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1218252740000.  Starting simulation...
+info: Entering event queue @ 1255132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1219252740000.  Starting simulation...
+info: Entering event queue @ 1256132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1220252740000.  Starting simulation...
+info: Entering event queue @ 1257132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1221252740000.  Starting simulation...
+info: Entering event queue @ 1258132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1222252740000.  Starting simulation...
+info: Entering event queue @ 1259132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1223252740000.  Starting simulation...
+info: Entering event queue @ 1260132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1224252740000.  Starting simulation...
+info: Entering event queue @ 1261132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1225252740000.  Starting simulation...
+info: Entering event queue @ 1262132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1226252740000.  Starting simulation...
+info: Entering event queue @ 1263132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1227252740000.  Starting simulation...
+info: Entering event queue @ 1264132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1228252740000.  Starting simulation...
+info: Entering event queue @ 1265132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1229252740000.  Starting simulation...
+info: Entering event queue @ 1266132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1230252740000.  Starting simulation...
+info: Entering event queue @ 1267132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1231252740000.  Starting simulation...
+info: Entering event queue @ 1268132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1232252740000.  Starting simulation...
+info: Entering event queue @ 1269132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1233252740000.  Starting simulation...
+info: Entering event queue @ 1270132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1234252740000.  Starting simulation...
+info: Entering event queue @ 1271132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1235252740000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1235252747500.  Starting simulation...
+info: Entering event queue @ 1272132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1236252747500.  Starting simulation...
+info: Entering event queue @ 1273132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1237252747500.  Starting simulation...
+info: Entering event queue @ 1274132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1238252747500.  Starting simulation...
+info: Entering event queue @ 1275132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1239252747500.  Starting simulation...
+info: Entering event queue @ 1276132205000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1277132205000.  Starting simulation...
+info: Entering event queue @ 1278868486250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1240252747500.  Starting simulation...
+info: Entering event queue @ 1278868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1241252747500.  Starting simulation...
+info: Entering event queue @ 1279868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1242252747500.  Starting simulation...
+info: Entering event queue @ 1280868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1243252747500.  Starting simulation...
+info: Entering event queue @ 1281868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1244252747500.  Starting simulation...
-info: Entering event queue @ 1244989355000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1244989357000.  Starting simulation...
+info: Entering event queue @ 1282868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1245989357000.  Starting simulation...
+info: Entering event queue @ 1283868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1246989357000.  Starting simulation...
+info: Entering event queue @ 1284868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1247989357000.  Starting simulation...
+info: Entering event queue @ 1285868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1248989357000.  Starting simulation...
+info: Entering event queue @ 1286868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1249989357000.  Starting simulation...
+info: Entering event queue @ 1287868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1250989357000.  Starting simulation...
+info: Entering event queue @ 1288868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1251989357000.  Starting simulation...
+info: Entering event queue @ 1289868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1252989357000.  Starting simulation...
+info: Entering event queue @ 1290868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1253989357000.  Starting simulation...
+info: Entering event queue @ 1291868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1254989357000.  Starting simulation...
+info: Entering event queue @ 1292868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1255989357000.  Starting simulation...
+info: Entering event queue @ 1293868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1256989357000.  Starting simulation...
+info: Entering event queue @ 1294868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1257989357000.  Starting simulation...
+info: Entering event queue @ 1295868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1258989357000.  Starting simulation...
+info: Entering event queue @ 1296868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1259989357000.  Starting simulation...
+info: Entering event queue @ 1297868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1260989357000.  Starting simulation...
+info: Entering event queue @ 1298868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1261989357000.  Starting simulation...
+info: Entering event queue @ 1299868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1262989357000.  Starting simulation...
+info: Entering event queue @ 1300868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1263989357000.  Starting simulation...
+info: Entering event queue @ 1301868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1264989357000.  Starting simulation...
+info: Entering event queue @ 1302868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1265989357000.  Starting simulation...
+info: Entering event queue @ 1303868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1266989357000.  Starting simulation...
+info: Entering event queue @ 1304868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1267989357000.  Starting simulation...
+info: Entering event queue @ 1305868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1268989357000.  Starting simulation...
+info: Entering event queue @ 1306868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1269989357000.  Starting simulation...
+info: Entering event queue @ 1307868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1270989357000.  Starting simulation...
+info: Entering event queue @ 1308868489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1309868489000.  Starting simulation...
+info: Entering event queue @ 1311604734250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1271989357000.  Starting simulation...
+info: Entering event queue @ 1311604737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1272989357000.  Starting simulation...
+info: Entering event queue @ 1312604737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1273989357000.  Starting simulation...
+info: Entering event queue @ 1313604737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1274989357000.  Starting simulation...
+info: Entering event queue @ 1314604737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1275989357000.  Starting simulation...
+info: Entering event queue @ 1315604737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1276989357000.  Starting simulation...
-info: Entering event queue @ 1277724922000.  Starting simulation...
+info: Entering event queue @ 1316604737000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1277724924000.  Starting simulation...
+info: Entering event queue @ 1316604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1278724924000.  Starting simulation...
+info: Entering event queue @ 1317604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1279724924000.  Starting simulation...
+info: Entering event queue @ 1318604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1280724924000.  Starting simulation...
+info: Entering event queue @ 1319604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1281724924000.  Starting simulation...
+info: Entering event queue @ 1320604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1282724924000.  Starting simulation...
+info: Entering event queue @ 1321604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1283724924000.  Starting simulation...
+info: Entering event queue @ 1322604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1284724924000.  Starting simulation...
+info: Entering event queue @ 1323604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1285724924000.  Starting simulation...
+info: Entering event queue @ 1324604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1286724924000.  Starting simulation...
+info: Entering event queue @ 1325604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1287724924000.  Starting simulation...
+info: Entering event queue @ 1326604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1288724924000.  Starting simulation...
+info: Entering event queue @ 1327604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1289724924000.  Starting simulation...
+info: Entering event queue @ 1328604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1290724924000.  Starting simulation...
+info: Entering event queue @ 1329604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1291724924000.  Starting simulation...
+info: Entering event queue @ 1330604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1292724924000.  Starting simulation...
+info: Entering event queue @ 1331604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1293724924000.  Starting simulation...
+info: Entering event queue @ 1332604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1294724924000.  Starting simulation...
+info: Entering event queue @ 1333604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1295724924000.  Starting simulation...
+info: Entering event queue @ 1334604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1296724924000.  Starting simulation...
+info: Entering event queue @ 1335604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1297724924000.  Starting simulation...
+info: Entering event queue @ 1336604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1298724924000.  Starting simulation...
+info: Entering event queue @ 1337604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1299724924000.  Starting simulation...
+info: Entering event queue @ 1338604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1300724924000.  Starting simulation...
+info: Entering event queue @ 1339604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1301724924000.  Starting simulation...
+info: Entering event queue @ 1340604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1302724924000.  Starting simulation...
+info: Entering event queue @ 1341604744500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1342604744500.  Starting simulation...
+info: Entering event queue @ 1344341022250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1303724924000.  Starting simulation...
+info: Entering event queue @ 1344341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1304724924000.  Starting simulation...
+info: Entering event queue @ 1345341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1305724924000.  Starting simulation...
+info: Entering event queue @ 1346341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1306724924000.  Starting simulation...
+info: Entering event queue @ 1347341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1307724924000.  Starting simulation...
+info: Entering event queue @ 1348341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1308724924000.  Starting simulation...
+info: Entering event queue @ 1349341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1309724924000.  Starting simulation...
-info: Entering event queue @ 1310461522000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1310461524000.  Starting simulation...
+info: Entering event queue @ 1350341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1311461524000.  Starting simulation...
+info: Entering event queue @ 1351341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1312461524000.  Starting simulation...
+info: Entering event queue @ 1352341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1313461524000.  Starting simulation...
+info: Entering event queue @ 1353341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1314461524000.  Starting simulation...
+info: Entering event queue @ 1354341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1315461524000.  Starting simulation...
+info: Entering event queue @ 1355341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1316461524000.  Starting simulation...
+info: Entering event queue @ 1356341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1317461524000.  Starting simulation...
+info: Entering event queue @ 1357341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1318461524000.  Starting simulation...
+info: Entering event queue @ 1358341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1319461524000.  Starting simulation...
+info: Entering event queue @ 1359341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1320461524000.  Starting simulation...
+info: Entering event queue @ 1360341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1321461524000.  Starting simulation...
+info: Entering event queue @ 1361341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1322461524000.  Starting simulation...
+info: Entering event queue @ 1362341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1323461524000.  Starting simulation...
+info: Entering event queue @ 1363341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1324461524000.  Starting simulation...
+info: Entering event queue @ 1364341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1325461524000.  Starting simulation...
+info: Entering event queue @ 1365341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1326461524000.  Starting simulation...
+info: Entering event queue @ 1366341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1327461524000.  Starting simulation...
+info: Entering event queue @ 1367341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1328461524000.  Starting simulation...
+info: Entering event queue @ 1368341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1329461524000.  Starting simulation...
+info: Entering event queue @ 1369341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1330461524000.  Starting simulation...
+info: Entering event queue @ 1370341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1331461524000.  Starting simulation...
+info: Entering event queue @ 1371341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1332461524000.  Starting simulation...
+info: Entering event queue @ 1372341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1333461524000.  Starting simulation...
+info: Entering event queue @ 1373341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1334461524000.  Starting simulation...
+info: Entering event queue @ 1374341025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1375341025000.  Starting simulation...
+info: Entering event queue @ 1377076990250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1335461524000.  Starting simulation...
+info: Entering event queue @ 1377076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1336461524000.  Starting simulation...
+info: Entering event queue @ 1378076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1337461524000.  Starting simulation...
+info: Entering event queue @ 1379076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1338461524000.  Starting simulation...
+info: Entering event queue @ 1380076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1339461524000.  Starting simulation...
+info: Entering event queue @ 1381076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1340461524000.  Starting simulation...
+info: Entering event queue @ 1382076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1341461524000.  Starting simulation...
+info: Entering event queue @ 1383076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1342461524000.  Starting simulation...
-info: Entering event queue @ 1343198143000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1343198145000.  Starting simulation...
+info: Entering event queue @ 1384076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1344198145000.  Starting simulation...
+info: Entering event queue @ 1385076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1345198145000.  Starting simulation...
+info: Entering event queue @ 1386076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1346198145000.  Starting simulation...
+info: Entering event queue @ 1387076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1347198145000.  Starting simulation...
+info: Entering event queue @ 1388076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1348198145000.  Starting simulation...
+info: Entering event queue @ 1389076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1349198145000.  Starting simulation...
+info: Entering event queue @ 1390076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1350198145000.  Starting simulation...
+info: Entering event queue @ 1391076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1351198145000.  Starting simulation...
+info: Entering event queue @ 1392076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1352198145000.  Starting simulation...
+info: Entering event queue @ 1393076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1353198145000.  Starting simulation...
+info: Entering event queue @ 1394076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1354198145000.  Starting simulation...
+info: Entering event queue @ 1395076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1355198145000.  Starting simulation...
+info: Entering event queue @ 1396076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1356198145000.  Starting simulation...
+info: Entering event queue @ 1397076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1357198145000.  Starting simulation...
+info: Entering event queue @ 1398076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1358198145000.  Starting simulation...
+info: Entering event queue @ 1399076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1359198145000.  Starting simulation...
+info: Entering event queue @ 1400076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1360198145000.  Starting simulation...
+info: Entering event queue @ 1401076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1361198145000.  Starting simulation...
+info: Entering event queue @ 1402076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1362198145000.  Starting simulation...
+info: Entering event queue @ 1403076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1363198145000.  Starting simulation...
+info: Entering event queue @ 1404076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1364198145000.  Starting simulation...
+info: Entering event queue @ 1405076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1365198145000.  Starting simulation...
+info: Entering event queue @ 1406076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1366198145000.  Starting simulation...
+info: Entering event queue @ 1407076993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1408076993000.  Starting simulation...
+info: Entering event queue @ 1409813242250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1367198145000.  Starting simulation...
+info: Entering event queue @ 1409813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1368198145000.  Starting simulation...
+info: Entering event queue @ 1410813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1369198145000.  Starting simulation...
+info: Entering event queue @ 1411813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1370198145000.  Starting simulation...
+info: Entering event queue @ 1412813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1371198145000.  Starting simulation...
+info: Entering event queue @ 1413813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1372198145000.  Starting simulation...
+info: Entering event queue @ 1414813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1373198145000.  Starting simulation...
+info: Entering event queue @ 1415813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1374198145000.  Starting simulation...
+info: Entering event queue @ 1416813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1375198145000.  Starting simulation...
-info: Entering event queue @ 1375934743000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1375934745000.  Starting simulation...
+info: Entering event queue @ 1417813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1376934745000.  Starting simulation...
+info: Entering event queue @ 1418813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1377934745000.  Starting simulation...
+info: Entering event queue @ 1419813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1378934745000.  Starting simulation...
+info: Entering event queue @ 1420813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1379934745000.  Starting simulation...
+info: Entering event queue @ 1421813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1380934745000.  Starting simulation...
+info: Entering event queue @ 1422813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1381934745000.  Starting simulation...
+info: Entering event queue @ 1423813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1382934745000.  Starting simulation...
+info: Entering event queue @ 1424813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1383934745000.  Starting simulation...
+info: Entering event queue @ 1425813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1384934745000.  Starting simulation...
+info: Entering event queue @ 1426813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1385934745000.  Starting simulation...
+info: Entering event queue @ 1427813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1386934745000.  Starting simulation...
+info: Entering event queue @ 1428813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1387934745000.  Starting simulation...
+info: Entering event queue @ 1429813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1388934745000.  Starting simulation...
+info: Entering event queue @ 1430813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1389934745000.  Starting simulation...
+info: Entering event queue @ 1431813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1390934745000.  Starting simulation...
+info: Entering event queue @ 1432813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1391934745000.  Starting simulation...
+info: Entering event queue @ 1433813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1392934745000.  Starting simulation...
+info: Entering event queue @ 1434813245000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1435813245000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1393934745000.  Starting simulation...
+info: Entering event queue @ 1435813252500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1394934745000.  Starting simulation...
+info: Entering event queue @ 1436813252500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1395934745000.  Starting simulation...
+info: Entering event queue @ 1437813252500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1396934745000.  Starting simulation...
+info: Entering event queue @ 1438813252500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1397934745000.  Starting simulation...
+info: Entering event queue @ 1439813252500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1440813252500.  Starting simulation...
+info: Entering event queue @ 1442549529250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1398934745000.  Starting simulation...
+info: Entering event queue @ 1442549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1399934745000.  Starting simulation...
+info: Entering event queue @ 1443549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1400934745000.  Starting simulation...
+info: Entering event queue @ 1444549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1401934745000.  Starting simulation...
+info: Entering event queue @ 1445549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1402934745000.  Starting simulation...
+info: Entering event queue @ 1446549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1403934745000.  Starting simulation...
+info: Entering event queue @ 1447549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1404934745000.  Starting simulation...
+info: Entering event queue @ 1448549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1405934745000.  Starting simulation...
+info: Entering event queue @ 1449549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1406934745000.  Starting simulation...
+info: Entering event queue @ 1450549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1407934745000.  Starting simulation...
-info: Entering event queue @ 1408670155000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1408670157000.  Starting simulation...
+info: Entering event queue @ 1451549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1409670157000.  Starting simulation...
+info: Entering event queue @ 1452549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1410670157000.  Starting simulation...
+info: Entering event queue @ 1453549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1411670157000.  Starting simulation...
+info: Entering event queue @ 1454549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1412670157000.  Starting simulation...
+info: Entering event queue @ 1455549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1413670157000.  Starting simulation...
+info: Entering event queue @ 1456549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1414670157000.  Starting simulation...
+info: Entering event queue @ 1457549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1415670157000.  Starting simulation...
+info: Entering event queue @ 1458549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1416670157000.  Starting simulation...
+info: Entering event queue @ 1459549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1417670157000.  Starting simulation...
+info: Entering event queue @ 1460549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1418670157000.  Starting simulation...
+info: Entering event queue @ 1461549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1419670157000.  Starting simulation...
+info: Entering event queue @ 1462549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1420670157000.  Starting simulation...
+info: Entering event queue @ 1463549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1421670157000.  Starting simulation...
+info: Entering event queue @ 1464549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1422670157000.  Starting simulation...
+info: Entering event queue @ 1465549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1423670157000.  Starting simulation...
+info: Entering event queue @ 1466549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1424670157000.  Starting simulation...
+info: Entering event queue @ 1467549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1425670157000.  Starting simulation...
+info: Entering event queue @ 1468549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1426670157000.  Starting simulation...
+info: Entering event queue @ 1469549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1427670157000.  Starting simulation...
+info: Entering event queue @ 1470549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1428670157000.  Starting simulation...
+info: Entering event queue @ 1471549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1429670157000.  Starting simulation...
+info: Entering event queue @ 1472549532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1473549532000.  Starting simulation...
+info: Entering event queue @ 1475285817250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1430670157000.  Starting simulation...
+info: Entering event queue @ 1475285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1431670157000.  Starting simulation...
+info: Entering event queue @ 1476285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1432670157000.  Starting simulation...
+info: Entering event queue @ 1477285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1433670157000.  Starting simulation...
+info: Entering event queue @ 1478285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1434670157000.  Starting simulation...
+info: Entering event queue @ 1479285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1435670157000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1435670164500.  Starting simulation...
+info: Entering event queue @ 1480285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1436670164500.  Starting simulation...
+info: Entering event queue @ 1481285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1437670164500.  Starting simulation...
+info: Entering event queue @ 1482285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1438670164500.  Starting simulation...
+info: Entering event queue @ 1483285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1439670164500.  Starting simulation...
+info: Entering event queue @ 1484285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1440670164500.  Starting simulation...
-info: Entering event queue @ 1441406755000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1441406757000.  Starting simulation...
+info: Entering event queue @ 1485285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1442406757000.  Starting simulation...
+info: Entering event queue @ 1486285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1443406757000.  Starting simulation...
+info: Entering event queue @ 1487285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1444406757000.  Starting simulation...
+info: Entering event queue @ 1488285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1445406757000.  Starting simulation...
+info: Entering event queue @ 1489285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1446406757000.  Starting simulation...
+info: Entering event queue @ 1490285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1447406757000.  Starting simulation...
+info: Entering event queue @ 1491285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1448406757000.  Starting simulation...
+info: Entering event queue @ 1492285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1449406757000.  Starting simulation...
+info: Entering event queue @ 1493285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1450406757000.  Starting simulation...
+info: Entering event queue @ 1494285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1451406757000.  Starting simulation...
+info: Entering event queue @ 1495285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1452406757000.  Starting simulation...
+info: Entering event queue @ 1496285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1453406757000.  Starting simulation...
+info: Entering event queue @ 1497285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1454406757000.  Starting simulation...
+info: Entering event queue @ 1498285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1455406757000.  Starting simulation...
+info: Entering event queue @ 1499285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1456406757000.  Starting simulation...
+info: Entering event queue @ 1500285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1457406757000.  Starting simulation...
+info: Entering event queue @ 1501285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1458406757000.  Starting simulation...
+info: Entering event queue @ 1502285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1459406757000.  Starting simulation...
+info: Entering event queue @ 1503285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1460406757000.  Starting simulation...
+info: Entering event queue @ 1504285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1461406757000.  Starting simulation...
+info: Entering event queue @ 1505285820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1506285820000.  Starting simulation...
+info: Entering event queue @ 1508022065250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1462406757000.  Starting simulation...
+info: Entering event queue @ 1508022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1463406757000.  Starting simulation...
+info: Entering event queue @ 1509022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1464406757000.  Starting simulation...
+info: Entering event queue @ 1510022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1465406757000.  Starting simulation...
+info: Entering event queue @ 1511022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1466406757000.  Starting simulation...
+info: Entering event queue @ 1512022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1467406757000.  Starting simulation...
+info: Entering event queue @ 1513022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1468406757000.  Starting simulation...
+info: Entering event queue @ 1514022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1469406757000.  Starting simulation...
+info: Entering event queue @ 1515022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1470406757000.  Starting simulation...
+info: Entering event queue @ 1516022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1471406757000.  Starting simulation...
+info: Entering event queue @ 1517022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1472406757000.  Starting simulation...
+info: Entering event queue @ 1518022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1473406757000.  Starting simulation...
-info: Entering event queue @ 1474143334000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1474143336000.  Starting simulation...
+info: Entering event queue @ 1519022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1475143336000.  Starting simulation...
+info: Entering event queue @ 1520022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1476143336000.  Starting simulation...
+info: Entering event queue @ 1521022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1477143336000.  Starting simulation...
+info: Entering event queue @ 1522022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1478143336000.  Starting simulation...
+info: Entering event queue @ 1523022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1479143336000.  Starting simulation...
+info: Entering event queue @ 1524022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1480143336000.  Starting simulation...
+info: Entering event queue @ 1525022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1481143336000.  Starting simulation...
+info: Entering event queue @ 1526022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1482143336000.  Starting simulation...
+info: Entering event queue @ 1527022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1483143336000.  Starting simulation...
+info: Entering event queue @ 1528022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1484143336000.  Starting simulation...
+info: Entering event queue @ 1529022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1485143336000.  Starting simulation...
+info: Entering event queue @ 1530022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1486143336000.  Starting simulation...
+info: Entering event queue @ 1531022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1487143336000.  Starting simulation...
+info: Entering event queue @ 1532022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1488143336000.  Starting simulation...
+info: Entering event queue @ 1533022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1489143336000.  Starting simulation...
+info: Entering event queue @ 1534022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1490143336000.  Starting simulation...
+info: Entering event queue @ 1535022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1491143336000.  Starting simulation...
+info: Entering event queue @ 1536022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1492143336000.  Starting simulation...
+info: Entering event queue @ 1537022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1493143336000.  Starting simulation...
+info: Entering event queue @ 1538022068000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1539022068000.  Starting simulation...
+info: Entering event queue @ 1540758349250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1494143336000.  Starting simulation...
+info: Entering event queue @ 1540758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1495143336000.  Starting simulation...
+info: Entering event queue @ 1541758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1496143336000.  Starting simulation...
+info: Entering event queue @ 1542758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1497143336000.  Starting simulation...
+info: Entering event queue @ 1543758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1498143336000.  Starting simulation...
+info: Entering event queue @ 1544758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1499143336000.  Starting simulation...
+info: Entering event queue @ 1545758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1500143336000.  Starting simulation...
+info: Entering event queue @ 1546758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1501143336000.  Starting simulation...
+info: Entering event queue @ 1547758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1502143336000.  Starting simulation...
+info: Entering event queue @ 1548758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1503143336000.  Starting simulation...
+info: Entering event queue @ 1549758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1504143336000.  Starting simulation...
+info: Entering event queue @ 1550758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1505143336000.  Starting simulation...
+info: Entering event queue @ 1551758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1506143336000.  Starting simulation...
-info: Entering event queue @ 1506878939000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1506878941000.  Starting simulation...
+info: Entering event queue @ 1552758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1507878941000.  Starting simulation...
+info: Entering event queue @ 1553758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1508878941000.  Starting simulation...
+info: Entering event queue @ 1554758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1509878941000.  Starting simulation...
+info: Entering event queue @ 1555758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1510878941000.  Starting simulation...
+info: Entering event queue @ 1556758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1511878941000.  Starting simulation...
+info: Entering event queue @ 1557758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1512878941000.  Starting simulation...
+info: Entering event queue @ 1558758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1513878941000.  Starting simulation...
+info: Entering event queue @ 1559758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1514878941000.  Starting simulation...
+info: Entering event queue @ 1560758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1515878941000.  Starting simulation...
+info: Entering event queue @ 1561758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1516878941000.  Starting simulation...
+info: Entering event queue @ 1562758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1517878941000.  Starting simulation...
+info: Entering event queue @ 1563758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1518878941000.  Starting simulation...
+info: Entering event queue @ 1564758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1519878941000.  Starting simulation...
+info: Entering event queue @ 1565758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1520878941000.  Starting simulation...
+info: Entering event queue @ 1566758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1521878941000.  Starting simulation...
+info: Entering event queue @ 1567758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1522878941000.  Starting simulation...
+info: Entering event queue @ 1568758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1523878941000.  Starting simulation...
+info: Entering event queue @ 1569758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1524878941000.  Starting simulation...
+info: Entering event queue @ 1570758352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1571758352000.  Starting simulation...
+info: Entering event queue @ 1573494637250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1525878941000.  Starting simulation...
+info: Entering event queue @ 1573494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1526878941000.  Starting simulation...
+info: Entering event queue @ 1574494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1527878941000.  Starting simulation...
+info: Entering event queue @ 1575494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1528878941000.  Starting simulation...
+info: Entering event queue @ 1576494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1529878941000.  Starting simulation...
+info: Entering event queue @ 1577494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1530878941000.  Starting simulation...
+info: Entering event queue @ 1578494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1531878941000.  Starting simulation...
+info: Entering event queue @ 1579494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1532878941000.  Starting simulation...
+info: Entering event queue @ 1580494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1533878941000.  Starting simulation...
+info: Entering event queue @ 1581494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1534878941000.  Starting simulation...
+info: Entering event queue @ 1582494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1535878941000.  Starting simulation...
+info: Entering event queue @ 1583494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1536878941000.  Starting simulation...
+info: Entering event queue @ 1584494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1537878941000.  Starting simulation...
+info: Entering event queue @ 1585494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1538878941000.  Starting simulation...
-info: Entering event queue @ 1539615539000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1539615541000.  Starting simulation...
+info: Entering event queue @ 1586494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1540615541000.  Starting simulation...
+info: Entering event queue @ 1587494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1541615541000.  Starting simulation...
+info: Entering event queue @ 1588494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1542615541000.  Starting simulation...
+info: Entering event queue @ 1589494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1543615541000.  Starting simulation...
+info: Entering event queue @ 1590494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1544615541000.  Starting simulation...
+info: Entering event queue @ 1591494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1545615541000.  Starting simulation...
+info: Entering event queue @ 1592494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1546615541000.  Starting simulation...
+info: Entering event queue @ 1593494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1547615541000.  Starting simulation...
+info: Entering event queue @ 1594494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1548615541000.  Starting simulation...
+info: Entering event queue @ 1595494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1549615541000.  Starting simulation...
+info: Entering event queue @ 1596494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1550615541000.  Starting simulation...
+info: Entering event queue @ 1597494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1551615541000.  Starting simulation...
+info: Entering event queue @ 1598494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1552615541000.  Starting simulation...
+info: Entering event queue @ 1599494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1553615541000.  Starting simulation...
+info: Entering event queue @ 1600494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1554615541000.  Starting simulation...
+info: Entering event queue @ 1601494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1555615541000.  Starting simulation...
+info: Entering event queue @ 1602494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1556615541000.  Starting simulation...
+info: Entering event queue @ 1603494640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1604494640000.  Starting simulation...
+info: Entering event queue @ 1606230882250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1557615541000.  Starting simulation...
+info: Entering event queue @ 1606230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1558615541000.  Starting simulation...
+info: Entering event queue @ 1607230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1559615541000.  Starting simulation...
+info: Entering event queue @ 1608230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1560615541000.  Starting simulation...
+info: Entering event queue @ 1609230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1561615541000.  Starting simulation...
+info: Entering event queue @ 1610230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1562615541000.  Starting simulation...
+info: Entering event queue @ 1611230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1563615541000.  Starting simulation...
+info: Entering event queue @ 1612230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1564615541000.  Starting simulation...
+info: Entering event queue @ 1613230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1565615541000.  Starting simulation...
+info: Entering event queue @ 1614230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1566615541000.  Starting simulation...
+info: Entering event queue @ 1615230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1567615541000.  Starting simulation...
+info: Entering event queue @ 1616230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1568615541000.  Starting simulation...
+info: Entering event queue @ 1617230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1569615541000.  Starting simulation...
+info: Entering event queue @ 1618230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1570615541000.  Starting simulation...
+info: Entering event queue @ 1619230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1571615541000.  Starting simulation...
-info: Entering event queue @ 1572352118000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1572352120000.  Starting simulation...
+info: Entering event queue @ 1620230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1573352120000.  Starting simulation...
+info: Entering event queue @ 1621230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1574352120000.  Starting simulation...
+info: Entering event queue @ 1622230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1575352120000.  Starting simulation...
+info: Entering event queue @ 1623230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1576352120000.  Starting simulation...
+info: Entering event queue @ 1624230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1577352120000.  Starting simulation...
+info: Entering event queue @ 1625230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1578352120000.  Starting simulation...
+info: Entering event queue @ 1626230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1579352120000.  Starting simulation...
+info: Entering event queue @ 1627230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1580352120000.  Starting simulation...
+info: Entering event queue @ 1628230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1581352120000.  Starting simulation...
+info: Entering event queue @ 1629230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1582352120000.  Starting simulation...
+info: Entering event queue @ 1630230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1583352120000.  Starting simulation...
+info: Entering event queue @ 1631230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1584352120000.  Starting simulation...
+info: Entering event queue @ 1632230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1585352120000.  Starting simulation...
+info: Entering event queue @ 1633230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1586352120000.  Starting simulation...
+info: Entering event queue @ 1634230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1587352120000.  Starting simulation...
+info: Entering event queue @ 1635230885000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1636230885000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1588352120000.  Starting simulation...
+info: Entering event queue @ 1636230892500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1637230892500.  Starting simulation...
+info: Entering event queue @ 1638967170250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1589352120000.  Starting simulation...
+info: Entering event queue @ 1638967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1590352120000.  Starting simulation...
+info: Entering event queue @ 1639967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1591352120000.  Starting simulation...
+info: Entering event queue @ 1640967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1592352120000.  Starting simulation...
+info: Entering event queue @ 1641967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1593352120000.  Starting simulation...
+info: Entering event queue @ 1642967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1594352120000.  Starting simulation...
+info: Entering event queue @ 1643967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1595352120000.  Starting simulation...
+info: Entering event queue @ 1644967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1596352120000.  Starting simulation...
+info: Entering event queue @ 1645967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1597352120000.  Starting simulation...
+info: Entering event queue @ 1646967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1598352120000.  Starting simulation...
+info: Entering event queue @ 1647967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1599352120000.  Starting simulation...
+info: Entering event queue @ 1648967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1600352120000.  Starting simulation...
+info: Entering event queue @ 1649967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1601352120000.  Starting simulation...
+info: Entering event queue @ 1650967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1602352120000.  Starting simulation...
+info: Entering event queue @ 1651967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1603352120000.  Starting simulation...
+info: Entering event queue @ 1652967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1604352120000.  Starting simulation...
-info: Entering event queue @ 1605087530000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1605087532000.  Starting simulation...
+info: Entering event queue @ 1653967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1606087532000.  Starting simulation...
+info: Entering event queue @ 1654967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1607087532000.  Starting simulation...
+info: Entering event queue @ 1655967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1608087532000.  Starting simulation...
+info: Entering event queue @ 1656967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1609087532000.  Starting simulation...
+info: Entering event queue @ 1657967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1610087532000.  Starting simulation...
+info: Entering event queue @ 1658967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1611087532000.  Starting simulation...
+info: Entering event queue @ 1659967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1612087532000.  Starting simulation...
+info: Entering event queue @ 1660967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1613087532000.  Starting simulation...
+info: Entering event queue @ 1661967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1614087532000.  Starting simulation...
+info: Entering event queue @ 1662967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1615087532000.  Starting simulation...
+info: Entering event queue @ 1663967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1616087532000.  Starting simulation...
+info: Entering event queue @ 1664967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1617087532000.  Starting simulation...
+info: Entering event queue @ 1665967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1618087532000.  Starting simulation...
+info: Entering event queue @ 1666967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1619087532000.  Starting simulation...
+info: Entering event queue @ 1667967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1620087532000.  Starting simulation...
+info: Entering event queue @ 1668967173000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1669967173000.  Starting simulation...
+info: Entering event queue @ 1671703454250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1621087532000.  Starting simulation...
+info: Entering event queue @ 1671703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1622087532000.  Starting simulation...
+info: Entering event queue @ 1672703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1623087532000.  Starting simulation...
+info: Entering event queue @ 1673703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1624087532000.  Starting simulation...
+info: Entering event queue @ 1674703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1625087532000.  Starting simulation...
+info: Entering event queue @ 1675703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1626087532000.  Starting simulation...
+info: Entering event queue @ 1676703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1627087532000.  Starting simulation...
+info: Entering event queue @ 1677703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1628087532000.  Starting simulation...
+info: Entering event queue @ 1678703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1629087532000.  Starting simulation...
+info: Entering event queue @ 1679703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1630087532000.  Starting simulation...
+info: Entering event queue @ 1680703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1631087532000.  Starting simulation...
+info: Entering event queue @ 1681703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1632087532000.  Starting simulation...
+info: Entering event queue @ 1682703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1633087532000.  Starting simulation...
+info: Entering event queue @ 1683703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1634087532000.  Starting simulation...
+info: Entering event queue @ 1684703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1635087532000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1635087539500.  Starting simulation...
+info: Entering event queue @ 1685703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1636087539500.  Starting simulation...
+info: Entering event queue @ 1686703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1637087539500.  Starting simulation...
-info: Entering event queue @ 1637824130000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1637824132000.  Starting simulation...
+info: Entering event queue @ 1687703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1638824132000.  Starting simulation...
+info: Entering event queue @ 1688703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1639824132000.  Starting simulation...
+info: Entering event queue @ 1689703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1640824132000.  Starting simulation...
+info: Entering event queue @ 1690703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1641824132000.  Starting simulation...
+info: Entering event queue @ 1691703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1642824132000.  Starting simulation...
+info: Entering event queue @ 1692703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1643824132000.  Starting simulation...
+info: Entering event queue @ 1693703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1644824132000.  Starting simulation...
+info: Entering event queue @ 1694703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1645824132000.  Starting simulation...
+info: Entering event queue @ 1695703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1646824132000.  Starting simulation...
+info: Entering event queue @ 1696703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1647824132000.  Starting simulation...
+info: Entering event queue @ 1697703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1648824132000.  Starting simulation...
+info: Entering event queue @ 1698703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1649824132000.  Starting simulation...
+info: Entering event queue @ 1699703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1650824132000.  Starting simulation...
+info: Entering event queue @ 1700703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1651824132000.  Starting simulation...
+info: Entering event queue @ 1701703457000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1702703457000.  Starting simulation...
+info: Entering event queue @ 1704439738250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1652824132000.  Starting simulation...
+info: Entering event queue @ 1704439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1653824132000.  Starting simulation...
+info: Entering event queue @ 1705439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1654824132000.  Starting simulation...
+info: Entering event queue @ 1706439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1655824132000.  Starting simulation...
+info: Entering event queue @ 1707439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1656824132000.  Starting simulation...
+info: Entering event queue @ 1708439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1657824132000.  Starting simulation...
+info: Entering event queue @ 1709439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1658824132000.  Starting simulation...
+info: Entering event queue @ 1710439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1659824132000.  Starting simulation...
+info: Entering event queue @ 1711439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1660824132000.  Starting simulation...
+info: Entering event queue @ 1712439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1661824132000.  Starting simulation...
+info: Entering event queue @ 1713439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1662824132000.  Starting simulation...
+info: Entering event queue @ 1714439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1663824132000.  Starting simulation...
+info: Entering event queue @ 1715439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1664824132000.  Starting simulation...
+info: Entering event queue @ 1716439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1665824132000.  Starting simulation...
+info: Entering event queue @ 1717439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1666824132000.  Starting simulation...
+info: Entering event queue @ 1718439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1667824132000.  Starting simulation...
+info: Entering event queue @ 1719439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1668824132000.  Starting simulation...
+info: Entering event queue @ 1720439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1669824132000.  Starting simulation...
-info: Entering event queue @ 1670560751000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1670560753000.  Starting simulation...
+info: Entering event queue @ 1721439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1671560753000.  Starting simulation...
+info: Entering event queue @ 1722439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1672560753000.  Starting simulation...
+info: Entering event queue @ 1723439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1673560753000.  Starting simulation...
+info: Entering event queue @ 1724439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1674560753000.  Starting simulation...
+info: Entering event queue @ 1725439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1675560753000.  Starting simulation...
+info: Entering event queue @ 1726439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1676560753000.  Starting simulation...
+info: Entering event queue @ 1727439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1677560753000.  Starting simulation...
+info: Entering event queue @ 1728439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1678560753000.  Starting simulation...
+info: Entering event queue @ 1729439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1679560753000.  Starting simulation...
+info: Entering event queue @ 1730439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1680560753000.  Starting simulation...
+info: Entering event queue @ 1731439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1681560753000.  Starting simulation...
+info: Entering event queue @ 1732439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1682560753000.  Starting simulation...
+info: Entering event queue @ 1733439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1683560753000.  Starting simulation...
+info: Entering event queue @ 1734439741000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1735439741000.  Starting simulation...
+info: Entering event queue @ 1737175990250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1684560753000.  Starting simulation...
+info: Entering event queue @ 1737175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1685560753000.  Starting simulation...
+info: Entering event queue @ 1738175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1686560753000.  Starting simulation...
+info: Entering event queue @ 1739175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1687560753000.  Starting simulation...
+info: Entering event queue @ 1740175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1688560753000.  Starting simulation...
+info: Entering event queue @ 1741175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1689560753000.  Starting simulation...
+info: Entering event queue @ 1742175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1690560753000.  Starting simulation...
+info: Entering event queue @ 1743175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1691560753000.  Starting simulation...
+info: Entering event queue @ 1744175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1692560753000.  Starting simulation...
+info: Entering event queue @ 1745175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1693560753000.  Starting simulation...
+info: Entering event queue @ 1746175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1694560753000.  Starting simulation...
+info: Entering event queue @ 1747175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1695560753000.  Starting simulation...
+info: Entering event queue @ 1748175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1696560753000.  Starting simulation...
+info: Entering event queue @ 1749175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1697560753000.  Starting simulation...
+info: Entering event queue @ 1750175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1698560753000.  Starting simulation...
+info: Entering event queue @ 1751175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1699560753000.  Starting simulation...
+info: Entering event queue @ 1752175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1700560753000.  Starting simulation...
+info: Entering event queue @ 1753175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1701560753000.  Starting simulation...
+info: Entering event queue @ 1754175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1702560753000.  Starting simulation...
-info: Entering event queue @ 1703297351000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1703297353000.  Starting simulation...
+info: Entering event queue @ 1755175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1704297353000.  Starting simulation...
+info: Entering event queue @ 1756175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1705297353000.  Starting simulation...
+info: Entering event queue @ 1757175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1706297353000.  Starting simulation...
+info: Entering event queue @ 1758175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1707297353000.  Starting simulation...
+info: Entering event queue @ 1759175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1708297353000.  Starting simulation...
+info: Entering event queue @ 1760175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1709297353000.  Starting simulation...
+info: Entering event queue @ 1761175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1710297353000.  Starting simulation...
+info: Entering event queue @ 1762175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1711297353000.  Starting simulation...
+info: Entering event queue @ 1763175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1712297353000.  Starting simulation...
+info: Entering event queue @ 1764175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1713297353000.  Starting simulation...
+info: Entering event queue @ 1765175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1714297353000.  Starting simulation...
+info: Entering event queue @ 1766175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1715297353000.  Starting simulation...
+info: Entering event queue @ 1767175993000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1768175993000.  Starting simulation...
+info: Entering event queue @ 1769912274250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1716297353000.  Starting simulation...
+info: Entering event queue @ 1769912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1717297353000.  Starting simulation...
+info: Entering event queue @ 1770912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1718297353000.  Starting simulation...
+info: Entering event queue @ 1771912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1719297353000.  Starting simulation...
+info: Entering event queue @ 1772912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1720297353000.  Starting simulation...
+info: Entering event queue @ 1773912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1721297353000.  Starting simulation...
+info: Entering event queue @ 1774912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1722297353000.  Starting simulation...
+info: Entering event queue @ 1775912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1723297353000.  Starting simulation...
+info: Entering event queue @ 1776912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1724297353000.  Starting simulation...
+info: Entering event queue @ 1777912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1725297353000.  Starting simulation...
+info: Entering event queue @ 1778912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1726297353000.  Starting simulation...
+info: Entering event queue @ 1779912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1727297353000.  Starting simulation...
+info: Entering event queue @ 1780912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1728297353000.  Starting simulation...
+info: Entering event queue @ 1781912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1729297353000.  Starting simulation...
+info: Entering event queue @ 1782912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1730297353000.  Starting simulation...
+info: Entering event queue @ 1783912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1731297353000.  Starting simulation...
+info: Entering event queue @ 1784912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1732297353000.  Starting simulation...
+info: Entering event queue @ 1785912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1733297353000.  Starting simulation...
+info: Entering event queue @ 1786912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1734297353000.  Starting simulation...
+info: Entering event queue @ 1787912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1735297353000.  Starting simulation...
-info: Entering event queue @ 1736032914000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1736032916000.  Starting simulation...
+info: Entering event queue @ 1788912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1737032916000.  Starting simulation...
+info: Entering event queue @ 1789912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1738032916000.  Starting simulation...
+info: Entering event queue @ 1790912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1739032916000.  Starting simulation...
+info: Entering event queue @ 1791912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1740032916000.  Starting simulation...
+info: Entering event queue @ 1792912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1741032916000.  Starting simulation...
+info: Entering event queue @ 1793912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1742032916000.  Starting simulation...
+info: Entering event queue @ 1794912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1743032916000.  Starting simulation...
+info: Entering event queue @ 1795912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1744032916000.  Starting simulation...
+info: Entering event queue @ 1796912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1745032916000.  Starting simulation...
+info: Entering event queue @ 1797912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1746032916000.  Starting simulation...
+info: Entering event queue @ 1798912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1747032916000.  Starting simulation...
+info: Entering event queue @ 1799912277000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1800912277000.  Starting simulation...
+info: Entering event queue @ 1802648565250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1748032916000.  Starting simulation...
+info: Entering event queue @ 1802648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1749032916000.  Starting simulation...
+info: Entering event queue @ 1803648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1750032916000.  Starting simulation...
+info: Entering event queue @ 1804648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1751032916000.  Starting simulation...
+info: Entering event queue @ 1805648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1752032916000.  Starting simulation...
+info: Entering event queue @ 1806648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1753032916000.  Starting simulation...
+info: Entering event queue @ 1807648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1754032916000.  Starting simulation...
+info: Entering event queue @ 1808648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1755032916000.  Starting simulation...
+info: Entering event queue @ 1809648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1756032916000.  Starting simulation...
+info: Entering event queue @ 1810648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1757032916000.  Starting simulation...
+info: Entering event queue @ 1811648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1758032916000.  Starting simulation...
+info: Entering event queue @ 1812648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1759032916000.  Starting simulation...
+info: Entering event queue @ 1813648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1760032916000.  Starting simulation...
+info: Entering event queue @ 1814648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1761032916000.  Starting simulation...
+info: Entering event queue @ 1815648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1762032916000.  Starting simulation...
+info: Entering event queue @ 1816648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1763032916000.  Starting simulation...
+info: Entering event queue @ 1817648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1764032916000.  Starting simulation...
+info: Entering event queue @ 1818648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1765032916000.  Starting simulation...
+info: Entering event queue @ 1819648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1766032916000.  Starting simulation...
+info: Entering event queue @ 1820648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1767032916000.  Starting simulation...
+info: Entering event queue @ 1821648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1768032916000.  Starting simulation...
-info: Entering event queue @ 1768769514000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1768769516000.  Starting simulation...
+info: Entering event queue @ 1822648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1769769516000.  Starting simulation...
+info: Entering event queue @ 1823648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1770769516000.  Starting simulation...
+info: Entering event queue @ 1824648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1771769516000.  Starting simulation...
+info: Entering event queue @ 1825648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1772769516000.  Starting simulation...
+info: Entering event queue @ 1826648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1773769516000.  Starting simulation...
+info: Entering event queue @ 1827648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1774769516000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1774769517000.  Starting simulation...
+info: Entering event queue @ 1828648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1775769517000.  Starting simulation...
+info: Entering event queue @ 1829648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1776769517000.  Starting simulation...
+info: Entering event queue @ 1830648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1777769517000.  Starting simulation...
+info: Entering event queue @ 1831648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1778769517000.  Starting simulation...
+info: Entering event queue @ 1832648568000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1833648568000.  Starting simulation...
+info: Entering event queue @ 1835384810250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1779769517000.  Starting simulation...
+info: Entering event queue @ 1835384813000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1836384813000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1780769517000.  Starting simulation...
+info: Entering event queue @ 1836384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1781769517000.  Starting simulation...
+info: Entering event queue @ 1837384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1782769517000.  Starting simulation...
+info: Entering event queue @ 1838384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1783769517000.  Starting simulation...
+info: Entering event queue @ 1839384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1784769517000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1784769518000.  Starting simulation...
+info: Entering event queue @ 1840384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1785769518000.  Starting simulation...
+info: Entering event queue @ 1841384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1786769518000.  Starting simulation...
+info: Entering event queue @ 1842384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1787769518000.  Starting simulation...
+info: Entering event queue @ 1843384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1788769518000.  Starting simulation...
+info: Entering event queue @ 1844384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1789769518000.  Starting simulation...
+info: Entering event queue @ 1845384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1790769518000.  Starting simulation...
+info: Entering event queue @ 1846384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1791769518000.  Starting simulation...
+info: Entering event queue @ 1847384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1792769518000.  Starting simulation...
+info: Entering event queue @ 1848384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1793769518000.  Starting simulation...
+info: Entering event queue @ 1849384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1794769518000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1794769519000.  Starting simulation...
+info: Entering event queue @ 1850384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1795769519000.  Starting simulation...
+info: Entering event queue @ 1851384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1796769519000.  Starting simulation...
+info: Entering event queue @ 1852384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1797769519000.  Starting simulation...
+info: Entering event queue @ 1853384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1798769519000.  Starting simulation...
+info: Entering event queue @ 1854384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1799769519000.  Starting simulation...
+info: Entering event queue @ 1855384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1800769519000.  Starting simulation...
-info: Entering event queue @ 1801506135000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1801506137000.  Starting simulation...
+info: Entering event queue @ 1856384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1802506137000.  Starting simulation...
+info: Entering event queue @ 1857384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1803506137000.  Starting simulation...
+info: Entering event queue @ 1858384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1804506137000.  Starting simulation...
+info: Entering event queue @ 1859384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1805506137000.  Starting simulation...
+info: Entering event queue @ 1860384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1806506137000.  Starting simulation...
+info: Entering event queue @ 1861384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1807506137000.  Starting simulation...
+info: Entering event queue @ 1862384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1808506137000.  Starting simulation...
+info: Entering event queue @ 1863384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1809506137000.  Starting simulation...
+info: Entering event queue @ 1864384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1810506137000.  Starting simulation...
+info: Entering event queue @ 1865384820500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1866384820500.  Starting simulation...
+info: Entering event queue @ 1868121097250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1811506137000.  Starting simulation...
+info: Entering event queue @ 1868121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1812506137000.  Starting simulation...
+info: Entering event queue @ 1869121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1813506137000.  Starting simulation...
+info: Entering event queue @ 1870121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1814506137000.  Starting simulation...
+info: Entering event queue @ 1871121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1815506137000.  Starting simulation...
+info: Entering event queue @ 1872121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1816506137000.  Starting simulation...
+info: Entering event queue @ 1873121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1817506137000.  Starting simulation...
+info: Entering event queue @ 1874121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1818506137000.  Starting simulation...
+info: Entering event queue @ 1875121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1819506137000.  Starting simulation...
+info: Entering event queue @ 1876121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1820506137000.  Starting simulation...
+info: Entering event queue @ 1877121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1821506137000.  Starting simulation...
+info: Entering event queue @ 1878121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1822506137000.  Starting simulation...
+info: Entering event queue @ 1879121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1823506137000.  Starting simulation...
+info: Entering event queue @ 1880121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1824506137000.  Starting simulation...
+info: Entering event queue @ 1881121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1825506137000.  Starting simulation...
+info: Entering event queue @ 1882121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1826506137000.  Starting simulation...
+info: Entering event queue @ 1883121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1827506137000.  Starting simulation...
+info: Entering event queue @ 1884121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1828506137000.  Starting simulation...
+info: Entering event queue @ 1885121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1829506137000.  Starting simulation...
+info: Entering event queue @ 1886121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1830506137000.  Starting simulation...
+info: Entering event queue @ 1887121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1831506137000.  Starting simulation...
+info: Entering event queue @ 1888121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1832506137000.  Starting simulation...
+info: Entering event queue @ 1889121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1833506137000.  Starting simulation...
-info: Entering event queue @ 1834241547000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1834241549000.  Starting simulation...
+info: Entering event queue @ 1890121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1835241549000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1835241556500.  Starting simulation...
+info: Entering event queue @ 1891121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1836241556500.  Starting simulation...
+info: Entering event queue @ 1892121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1837241556500.  Starting simulation...
+info: Entering event queue @ 1893121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1838241556500.  Starting simulation...
+info: Entering event queue @ 1894121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1839241556500.  Starting simulation...
+info: Entering event queue @ 1895121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1840241556500.  Starting simulation...
+info: Entering event queue @ 1896121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1841241556500.  Starting simulation...
+info: Entering event queue @ 1897121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1842241556500.  Starting simulation...
+info: Entering event queue @ 1898121100000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1899121100000.  Starting simulation...
+info: Entering event queue @ 1900857382250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1843241556500.  Starting simulation...
+info: Entering event queue @ 1900857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1844241556500.  Starting simulation...
+info: Entering event queue @ 1901857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1845241556500.  Starting simulation...
+info: Entering event queue @ 1902857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1846241556500.  Starting simulation...
+info: Entering event queue @ 1903857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1847241556500.  Starting simulation...
+info: Entering event queue @ 1904857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1848241556500.  Starting simulation...
+info: Entering event queue @ 1905857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1849241556500.  Starting simulation...
+info: Entering event queue @ 1906857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1850241556500.  Starting simulation...
+info: Entering event queue @ 1907857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1851241556500.  Starting simulation...
+info: Entering event queue @ 1908857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1852241556500.  Starting simulation...
+info: Entering event queue @ 1909857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1853241556500.  Starting simulation...
+info: Entering event queue @ 1910857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1854241556500.  Starting simulation...
+info: Entering event queue @ 1911857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1855241556500.  Starting simulation...
+info: Entering event queue @ 1912857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1856241556500.  Starting simulation...
+info: Entering event queue @ 1913857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1857241556500.  Starting simulation...
+info: Entering event queue @ 1914857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1858241556500.  Starting simulation...
+info: Entering event queue @ 1915857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1859241556500.  Starting simulation...
+info: Entering event queue @ 1916857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1860241556500.  Starting simulation...
+info: Entering event queue @ 1917857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1861241556500.  Starting simulation...
+info: Entering event queue @ 1918857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1862241556500.  Starting simulation...
+info: Entering event queue @ 1919857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1863241556500.  Starting simulation...
+info: Entering event queue @ 1920857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1864241556500.  Starting simulation...
+info: Entering event queue @ 1921857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1865241556500.  Starting simulation...
+info: Entering event queue @ 1922857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1866241556500.  Starting simulation...
-info: Entering event queue @ 1866978147000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1866978149000.  Starting simulation...
+info: Entering event queue @ 1923857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1867978149000.  Starting simulation...
+info: Entering event queue @ 1924857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1868978149000.  Starting simulation...
+info: Entering event queue @ 1925857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1869978149000.  Starting simulation...
+info: Entering event queue @ 1926857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1870978149000.  Starting simulation...
+info: Entering event queue @ 1927857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1871978149000.  Starting simulation...
+info: Entering event queue @ 1928857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1872978149000.  Starting simulation...
+info: Entering event queue @ 1929857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1873978149000.  Starting simulation...
+info: Entering event queue @ 1930857385000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1931857385000.  Starting simulation...
+info: Entering event queue @ 1933593673250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1874978149000.  Starting simulation...
+info: Entering event queue @ 1933593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1875978149000.  Starting simulation...
+info: Entering event queue @ 1934593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1876978149000.  Starting simulation...
+info: Entering event queue @ 1935593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1877978149000.  Starting simulation...
+info: Entering event queue @ 1936593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1878978149000.  Starting simulation...
+info: Entering event queue @ 1937593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1879978149000.  Starting simulation...
+info: Entering event queue @ 1938593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1880978149000.  Starting simulation...
+info: Entering event queue @ 1939593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1881978149000.  Starting simulation...
+info: Entering event queue @ 1940593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1882978149000.  Starting simulation...
+info: Entering event queue @ 1941593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1883978149000.  Starting simulation...
+info: Entering event queue @ 1942593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1884978149000.  Starting simulation...
+info: Entering event queue @ 1943593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1885978149000.  Starting simulation...
+info: Entering event queue @ 1944593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1886978149000.  Starting simulation...
+info: Entering event queue @ 1945593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1887978149000.  Starting simulation...
+info: Entering event queue @ 1946593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1888978149000.  Starting simulation...
+info: Entering event queue @ 1947593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1889978149000.  Starting simulation...
+info: Entering event queue @ 1948593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1890978149000.  Starting simulation...
+info: Entering event queue @ 1949593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1891978149000.  Starting simulation...
+info: Entering event queue @ 1950593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1892978149000.  Starting simulation...
+info: Entering event queue @ 1951593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1893978149000.  Starting simulation...
+info: Entering event queue @ 1952593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1894978149000.  Starting simulation...
+info: Entering event queue @ 1953593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1895978149000.  Starting simulation...
+info: Entering event queue @ 1954593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1896978149000.  Starting simulation...
+info: Entering event queue @ 1955593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1897978149000.  Starting simulation...
+info: Entering event queue @ 1956593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1898978149000.  Starting simulation...
-info: Entering event queue @ 1899714726000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1899714728000.  Starting simulation...
+info: Entering event queue @ 1957593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1900714728000.  Starting simulation...
+info: Entering event queue @ 1958593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1901714728000.  Starting simulation...
+info: Entering event queue @ 1959593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1902714728000.  Starting simulation...
+info: Entering event queue @ 1960593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1903714728000.  Starting simulation...
+info: Entering event queue @ 1961593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1904714728000.  Starting simulation...
+info: Entering event queue @ 1962593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1905714728000.  Starting simulation...
+info: Entering event queue @ 1963593676000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1964593676000.  Starting simulation...
+info: Entering event queue @ 1966329918250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1906714728000.  Starting simulation...
+info: Entering event queue @ 1966329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1907714728000.  Starting simulation...
+info: Entering event queue @ 1967329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1908714728000.  Starting simulation...
+info: Entering event queue @ 1968329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1909714728000.  Starting simulation...
+info: Entering event queue @ 1969329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1910714728000.  Starting simulation...
+info: Entering event queue @ 1970329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1911714728000.  Starting simulation...
+info: Entering event queue @ 1971329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1912714728000.  Starting simulation...
+info: Entering event queue @ 1972329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1913714728000.  Starting simulation...
+info: Entering event queue @ 1973329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1914714728000.  Starting simulation...
+info: Entering event queue @ 1974329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1915714728000.  Starting simulation...
+info: Entering event queue @ 1975329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1916714728000.  Starting simulation...
+info: Entering event queue @ 1976329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1917714728000.  Starting simulation...
+info: Entering event queue @ 1977329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1918714728000.  Starting simulation...
+info: Entering event queue @ 1978329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1919714728000.  Starting simulation...
+info: Entering event queue @ 1979329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1920714728000.  Starting simulation...
+info: Entering event queue @ 1980329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1921714728000.  Starting simulation...
+info: Entering event queue @ 1981329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1922714728000.  Starting simulation...
+info: Entering event queue @ 1982329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1923714728000.  Starting simulation...
+info: Entering event queue @ 1983329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1924714728000.  Starting simulation...
+info: Entering event queue @ 1984329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1925714728000.  Starting simulation...
+info: Entering event queue @ 1985329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1926714728000.  Starting simulation...
+info: Entering event queue @ 1986329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1927714728000.  Starting simulation...
+info: Entering event queue @ 1987329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1928714728000.  Starting simulation...
+info: Entering event queue @ 1988329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1929714728000.  Starting simulation...
+info: Entering event queue @ 1989329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1930714728000.  Starting simulation...
+info: Entering event queue @ 1990329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1931714728000.  Starting simulation...
-info: Entering event queue @ 1932450138000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1932450140000.  Starting simulation...
+info: Entering event queue @ 1991329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1933450140000.  Starting simulation...
+info: Entering event queue @ 1992329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1934450140000.  Starting simulation...
+info: Entering event queue @ 1993329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1935450140000.  Starting simulation...
+info: Entering event queue @ 1994329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1936450140000.  Starting simulation...
+info: Entering event queue @ 1995329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1937450140000.  Starting simulation...
+info: Entering event queue @ 1996329921000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1997329921000.  Starting simulation...
+info: Entering event queue @ 1999066205250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1938450140000.  Starting simulation...
+info: Entering event queue @ 1999066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1939450140000.  Starting simulation...
+info: Entering event queue @ 2000066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1940450140000.  Starting simulation...
+info: Entering event queue @ 2001066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1941450140000.  Starting simulation...
+info: Entering event queue @ 2002066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1942450140000.  Starting simulation...
+info: Entering event queue @ 2003066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1943450140000.  Starting simulation...
+info: Entering event queue @ 2004066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1944450140000.  Starting simulation...
+info: Entering event queue @ 2005066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1945450140000.  Starting simulation...
+info: Entering event queue @ 2006066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1946450140000.  Starting simulation...
+info: Entering event queue @ 2007066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1947450140000.  Starting simulation...
+info: Entering event queue @ 2008066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1948450140000.  Starting simulation...
+info: Entering event queue @ 2009066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1949450140000.  Starting simulation...
+info: Entering event queue @ 2010066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1950450140000.  Starting simulation...
+info: Entering event queue @ 2011066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1951450140000.  Starting simulation...
+info: Entering event queue @ 2012066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1952450140000.  Starting simulation...
+info: Entering event queue @ 2013066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1953450140000.  Starting simulation...
+info: Entering event queue @ 2014066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1954450140000.  Starting simulation...
+info: Entering event queue @ 2015066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1955450140000.  Starting simulation...
+info: Entering event queue @ 2016066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1956450140000.  Starting simulation...
+info: Entering event queue @ 2017066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1957450140000.  Starting simulation...
+info: Entering event queue @ 2018066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1958450140000.  Starting simulation...
+info: Entering event queue @ 2019066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1959450140000.  Starting simulation...
+info: Entering event queue @ 2020066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1960450140000.  Starting simulation...
+info: Entering event queue @ 2021066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1961450140000.  Starting simulation...
+info: Entering event queue @ 2022066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1962450140000.  Starting simulation...
+info: Entering event queue @ 2023066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1963450140000.  Starting simulation...
+info: Entering event queue @ 2024066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1964450140000.  Starting simulation...
-info: Entering event queue @ 1965186738000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1965186740000.  Starting simulation...
+info: Entering event queue @ 2025066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1966186740000.  Starting simulation...
+info: Entering event queue @ 2026066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1967186740000.  Starting simulation...
+info: Entering event queue @ 2027066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1968186740000.  Starting simulation...
+info: Entering event queue @ 2028066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1969186740000.  Starting simulation...
+info: Entering event queue @ 2029066208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2030066208000.  Starting simulation...
+info: Entering event queue @ 2031802486250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1970186740000.  Starting simulation...
+info: Entering event queue @ 2031802489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1971186740000.  Starting simulation...
+info: Entering event queue @ 2032802489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1972186740000.  Starting simulation...
+info: Entering event queue @ 2033802489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1973186740000.  Starting simulation...
+info: Entering event queue @ 2034802489000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2035802489000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1974186740000.  Starting simulation...
+info: Entering event queue @ 2035802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1975186740000.  Starting simulation...
+info: Entering event queue @ 2036802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1976186740000.  Starting simulation...
+info: Entering event queue @ 2037802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1977186740000.  Starting simulation...
+info: Entering event queue @ 2038802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1978186740000.  Starting simulation...
+info: Entering event queue @ 2039802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1979186740000.  Starting simulation...
+info: Entering event queue @ 2040802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1980186740000.  Starting simulation...
+info: Entering event queue @ 2041802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1981186740000.  Starting simulation...
+info: Entering event queue @ 2042802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1982186740000.  Starting simulation...
+info: Entering event queue @ 2043802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1983186740000.  Starting simulation...
+info: Entering event queue @ 2044802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1984186740000.  Starting simulation...
+info: Entering event queue @ 2045802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1985186740000.  Starting simulation...
+info: Entering event queue @ 2046802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1986186740000.  Starting simulation...
+info: Entering event queue @ 2047802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1987186740000.  Starting simulation...
+info: Entering event queue @ 2048802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1988186740000.  Starting simulation...
+info: Entering event queue @ 2049802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1989186740000.  Starting simulation...
+info: Entering event queue @ 2050802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1990186740000.  Starting simulation...
+info: Entering event queue @ 2051802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1991186740000.  Starting simulation...
+info: Entering event queue @ 2052802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1992186740000.  Starting simulation...
+info: Entering event queue @ 2053802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1993186740000.  Starting simulation...
+info: Entering event queue @ 2054802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1994186740000.  Starting simulation...
+info: Entering event queue @ 2055802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1995186740000.  Starting simulation...
+info: Entering event queue @ 2056802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1996186740000.  Starting simulation...
+info: Entering event queue @ 2057802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 1997186740000.  Starting simulation...
-info: Entering event queue @ 1997923355000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 1997923357000.  Starting simulation...
+info: Entering event queue @ 2058802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1998923357000.  Starting simulation...
+info: Entering event queue @ 2059802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 1999923357000.  Starting simulation...
+info: Entering event queue @ 2060802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2000923357000.  Starting simulation...
+info: Entering event queue @ 2061802496500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2062802496500.  Starting simulation...
+info: Entering event queue @ 2064538734250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2001923357000.  Starting simulation...
+info: Entering event queue @ 2064538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2002923357000.  Starting simulation...
+info: Entering event queue @ 2065538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2003923357000.  Starting simulation...
+info: Entering event queue @ 2066538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2004923357000.  Starting simulation...
+info: Entering event queue @ 2067538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2005923357000.  Starting simulation...
+info: Entering event queue @ 2068538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2006923357000.  Starting simulation...
+info: Entering event queue @ 2069538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2007923357000.  Starting simulation...
+info: Entering event queue @ 2070538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2008923357000.  Starting simulation...
+info: Entering event queue @ 2071538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2009923357000.  Starting simulation...
+info: Entering event queue @ 2072538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2010923357000.  Starting simulation...
+info: Entering event queue @ 2073538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2011923357000.  Starting simulation...
+info: Entering event queue @ 2074538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2012923357000.  Starting simulation...
+info: Entering event queue @ 2075538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2013923357000.  Starting simulation...
+info: Entering event queue @ 2076538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2014923357000.  Starting simulation...
+info: Entering event queue @ 2077538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2015923357000.  Starting simulation...
+info: Entering event queue @ 2078538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2016923357000.  Starting simulation...
+info: Entering event queue @ 2079538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2017923357000.  Starting simulation...
+info: Entering event queue @ 2080538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2018923357000.  Starting simulation...
+info: Entering event queue @ 2081538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2019923357000.  Starting simulation...
+info: Entering event queue @ 2082538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2020923357000.  Starting simulation...
+info: Entering event queue @ 2083538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2021923357000.  Starting simulation...
+info: Entering event queue @ 2084538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2022923357000.  Starting simulation...
+info: Entering event queue @ 2085538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2023923357000.  Starting simulation...
+info: Entering event queue @ 2086538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2024923357000.  Starting simulation...
+info: Entering event queue @ 2087538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2025923357000.  Starting simulation...
+info: Entering event queue @ 2088538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2026923357000.  Starting simulation...
+info: Entering event queue @ 2089538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2027923357000.  Starting simulation...
+info: Entering event queue @ 2090538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2028923357000.  Starting simulation...
+info: Entering event queue @ 2091538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2029923357000.  Starting simulation...
-info: Entering event queue @ 2030658922000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2030658924000.  Starting simulation...
+info: Entering event queue @ 2092538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2031658924000.  Starting simulation...
+info: Entering event queue @ 2093538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2032658924000.  Starting simulation...
+info: Entering event queue @ 2094538737000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2095538737000.  Starting simulation...
+info: Entering event queue @ 2097275022250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2033658924000.  Starting simulation...
+info: Entering event queue @ 2097275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2034658924000.  Starting simulation...
+info: Entering event queue @ 2098275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2035658924000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2035658931500.  Starting simulation...
+info: Entering event queue @ 2099275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2036658931500.  Starting simulation...
+info: Entering event queue @ 2100275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2037658931500.  Starting simulation...
+info: Entering event queue @ 2101275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2038658931500.  Starting simulation...
+info: Entering event queue @ 2102275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2039658931500.  Starting simulation...
+info: Entering event queue @ 2103275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2040658931500.  Starting simulation...
+info: Entering event queue @ 2104275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2041658931500.  Starting simulation...
+info: Entering event queue @ 2105275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2042658931500.  Starting simulation...
+info: Entering event queue @ 2106275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2043658931500.  Starting simulation...
+info: Entering event queue @ 2107275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2044658931500.  Starting simulation...
+info: Entering event queue @ 2108275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2045658931500.  Starting simulation...
+info: Entering event queue @ 2109275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2046658931500.  Starting simulation...
+info: Entering event queue @ 2110275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2047658931500.  Starting simulation...
+info: Entering event queue @ 2111275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2048658931500.  Starting simulation...
+info: Entering event queue @ 2112275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2049658931500.  Starting simulation...
+info: Entering event queue @ 2113275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2050658931500.  Starting simulation...
+info: Entering event queue @ 2114275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2051658931500.  Starting simulation...
+info: Entering event queue @ 2115275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2052658931500.  Starting simulation...
+info: Entering event queue @ 2116275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2053658931500.  Starting simulation...
+info: Entering event queue @ 2117275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2054658931500.  Starting simulation...
+info: Entering event queue @ 2118275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2055658931500.  Starting simulation...
+info: Entering event queue @ 2119275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2056658931500.  Starting simulation...
+info: Entering event queue @ 2120275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2057658931500.  Starting simulation...
+info: Entering event queue @ 2121275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2058658931500.  Starting simulation...
+info: Entering event queue @ 2122275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2059658931500.  Starting simulation...
+info: Entering event queue @ 2123275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2060658931500.  Starting simulation...
+info: Entering event queue @ 2124275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2061658931500.  Starting simulation...
+info: Entering event queue @ 2125275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2062658931500.  Starting simulation...
-info: Entering event queue @ 2063395522000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2063395524000.  Starting simulation...
+info: Entering event queue @ 2126275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2064395524000.  Starting simulation...
+info: Entering event queue @ 2127275025000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2128275025000.  Starting simulation...
+info: Entering event queue @ 2130011306250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2065395524000.  Starting simulation...
+info: Entering event queue @ 2130011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2066395524000.  Starting simulation...
+info: Entering event queue @ 2131011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2067395524000.  Starting simulation...
+info: Entering event queue @ 2132011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2068395524000.  Starting simulation...
+info: Entering event queue @ 2133011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2069395524000.  Starting simulation...
+info: Entering event queue @ 2134011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2070395524000.  Starting simulation...
+info: Entering event queue @ 2135011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2071395524000.  Starting simulation...
+info: Entering event queue @ 2136011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2072395524000.  Starting simulation...
+info: Entering event queue @ 2137011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2073395524000.  Starting simulation...
+info: Entering event queue @ 2138011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2074395524000.  Starting simulation...
+info: Entering event queue @ 2139011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2075395524000.  Starting simulation...
+info: Entering event queue @ 2140011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2076395524000.  Starting simulation...
+info: Entering event queue @ 2141011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2077395524000.  Starting simulation...
+info: Entering event queue @ 2142011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2078395524000.  Starting simulation...
+info: Entering event queue @ 2143011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2079395524000.  Starting simulation...
+info: Entering event queue @ 2144011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2080395524000.  Starting simulation...
+info: Entering event queue @ 2145011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2081395524000.  Starting simulation...
+info: Entering event queue @ 2146011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2082395524000.  Starting simulation...
+info: Entering event queue @ 2147011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2083395524000.  Starting simulation...
+info: Entering event queue @ 2148011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2084395524000.  Starting simulation...
+info: Entering event queue @ 2149011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2085395524000.  Starting simulation...
+info: Entering event queue @ 2150011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2086395524000.  Starting simulation...
+info: Entering event queue @ 2151011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2087395524000.  Starting simulation...
+info: Entering event queue @ 2152011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2088395524000.  Starting simulation...
+info: Entering event queue @ 2153011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2089395524000.  Starting simulation...
+info: Entering event queue @ 2154011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2090395524000.  Starting simulation...
+info: Entering event queue @ 2155011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2091395524000.  Starting simulation...
+info: Entering event queue @ 2156011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2092395524000.  Starting simulation...
+info: Entering event queue @ 2157011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2093395524000.  Starting simulation...
+info: Entering event queue @ 2158011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2094395524000.  Starting simulation...
+info: Entering event queue @ 2159011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2095395524000.  Starting simulation...
-info: Entering event queue @ 2096132143000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2096132145000.  Starting simulation...
+info: Entering event queue @ 2160011309000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2161011309000.  Starting simulation...
+info: Entering event queue @ 2162747241250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2097132145000.  Starting simulation...
+info: Entering event queue @ 2162747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2098132145000.  Starting simulation...
+info: Entering event queue @ 2163747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2099132145000.  Starting simulation...
+info: Entering event queue @ 2164747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2100132145000.  Starting simulation...
+info: Entering event queue @ 2165747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2101132145000.  Starting simulation...
+info: Entering event queue @ 2166747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2102132145000.  Starting simulation...
+info: Entering event queue @ 2167747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2103132145000.  Starting simulation...
+info: Entering event queue @ 2168747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2104132145000.  Starting simulation...
+info: Entering event queue @ 2169747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2105132145000.  Starting simulation...
+info: Entering event queue @ 2170747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2106132145000.  Starting simulation...
+info: Entering event queue @ 2171747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2107132145000.  Starting simulation...
+info: Entering event queue @ 2172747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2108132145000.  Starting simulation...
+info: Entering event queue @ 2173747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2109132145000.  Starting simulation...
+info: Entering event queue @ 2174747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2110132145000.  Starting simulation...
+info: Entering event queue @ 2175747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2111132145000.  Starting simulation...
+info: Entering event queue @ 2176747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2112132145000.  Starting simulation...
+info: Entering event queue @ 2177747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2113132145000.  Starting simulation...
+info: Entering event queue @ 2178747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2114132145000.  Starting simulation...
+info: Entering event queue @ 2179747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2115132145000.  Starting simulation...
+info: Entering event queue @ 2180747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2116132145000.  Starting simulation...
+info: Entering event queue @ 2181747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2117132145000.  Starting simulation...
+info: Entering event queue @ 2182747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2118132145000.  Starting simulation...
+info: Entering event queue @ 2183747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2119132145000.  Starting simulation...
+info: Entering event queue @ 2184747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2120132145000.  Starting simulation...
+info: Entering event queue @ 2185747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2121132145000.  Starting simulation...
+info: Entering event queue @ 2186747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2122132145000.  Starting simulation...
+info: Entering event queue @ 2187747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2123132145000.  Starting simulation...
+info: Entering event queue @ 2188747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2124132145000.  Starting simulation...
+info: Entering event queue @ 2189747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2125132145000.  Starting simulation...
+info: Entering event queue @ 2190747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2126132145000.  Starting simulation...
+info: Entering event queue @ 2191747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2127132145000.  Starting simulation...
+info: Entering event queue @ 2192747244000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2128132145000.  Starting simulation...
-info: Entering event queue @ 2128868743000.  Starting simulation...
+info: Entering event queue @ 2193747244000.  Starting simulation...
+info: Entering event queue @ 2195483842250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2128868745000.  Starting simulation...
+info: Entering event queue @ 2195483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2129868745000.  Starting simulation...
+info: Entering event queue @ 2196483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2130868745000.  Starting simulation...
+info: Entering event queue @ 2197483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2131868745000.  Starting simulation...
+info: Entering event queue @ 2198483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2132868745000.  Starting simulation...
+info: Entering event queue @ 2199483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2133868745000.  Starting simulation...
+info: Entering event queue @ 2200483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2134868745000.  Starting simulation...
+info: Entering event queue @ 2201483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2135868745000.  Starting simulation...
+info: Entering event queue @ 2202483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2136868745000.  Starting simulation...
+info: Entering event queue @ 2203483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2137868745000.  Starting simulation...
+info: Entering event queue @ 2204483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2138868745000.  Starting simulation...
+info: Entering event queue @ 2205483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2139868745000.  Starting simulation...
+info: Entering event queue @ 2206483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2140868745000.  Starting simulation...
+info: Entering event queue @ 2207483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2141868745000.  Starting simulation...
+info: Entering event queue @ 2208483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2142868745000.  Starting simulation...
+info: Entering event queue @ 2209483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2143868745000.  Starting simulation...
+info: Entering event queue @ 2210483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2144868745000.  Starting simulation...
+info: Entering event queue @ 2211483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2145868745000.  Starting simulation...
+info: Entering event queue @ 2212483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2146868745000.  Starting simulation...
+info: Entering event queue @ 2213483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2147868745000.  Starting simulation...
+info: Entering event queue @ 2214483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2148868745000.  Starting simulation...
+info: Entering event queue @ 2215483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2149868745000.  Starting simulation...
+info: Entering event queue @ 2216483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2150868745000.  Starting simulation...
+info: Entering event queue @ 2217483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2151868745000.  Starting simulation...
+info: Entering event queue @ 2218483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2152868745000.  Starting simulation...
+info: Entering event queue @ 2219483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2153868745000.  Starting simulation...
+info: Entering event queue @ 2220483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2154868745000.  Starting simulation...
+info: Entering event queue @ 2221483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2155868745000.  Starting simulation...
+info: Entering event queue @ 2222483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2156868745000.  Starting simulation...
+info: Entering event queue @ 2223483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2157868745000.  Starting simulation...
+info: Entering event queue @ 2224483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2158868745000.  Starting simulation...
+info: Entering event queue @ 2225483845000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2226483845000.  Starting simulation...
+info: Entering event queue @ 2228219817250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2159868745000.  Starting simulation...
+info: Entering event queue @ 2228219820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2160868745000.  Starting simulation...
-info: Entering event queue @ 2161604155000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2161604157000.  Starting simulation...
+info: Entering event queue @ 2229219820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2162604157000.  Starting simulation...
+info: Entering event queue @ 2230219820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2163604157000.  Starting simulation...
+info: Entering event queue @ 2231219820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2164604157000.  Starting simulation...
+info: Entering event queue @ 2232219820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2165604157000.  Starting simulation...
+info: Entering event queue @ 2233219820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2166604157000.  Starting simulation...
+info: Entering event queue @ 2234219820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2167604157000.  Starting simulation...
+info: Entering event queue @ 2235219820000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2236219820000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2168604157000.  Starting simulation...
+info: Entering event queue @ 2236219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2169604157000.  Starting simulation...
+info: Entering event queue @ 2237219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2170604157000.  Starting simulation...
+info: Entering event queue @ 2238219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2171604157000.  Starting simulation...
+info: Entering event queue @ 2239219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2172604157000.  Starting simulation...
+info: Entering event queue @ 2240219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2173604157000.  Starting simulation...
+info: Entering event queue @ 2241219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2174604157000.  Starting simulation...
+info: Entering event queue @ 2242219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2175604157000.  Starting simulation...
+info: Entering event queue @ 2243219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2176604157000.  Starting simulation...
+info: Entering event queue @ 2244219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2177604157000.  Starting simulation...
+info: Entering event queue @ 2245219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2178604157000.  Starting simulation...
+info: Entering event queue @ 2246219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2179604157000.  Starting simulation...
+info: Entering event queue @ 2247219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2180604157000.  Starting simulation...
+info: Entering event queue @ 2248219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2181604157000.  Starting simulation...
+info: Entering event queue @ 2249219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2182604157000.  Starting simulation...
+info: Entering event queue @ 2250219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2183604157000.  Starting simulation...
+info: Entering event queue @ 2251219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2184604157000.  Starting simulation...
+info: Entering event queue @ 2252219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2185604157000.  Starting simulation...
+info: Entering event queue @ 2253219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2186604157000.  Starting simulation...
+info: Entering event queue @ 2254219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2187604157000.  Starting simulation...
+info: Entering event queue @ 2255219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2188604157000.  Starting simulation...
+info: Entering event queue @ 2256219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2189604157000.  Starting simulation...
+info: Entering event queue @ 2257219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2190604157000.  Starting simulation...
+info: Entering event queue @ 2258219827500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2259219827500.  Starting simulation...
+info: Entering event queue @ 2260956062250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2191604157000.  Starting simulation...
+info: Entering event queue @ 2260956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2192604157000.  Starting simulation...
+info: Entering event queue @ 2261956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2193604157000.  Starting simulation...
-info: Entering event queue @ 2194340734000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2194340736000.  Starting simulation...
+info: Entering event queue @ 2262956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2195340736000.  Starting simulation...
+info: Entering event queue @ 2263956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2196340736000.  Starting simulation...
+info: Entering event queue @ 2264956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2197340736000.  Starting simulation...
+info: Entering event queue @ 2265956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2198340736000.  Starting simulation...
+info: Entering event queue @ 2266956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2199340736000.  Starting simulation...
+info: Entering event queue @ 2267956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2200340736000.  Starting simulation...
+info: Entering event queue @ 2268956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2201340736000.  Starting simulation...
+info: Entering event queue @ 2269956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2202340736000.  Starting simulation...
+info: Entering event queue @ 2270956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2203340736000.  Starting simulation...
+info: Entering event queue @ 2271956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2204340736000.  Starting simulation...
+info: Entering event queue @ 2272956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2205340736000.  Starting simulation...
+info: Entering event queue @ 2273956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2206340736000.  Starting simulation...
+info: Entering event queue @ 2274956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2207340736000.  Starting simulation...
+info: Entering event queue @ 2275956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2208340736000.  Starting simulation...
+info: Entering event queue @ 2276956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2209340736000.  Starting simulation...
+info: Entering event queue @ 2277956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2210340736000.  Starting simulation...
+info: Entering event queue @ 2278956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2211340736000.  Starting simulation...
+info: Entering event queue @ 2279956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2212340736000.  Starting simulation...
+info: Entering event queue @ 2280956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2213340736000.  Starting simulation...
+info: Entering event queue @ 2281956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2214340736000.  Starting simulation...
+info: Entering event queue @ 2282956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2215340736000.  Starting simulation...
+info: Entering event queue @ 2283956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2216340736000.  Starting simulation...
+info: Entering event queue @ 2284956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2217340736000.  Starting simulation...
+info: Entering event queue @ 2285956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2218340736000.  Starting simulation...
+info: Entering event queue @ 2286956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2219340736000.  Starting simulation...
+info: Entering event queue @ 2287956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2220340736000.  Starting simulation...
+info: Entering event queue @ 2288956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2221340736000.  Starting simulation...
+info: Entering event queue @ 2289956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2222340736000.  Starting simulation...
+info: Entering event queue @ 2290956065000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2291956065000.  Starting simulation...
+info: Entering event queue @ 2293692349250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2223340736000.  Starting simulation...
+info: Entering event queue @ 2293692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2224340736000.  Starting simulation...
+info: Entering event queue @ 2294692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2225340736000.  Starting simulation...
+info: Entering event queue @ 2295692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2226340736000.  Starting simulation...
-info: Entering event queue @ 2227077334000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2227077336000.  Starting simulation...
+info: Entering event queue @ 2296692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2228077336000.  Starting simulation...
+info: Entering event queue @ 2297692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2229077336000.  Starting simulation...
+info: Entering event queue @ 2298692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2230077336000.  Starting simulation...
+info: Entering event queue @ 2299692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2231077336000.  Starting simulation...
+info: Entering event queue @ 2300692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2232077336000.  Starting simulation...
+info: Entering event queue @ 2301692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2233077336000.  Starting simulation...
+info: Entering event queue @ 2302692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2234077336000.  Starting simulation...
+info: Entering event queue @ 2303692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2235077336000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2235077343500.  Starting simulation...
+info: Entering event queue @ 2304692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2236077343500.  Starting simulation...
+info: Entering event queue @ 2305692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2237077343500.  Starting simulation...
+info: Entering event queue @ 2306692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2238077343500.  Starting simulation...
+info: Entering event queue @ 2307692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2239077343500.  Starting simulation...
+info: Entering event queue @ 2308692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2240077343500.  Starting simulation...
+info: Entering event queue @ 2309692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2241077343500.  Starting simulation...
+info: Entering event queue @ 2310692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2242077343500.  Starting simulation...
+info: Entering event queue @ 2311692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2243077343500.  Starting simulation...
+info: Entering event queue @ 2312692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2244077343500.  Starting simulation...
+info: Entering event queue @ 2313692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2245077343500.  Starting simulation...
+info: Entering event queue @ 2314692352000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2315692352000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2246077343500.  Starting simulation...
+info: Entering event queue @ 2315692410000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2316692410000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2247077343500.  Starting simulation...
+info: Entering event queue @ 2316692443000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2317692443000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2248077343500.  Starting simulation...
+info: Entering event queue @ 2317692450500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2249077343500.  Starting simulation...
+info: Entering event queue @ 2318692450500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2250077343500.  Starting simulation...
+info: Entering event queue @ 2319692450500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2251077343500.  Starting simulation...
+info: Entering event queue @ 2320692450500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2252077343500.  Starting simulation...
+info: Entering event queue @ 2321692450500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2253077343500.  Starting simulation...
+info: Entering event queue @ 2322692450500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2254077343500.  Starting simulation...
+info: Entering event queue @ 2323692450500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2324692450500.  Starting simulation...
+info: Entering event queue @ 2326428637250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2255077343500.  Starting simulation...
+info: Entering event queue @ 2326428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2256077343500.  Starting simulation...
+info: Entering event queue @ 2327428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2257077343500.  Starting simulation...
+info: Entering event queue @ 2328428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2258077343500.  Starting simulation...
+info: Entering event queue @ 2329428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2259077343500.  Starting simulation...
-info: Entering event queue @ 2259812939000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2259812941000.  Starting simulation...
+info: Entering event queue @ 2330428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2260812941000.  Starting simulation...
+info: Entering event queue @ 2331428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2261812941000.  Starting simulation...
+info: Entering event queue @ 2332428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2262812941000.  Starting simulation...
+info: Entering event queue @ 2333428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2263812941000.  Starting simulation...
+info: Entering event queue @ 2334428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2264812941000.  Starting simulation...
+info: Entering event queue @ 2335428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2265812941000.  Starting simulation...
+info: Entering event queue @ 2336428640000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2337428640000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2266812941000.  Starting simulation...
+info: Entering event queue @ 2337428647500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2338428647500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2267812941000.  Starting simulation...
+info: Entering event queue @ 2338428655000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2339428655000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2268812941000.  Starting simulation...
+info: Entering event queue @ 2339428750000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2340428750000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2269812941000.  Starting simulation...
+info: Entering event queue @ 2340428757500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2341428757500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2270812941000.  Starting simulation...
+info: Entering event queue @ 2341428765000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2342428765000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2271812941000.  Starting simulation...
+info: Entering event queue @ 2342428793000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2343428793000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2272812941000.  Starting simulation...
+info: Entering event queue @ 2343428910000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2344428910000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2273812941000.  Starting simulation...
+info: Entering event queue @ 2344428917500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2345428917500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2274812941000.  Starting simulation...
+info: Entering event queue @ 2345429049000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2346429049000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2275812941000.  Starting simulation...
+info: Entering event queue @ 2346429169000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
 switching cpus
-info: Entering event queue @ 2276812941000.  Starting simulation...
+info: Entering event queue @ 2347429169000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2348429169000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2277812941000.  Starting simulation...
+info: Entering event queue @ 2348429176500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2349429176500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2278812941000.  Starting simulation...
+info: Entering event queue @ 2349429190000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2350429190000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2279812941000.  Starting simulation...
+info: Entering event queue @ 2350429305000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2351429305000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2280812941000.  Starting simulation...
+info: Entering event queue @ 2351429312500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2352429312500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2281812941000.  Starting simulation...
+info: Entering event queue @ 2352429345000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2353429345000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2282812941000.  Starting simulation...
+info: Entering event queue @ 2353429366000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2354429366000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2283812941000.  Starting simulation...
+info: Entering event queue @ 2354429463000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2355429463000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2284812941000.  Starting simulation...
+info: Entering event queue @ 2355429586000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2356429586000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2285812941000.  Starting simulation...
+info: Entering event queue @ 2356429633000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2357429633000.  Starting simulation...
+info: Entering event queue @ 2359165549250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2286812941000.  Starting simulation...
+info: Entering event queue @ 2359165552000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2360165552000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2287812941000.  Starting simulation...
+info: Entering event queue @ 2360165559500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2361165559500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2288812941000.  Starting simulation...
+info: Entering event queue @ 2361165567000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2362165567000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2289812941000.  Starting simulation...
+info: Entering event queue @ 2362165602000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2363165602000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2290812941000.  Starting simulation...
+info: Entering event queue @ 2363165722000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2291812941000.  Starting simulation...
-info: Entering event queue @ 2292549539000.  Starting simulation...
+info: Entering event queue @ 2364165722000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2292549541000.  Starting simulation...
+info: Entering event queue @ 2364165818000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2365165818000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2293549541000.  Starting simulation...
+info: Entering event queue @ 2365165956000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2366165956000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2294549541000.  Starting simulation...
+info: Entering event queue @ 2366166000000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2367166000000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2295549541000.  Starting simulation...
+info: Entering event queue @ 2367166007500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2368166007500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2296549541000.  Starting simulation...
+info: Entering event queue @ 2368166148000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2369166148000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2297549541000.  Starting simulation...
+info: Entering event queue @ 2369166232000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2370166232000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2298549541000.  Starting simulation...
+info: Entering event queue @ 2370166258000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2371166258000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2299549541000.  Starting simulation...
+info: Entering event queue @ 2371166376000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2372166376000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2300549541000.  Starting simulation...
+info: Entering event queue @ 2372166411000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2373166411000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2301549541000.  Starting simulation...
+info: Entering event queue @ 2373166428000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2374166428000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2302549541000.  Starting simulation...
+info: Entering event queue @ 2374166455000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2375166455000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2303549541000.  Starting simulation...
+info: Entering event queue @ 2375166576000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2376166576000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2304549541000.  Starting simulation...
+info: Entering event queue @ 2376166696000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2305549541000.  Starting simulation...
+info: Entering event queue @ 2377166696000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2305549582000.  Starting simulation...
+info: Entering event queue @ 2377166781000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2306549582000.  Starting simulation...
+info: Entering event queue @ 2378166781000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2306549589500.  Starting simulation...
+info: Entering event queue @ 2378166854000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2379166854000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2307549589500.  Starting simulation...
+info: Entering event queue @ 2379166934000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2380166934000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2308549589500.  Starting simulation...
+info: Entering event queue @ 2380167067000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2381167067000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2309549589500.  Starting simulation...
+info: Entering event queue @ 2381167110000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2382167110000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2310549589500.  Starting simulation...
+info: Entering event queue @ 2382167211000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2383167211000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2311549589500.  Starting simulation...
+info: Entering event queue @ 2383167257000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2384167257000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2312549589500.  Starting simulation...
+info: Entering event queue @ 2384167406000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2385167406000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2313549589500.  Starting simulation...
+info: Entering event queue @ 2385167550000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2386167550000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2314549589500.  Starting simulation...
+info: Entering event queue @ 2386167557500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2387167557500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2315549589500.  Starting simulation...
+info: Entering event queue @ 2387167694000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2388167694000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2316549589500.  Starting simulation...
+info: Entering event queue @ 2388167701500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2389167701500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2317549589500.  Starting simulation...
+info: Entering event queue @ 2389167857000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2390167857000.  Starting simulation...
+info: Entering event queue @ 2391903793250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2318549589500.  Starting simulation...
+info: Entering event queue @ 2391903869000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2392903869000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2319549589500.  Starting simulation...
+info: Entering event queue @ 2392903975000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2393903975000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2320549589500.  Starting simulation...
+info: Entering event queue @ 2393903982500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2394903982500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2321549589500.  Starting simulation...
+info: Entering event queue @ 2394903990000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2395903990000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2322549589500.  Starting simulation...
+info: Entering event queue @ 2395904067000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2396904067000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2323549589500.  Starting simulation...
+info: Entering event queue @ 2396904208000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2324549589500.  Starting simulation...
-info: Entering event queue @ 2325286118000.  Starting simulation...
-info: Entering event queue @ 2325286124000.  Starting simulation...
+info: Entering event queue @ 2397904208000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2325286125500.  Starting simulation...
+info: Entering event queue @ 2397904284000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2326286125500.  Starting simulation...
+info: Entering event queue @ 2398904284000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2326286133000.  Starting simulation...
+info: Entering event queue @ 2398904291500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2327286133000.  Starting simulation...
+info: Entering event queue @ 2399904291500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2327286140500.  Starting simulation...
+info: Entering event queue @ 2399904429000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2328286140500.  Starting simulation...
+info: Entering event queue @ 2400904429000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2328286186000.  Starting simulation...
+info: Entering event queue @ 2400904566000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2329286186000.  Starting simulation...
+info: Entering event queue @ 2401904566000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2329286223000.  Starting simulation...
+info: Entering event queue @ 2401904685000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2330286223000.  Starting simulation...
+info: Entering event queue @ 2402904685000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2330286230500.  Starting simulation...
+info: Entering event queue @ 2402904751000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2331286230500.  Starting simulation...
+info: Entering event queue @ 2403904751000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2331286254000.  Starting simulation...
+info: Entering event queue @ 2403904799000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2332286254000.  Starting simulation...
+info: Entering event queue @ 2404904799000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2332286408000.  Starting simulation...
+info: Entering event queue @ 2404904899000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2333286408000.  Starting simulation...
+info: Entering event queue @ 2405904899000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2333286415500.  Starting simulation...
+info: Entering event queue @ 2405905038000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2334286415500.  Starting simulation...
+info: Entering event queue @ 2406905038000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2334286517000.  Starting simulation...
+info: Entering event queue @ 2406905047000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2335286517000.  Starting simulation...
+info: Entering event queue @ 2407905047000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2335286619000.  Starting simulation...
+info: Entering event queue @ 2407905061000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2336286619000.  Starting simulation...
+info: Entering event queue @ 2408905061000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2336286772000.  Starting simulation...
+info: Entering event queue @ 2408905068500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2337286772000.  Starting simulation...
+info: Entering event queue @ 2409905068500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2337286779500.  Starting simulation...
+info: Entering event queue @ 2409905214000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2338286779500.  Starting simulation...
+info: Entering event queue @ 2410905214000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2338286858000.  Starting simulation...
+info: Entering event queue @ 2410905221500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2339286858000.  Starting simulation...
+info: Entering event queue @ 2411905221500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2339286865500.  Starting simulation...
+info: Entering event queue @ 2411905292000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2340286865500.  Starting simulation...
+info: Entering event queue @ 2412905292000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2340286954000.  Starting simulation...
+info: Entering event queue @ 2412905313000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2341286954000.  Starting simulation...
+info: Entering event queue @ 2413905313000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2341287003000.  Starting simulation...
+info: Entering event queue @ 2413905320500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2342287003000.  Starting simulation...
+info: Entering event queue @ 2414905320500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2342287101000.  Starting simulation...
+info: Entering event queue @ 2414905328000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2343287101000.  Starting simulation...
+info: Entering event queue @ 2415905328000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2343287108500.  Starting simulation...
+info: Entering event queue @ 2415905341000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2344287108500.  Starting simulation...
+info: Entering event queue @ 2416905341000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2344287231000.  Starting simulation...
+info: Entering event queue @ 2416905490000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2345287231000.  Starting simulation...
+info: Entering event queue @ 2417905490000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2345287255000.  Starting simulation...
+info: Entering event queue @ 2417905532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2346287255000.  Starting simulation...
+info: Entering event queue @ 2418905532000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2346287350000.  Starting simulation...
+info: Entering event queue @ 2418905539500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2347287350000.  Starting simulation...
+info: Entering event queue @ 2419905539500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2347287397000.  Starting simulation...
+info: Entering event queue @ 2419905643000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2348287397000.  Starting simulation...
+info: Entering event queue @ 2420905643000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2348287404500.  Starting simulation...
+info: Entering event queue @ 2420905687000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2349287404500.  Starting simulation...
+info: Entering event queue @ 2421905687000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2349287448000.  Starting simulation...
+info: Entering event queue @ 2421905694500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2350287448000.  Starting simulation...
+info: Entering event queue @ 2422905694500.  Starting simulation...
+info: Entering event queue @ 2424637770250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2350287455500.  Starting simulation...
+info: Entering event queue @ 2424637773000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2351287455500.  Starting simulation...
+info: Entering event queue @ 2425637773000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2351287463000.  Starting simulation...
+info: Entering event queue @ 2425637788000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2352287463000.  Starting simulation...
+info: Entering event queue @ 2426637788000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2352287470500.  Starting simulation...
+info: Entering event queue @ 2426637903000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2353287470500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2353287572000.  Starting simulation...
+info: Entering event queue @ 2427637903000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2354287572000.  Starting simulation...
+info: Entering event queue @ 2428637903000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2354287703000.  Starting simulation...
+info: Entering event queue @ 2428638049000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2355287703000.  Starting simulation...
+info: Entering event queue @ 2429638049000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2355287710500.  Starting simulation...
+info: Entering event queue @ 2429638099000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2356287710500.  Starting simulation...
+info: Entering event queue @ 2430638099000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2356287765000.  Starting simulation...
+info: Entering event queue @ 2430638106500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2357287765000.  Starting simulation...
-info: Entering event queue @ 2358021530000.  Starting simulation...
+info: Entering event queue @ 2431638106500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2358021532000.  Starting simulation...
+info: Entering event queue @ 2431638195000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2359021532000.  Starting simulation...
+info: Entering event queue @ 2432638195000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2359021676000.  Starting simulation...
+info: Entering event queue @ 2432638349000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2360021676000.  Starting simulation...
+info: Entering event queue @ 2433638349000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2360021831000.  Starting simulation...
+info: Entering event queue @ 2433638486000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2361021831000.  Starting simulation...
+info: Entering event queue @ 2434638486000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2361021907000.  Starting simulation...
+info: Entering event queue @ 2434638493500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2362021907000.  Starting simulation...
+info: Entering event queue @ 2435638493500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2362021914500.  Starting simulation...
+info: Entering event queue @ 2435638590000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2363021914500.  Starting simulation...
+info: Entering event queue @ 2436638590000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2363021992000.  Starting simulation...
+info: Entering event queue @ 2436638614000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2364021992000.  Starting simulation...
+info: Entering event queue @ 2437638614000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2364022007000.  Starting simulation...
+info: Entering event queue @ 2437638621500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2365022007000.  Starting simulation...
+info: Entering event queue @ 2438638621500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2365022014500.  Starting simulation...
+info: Entering event queue @ 2438638710000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2366022014500.  Starting simulation...
+info: Entering event queue @ 2439638710000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2366022027000.  Starting simulation...
+info: Entering event queue @ 2439638725000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2367022027000.  Starting simulation...
+info: Entering event queue @ 2440638725000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2367022117000.  Starting simulation...
+info: Entering event queue @ 2440638747000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2368022117000.  Starting simulation...
+info: Entering event queue @ 2441638747000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2368022124500.  Starting simulation...
+info: Entering event queue @ 2441638754500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2369022124500.  Starting simulation...
+info: Entering event queue @ 2442638754500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2369022270000.  Starting simulation...
+info: Entering event queue @ 2442638803000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2370022270000.  Starting simulation...
+info: Entering event queue @ 2443638803000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2370022277500.  Starting simulation...
+info: Entering event queue @ 2443638912000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2371022277500.  Starting simulation...
+info: Entering event queue @ 2444638912000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2371022285000.  Starting simulation...
+info: Entering event queue @ 2444639034000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2372022285000.  Starting simulation...
+info: Entering event queue @ 2445639034000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2372022414000.  Starting simulation...
+info: Entering event queue @ 2445639125000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2373022414000.  Starting simulation...
+info: Entering event queue @ 2446639125000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2373022432000.  Starting simulation...
+info: Entering event queue @ 2446639160000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2374022432000.  Starting simulation...
+info: Entering event queue @ 2447639160000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2374022439500.  Starting simulation...
+info: Entering event queue @ 2447639271000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2375022439500.  Starting simulation...
+info: Entering event queue @ 2448639271000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2375022569000.  Starting simulation...
+info: Entering event queue @ 2448639278500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2376022569000.  Starting simulation...
+info: Entering event queue @ 2449639278500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2376022686000.  Starting simulation...
+info: Entering event queue @ 2449639286000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2377022686000.  Starting simulation...
+info: Entering event queue @ 2450639286000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2377022827000.  Starting simulation...
+info: Entering event queue @ 2450639415000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2378022827000.  Starting simulation...
+info: Entering event queue @ 2451639415000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2378022982000.  Starting simulation...
+info: Entering event queue @ 2451639552000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2379022982000.  Starting simulation...
+info: Entering event queue @ 2452639552000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2379023037000.  Starting simulation...
+info: Entering event queue @ 2452639559500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2380023037000.  Starting simulation...
+info: Entering event queue @ 2453639559500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2380023062000.  Starting simulation...
+info: Entering event queue @ 2453639643000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2381023062000.  Starting simulation...
+info: Entering event queue @ 2454639643000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2381023069500.  Starting simulation...
+info: Entering event queue @ 2454639650500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2382023069500.  Starting simulation...
+info: Entering event queue @ 2455639650500.  Starting simulation...
+info: Entering event queue @ 2457374369250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2382023080500.  Starting simulation...
+info: Entering event queue @ 2457374372000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2383023080500.  Starting simulation...
+info: Entering event queue @ 2458374372000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2383023209000.  Starting simulation...
+info: Entering event queue @ 2458374511000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2384023209000.  Starting simulation...
+info: Entering event queue @ 2459374511000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2384023216500.  Starting simulation...
+info: Entering event queue @ 2459374526000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2385023216500.  Starting simulation...
+info: Entering event queue @ 2460374526000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2385023294000.  Starting simulation...
+info: Entering event queue @ 2460374533500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2386023294000.  Starting simulation...
+info: Entering event queue @ 2461374533500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2386023307500.  Starting simulation...
+info: Entering event queue @ 2461374550000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2387023307500.  Starting simulation...
+info: Entering event queue @ 2462374550000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2387023398000.  Starting simulation...
+info: Entering event queue @ 2462374597000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2388023398000.  Starting simulation...
+info: Entering event queue @ 2463374597000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2388023422000.  Starting simulation...
+info: Entering event queue @ 2463374619000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2389023422000.  Starting simulation...
+info: Entering event queue @ 2464374619000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2389023429500.  Starting simulation...
+info: Entering event queue @ 2464374710000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2390023429500.  Starting simulation...
-info: Entering event queue @ 2390758151000.  Starting simulation...
+info: Entering event queue @ 2465374710000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2390758153000.  Starting simulation...
+info: Entering event queue @ 2465374766000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2391758153000.  Starting simulation...
+info: Entering event queue @ 2466374766000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2391758161000.  Starting simulation...
+info: Entering event queue @ 2466374797000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2392758161000.  Starting simulation...
+info: Entering event queue @ 2467374797000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2392758168500.  Starting simulation...
+info: Entering event queue @ 2467374945000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2393758168500.  Starting simulation...
+info: Entering event queue @ 2468374945000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2393758292000.  Starting simulation...
+info: Entering event queue @ 2468374967000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2394758292000.  Starting simulation...
+info: Entering event queue @ 2469374967000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2394758302000.  Starting simulation...
+info: Entering event queue @ 2469375044000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2395758302000.  Starting simulation...
+info: Entering event queue @ 2470375044000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2395758458000.  Starting simulation...
+info: Entering event queue @ 2470375126000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2396758458000.  Starting simulation...
+info: Entering event queue @ 2471375126000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2396758470000.  Starting simulation...
+info: Entering event queue @ 2471375215000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2397758470000.  Starting simulation...
+info: Entering event queue @ 2472375215000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2397758606000.  Starting simulation...
+info: Entering event queue @ 2472375222500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2398758606000.  Starting simulation...
+info: Entering event queue @ 2473375222500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2398758753000.  Starting simulation...
+info: Entering event queue @ 2473375265000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2399758753000.  Starting simulation...
+info: Entering event queue @ 2474375265000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2399758906000.  Starting simulation...
+info: Entering event queue @ 2474375295000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2400758906000.  Starting simulation...
+info: Entering event queue @ 2475375295000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2400759041000.  Starting simulation...
+info: Entering event queue @ 2475375442000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2401759041000.  Starting simulation...
+info: Entering event queue @ 2476375442000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2401759189000.  Starting simulation...
+info: Entering event queue @ 2476375449500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2402759189000.  Starting simulation...
+info: Entering event queue @ 2477375449500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2402759220000.  Starting simulation...
+info: Entering event queue @ 2477375520000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2403759220000.  Starting simulation...
+info: Entering event queue @ 2478375520000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2403759362000.  Starting simulation...
+info: Entering event queue @ 2478375603000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2404759362000.  Starting simulation...
+info: Entering event queue @ 2479375603000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2404759454000.  Starting simulation...
+info: Entering event queue @ 2479375656000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2405759454000.  Starting simulation...
+info: Entering event queue @ 2480375656000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2405759609000.  Starting simulation...
+info: Entering event queue @ 2480375751000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2406759609000.  Starting simulation...
+info: Entering event queue @ 2481375751000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2406759693000.  Starting simulation...
+info: Entering event queue @ 2481375870000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2407759693000.  Starting simulation...
+info: Entering event queue @ 2482375870000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2407759791000.  Starting simulation...
+info: Entering event queue @ 2482375877500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2408759791000.  Starting simulation...
+info: Entering event queue @ 2483375877500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2408759806000.  Starting simulation...
+info: Entering event queue @ 2483375900000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2409759806000.  Starting simulation...
+info: Entering event queue @ 2484375900000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2409759845000.  Starting simulation...
+info: Entering event queue @ 2484375923000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2410759845000.  Starting simulation...
+info: Entering event queue @ 2485375923000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2410759950000.  Starting simulation...
+info: Entering event queue @ 2485376001000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2411759950000.  Starting simulation...
+info: Entering event queue @ 2486376001000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2411759976000.  Starting simulation...
+info: Entering event queue @ 2486376008500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2412759976000.  Starting simulation...
+info: Entering event queue @ 2487376008500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2412759983500.  Starting simulation...
+info: Entering event queue @ 2487376146000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2413759983500.  Starting simulation...
+info: Entering event queue @ 2488376146000.  Starting simulation...
+info: Entering event queue @ 2490110657250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2413760084000.  Starting simulation...
+info: Entering event queue @ 2490110660000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2414760084000.  Starting simulation...
+info: Entering event queue @ 2491110660000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2414760142000.  Starting simulation...
+info: Entering event queue @ 2491110682000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2415760142000.  Starting simulation...
+info: Entering event queue @ 2492110682000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2415760169000.  Starting simulation...
+info: Entering event queue @ 2492110689500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2416760169000.  Starting simulation...
+info: Entering event queue @ 2493110689500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2416760278000.  Starting simulation...
+info: Entering event queue @ 2493110765000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2417760278000.  Starting simulation...
+info: Entering event queue @ 2494110765000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2417760378000.  Starting simulation...
+info: Entering event queue @ 2494110772500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2418760378000.  Starting simulation...
+info: Entering event queue @ 2495110772500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2418760524000.  Starting simulation...
+info: Entering event queue @ 2495110780000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2419760524000.  Starting simulation...
+info: Entering event queue @ 2496110780000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2419760601000.  Starting simulation...
+info: Entering event queue @ 2496110878000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2420760601000.  Starting simulation...
+info: Entering event queue @ 2497110878000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2420760619000.  Starting simulation...
+info: Entering event queue @ 2497111028000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2421760619000.  Starting simulation...
+info: Entering event queue @ 2498111028000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2421760647000.  Starting simulation...
+info: Entering event queue @ 2498111170000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2422760647000.  Starting simulation...
-info: Entering event queue @ 2423494730000.  Starting simulation...
+info: Entering event queue @ 2499111170000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2423494732000.  Starting simulation...
+info: Entering event queue @ 2499111184000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2424494732000.  Starting simulation...
+info: Entering event queue @ 2500111184000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2424494817000.  Starting simulation...
+info: Entering event queue @ 2500111332000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2501111332000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2425494817000.  Starting simulation...
+info: Entering event queue @ 2501111339500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2426494817000.  Starting simulation...
+info: Entering event queue @ 2502111339500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2426494898000.  Starting simulation...
+info: Entering event queue @ 2502111354000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2427494898000.  Starting simulation...
+info: Entering event queue @ 2503111354000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2427494973000.  Starting simulation...
+info: Entering event queue @ 2503111446000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2428494973000.  Starting simulation...
+info: Entering event queue @ 2504111446000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2428494980500.  Starting simulation...
+info: Entering event queue @ 2504111532000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2429494980500.  Starting simulation...
+info: Entering event queue @ 2505111532000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2429495036000.  Starting simulation...
+info: Entering event queue @ 2505111539500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2430495036000.  Starting simulation...
+info: Entering event queue @ 2506111539500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2430495139000.  Starting simulation...
+info: Entering event queue @ 2506111646000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2431495139000.  Starting simulation...
+info: Entering event queue @ 2507111646000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2431495146500.  Starting simulation...
+info: Entering event queue @ 2507111682000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2432495146500.  Starting simulation...
+info: Entering event queue @ 2508111682000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2432495281000.  Starting simulation...
+info: Entering event queue @ 2508111689500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2433495281000.  Starting simulation...
+info: Entering event queue @ 2509111689500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2433495390000.  Starting simulation...
+info: Entering event queue @ 2509111831000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2434495390000.  Starting simulation...
+info: Entering event queue @ 2510111831000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2434495397500.  Starting simulation...
+info: Entering event queue @ 2510111941000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2435495397500.  Starting simulation...
+info: Entering event queue @ 2511111941000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2435495416000.  Starting simulation...
+info: Entering event queue @ 2511111948500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2436495416000.  Starting simulation...
+info: Entering event queue @ 2512111948500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2436495532000.  Starting simulation...
+info: Entering event queue @ 2512111990000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2437495532000.  Starting simulation...
+info: Entering event queue @ 2513111990000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2437495571000.  Starting simulation...
+info: Entering event queue @ 2513112001000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2438495571000.  Starting simulation...
+info: Entering event queue @ 2514112001000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2438495727000.  Starting simulation...
+info: Entering event queue @ 2514112009000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2439495727000.  Starting simulation...
+info: Entering event queue @ 2515112009000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2439495866000.  Starting simulation...
+info: Entering event queue @ 2515112016500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2440495866000.  Starting simulation...
+info: Entering event queue @ 2516112016500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2440495930000.  Starting simulation...
+info: Entering event queue @ 2516112091000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2441495930000.  Starting simulation...
+info: Entering event queue @ 2517112091000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2441495956000.  Starting simulation...
+info: Entering event queue @ 2517112172000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2442495956000.  Starting simulation...
+info: Entering event queue @ 2518112172000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2442496014000.  Starting simulation...
+info: Entering event queue @ 2518112317000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2443496014000.  Starting simulation...
+info: Entering event queue @ 2519112317000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2443496047000.  Starting simulation...
+info: Entering event queue @ 2519112324500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2444496047000.  Starting simulation...
+info: Entering event queue @ 2520112324500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2444496070000.  Starting simulation...
+info: Entering event queue @ 2520112394000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2445496070000.  Starting simulation...
+info: Entering event queue @ 2521112394000.  Starting simulation...
+info: Entering event queue @ 2522846938250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2445496224000.  Starting simulation...
+info: Entering event queue @ 2522846941000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2446496224000.  Starting simulation...
+info: Entering event queue @ 2523846941000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2446496340000.  Starting simulation...
+info: Entering event queue @ 2523846948500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2447496340000.  Starting simulation...
+info: Entering event queue @ 2524846948500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2447496437000.  Starting simulation...
+info: Entering event queue @ 2524847092000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2448496437000.  Starting simulation...
+info: Entering event queue @ 2525847092000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2448496470000.  Starting simulation...
+info: Entering event queue @ 2525847224000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2449496470000.  Starting simulation...
+info: Entering event queue @ 2526847224000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2449496529000.  Starting simulation...
+info: Entering event queue @ 2526847351000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2450496529000.  Starting simulation...
+info: Entering event queue @ 2527847351000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2450496616000.  Starting simulation...
+info: Entering event queue @ 2527847362000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2451496616000.  Starting simulation...
+info: Entering event queue @ 2528847362000.  Starting simulation...
+info: Entering event queue @ 2528847390000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2451496657000.  Starting simulation...
+info: Entering event queue @ 2528847597000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2452496657000.  Starting simulation...
+info: Entering event queue @ 2529847597000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2452496803000.  Starting simulation...
+info: Entering event queue @ 2529847604500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2453496803000.  Starting simulation...
+info: Entering event queue @ 2530847604500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2453496810500.  Starting simulation...
+info: Entering event queue @ 2530847667000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2454496810500.  Starting simulation...
+info: Entering event queue @ 2531847667000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2454496936000.  Starting simulation...
+info: Entering event queue @ 2531847805000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2455496936000.  Starting simulation...
-info: Entering event queue @ 2456231330000.  Starting simulation...
+info: Entering event queue @ 2532847805000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2456231332000.  Starting simulation...
+info: Entering event queue @ 2532847812500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2457231332000.  Starting simulation...
+info: Entering event queue @ 2533847812500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2457231468000.  Starting simulation...
+info: Entering event queue @ 2533847917000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2458231468000.  Starting simulation...
+info: Entering event queue @ 2534847917000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2458231599000.  Starting simulation...
+info: Entering event queue @ 2534847924500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2459231599000.  Starting simulation...
+info: Entering event queue @ 2535847924500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2459231662000.  Starting simulation...
+info: Entering event queue @ 2535847932000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2460231662000.  Starting simulation...
+info: Entering event queue @ 2536847932000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2460231735000.  Starting simulation...
+info: Entering event queue @ 2536847958000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2461231735000.  Starting simulation...
+info: Entering event queue @ 2537847958000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2461231751000.  Starting simulation...
+info: Entering event queue @ 2537847987000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2462231751000.  Starting simulation...
+info: Entering event queue @ 2538847987000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2462231781000.  Starting simulation...
+info: Entering event queue @ 2538848125000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2463231781000.  Starting simulation...
+info: Entering event queue @ 2539848125000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2463231788500.  Starting simulation...
+info: Entering event queue @ 2539848132500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2464231788500.  Starting simulation...
+info: Entering event queue @ 2540848132500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2464231848000.  Starting simulation...
+info: Entering event queue @ 2540848144000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2465231848000.  Starting simulation...
+info: Entering event queue @ 2541848144000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2465231865000.  Starting simulation...
+info: Entering event queue @ 2541848249000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2466231865000.  Starting simulation...
+info: Entering event queue @ 2542848249000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2466231917000.  Starting simulation...
+info: Entering event queue @ 2542848256500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2467231917000.  Starting simulation...
+info: Entering event queue @ 2543848256500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2467232004000.  Starting simulation...
+info: Entering event queue @ 2543848264000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2468232004000.  Starting simulation...
+info: Entering event queue @ 2544848264000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2468232072000.  Starting simulation...
+info: Entering event queue @ 2544848271500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2469232072000.  Starting simulation...
+info: Entering event queue @ 2545848271500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2469232192000.  Starting simulation...
+info: Entering event queue @ 2545848283000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2470232192000.  Starting simulation...
+info: Entering event queue @ 2546848283000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2470232287000.  Starting simulation...
+info: Entering event queue @ 2546848427000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2471232287000.  Starting simulation...
+info: Entering event queue @ 2547848427000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2471232409000.  Starting simulation...
+info: Entering event queue @ 2547848471000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2472232409000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2472232561000.  Starting simulation...
+info: Entering event queue @ 2548848471000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2473232561000.  Starting simulation...
+info: Entering event queue @ 2549848471000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2473232685000.  Starting simulation...
+info: Entering event queue @ 2549848567000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2474232685000.  Starting simulation...
+info: Entering event queue @ 2550848567000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2474232739000.  Starting simulation...
+info: Entering event queue @ 2550848594000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2475232739000.  Starting simulation...
+info: Entering event queue @ 2551848594000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2475232746500.  Starting simulation...
+info: Entering event queue @ 2551848739000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2476232746500.  Starting simulation...
+info: Entering event queue @ 2552848739000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2476232869000.  Starting simulation...
+info: Entering event queue @ 2552848772000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2477232869000.  Starting simulation...
+info: Entering event queue @ 2553848772000.  Starting simulation...
+info: Entering event queue @ 2555582877250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2477232953000.  Starting simulation...
+info: Entering event queue @ 2555582880000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2478232953000.  Starting simulation...
+info: Entering event queue @ 2556582880000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2478232960500.  Starting simulation...
+info: Entering event queue @ 2556582963000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2479232960500.  Starting simulation...
+info: Entering event queue @ 2557582963000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2479232968000.  Starting simulation...
+info: Entering event queue @ 2557582970500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2480232968000.  Starting simulation...
+info: Entering event queue @ 2558582970500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2480233089000.  Starting simulation...
+info: Entering event queue @ 2558583082000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2481233089000.  Starting simulation...
+info: Entering event queue @ 2559583082000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2481233134000.  Starting simulation...
+info: Entering event queue @ 2559583164000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2482233134000.  Starting simulation...
+info: Entering event queue @ 2560583164000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2482233141500.  Starting simulation...
+info: Entering event queue @ 2560583171500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2483233141500.  Starting simulation...
+info: Entering event queue @ 2561583171500.  Starting simulation...
+info: Entering event queue @ 2561583230000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2483233286000.  Starting simulation...
+info: Entering event queue @ 2561583429750.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2484233286000.  Starting simulation...
+info: Entering event queue @ 2562583429750.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2484233426000.  Starting simulation...
+info: Entering event queue @ 2562583496000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2485233426000.  Starting simulation...
+info: Entering event queue @ 2563583496000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2485233556000.  Starting simulation...
+info: Entering event queue @ 2563583643000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2486233556000.  Starting simulation...
+info: Entering event queue @ 2564583643000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2486233563500.  Starting simulation...
+info: Entering event queue @ 2564583650500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2487233563500.  Starting simulation...
+info: Entering event queue @ 2565583650500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2487233646000.  Starting simulation...
+info: Entering event queue @ 2565583710000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2488233646000.  Starting simulation...
-info: Entering event queue @ 2488966935000.  Starting simulation...
+info: Entering event queue @ 2566583710000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2488966937000.  Starting simulation...
+info: Entering event queue @ 2566583851000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2489966937000.  Starting simulation...
+info: Entering event queue @ 2567583851000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2489966944500.  Starting simulation...
+info: Entering event queue @ 2567584002000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2490966944500.  Starting simulation...
+info: Entering event queue @ 2568584002000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2490967075000.  Starting simulation...
+info: Entering event queue @ 2568584009500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2491967075000.  Starting simulation...
+info: Entering event queue @ 2569584009500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2491967146000.  Starting simulation...
+info: Entering event queue @ 2569584017000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2492967146000.  Starting simulation...
+info: Entering event queue @ 2570584017000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2492967153500.  Starting simulation...
+info: Entering event queue @ 2570584089000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2493967153500.  Starting simulation...
+info: Entering event queue @ 2571584089000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2493967161000.  Starting simulation...
+info: Entering event queue @ 2571584096500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2494967161000.  Starting simulation...
+info: Entering event queue @ 2572584096500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2494967168500.  Starting simulation...
+info: Entering event queue @ 2572584190000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2495967168500.  Starting simulation...
+info: Entering event queue @ 2573584190000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2495967212000.  Starting simulation...
+info: Entering event queue @ 2573584197500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2496967212000.  Starting simulation...
+info: Entering event queue @ 2574584197500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2496967335000.  Starting simulation...
+info: Entering event queue @ 2574584350000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
+info: Entering event queue @ 2575584350000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2497967335000.  Starting simulation...
+info: Entering event queue @ 2575584357500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2498967335000.  Starting simulation...
+info: Entering event queue @ 2576584357500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2498967427000.  Starting simulation...
+info: Entering event queue @ 2576584365000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2499967427000.  Starting simulation...
+info: Entering event queue @ 2577584365000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2499967545000.  Starting simulation...
+info: Entering event queue @ 2577584454000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2500967545000.  Starting simulation...
+info: Entering event queue @ 2578584454000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2500967552500.  Starting simulation...
+info: Entering event queue @ 2578584461500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2501967552500.  Starting simulation...
+info: Entering event queue @ 2579584461500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2501967556000.  Starting simulation...
+info: Entering event queue @ 2579584495000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2502967556000.  Starting simulation...
+info: Entering event queue @ 2580584495000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2502967624000.  Starting simulation...
+info: Entering event queue @ 2580584642000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2503967624000.  Starting simulation...
+info: Entering event queue @ 2581584642000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2503967631500.  Starting simulation...
+info: Entering event queue @ 2581584673000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2504967631500.  Starting simulation...
+info: Entering event queue @ 2582584673000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2504967739000.  Starting simulation...
+info: Entering event queue @ 2582584799000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2505967739000.  Starting simulation...
+info: Entering event queue @ 2583584799000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2505967746500.  Starting simulation...
+info: Entering event queue @ 2583584838000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2506967746500.  Starting simulation...
+info: Entering event queue @ 2584584838000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2506967777000.  Starting simulation...
+info: Entering event queue @ 2584584958000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2507967777000.  Starting simulation...
+info: Entering event queue @ 2585584958000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2507967850000.  Starting simulation...
+info: Entering event queue @ 2585585101000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2508967850000.  Starting simulation...
+info: Entering event queue @ 2586585101000.  Starting simulation...
+info: Entering event queue @ 2588319477250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2508967857500.  Starting simulation...
+info: Entering event queue @ 2588319480000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2509967857500.  Starting simulation...
+info: Entering event queue @ 2589319480000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2509967904000.  Starting simulation...
+info: Entering event queue @ 2589319487500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2510967904000.  Starting simulation...
+info: Entering event queue @ 2590319487500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2510968030000.  Starting simulation...
+info: Entering event queue @ 2590319506000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2511968030000.  Starting simulation...
+info: Entering event queue @ 2591319506000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2511968037500.  Starting simulation...
+info: Entering event queue @ 2591319513500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2512968037500.  Starting simulation...
+info: Entering event queue @ 2592319513500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2512968149000.  Starting simulation...
+info: Entering event queue @ 2592319521000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2513968149000.  Starting simulation...
+info: Entering event queue @ 2593319521000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2513968255000.  Starting simulation...
+info: Entering event queue @ 2593319528500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2514968255000.  Starting simulation...
+info: Entering event queue @ 2594319528500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2514968262500.  Starting simulation...
+info: Entering event queue @ 2594319578000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2515968262500.  Starting simulation...
+info: Entering event queue @ 2595319578000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2515968353000.  Starting simulation...
+info: Entering event queue @ 2595319585500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2516968353000.  Starting simulation...
+info: Entering event queue @ 2596319585500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2516968367000.  Starting simulation...
+info: Entering event queue @ 2596319687000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2517968367000.  Starting simulation...
+info: Entering event queue @ 2597319687000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2517968374500.  Starting simulation...
+info: Entering event queue @ 2597319740000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2518968374500.  Starting simulation...
+info: Entering event queue @ 2598319740000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2518968382000.  Starting simulation...
+info: Entering event queue @ 2598319767000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2519968382000.  Starting simulation...
+info: Entering event queue @ 2599319767000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2519968393000.  Starting simulation...
+info: Entering event queue @ 2599319774500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2520968393000.  Starting simulation...
-info: Entering event queue @ 2521703535000.  Starting simulation...
+info: Entering event queue @ 2600319774500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2521703537000.  Starting simulation...
+info: Entering event queue @ 2600319782000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2522703537000.  Starting simulation...
+info: Entering event queue @ 2601319782000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2522703612000.  Starting simulation...
+info: Entering event queue @ 2601319789500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2523703612000.  Starting simulation...
+info: Entering event queue @ 2602319789500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2523703619500.  Starting simulation...
+info: Entering event queue @ 2602319797000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2524703619500.  Starting simulation...
+info: Entering event queue @ 2603319797000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2524703726000.  Starting simulation...
+info: Entering event queue @ 2603319799500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2525703726000.  Starting simulation...
+info: Entering event queue @ 2604319799500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2525703841000.  Starting simulation...
+info: Entering event queue @ 2604319800000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2526703841000.  Starting simulation...
-info: Entering event queue @ 2526703980500.  Starting simulation...
+info: Entering event queue @ 2605319800000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2526703988000.  Starting simulation...
+info: Entering event queue @ 2605319807500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2527703988000.  Starting simulation...
+info: Entering event queue @ 2606319807500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2527704057000.  Starting simulation...
+info: Entering event queue @ 2606319815000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2528704057000.  Starting simulation...
-info: Entering event queue @ 2528704070000.  Starting simulation...
+info: Entering event queue @ 2607319815000.  Starting simulation...
+info: Entering event queue @ 2607319822500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2528704072500.  Starting simulation...
+info: Entering event queue @ 2607319825500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2529704072500.  Starting simulation...
+info: Entering event queue @ 2608319825500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2529704080000.  Starting simulation...
+info: Entering event queue @ 2608319833000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2530704080000.  Starting simulation...
+info: Entering event queue @ 2609319833000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2530704175000.  Starting simulation...
+info: Entering event queue @ 2609319840500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2531704175000.  Starting simulation...
+info: Entering event queue @ 2610319840500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2531704259000.  Starting simulation...
+info: Entering event queue @ 2610319848000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2532704259000.  Starting simulation...
+info: Entering event queue @ 2611319848000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2532704266500.  Starting simulation...
+info: Entering event queue @ 2611319855500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2533704266500.  Starting simulation...
+info: Entering event queue @ 2612319855500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2533704275000.  Starting simulation...
+info: Entering event queue @ 2612319863000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2534704275000.  Starting simulation...
+info: Entering event queue @ 2613319863000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2534704354000.  Starting simulation...
+info: Entering event queue @ 2613319870500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2535704354000.  Starting simulation...
+info: Entering event queue @ 2614319870500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2535704361500.  Starting simulation...
+info: Entering event queue @ 2614319871000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2536704361500.  Starting simulation...
+info: Entering event queue @ 2615319871000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2536704449000.  Starting simulation...
+info: Entering event queue @ 2615319878500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2537704449000.  Starting simulation...
+info: Entering event queue @ 2616319878500.  Starting simulation...
+info: Entering event queue @ 2616319886000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2537704557000.  Starting simulation...
+info: Entering event queue @ 2616319887000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2538704557000.  Starting simulation...
+info: Entering event queue @ 2617319887000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2538704705000.  Starting simulation...
+info: Entering event queue @ 2617319894500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2539704705000.  Starting simulation...
+info: Entering event queue @ 2618319894500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2539704773000.  Starting simulation...
+info: Entering event queue @ 2618319896500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2540704773000.  Starting simulation...
+info: Entering event queue @ 2619319896500.  Starting simulation...
+info: Entering event queue @ 2621055410250.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2540704780500.  Starting simulation...
+info: Entering event queue @ 2621055413000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2541704780500.  Starting simulation...
+info: Entering event queue @ 2622055413000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2541704788000.  Starting simulation...
+info: Entering event queue @ 2622055452000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2542704788000.  Starting simulation...
+info: Entering event queue @ 2623055452000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2542704795500.  Starting simulation...
+info: Entering event queue @ 2623055459500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2543704795500.  Starting simulation...
+info: Entering event queue @ 2624055459500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2543704917000.  Starting simulation...
+info: Entering event queue @ 2624055612000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2544704917000.  Starting simulation...
+info: Entering event queue @ 2625055612000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2544705016000.  Starting simulation...
+info: Entering event queue @ 2625055673000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2545705016000.  Starting simulation...
+info: Entering event queue @ 2626055673000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2545705132000.  Starting simulation...
+info: Entering event queue @ 2626055680500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2546705132000.  Starting simulation...
+info: Entering event queue @ 2627055680500.  Starting simulation...
+info: Entering event queue @ 2627055945000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2546705217000.  Starting simulation...
+info: Entering event queue @ 2627055952500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2547705217000.  Starting simulation...
+info: Entering event queue @ 2628055952500.  Starting simulation...
+info: Entering event queue @ 2628055960000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2547705224500.  Starting simulation...
+info: Entering event queue @ 2628055963000.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2548705224500.  Starting simulation...
+info: Entering event queue @ 2629055963000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2548705235000.  Starting simulation...
+info: Entering event queue @ 2629055970500.  Starting simulation...
 Switching CPUs...
 Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2549705235000.  Starting simulation...
+info: Entering event queue @ 2630055970500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2549705357000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2550705357000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2550705364500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2551705364500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2551705395000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2552705395000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2552705402500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2553705402500.  Starting simulation...
-info: Entering event queue @ 2554438939000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2554438946500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2555438946500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2555438954000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2556438954000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2556438961500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2557438961500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2557438969000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2558438969000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2558438976500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2559438976500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2559439045000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2560439045000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2560439111000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2561439111000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2561439229000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2562439229000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2562439304000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2563439304000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2563439451000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2564439451000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2564439484000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2565439484000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2565439632000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2566439632000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2566439771000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2567439771000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2567439778500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2568439778500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2568439829000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2569439829000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2569439894000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2570439894000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2570439901500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2571439901500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2571440025000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2572440025000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2572440157000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2573440157000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2573440165000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2574440165000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2574440172500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2575440172500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2575440283000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2576440283000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2576440290500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2577440290500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2577440355000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2578440355000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2578440362500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2579440362500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2579440365000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2580440365000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2580440372500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2581440372500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2581440380000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2582440380000.  Starting simulation...
-info: Entering event queue @ 2582440388500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2582440391000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2583440391000.  Starting simulation...
-info: Entering event queue @ 2583440399500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2583440403000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2584440403000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2584440412000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2585440412000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2585440419500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2586440419500.  Starting simulation...
-info: Entering event queue @ 2587181122000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2587181124000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2588181124000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2588181131500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2589181131500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2589181133000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2590181133000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2590181140500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2591181140500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2591181172000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2592181172000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2592181179500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2593181179500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2593181187000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2594181187000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2594181194500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2595181194500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2595181202000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2596181202000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2596181209500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2597181209500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2597181217000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2598181217000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2598181222000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2599181222000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2599181229500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2600181229500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2600181237000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2601181237000.  Starting simulation...
-info: Entering event queue @ 2601181244500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2601181247500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2602181247500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2602181255000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2603181255000.  Starting simulation...
-info: Entering event queue @ 2603181266500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2603181269000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2604181269000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2604181375000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2605181375000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2605181382500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2606181382500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2606181390000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2607181390000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2607181397500.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2608181397500.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2608181405000.  Starting simulation...
-Switching CPUs...
-Next CPU: TimingSimpleCPU
-info: Entering event queue @ 2609181405000.  Starting simulation...
-switching cpus
-info: Entering event queue @ 2609181412500.  Starting simulation...
+info: Entering event queue @ 2630055978000.  Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal
index 8dd192b7e..711cdcec2 100644
--- a/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal
+++ b/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-timing/system.terminal
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
index 30a638b3d..e59e9b3f5 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/config.ini
@@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table
+children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain
 acpi_description_table_pointer=system.acpi_description_table_pointer
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 mem_ranges=0:134217727
@@ -53,7 +54,7 @@ oem_table_id=
 
 [system.apicbridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=11529215046068469760:11529215046068473855
 req_size=16
@@ -63,17 +64,22 @@ slave=system.iobus.master[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
-slave=system.membus.master[1]
+slave=system.membus.master[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
 
 [system.cpu]
 type=DerivO3CPU
-children=branchPred dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
+children=apic_clk_domain branchPred dcache dtb dtb_walker_cache fuPool icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
@@ -85,7 +91,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -134,6 +140,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -155,6 +162,11 @@ workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.branchPred]
 type=BranchPredictor
 BTBEntries=4096
@@ -163,11 +175,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -175,10 +185,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -189,12 +199,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -203,16 +222,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.dtb_walker_cache.cpu_side
 
 [system.cpu.dtb_walker_cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -223,12 +243,21 @@ prefetcher=Null
 response_latency=2
 size=1024
 system=system
+tags=system.cpu.dtb_walker_cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dtb.walker.port
 mem_side=system.cpu.toL2Bus.slave[3]
 
+[system.cpu.dtb_walker_cache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=1024
+
 [system.cpu.fuPool]
 type=FUPool
 children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
@@ -494,10 +523,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -508,22 +537,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
 system=system
 int_master=system.membus.slave[3]
-int_slave=system.membus.master[3]
-pio=system.membus.master[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
@@ -536,16 +574,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.itb_walker_cache.cpu_side
 
 [system.cpu.itb_walker_cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -556,18 +595,27 @@ prefetcher=Null
 response_latency=2
 size=1024
 system=system
+tags=system.cpu.itb_walker_cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.itb.walker.port
 mem_side=system.cpu.toL2Bus.slave[2]
 
+[system.cpu.itb_walker_cache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=1024
+
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -578,16 +626,24 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -598,6 +654,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.e820_table]
 type=X86E820Table
 children=entries0 entries1 entries2
@@ -969,8 +1030,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -980,10 +1040,10 @@ slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -994,28 +1054,36 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[18]
 mem_side=system.membus.slave[4]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
 slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -1038,7 +1106,7 @@ system=system
 
 [system.pc.behind_pci]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854779128
 pio_latency=100000
@@ -1056,7 +1124,7 @@ pio=system.iobus.master[12]
 [system.pc.com_1]
 type=Uart8250
 children=terminal
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=9223372036854776824
 pio_latency=100000
 platform=system.pc
@@ -1080,7 +1148,7 @@ port=3456
 
 [system.pc.fake_com_2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776568
 pio_latency=100000
@@ -1097,7 +1165,7 @@ pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776808
 pio_latency=100000
@@ -1114,7 +1182,7 @@ pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776552
 pio_latency=100000
@@ -1131,7 +1199,7 @@ pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776818
 pio_latency=100000
@@ -1148,7 +1216,7 @@ pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854775936
 pio_latency=100000
@@ -1166,7 +1234,8 @@ pio=system.iobus.master[11]
 [system.pc.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.pc
 size=16777216
@@ -1189,7 +1258,7 @@ speaker=system.pc.south_bridge.speaker
 [system.pc.south_bridge.cmos]
 type=Cmos
 children=int_pin
-clock=1000
+clk_domain=system.clk_domain
 int_pin=system.pc.south_bridge.cmos.int_pin
 pio_addr=9223372036854775920
 pio_latency=100000
@@ -1202,7 +1271,7 @@ type=X86IntSourcePin
 
 [system.pc.south_bridge.dma1]
 type=I8237
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=9223372036854775808
 pio_latency=100000
 system=system
@@ -1249,7 +1318,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
@@ -1281,7 +1350,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1301,7 +1370,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1384,7 +1453,7 @@ number=12
 [system.pc.south_bridge.io_apic]
 type=I82094AA
 apic_id=1
-clock=1000
+clk_domain=system.clk_domain
 external_int_pic=system.pc.south_bridge.pic1
 int_latency=1000
 pio_addr=4273995776
@@ -1396,7 +1465,7 @@ pio=system.iobus.master[10]
 [system.pc.south_bridge.keyboard]
 type=I8042
 children=keyboard_int_pin mouse_int_pin
-clock=1000
+clk_domain=system.clk_domain
 command_port=9223372036854775908
 data_port=9223372036854775904
 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
@@ -1415,7 +1484,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pic1]
 type=I8259
 children=output
-clock=1000
+clk_domain=system.clk_domain
 mode=I8259Master
 output=system.pc.south_bridge.pic1.output
 pio_addr=9223372036854775840
@@ -1430,7 +1499,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pic2]
 type=I8259
 children=output
-clock=1000
+clk_domain=system.clk_domain
 mode=I8259Slave
 output=system.pc.south_bridge.pic2.output
 pio_addr=9223372036854775968
@@ -1445,7 +1514,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pit]
 type=I8254
 children=int_pin
-clock=1000
+clk_domain=system.clk_domain
 int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=100000
@@ -1457,7 +1526,7 @@ type=X86IntSourcePin
 
 [system.pc.south_bridge.speaker]
 type=PcSpeaker
-clock=1000
+clk_domain=system.clk_domain
 i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=100000
@@ -1467,19 +1536,24 @@ pio=system.iobus.master[9]
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -1490,8 +1564,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[0]
+port=system.membus.master[3]
 
 [system.smbios_table]
 type=X86SMBiosSMBiosTable
@@ -1514,3 +1587,7 @@ starting_addr_segment=0
 vendor=
 version=
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
index 92855d998..a681181ed 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simerr
@@ -3,8 +3,6 @@ warn: Sockets disabled, not accepting terminal connections
 warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
 warn: Don't know what interrupt to clear for console.
-warn: x86 cpuid: unknown family 0xbacc
-warn: x86 cpuid: unknown family 0xbacc
 warn: instruction 'fxsave' unimplemented
 warn: x86 cpuid: unknown family 0x8086
 warn: x86 cpuid: unknown family 0x8086
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
index 16e62cf5e..332ea85eb 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 18 2013 13:37:41
-gem5 started Apr 18 2013 13:56:06
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:54:38
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5132953103000 because m5_exit instruction encountered
+Exiting @ tick 5133762710000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
index 90e730a89..f7f063037 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-o3-timing/system.pc.com_1.terminal
@@ -1,16 +1,18 @@
 Linux version 2.6.22.9 (blackga@nacho) (gcc version 4.1.2 (Gentoo 4.1.2)) #2 Mon Oct 8 13:13:00 PDT 2007

 Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

 BIOS-provided physical RAM map:

- BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)

+ BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)

+ BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)

  BIOS-e820: 0000000000100000 - 0000000008000000 (usable)

 end_pfn_map = 32768

-kernel direct mapping tables up to 8000000 @ 100000-102000

+kernel direct mapping tables up to 8000000 @ 8000-a000

 DMI 2.5 present.

 Zone PFN ranges:

-  DMA           256 ->     4096

+  DMA             0 ->     4096

   DMA32        4096 ->  1048576

   Normal    1048576 ->  1048576

-early_node_map[1] active PFN ranges

+early_node_map[2] active PFN ranges

+    0:        0 ->      159

     0:      256 ->    32768

 Intel MultiProcessor Specification v1.4

 MPTABLE: OEM ID:  MPTABLE: Product ID:  MPTABLE: APIC at: 0xFEE00000

@@ -18,8 +20,10 @@ Processor #0 (Bootup-CPU)
 I/O APIC #1 at 0xFEC00000.

 Setting APIC routing to flat

 Processors: 1

+swsusp: Registered nosave memory region: 000000000009f000 - 00000000000a0000

+swsusp: Registered nosave memory region: 00000000000a0000 - 0000000000100000

 Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)

-Built 1 zonelists.  Total pages: 30458

+Built 1 zonelists.  Total pages: 30613

 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

 Initializing CPU#0

 PID hash table entries: 512 (order: 9, 4096 bytes)

@@ -29,7 +33,7 @@ console handover: boot [earlyser0] -> real [ttyS0]
 Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)

 Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)

 Checking aperture...

-Memory: 121556k/131072k available (3742k kernel code, 8456k reserved, 1874k data, 232k init)

+Memory: 122188k/131072k available (3742k kernel code, 8460k reserved, 1874k data, 232k init)

 Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset

 Mount-cache hash table entries: 256

 CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)

@@ -39,7 +43,7 @@ ACPI: Core revision 20070126
 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]

 ACPI: Unable to load the System Description Tables

 Using local APIC timer interrupts.

-result 7812557

+result 7812560

 Detected 7.812 MHz APIC timer.

 NET: Registered protocol family 16

 PCI: Using configuration type 1

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
index b9785e6b5..e645b1548 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -17,7 +17,7 @@ e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
 load_addr_mask=18446744073709551615
 mem_mode=timing
 mem_ranges=0:134217727
@@ -60,7 +60,6 @@ voltage_domain=system.voltage_domain
 [system.cpu0]
 type=TimingSimpleCPU
 children=apic_clk_domain dtb interrupts isa itb tracer
-branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
@@ -139,7 +138,6 @@ type=ExeTracer
 [system.cpu1]
 type=TimingSimpleCPU
 children=apic_clk_domain dtb interrupts isa itb tracer
-branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=1
@@ -852,7 +850,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -872,7 +870,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 83ecaea08..e925af082 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:24:02
+Real time: Sep/22/2013 07:54:54
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 771
-Elapsed_time_in_minutes: 12.85
-Elapsed_time_in_hours: 0.214167
-Elapsed_time_in_days: 0.00892361
+Elapsed_time_in_seconds: 689
+Elapsed_time_in_minutes: 11.4833
+Elapsed_time_in_hours: 0.191389
+Elapsed_time_in_days: 0.00797454
 
-Virtual_time_in_seconds: 767.55
-Virtual_time_in_minutes: 12.7925
-Virtual_time_in_hours:   0.213208
-Virtual_time_in_days:    0.00888368
+Virtual_time_in_seconds: 688.52
+Virtual_time_in_minutes: 11.4753
+Virtual_time_in_hours:   0.191256
+Virtual_time_in_days:    0.00796898
 
 Ruby_current_time: 10608810122
 Ruby_start_time: 0
 Ruby_cycles: 10608810122
 
-mbytes_resident: 612.449
-mbytes_total: 859.008
-resident_ratio: 0.712982
+mbytes_resident: 589.816
+mbytes_total: 810.262
+resident_ratio: 0.727933
 
 Busy Controller Counts:
 L1Cache-0:10  L1Cache-1:9  
@@ -28,28 +28,28 @@ DMA-0:0
 
 Busy Bank Count:0
 
-sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154826686 average: 1.00012 | standard deviation: 0.0109671 | 0 154808062 18624 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154826690 average: 1.00012 | standard deviation: 0.0109671 | 0 154808066 18624 ]
 
 All Non-Zero Cycle Demand Cache Accesses
 ----------------------------------------
-latency: [binsize: 8 max: 146 count: 154826685 average: 3.40667 | standard deviation: 3.89546 | 152128103 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88160 4468 159 160 697 95 ]
-latency: LD: [binsize: 8 max: 145 count: 15355330 average: 5.00367 | standard deviation: 7.1602 | 13922963 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20230 1017 49 23 146 37 ]
-latency: ST: [binsize: 8 max: 146 count: 9754589 average: 4.6097 | standard deviation: 10.5962 | 9399925 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
-latency: IFETCH: [binsize: 8 max: 145 count: 128502467 average: 3.10882 | standard deviation: 1.62805 | 127704896 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 17 24 76 1 ]
-latency: RMW_Read: [binsize: 8 max: 143 count: 526559 average: 6.05821 | standard deviation: 8.42497 | 454440 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
+latency: [binsize: 8 max: 146 count: 154826689 average: 3.40667 | standard deviation: 3.89546 | 152128107 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
+latency: LD: [binsize: 8 max: 145 count: 15355330 average: 5.00367 | standard deviation: 7.16019 | 13922963 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
+latency: ST: [binsize: 8 max: 146 count: 9754590 average: 4.6097 | standard deviation: 10.5962 | 9399926 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
+latency: IFETCH: [binsize: 8 max: 145 count: 128502469 average: 3.10882 | standard deviation: 1.62805 | 127704898 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
+latency: RMW_Read: [binsize: 8 max: 143 count: 526560 average: 6.05821 | standard deviation: 8.42496 | 454441 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
 latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 343870 average: 5.61917 | standard deviation: 7.40449 | 302009 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]
 latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average:     3 | standard deviation: 0 | 0 0 0 343870 ]
-hit latency: [binsize: 1 max: 3 count: 152128103 average:     3 | standard deviation: 0 | 0 0 0 152128103 ]
+hit latency: [binsize: 1 max: 3 count: 152128107 average:     3 | standard deviation: 0 | 0 0 0 152128107 ]
 hit latency: LD: [binsize: 1 max: 3 count: 13922963 average:     3 | standard deviation: 0 | 0 0 0 13922963 ]
-hit latency: ST: [binsize: 1 max: 3 count: 9399925 average:     3 | standard deviation: 0 | 0 0 0 9399925 ]
-hit latency: IFETCH: [binsize: 1 max: 3 count: 127704896 average:     3 | standard deviation: 0 | 0 0 0 127704896 ]
-hit latency: RMW_Read: [binsize: 1 max: 3 count: 454440 average:     3 | standard deviation: 0 | 0 0 0 454440 ]
+hit latency: ST: [binsize: 1 max: 3 count: 9399926 average:     3 | standard deviation: 0 | 0 0 0 9399926 ]
+hit latency: IFETCH: [binsize: 1 max: 3 count: 127704898 average:     3 | standard deviation: 0 | 0 0 0 127704898 ]
+hit latency: RMW_Read: [binsize: 1 max: 3 count: 454441 average:     3 | standard deviation: 0 | 0 0 0 454441 ]
 hit latency: Locked_RMW_Read: [binsize: 1 max: 3 count: 302009 average:     3 | standard deviation: 0 | 0 0 0 302009 ]
 hit latency: Locked_RMW_Write: [binsize: 1 max: 3 count: 343870 average:     3 | standard deviation: 0 | 0 0 0 343870 ]
-miss latency: [binsize: 8 max: 146 count: 2698582 average: 26.332 | standard deviation: 18.3228 | 0 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88160 4468 159 160 697 95 ]
-miss latency: LD: [binsize: 8 max: 145 count: 1432367 average: 24.4798 | standard deviation: 11.4572 | 0 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20230 1017 49 23 146 37 ]
+miss latency: [binsize: 8 max: 146 count: 2698582 average: 26.332 | standard deviation: 18.3228 | 0 0 2401408 123714 808 2 0 0 0 77303 1369 61 178 88161 4467 160 159 697 95 ]
+miss latency: LD: [binsize: 8 max: 145 count: 1432367 average: 24.4798 | standard deviation: 11.4571 | 0 0 1353229 47168 707 0 0 0 0 9533 185 18 25 20231 1016 49 23 146 37 ]
 miss latency: ST: [binsize: 8 max: 146 count: 354664 average: 47.2728 | standard deviation: 34.6308 | 0 0 199287 31109 53 1 0 0 0 62468 1144 36 142 56433 3258 93 112 471 57 ]
-miss latency: IFETCH: [binsize: 8 max: 145 count: 797571 average: 20.5324 | standard deviation: 11.0261 | 0 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 17 24 76 1 ]
+miss latency: IFETCH: [binsize: 8 max: 145 count: 797571 average: 20.5323 | standard deviation: 11.026 | 0 0 781778 353 6 0 0 0 0 4133 20 5 6 10992 160 18 23 76 1 ]
 miss latency: RMW_Read: [binsize: 8 max: 143 count: 72119 average: 25.3288 | standard deviation: 9.37846 | 0 0 43162 27521 11 1 0 0 0 999 18 2 4 371 26 0 1 3 ]
 miss latency: Locked_RMW_Read: [binsize: 8 max: 143 count: 41861 average: 24.5153 | standard deviation: 6.61955 | 0 0 23952 17563 31 0 0 0 0 170 2 0 1 134 7 0 0 1 ]
 
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
index 0fb07bdf2..378d964ed 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-bo
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 18 2013 13:38:36
-gem5 started Apr 18 2013 13:38:48
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:43:05
+gem5 started Sep 22 2013 07:43:21
+gem5 executing on zizzer
 command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5205148879000 because m5_exit instruction encountered
+Exiting @ tick 5304405061000 because m5_exit instruction encountered
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
index 28e4438dd..c29ed4fd3 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,74 +4,74 @@ sim_seconds                                  5.304405                       # Nu
 sim_ticks                                5304405061000                       # Number of ticks simulated
 final_tick                               5304405061000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 140464                       # Simulator instruction rate (inst/s)
-host_op_rate                                   269516                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             6884731594                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 879628                       # Number of bytes of host memory used
-host_seconds                                   770.46                       # Real time elapsed on the host
-sim_insts                                   108221986                       # Number of instructions simulated
-sim_ops                                     207651285                       # Number of ops (including micro ops) simulated
+host_inst_rate                                 157121                       # Simulator instruction rate (inst/s)
+host_op_rate                                   301476                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             7701146515                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 829712                       # Number of bytes of host memory used
+host_seconds                                   688.78                       # Real time elapsed on the host
+sim_insts                                   108221987                       # Number of instructions simulated
+sim_ops                                     207651289                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::pc.south_bridge.ide        35104                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.dtb.walker       136528                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu0.itb.walker        67168                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst        857531504                       # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data         68407513                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst        857531520                       # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data         68407514                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.dtb.walker        89360                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.itb.walker        41152                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.inst        170488232                       # Number of bytes read from this memory
 system.physmem.bytes_read::cpu1.data         28476928                       # Number of bytes read from this memory
-system.physmem.bytes_read::total           1125273489                       # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst    857531504                       # Number of instructions bytes read from this memory
+system.physmem.bytes_read::total           1125273506                       # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst    857531520                       # Number of instructions bytes read from this memory
 system.physmem.bytes_inst_read::cpu1.inst    170488232                       # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total      1028019736                       # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total      1028019752                       # Number of instructions bytes read from this memory
 system.physmem.bytes_written::pc.south_bridge.ide      2991104                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu0.itb.walker           16                       # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data      47712171                       # Number of bytes written to this memory
+system.physmem.bytes_written::cpu0.data      47712172                       # Number of bytes written to this memory
 system.physmem.bytes_written::cpu1.data      22210158                       # Number of bytes written to this memory
-system.physmem.bytes_written::total          72913449                       # Number of bytes written to this memory
+system.physmem.bytes_written::total          72913450                       # Number of bytes written to this memory
 system.physmem.num_reads::pc.south_bridge.ide          804                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.dtb.walker        17066                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu0.itb.walker         8396                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst         107191438                       # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data          11941415                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst         107191440                       # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data          11941416                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.dtb.walker        11170                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.itb.walker         5144                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.inst          21311029                       # Number of read requests responded to by this memory
 system.physmem.num_reads::cpu1.data           4242568                       # Number of read requests responded to by this memory
-system.physmem.num_reads::total             144729030                       # Number of read requests responded to by this memory
+system.physmem.num_reads::total             144729033                       # Number of read requests responded to by this memory
 system.physmem.num_writes::pc.south_bridge.ide        46736                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu0.itb.walker            2                       # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data          7031339                       # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu0.data          7031340                       # Number of write requests responded to by this memory
 system.physmem.num_writes::cpu1.data          3067118                       # Number of write requests responded to by this memory
-system.physmem.num_writes::total             10145195                       # Number of write requests responded to by this memory
+system.physmem.num_writes::total             10145196                       # Number of write requests responded to by this memory
 system.physmem.bw_read::pc.south_bridge.ide         6618                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.dtb.walker         25739                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.itb.walker         12663                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst           161664031                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst           161664034                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu0.data            12896359                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.dtb.walker         16846                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.itb.walker          7758                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.inst            32140877                       # Total read bandwidth from this memory (bytes/s)
 system.physmem.bw_read::cpu1.data             5368543                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total               212139434                       # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst      161664031                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total               212139438                       # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst      161664034                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_inst_read::cpu1.inst       32140877                       # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total          193804908                       # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total          193804911                       # Instruction read bandwidth from this memory (bytes/s)
 system.physmem.bw_write::pc.south_bridge.ide       563891                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu0.itb.walker            3                       # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data            8994820                       # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu0.data            8994821                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::cpu1.data            4187116                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_write::total               13745830                       # Write bandwidth from this memory (bytes/s)
 system.physmem.bw_total::pc.south_bridge.ide       570508                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.dtb.walker        25739                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.itb.walker        12666                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst          161664031                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst          161664034                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu0.data           21891180                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.dtb.walker        16846                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.itb.walker         7758                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.inst           32140877                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.bw_total::cpu1.data            9555659                       # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total              225885264                       # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total              225885267                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem.readReqs                           804                       # Total number of read requests accepted by DRAM controller
 system.physmem.writeReqs                        46736                       # Total number of write requests accepted by DRAM controller
 system.physmem.readBursts                         804                       # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
@@ -409,12 +409,12 @@ system.piobus.respLayer4.occupancy             644500                       # La
 system.piobus.respLayer4.utilization              0.0                       # Layer utilization (%)
 system.piobus.respLayer5.occupancy             632500                       # Layer occupancy (ticks)
 system.piobus.respLayer5.utilization              0.0                       # Layer utilization (%)
-system.ruby.l1_cntrl0.L1Dcache.demand_hits     17394866                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_hits     17394868                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses      1603352                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Dcache.demand_accesses     18998218                       # Number of cache demand accesses
-system.ruby.l1_cntrl0.L1Icache.demand_hits    106683217                       # Number of cache demand hits
+system.ruby.l1_cntrl0.L1Dcache.demand_accesses     18998220                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_hits    106683219                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Icache.demand_misses       508221                       # Number of cache demand misses
-system.ruby.l1_cntrl0.L1Icache.demand_accesses    107191438                       # Number of cache demand accesses
+system.ruby.l1_cntrl0.L1Icache.demand_accesses    107191440                       # Number of cache demand accesses
 system.ruby.l1_cntrl0.prefetcher.miss_observed            0                       # number of misses observed
 system.ruby.l1_cntrl0.prefetcher.allocated_streams            0                       # number of streams allocated for prefetching
 system.ruby.l1_cntrl0.prefetcher.prefetches_requested            0                       # number of prefetch requests made
@@ -497,16 +497,16 @@ system.ruby.dir_cntrl0.memBuffer.memReq        266936                       # To
 system.ruby.dir_cntrl0.memBuffer.memRead       172650                       # Number of memory reads
 system.ruby.dir_cntrl0.memBuffer.memWrite        94286                       # Number of memory writes
 system.ruby.dir_cntrl0.memBuffer.memRefresh       684164                       # Number of memory refreshes
-system.ruby.dir_cntrl0.memBuffer.memWaitCycles       919467                       # Delay stalled at the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.memWaitCycles       919462                       # Delay stalled at the head of the bank queue
 system.ruby.dir_cntrl0.memBuffer.memInputQ           20                       # Delay in the input queue
-system.ruby.dir_cntrl0.memBuffer.memBankQ         5913                       # Delay behind the head of the bank queue
-system.ruby.dir_cntrl0.memBuffer.totalStalls       925400                       # Total number of stall cycles
-system.ruby.dir_cntrl0.memBuffer.stallsPerReq     3.466749                       # Expected number of stall cycles per request
-system.ruby.dir_cntrl0.memBuffer.memBankBusy       908855                       # memory stalls due to busy bank
-system.ruby.dir_cntrl0.memBuffer.memBusBusy         7819                       # memory stalls due to busy bus
+system.ruby.dir_cntrl0.memBuffer.memBankQ         5908                       # Delay behind the head of the bank queue
+system.ruby.dir_cntrl0.memBuffer.totalStalls       925390                       # Total number of stall cycles
+system.ruby.dir_cntrl0.memBuffer.stallsPerReq     3.466711                       # Expected number of stall cycles per request
+system.ruby.dir_cntrl0.memBuffer.memBankBusy       908852                       # memory stalls due to busy bank
+system.ruby.dir_cntrl0.memBuffer.memBusBusy         7818                       # memory stalls due to busy bus
 system.ruby.dir_cntrl0.memBuffer.memReadWriteBusy            5                       # memory stalls due to read write turnaround
 system.ruby.dir_cntrl0.memBuffer.memDataBusBusy            3                       # memory stalls due to read read turnaround
-system.ruby.dir_cntrl0.memBuffer.memArbWait         2785                       # memory stalls due to arbitration
+system.ruby.dir_cntrl0.memBuffer.memArbWait         2784                       # memory stalls due to arbitration
 system.ruby.dir_cntrl0.memBuffer.memBankCount |        8698      3.26%      3.26% |        8135      3.05%      6.31% |        8180      3.06%      9.37% |        8226      3.08%     12.45% |        8503      3.19%     15.64% |        8270      3.10%     18.74% |        8180      3.06%     21.80% |        8201      3.07%     24.87% |        8428      3.16%     28.03% |        8229      3.08%     31.11% |        8315      3.11%     34.23% |        8269      3.10%     37.33% |        8279      3.10%     40.43% |        8033      3.01%     43.44% |        8160      3.06%     46.49% |        7316      2.74%     49.23% |        8186      3.07%     52.30% |        8370      3.14%     55.44% |        8196      3.07%     58.51% |        8109      3.04%     61.54% |        8870      3.32%     64.87% |        8313      3.11%     67.98% |        8266      3.10%     71.08% |        8194      3.07%     74.15% |        8414      3.15%     77.30% |        8231      3.08%     80.38% |        8474      3.17%     83.56% |        9055      3.39%     86.95% |        8979      3.36%     90.31% |        8905      3.34%     93.65% |        8853      3.32%     96.97% |        8099      3.03%    100.00% # Number of accesses per bank
 system.ruby.dir_cntrl0.memBuffer.memBankCount::total       266936                       # Number of accesses per bank
 
@@ -535,6 +535,18 @@ system.ruby.network.routers5.msg_bytes.Response_Control::2     14631224
 system.ruby.network.routers5.msg_bytes.Writeback_Data::0    116862408                      
 system.ruby.network.routers5.msg_bytes.Writeback_Data::1        23472                      
 system.ruby.network.routers5.msg_bytes.Writeback_Control::0       657680                      
+system.ruby.network.msg_count.Control         8613696                      
+system.ruby.network.msg_count.Request_Control       388888                      
+system.ruby.network.msg_count.Response_Data      8909307                      
+system.ruby.network.msg_count.Response_Control     11246253                      
+system.ruby.network.msg_count.Writeback_Data      4870245                      
+system.ruby.network.msg_count.Writeback_Control       246630                      
+system.ruby.network.msg_byte.Control         68909568                      
+system.ruby.network.msg_byte.Request_Control      3111104                      
+system.ruby.network.msg_byte.Response_Data    641470104                      
+system.ruby.network.msg_byte.Response_Control     89970024                      
+system.ruby.network.msg_byte.Writeback_Data    350657640                      
+system.ruby.network.msg_byte.Writeback_Control      1973040                      
 system.pc.south_bridge.ide.disks0.dma_read_full_pages            0                       # Number of full page size DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_bytes        32768                       # Number of bytes transfered via DMA reads (not PRD).
 system.pc.south_bridge.ide.disks0.dma_read_txs           30                       # Number of DMA read transactions (not PRD).
@@ -550,21 +562,21 @@ system.pc.south_bridge.ide.disks1.dma_write_txs            1
 system.cpu0.numCycles                     10606609404                       # number of cpu cycles simulated
 system.cpu0.numWorkItemsStarted                     0                       # number of work items this cpu started
 system.cpu0.numWorkItemsCompleted                   0                       # number of work items this cpu completed
-system.cpu0.committedInsts                   91816947                       # Number of instructions committed
-system.cpu0.committedOps                    177194839                       # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses            167195942                       # Number of integer alu accesses
+system.cpu0.committedInsts                   91816948                       # Number of instructions committed
+system.cpu0.committedOps                    177194843                       # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses            167195946                       # Number of integer alu accesses
 system.cpu0.num_fp_alu_accesses                     0                       # Number of float alu accesses
 system.cpu0.num_func_calls                    2105705                       # number of times a function call or return occured
 system.cpu0.num_conditional_control_insts     16302138                       # number of instructions that are conditional controls
-system.cpu0.num_int_insts                   167195942                       # number of integer instructions
+system.cpu0.num_int_insts                   167195946                       # number of integer instructions
 system.cpu0.num_fp_insts                            0                       # number of float instructions
-system.cpu0.num_int_register_reads          412764336                       # number of times the integer registers were read
-system.cpu0.num_int_register_writes         208844309                       # number of times the integer registers were written
+system.cpu0.num_int_register_reads          412764349                       # number of times the integer registers were read
+system.cpu0.num_int_register_writes         208844314                       # number of times the integer registers were written
 system.cpu0.num_fp_register_reads                   0                       # number of times the floating registers were read
 system.cpu0.num_fp_register_writes                  0                       # number of times the floating registers were written
-system.cpu0.num_mem_refs                     19832606                       # number of memory refs
-system.cpu0.num_load_insts                   12787611                       # Number of load instructions
-system.cpu0.num_store_insts                   7044995                       # Number of store instructions
+system.cpu0.num_mem_refs                     19832608                       # number of memory refs
+system.cpu0.num_load_insts                   12787612                       # Number of load instructions
+system.cpu0.num_store_insts                   7044996                       # Number of store instructions
 system.cpu0.num_idle_cycles              9879410853.538599                       # Number of idle cycles
 system.cpu0.num_busy_cycles              727198550.461401                       # Number of busy cycles
 system.cpu0.not_idle_fraction                0.068561                       # Percentage of non-idle cycles
@@ -717,11 +729,11 @@ system.ruby.network.routers5.throttle4.link_utilization            0
 system.ruby.l1_cntrl0.Load               |    11418758     74.36%     74.36% |     3936572     25.64%    100.00%
 system.ruby.l1_cntrl0.Load::total            15355330                      
 
-system.ruby.l1_cntrl0.Ifetch             |   107191441     83.42%     83.42% |    21311032     16.58%    100.00%
-system.ruby.l1_cntrl0.Ifetch::total         128502473                      
+system.ruby.l1_cntrl0.Ifetch             |   107191443     83.42%     83.42% |    21311032     16.58%    100.00%
+system.ruby.l1_cntrl0.Ifetch::total         128502475                      
 
-system.ruby.l1_cntrl0.Store              |     7579460     69.10%     69.10% |     3389428     30.90%    100.00%
-system.ruby.l1_cntrl0.Store::total           10968888                      
+system.ruby.l1_cntrl0.Store              |     7579462     69.10%     69.10% |     3389428     30.90%    100.00%
+system.ruby.l1_cntrl0.Store::total           10968890                      
 
 system.ruby.l1_cntrl0.Inv                |       28983     54.10%     54.10% |       24594     45.90%    100.00%
 system.ruby.l1_cntrl0.Inv::total                53577                      
@@ -786,8 +798,8 @@ system.ruby.l1_cntrl0.I.L1_Replacement::total        26006
 system.ruby.l1_cntrl0.S.Load             |      738269     59.20%     59.20% |      508761     40.80%    100.00%
 system.ruby.l1_cntrl0.S.Load::total           1247030                      
 
-system.ruby.l1_cntrl0.S.Ifetch           |   106683217     83.54%     83.54% |    21021679     16.46%    100.00%
-system.ruby.l1_cntrl0.S.Ifetch::total       127704896                      
+system.ruby.l1_cntrl0.S.Ifetch           |   106683219     83.54%     83.54% |    21021679     16.46%    100.00%
+system.ruby.l1_cntrl0.S.Ifetch::total       127704898                      
 
 system.ruby.l1_cntrl0.S.Store            |       19704     47.71%     47.71% |       21592     52.29%    100.00%
 system.ruby.l1_cntrl0.S.Store::total            41296                      
@@ -819,8 +831,8 @@ system.ruby.l1_cntrl0.E.Fwd_GETS::total          2430
 system.ruby.l1_cntrl0.M.Load             |     6351147     70.61%     70.61% |     2643736     29.39%    100.00%
 system.ruby.l1_cntrl0.M.Load::total           8994883                      
 
-system.ruby.l1_cntrl0.M.Store            |     7142229     69.03%     69.03% |     3204343     30.97%    100.00%
-system.ruby.l1_cntrl0.M.Store::total         10346572                      
+system.ruby.l1_cntrl0.M.Store            |     7142231     69.03%     69.03% |     3204343     30.97%    100.00%
+system.ruby.l1_cntrl0.M.Store::total         10346574                      
 
 system.ruby.l1_cntrl0.M.Inv              |          52     15.95%     15.95% |         274     84.05%    100.00%
 system.ruby.l1_cntrl0.M.Inv::total                326                      
@@ -922,18 +934,6 @@ system.ruby.l2_cntrl0.MT_IIB.WB_Data_clean          561      0.00%      0.00%
 system.ruby.l2_cntrl0.MT_IIB.Unblock               98      0.00%      0.00%
 system.ruby.l2_cntrl0.MT_IB.WB_Data                98      0.00%      0.00%
 system.ruby.l2_cntrl0.MT_SB.Unblock             45449      0.00%      0.00%
-system.ruby.network.msg_count.Control         8613696                      
-system.ruby.network.msg_count.Request_Control       388888                      
-system.ruby.network.msg_count.Response_Data      8909307                      
-system.ruby.network.msg_count.Response_Control     11246253                      
-system.ruby.network.msg_count.Writeback_Data      4870245                      
-system.ruby.network.msg_count.Writeback_Control       246630                      
-system.ruby.network.msg_byte.Control         68909568                      
-system.ruby.network.msg_byte.Request_Control      3111104                      
-system.ruby.network.msg_byte.Response_Data    641470104                      
-system.ruby.network.msg_byte.Response_Control     89970024                      
-system.ruby.network.msg_byte.Writeback_Data    350657640                      
-system.ruby.network.msg_byte.Writeback_Control      1973040                      
 system.ruby.dir_cntrl0.Fetch                   172650      0.00%      0.00%
 system.ruby.dir_cntrl0.Data                     94286      0.00%      0.00%
 system.ruby.dir_cntrl0.Memory_Data             172650      0.00%      0.00%
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
index 2f2e7d9da..7d0863a29 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory/system.pc.com_1.terminal
@@ -1,16 +1,18 @@
 Linux version 2.6.22.9 (gblack@fajita) (gcc version 4.1.2 (Gentoo 4.1.2 p1.1)) #12 SMP Fri Feb 27 22:10:33 PST 2009

 Command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

 BIOS-provided physical RAM map:

- BIOS-e820: 0000000000000000 - 0000000000100000 (reserved)

+ BIOS-e820: 0000000000000000 - 000000000009fc00 (usable)

+ BIOS-e820: 000000000009fc00 - 0000000000100000 (reserved)

  BIOS-e820: 0000000000100000 - 0000000008000000 (usable)

 end_pfn_map = 32768

-kernel direct mapping tables up to 8000000 @ 100000-102000

+kernel direct mapping tables up to 8000000 @ 8000-a000

 DMI 2.5 present.

 Zone PFN ranges:

-  DMA           256 ->     4096

+  DMA             0 ->     4096

   DMA32        4096 ->  1048576

   Normal    1048576 ->  1048576

-early_node_map[1] active PFN ranges

+early_node_map[2] active PFN ranges

+    0:        0 ->      159

     0:      256 ->    32768

 Intel MultiProcessor Specification v1.4

 MPTABLE: OEM ID:  MPTABLE: Product ID:  MPTABLE: APIC at: 0xFEE00000

@@ -21,25 +23,25 @@ Setting APIC routing to flat
 Processors: 2

 Allocating PCI resources starting at 10000000 (gap: 8000000:f8000000)

 PERCPU: Allocating 34160 bytes of per cpu data

-Built 1 zonelists.  Total pages: 30461

+Built 1 zonelists.  Total pages: 30616

 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

 Initializing CPU#0

 PID hash table entries: 512 (order: 9, 4096 bytes)

 Marking TSC unstable due to TSCs unsynchronized

-time.c: Detected 2000.001 MHz processor.

+time.c: Detected 2000.000 MHz processor.

 Console: colour dummy device 80x25

 console handover: boot [earlyser0] -> real [ttyS0]

 Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)

 Inode-cache hash table entries: 8192 (order: 4, 65536 bytes)

 Checking aperture...

-Memory: 121384k/131072k available (3699k kernel code, 8500k reserved, 1767k data, 248k init)

+Memory: 122008k/131072k available (3699k kernel code, 8512k reserved, 1767k data, 248k init)

 Calibrating delay loop (skipped)... 3999.96 BogoMIPS preset

 Mount-cache hash table entries: 256

 CPU: L1 I Cache: 64K (64 bytes/line), D cache 64K (64 bytes/line)

 CPU: L2 Cache: 1024K (64 bytes/line)

 Freeing SMP alternatives: 34k freed

 Using local APIC timer interrupts.

-result 7812503

+result 7812500

 Detected 7.812 MHz APIC timer.

 Booting processor 1/2 APIC 0x1

 Initializing CPU#1

@@ -125,8 +127,8 @@ oprofile: using timer interrupt.
 TCP cubic registered

 NET: Registered protocol family 1

 NET: Registered protocol family 10

-input: PS/2 Generic Mouse as /class/input/input1

 IPv6 over IPv4 tunneling driver

+input: PS/2 Generic Mouse as /class/input/input1

 NET: Registered protocol family 17

 EXT2-fs warning: mounting unchecked fs, running e2fsck is recommended

 VFS: Mounted root (ext2 filesystem).

diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
index 2c35efbdd..9c98f7142 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/config.ini
@@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge cpu0 cpu1 cpu2 e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus
+children=acpi_description_table_pointer apicbridge bridge clk_domain cpu0 cpu1 cpu2 cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache l2c membus pc physmem smbios_table toL2Bus voltage_domain
 acpi_description_table_pointer=system.acpi_description_table_pointer
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=atomic
 mem_ranges=0:134217727
@@ -53,7 +54,7 @@ oem_table_id=
 
 [system.apicbridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=11529215046068469760:11529215046068473855
 req_size=16
@@ -63,20 +64,24 @@ slave=system.iobus.master[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
-slave=system.membus.master[1]
+slave=system.membus.master[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=AtomicSimpleCPU
-children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
+children=apic_clk_domain dcache dtb icache interrupts isa itb tracer
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -109,12 +114,17 @@ workload=
 dcache_port=system.cpu0.dcache.cpu_side
 icache_port=system.cpu0.icache.cpu_side
 
+[system.cpu0.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -125,12 +135,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=X86TLB
 children=walker
@@ -139,16 +158,17 @@ walker=system.cpu0.dtb.walker
 
 [system.cpu0.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -159,22 +179,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu0.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
 system=system
 int_master=system.membus.slave[3]
-int_slave=system.membus.master[3]
-pio=system.membus.master[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu0.isa]
 type=X86ISA
@@ -187,7 +216,8 @@ walker=system.cpu0.itb.walker
 
 [system.cpu0.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.toL2Bus.slave[2]
 
@@ -197,9 +227,8 @@ type=ExeTracer
 [system.cpu1]
 type=TimingSimpleCPU
 children=dtb isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -231,7 +260,8 @@ walker=system.cpu1.dtb.walker
 
 [system.cpu1.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 
 [system.cpu1.isa]
@@ -245,7 +275,8 @@ walker=system.cpu1.itb.walker
 
 [system.cpu1.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 
 [system.cpu1.tracer]
@@ -265,7 +296,7 @@ backComSize=5
 branchPred=system.cpu2.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -342,11 +373,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -360,7 +389,8 @@ walker=system.cpu2.dtb.walker
 
 [system.cpu2.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 
 [system.cpu2.fuPool]
@@ -637,12 +667,18 @@ walker=system.cpu2.itb.walker
 
 [system.cpu2.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 
 [system.cpu2.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.e820_table]
 type=X86E820Table
 children=entries0 entries1 entries2
@@ -1014,8 +1050,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -1025,10 +1060,10 @@ slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -1039,18 +1074,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[18]
 mem_side=system.membus.slave[4]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -1061,28 +1105,36 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.physmem.port system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave
+master=system.bridge.slave system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.physmem.port
 slave=system.apicbridge.master system.system_port system.l2c.mem_side system.cpu0.interrupts.int_master system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -1105,7 +1157,7 @@ system=system
 
 [system.pc.behind_pci]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854779128
 pio_latency=100000
@@ -1123,7 +1175,7 @@ pio=system.iobus.master[12]
 [system.pc.com_1]
 type=Uart8250
 children=terminal
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=9223372036854776824
 pio_latency=100000
 platform=system.pc
@@ -1147,7 +1199,7 @@ port=3456
 
 [system.pc.fake_com_2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776568
 pio_latency=100000
@@ -1164,7 +1216,7 @@ pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776808
 pio_latency=100000
@@ -1181,7 +1233,7 @@ pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776552
 pio_latency=100000
@@ -1198,7 +1250,7 @@ pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776818
 pio_latency=100000
@@ -1215,7 +1267,7 @@ pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854775936
 pio_latency=100000
@@ -1233,7 +1285,8 @@ pio=system.iobus.master[11]
 [system.pc.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.pc
 size=16777216
@@ -1256,7 +1309,7 @@ speaker=system.pc.south_bridge.speaker
 [system.pc.south_bridge.cmos]
 type=Cmos
 children=int_pin
-clock=1000
+clk_domain=system.clk_domain
 int_pin=system.pc.south_bridge.cmos.int_pin
 pio_addr=9223372036854775920
 pio_latency=100000
@@ -1269,7 +1322,7 @@ type=X86IntSourcePin
 
 [system.pc.south_bridge.dma1]
 type=I8237
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=9223372036854775808
 pio_latency=100000
 system=system
@@ -1316,7 +1369,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
@@ -1348,7 +1401,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -1368,7 +1421,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1451,7 +1504,7 @@ number=12
 [system.pc.south_bridge.io_apic]
 type=I82094AA
 apic_id=1
-clock=1000
+clk_domain=system.clk_domain
 external_int_pic=system.pc.south_bridge.pic1
 int_latency=1000
 pio_addr=4273995776
@@ -1463,7 +1516,7 @@ pio=system.iobus.master[10]
 [system.pc.south_bridge.keyboard]
 type=I8042
 children=keyboard_int_pin mouse_int_pin
-clock=1000
+clk_domain=system.clk_domain
 command_port=9223372036854775908
 data_port=9223372036854775904
 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
@@ -1482,7 +1535,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pic1]
 type=I8259
 children=output
-clock=1000
+clk_domain=system.clk_domain
 mode=I8259Master
 output=system.pc.south_bridge.pic1.output
 pio_addr=9223372036854775840
@@ -1497,7 +1550,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pic2]
 type=I8259
 children=output
-clock=1000
+clk_domain=system.clk_domain
 mode=I8259Slave
 output=system.pc.south_bridge.pic2.output
 pio_addr=9223372036854775968
@@ -1512,7 +1565,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pit]
 type=I8254
 children=int_pin
-clock=1000
+clk_domain=system.clk_domain
 int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=100000
@@ -1524,7 +1577,7 @@ type=X86IntSourcePin
 
 [system.pc.south_bridge.speaker]
 type=PcSpeaker
-clock=1000
+clk_domain=system.clk_domain
 i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=100000
@@ -1536,17 +1589,22 @@ type=SimpleDRAM
 activation_limit=4
 addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -1557,8 +1615,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[0]
+port=system.membus.master[3]
 
 [system.smbios_table]
 type=X86SMBiosSMBiosTable
@@ -1583,8 +1640,7 @@ version=
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -1592,3 +1648,7 @@ width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
index 56eeabc7e..4cf24e39a 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simerr
@@ -4,7 +4,6 @@ warn: Reading current count from inactive timer.
 warn: Sockets disabled, not accepting gdb connections
 warn: Don't know what interrupt to clear for console.
 hack: be nice to actually delete the event here
-warn: x86 cpuid: unknown family 0xbacc
 warn: instruction 'fxsave' unimplemented
 warn: x86 cpuid: unknown family 0x8086
 warn: x86 cpuid: unknown family 0x8086
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
index 9d0993153..f6878036a 100755
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/simout
@@ -1,12 +1,17142 @@
-Redirecting stdout to build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full/simout
-Redirecting stderr to build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full/simerr
+Redirecting stdout to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full/simout
+Redirecting stderr to build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 22 2013 15:54:37
-gem5 started Apr 22 2013 16:25:06
-gem5 executing on ribera.cs.wisc.edu
-command line: build/X86/gem5.fast -d build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re tests/run.py build/X86/tests/fast/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:36:11
+gem5 executing on zizzer
+command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-switcheroo-full
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
+      0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 1000000000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1000000500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 2000000500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2000001500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3000001500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3000012500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4000012500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5000012500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5000026000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 6000026000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 6000200500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 7000200500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 8000200500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 8000274000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 9000274000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 9000434500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 10000434500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 11000434500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 11000508000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 12000508000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 12000668500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 13000668500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 14000668500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 14000742000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 15000742000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 15000902500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 16000902500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 17000902500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 17000976000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 18000976000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 18001136500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 19001136500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 20001136500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 20001210000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 21001210000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 21001370500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 22001370500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 23001370500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 23001444000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 24001444000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 24001604500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 25001604500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 26001604500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 26001678000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 27001678000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 27001838500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 28001838500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 29001838500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 29001912000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 30001912000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 30002072500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 31002072500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 32002072500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 32002146000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 33002146000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 33002306500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 34002306500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 35002306500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 35002380000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 36002380000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 36002540500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 37002540500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 38002540500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 38002614000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 39002614000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 39002774500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 40002774500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 41002774500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 41002848000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 42002848000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 42003008500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 43003008500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 44003008500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 44003082000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 45003082000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 45003242500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 46003242500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 47003242500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 47003316000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 48003316000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 48003476500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 49003476500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 50003476500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 50003550000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 51003550000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 51003710500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 52003710500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 53003710500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 53003784000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 54003784000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 54003944500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 55003944500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 55003945500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 56003945500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 56003946000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 57003946000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 57004051500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 58004051500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 58004052500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 59004052500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 59004053000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 60004053000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 60004057000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 61004057000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 62004057000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 62004057500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 63004057500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 63004061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 64004061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 64004062000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 65004062000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 65004063000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 66004063000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 66004073000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 67004073000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 67004073500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 68004073500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 68004074000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 69004074000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 69004078000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 70004078000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 70004078500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 71004078500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 71004079000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 72004079000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 72004083000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 73004083000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 73004084500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 74004084500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 74004085000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 75004085000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 75004095000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 76004095000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 76004096500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 77004096500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 77004097000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 78004097000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 78004107000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 79004107000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 79004107500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 80004107500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 80004108000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 81004108000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 81004112000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 82004112000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 82004112500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 83004112500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 83004113000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 84004113000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 84004117000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 85004117000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 85004117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 86004117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 86004118000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 87004118000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 87004128000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 88004128000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 88004128500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 89004128500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 89004129500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 90004129500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 90004139500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 91004139500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 91004141000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 92004141000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 92004141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 93004141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 93004145500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 94004145500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 94004147000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 95004147000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 95004147500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 96004147500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 96004151500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 97004151500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 98004151500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 98004216000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 99004216000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 99004289500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 100004289500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 100004291000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 101004291000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 101004324000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 102004324000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 102004367500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 103004367500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 103004369000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 104004369000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 104004402000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 105004402000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 105004445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 106004445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 106004447000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 107004447000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 107004480000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 108004480000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 108004523500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 109004523500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 109004525000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 110004525000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 110004558000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 111004558000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 111004601500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 112004601500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 112004603000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 113004603000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 113004636000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 114004636000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 114004679500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 115004679500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 115004681000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 116004681000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 116004714000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 117004714000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 117004757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 118004757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 118004759000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 119004759000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 119004792000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 120004792000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 120004835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 121004835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 121004837000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 122004837000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 122004870000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 123004870000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 123004913500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 124004913500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 124004915000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 125004915000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 125004948000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 126004948000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 126004991500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 127004991500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 127004993000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 128004993000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 128005026000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 129005026000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 129005069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 130005069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 130005071000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 131005071000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 131005104000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 132005104000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 132005147500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 133005147500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 133005149000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 134005149000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 134005182000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 135005182000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 135005225500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 136005225500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 136005227000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 137005227000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 137005260000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 138005260000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 138005303500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 139005303500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 139005305000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 140005305000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 140005338000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 141005338000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 141005381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 142005381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 142005383000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 143005383000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 143005416000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 144005416000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 144005459500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 145005459500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 145005461000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 146005461000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 146005494000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 147005494000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 147005537500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 148005537500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 148005538000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 149005538000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 149005545500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 150005545500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 150005555000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 151005555000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 152005555000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 152005562500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 153005562500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 155293174000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 156293174000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 157293174000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 157293181500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 158293181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 159293125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 160293125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 161293125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 162293125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 163292997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 164292997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 165292997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 166292997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 167292869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 168292869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 169292869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 170292869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 171292741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 172292741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 173292741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 174292741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 175292613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 176292613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 177292613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 178292613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 179292485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 180292485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 181292485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 181292493000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 182292493000.  Starting simulation...
+info: Entering event queue @ 183292357000.  Starting simulation...
+info: Entering event queue @ 183292358000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 183292362500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 184292362500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 185292362500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 186292362500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 187292229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 188292229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 189292229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 190292229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 191292101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 192292101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 193292101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 193292109000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 194292109000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 194292215000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 195292215000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 195292215500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 196292215500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 196292223000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 197292223000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 197292262000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 198292262000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 199292262000.  Starting simulation...
+info: Entering event queue @ 199292269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 199292273000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 200292273000.  Starting simulation...
+info: Entering event queue @ 200292294500.  Starting simulation...
+info: Entering event queue @ 200292304500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 200292310000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 201292310000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 202292310000.  Starting simulation...
+info: Entering event queue @ 202292318000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 202292321000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 203292321000.  Starting simulation...
+info: Entering event queue @ 203292344000.  Starting simulation...
+info: Entering event queue @ 203292344500.  Starting simulation...
+info: Entering event queue @ 203292349000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 203292350000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 204292350000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 204292350500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 205292350500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 205292358000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 206292358000.  Starting simulation...
+info: Entering event queue @ 206292372500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 206292378000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 207292378000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 207292378500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 208292378500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 208292386000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 209292386000.  Starting simulation...
+info: Entering event queue @ 209292405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 209292411000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 210292411000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 210292412000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 211292412000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 211292428500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 212292428500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 212292441500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 213292441500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 214292441500.  Starting simulation...
+info: Entering event queue @ 214292451000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 214292454500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 215292454500.  Starting simulation...
+info: Entering event queue @ 215292695500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 215292703000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 216292703000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 216292704000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 217292704000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 217292711500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 218292711500.  Starting simulation...
+info: Entering event queue @ 218293082000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 218293089500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 219293089500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 220293089500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 220293097000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 221293097000.  Starting simulation...
+info: Entering event queue @ 221293105500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 221293110000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 222293110000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 222293110500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 223293110500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 223293118000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 224293118000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 224293159000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 225293159000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 225293159500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 226293159500.  Starting simulation...
+info: Entering event queue @ 226293167000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 226293169000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 227293169000.  Starting simulation...
+info: Entering event queue @ 227293269000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 227293276500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 228293276500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 228293277000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 229293277000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 229293284500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 230293284500.  Starting simulation...
+info: Entering event queue @ 231290821000.  Starting simulation...
+info: Entering event queue @ 231290822000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 231290826500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 232290826500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 233290826500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 233290834000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 234290834000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 235290693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 236290693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 237290693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 237290701000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 238290701000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 239290565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 240290565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 241290565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 241290573000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 242290573000.  Starting simulation...
+info: Entering event queue @ 243290437000.  Starting simulation...
+info: Entering event queue @ 243290438000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 243290442500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 244290442500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 245290442500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 246290442500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 247290309500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 248290309500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 249290309500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 250290309500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 251290181500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 252290181500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 253290181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 253290189000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 254290189000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 255290053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 256290053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 257290053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 258290053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 259289925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 260289925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 261289925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 262289925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 263289797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 264289797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 265289797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 266289797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 267289669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 268289669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 269289669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 269289677000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 270289677000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 271289541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 272289541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 273289541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 274289541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 275289413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 276289413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 277289413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 278289413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 279289285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 280289285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 281289285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 282289285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 283289157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 284289157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 285289157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 285289165000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 286289165000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 287289029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 288289029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 289289029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 290289029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 291288901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 292288901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 293288901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 294288901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 295288773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 296288773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 297288773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 298288773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 299288645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 300288645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 301288645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 301288653000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 302288653000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 303288517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 304288517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 305288517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 306288517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 307288389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 308288389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 309288389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 310288389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 311288261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 312288261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 313288261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 314288261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 315288133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 316288133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 317288133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 317288141000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 318288141000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 319288005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 320288005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 321288005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 322288005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 323287877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 324287877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 325287877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 326287877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 327287749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 328287749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 329287749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 330287749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 331287621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 332287621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 333287621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 334287621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 335287493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 336287493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 337287493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 338287493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 339287365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 340287365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 341287365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 342287365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 343287237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 344287237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 345287237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 346287237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 347287109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 348287109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 349287109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 350287109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 351286981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 352286981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 353286981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 354286981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 355286853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 356286853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 357286853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 358286853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 359286725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 360286725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 361286725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 362286725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 363286597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 364286597500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 365286597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 365286605000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 366286605000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 367286469500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 368286469500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 369286469500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 370286469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 371286341500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 372286341500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 373286341500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 374286341500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 375286213500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 376286213500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 377286213500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 378286213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 379286085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 380286085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 381286085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 381286093000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 382286093000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 383285957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 384285957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 385285957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 386285957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 387285829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 388285829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 389285829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 390285829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 391285701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 392285701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 393285701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 394285701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 395285573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 396285573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 397285573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 397285581000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 398285581000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 399285445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 400285445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 401285445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 402285445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 403285317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 404285317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 405285317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 406285317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 407285189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 408285189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 409285189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 410285189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 411285061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 412285061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 413285061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 413285069000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 414285069000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 415284933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 416284933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 417284933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 418284933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 419284805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 420284805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 421284805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 422284805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 423284677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 424284677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 425284677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 426284677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 427284549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 428284549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 429284549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 429284557000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 430284557000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 431284421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 432284421500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 433284421500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 434284421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 435284293500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 436284293500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 437284293500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 438284293500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 439284165500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 440284165500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 441284165500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 442284165500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 443284037500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 444284037500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 445284037500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 445284045000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 446284045000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 447283909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 448283909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 449283909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 450283909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 451283781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 452283781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 453283781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 454283781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 455283653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 456283653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 457283653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 458283653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 459283525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 460283525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 461283525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 461283533000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 462283533000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 463283397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 464283397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 465283397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 466283397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 467283269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 468283269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 469283269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 470283269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 471283141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 472283141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 473283141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 474283141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 475283013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 476283013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 477283013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 477283021000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 478283021000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 479282885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 480282885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 481282885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 482282885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 483282757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 484282757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 485282757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 486282757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 487282629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 488282629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 489282629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 490282629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 491282501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 492282501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 493282501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 493282509000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 494282509000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 495282373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 496282373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 497282373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 498282373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 499282245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 500282245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 501282245500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 502282245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 503282117500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 504282117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 505282117500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 506282117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 507281989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 508281989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 509281989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 510281989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 511281861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 512281861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 513281861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 514281861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 515281733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 516281733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 517281733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 518281733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 519281605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 520281605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 521281605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 522281605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 523281477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 524281477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 525281477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 526281477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 527281349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 528281349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 529281349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 530281349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 531281221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 532281221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 533281221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 534281221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 535281093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 536281093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 536281103000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 537281103000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 538281103000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 539280965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 540280965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 540280967500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 541280967500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 542280967500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 543280837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 544280837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 545280837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 546280837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 547280709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 548280709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 549280709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 550280709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 551280581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 552280581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 553280581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 554280581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 555280453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 556280453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 557280453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 558280453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 559280325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 560280325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 561280325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 562280325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 563280197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 564280197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 565280197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 566280197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 567280069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 568280069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 569280069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 570280069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 571279941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 572279941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 573279941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 574279941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 575279813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 576279813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 577279813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 578279813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 579279685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 580279685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 581279685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 582279685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 583279557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 584279557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 585279557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 586279557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 587279429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 588279429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 589279429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 590279429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 591279301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 592279301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 593279301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 594279301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 595279173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 596279173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 597279173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 598279173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 599279045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 600279045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 601279045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 602279045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 603278917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 604278917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 605278917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 606278917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 607278789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 608278789500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 609278789500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 610278789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 611278661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 612278661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 613278661500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 614278661500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 615278533500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 616278533500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 617278533500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 618278533500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 619278405500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 620278405500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 621278405500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 622278405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 623278277500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 624278277500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 625278277500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 626278277500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 627278149500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 628278149500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 629278149500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 630278149500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 631278021500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 632278021500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 633278021500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 634278021500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 635277893500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 636277893500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 637277893500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 638277893500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 639277765500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 640277765500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 641277765500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 642277765500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 643277637500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 644277637500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 645277637500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 646277637500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 647277509500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 648277509500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 649277509500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 650277509500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 651277381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 652277381500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 653277381500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 654277381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 655277253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 656277253500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 657277253500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 658277253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 659277125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 660277125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 661277125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 662277125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 663276997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 664276997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 665276997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 666276997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 667276869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 668276869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 669276869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 670276869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 671276741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 672276741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 673276741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 674276741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 675276613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 676276613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 677276613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 678276613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 679276485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 680276485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 681276485500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 682276485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 683276357500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 684276357500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 685276357500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 686276357500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 687276229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 688276229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 689276229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 690276229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 691276101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 692276101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 693276101500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 694276101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 695275973500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 696275973500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 697275973500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 698275973500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 699275845500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 700275845500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 701275845500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 702275845500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 703275717500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 704275717500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 705275717500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 706275717500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 707275589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 708275589500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 709275589500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 710275589500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 711275461500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 712275461500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 713275461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 714275461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 715275333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 716275333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 717275333500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 718275333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 719275205500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 720275205500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 721275205500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 722275205500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 723275077500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 724275077500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 725275077500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 726275077500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 727274949500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 728274949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 729274949500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 730274949500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 731274821500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 732274821500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 733274821500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 734274821500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 735274693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 736274693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 737274693500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 738274693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 739274565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 740274565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 741274565500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 742274565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 743274437500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 744274437500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 745274437500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 746274437500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 747274309500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 748274309500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 749274309500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 750274309500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 751274181500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 752274181500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 753274181500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 754274181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 755274053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 756274053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 757274053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 758274053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 759273925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 760273925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 761273925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 762273925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 763273797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 764273797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 765273797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 766273797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 767273669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 768273669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 769273669500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 770273669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 771273541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 772273541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 773273541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 774273541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 775273413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 776273413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 777273413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 778273413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 779273285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 780273285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 781273285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 782273285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 783273157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 784273157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 785273157500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 786273157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 787273029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 788273029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 789273029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 790273029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 791272901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 792272901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 793272901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 794272901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 795272773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 796272773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 797272773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 798272773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 799272645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 800272645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 801272645500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 802272645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 803272517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 804272517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 805272517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 806272517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 807272389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 808272389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 809272389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 810272389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 811272261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 812272261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 813272261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 814272261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 815272133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 816272133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 817272133500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 818272133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 819272005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 820272005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 821272005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 822272005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 823271877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 824271877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 825271877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 826271877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 827271749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 828271749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 829271749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 830271749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 831271621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 832271621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 833271621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 834271621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 835271493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 836271493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 837271493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 838271493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 839271365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 840271365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 841271365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 842271365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 843271237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 844271237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 845271237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 846271237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 847271109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 848271109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 849271109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 850271109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 851270981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 852270981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 853270981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 854270981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 855270853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 856270853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 857270853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 858270853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 859270725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 860270725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 861270725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 862270725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 863270597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 864270597500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 865270597500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 866270597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 867270469500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 868270469500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 869270469500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 870270469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 871270341500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 872270341500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 873270341500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 874270341500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 875270213500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 876270213500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 877270213500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 878270213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 879270085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 880270085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 881270085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 882270085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 883269957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 884269957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 885269957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 886269957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 887269829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 888269829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 889269829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 890269829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 891269701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 892269701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 893269701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 894269701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 895269573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 896269573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 897269573500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 898269573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 899269445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 900269445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 901269445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 902269445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 903269317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 904269317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 905269317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 906269317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 907269189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 908269189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 909269189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 910269189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 911269061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 912269061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 913269061500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 914269061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 915268933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 916268933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 917268933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 918268933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 919268805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 920268805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 921268805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 922268805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 923268677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 924268677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 925268677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 926268677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 927268549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 928268549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 929268549500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 930268549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 931268421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 932268421500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 933268421500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 934268421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 935268293500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 936268293500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 937268293500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 938268293500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 939268165500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 940268165500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 941268165500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 942268165500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 943268037500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 944268037500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 945268037500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 946268037500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 947267909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 948267909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 949267909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 950267909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 951267781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 952267781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 953267781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 954267781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 955267653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 956267653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 957267653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 958267653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 959267525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 960267525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 961267525500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 962267525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 963267397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 964267397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 965267397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 966267397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 967267269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 968267269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 969267269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 970267269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 971267141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 972267141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 973267141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 974267141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 975267013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 976267013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 977267013500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 978267013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 979266885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 980266885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 981266885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 982266885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 983266757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 984266757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 985266757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 986266757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 987266629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 988266629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 989266629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 990266629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 991266501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 992266501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 993266501500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 994266501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 995266373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 996266373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 997266373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 998266373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 999266245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1000266245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1001266245500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1002266245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1003266117500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1004266117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1005266117500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1006266117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1007265989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1008265989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1009265989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1010265989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1011265861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1012265861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1013265861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1014265861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1015265733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1016265733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1017265733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1018265733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1019265605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1020265605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1021265605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1022265605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1023265477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1024265477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1025265477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1026265477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1027265349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1028265349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1029265349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1030265349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1031265221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1032265221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1033265221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1034265221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1035265093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1036265093500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1037265093500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1038265093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1039264965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1040264965500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1041264965500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1042264965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1043264837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1044264837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1045264837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1046264837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1047264709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1048264709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1049264709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1050264709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1051264581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1052264581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1053264581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1054264581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1055264453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1056264453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1057264453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1058264453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1059264325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1060264325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1061264325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1062264325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1063264197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1064264197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1065264197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1066264197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1067264069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1068264069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1069264069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1070264069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1071263941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1072263941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1073263941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1074263941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1075263813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1076263813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1077263813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1078263813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1079263685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1080263685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1081263685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1082263685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1083263557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1084263557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1085263557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1086263557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1087263429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1088263429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1089263429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1090263429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1091263301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1092263301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1093263301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1094263301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1095263173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1096263173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1097263173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1098263173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1099263045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1100263045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1101263045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1102263045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1103262917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1104262917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1105262917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1106262917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1107262789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1108262789500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1109262789500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1110262789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1111262661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1112262661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1113262661500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1114262661500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1115262533500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1116262533500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1117262533500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1118262533500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1119262405500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1120262405500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1121262405500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1122262405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1123262277500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1124262277500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1125262277500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1126262277500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1127262149500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1128262149500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1129262149500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1130262149500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1131262021500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1132262021500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1133262021500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1134262021500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1135261893500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1136261893500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1137261893500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1138261893500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1139261765500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1140261765500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1141261765500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1142261765500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1143261637500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1144261637500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1145261637500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1146261637500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1147261509500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1148261509500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1149261509500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1150261509500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1151261381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1152261381500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1153261381500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1154261381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1155261253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1156261253500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1157261253500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1158261253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1159261125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1160261125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1161261125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1162261125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1163260997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1164260997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1165260997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1166260997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1167260869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1168260869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1169260869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1170260869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1171260741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1172260741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1173260741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1174260741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1175260613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1176260613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1177260613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1178260613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1179260485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1180260485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1181260485500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1182260485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1183260357500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1184260357500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1185260357500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1186260357500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1187260229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1188260229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1189260229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1190260229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1191260101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1192260101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1193260101500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1194260101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1195259973500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1196259973500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1197259973500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1198259973500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1199259845500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1200259845500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1201259845500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1202259845500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1203259717500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1204259717500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1205259717500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1206259717500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1207259589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1208259589500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1209259589500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1210259589500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1211259461500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1212259461500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1213259461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1214259461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1215259333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1216259333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1217259333500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1218259333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1219259205500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1220259205500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1221259205500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1222259205500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1223259077500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1224259077500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1225259077500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1226259077500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1227258949500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1228258949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1229258949500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1230258949500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1231258821500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1232258821500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1233258821500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1234258821500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1235258693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1236258693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1237258693500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1238258693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1239258565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1240258565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1241258565500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1242258565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1243258437500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1244258437500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1245258437500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1246258437500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1247258309500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1248258309500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1249258309500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1250258309500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1251258181500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1252258181500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1253258181500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1254258181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1255258053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1256258053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1257258053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1258258053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1259257925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1260257925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1261257925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1262257925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1263257797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1264257797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1265257797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1266257797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1267257669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1268257669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1269257669500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1270257669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1271257541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1272257541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1273257541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1274257541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1275257413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1276257413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1277257413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1278257413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1279257285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1280257285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1281257285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1282257285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1283257157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1284257157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1285257157500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1286257157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1287257029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1288257029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1289257029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1290257029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1291256901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1292256901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1293256901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1294256901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1295256773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1296256773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1297256773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1298256773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1299256645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1300256645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1301256645500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1302256645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1303256517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1304256517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1305256517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1306256517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1307256389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1308256389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1309256389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1310256389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1311256261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1312256261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1313256261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1314256261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1315256133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1316256133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1317256133500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1318256133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1319256005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1320256005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1321256005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1322256005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1323255877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1324255877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1325255877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1326255877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1327255749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1328255749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1329255749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1330255749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1331255621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1332255621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1333255621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1334255621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1335255493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1336255493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1337255493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1338255493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1339255365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1340255365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1341255365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1342255365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1343255237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1344255237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1345255237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1346255237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1347255109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1348255109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1349255109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1350255109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1351254981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1352254981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1353254981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1354254981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1355254853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1356254853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1357254853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1358254853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1359254725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1360254725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1361254725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1362254725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1363254597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1364254597500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1365254597500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1366254597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1367254469500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1368254469500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1369254469500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1370254469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1371254341500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1372254341500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1373254341500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1374254341500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1375254213500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1376254213500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1377254213500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1378254213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1379254085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1380254085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1381254085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1382254085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1383253957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1384253957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1385253957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1386253957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1387253829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1388253829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1389253829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1390253829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1391253701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1392253701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1393253701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1394253701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1395253573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1396253573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1397253573500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1398253573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1399253445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1400253445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1401253445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1402253445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1403253317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1404253317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1405253317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1406253317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1407253189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1408253189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1409253189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1410253189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1411253061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1412253061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1413253061500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1414253061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1415252933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1416252933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1417252933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1418252933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1419252805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1420252805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1421252805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1422252805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1423252677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1424252677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1425252677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1426252677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1427252549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1428252549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1429252549500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1430252549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1431252421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1432252421500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1433252421500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1434252421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1435252293500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1436252293500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1437252293500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1438252293500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1439252165500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1440252165500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1441252165500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1442252165500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1443252037500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1444252037500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1445252037500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1446252037500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1447251909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1448251909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1449251909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1450251909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1451251781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1452251781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1453251781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1454251781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1455251653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1456251653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1457251653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1458251653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1459251525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1460251525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1461251525500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1462251525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1463251397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1464251397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1465251397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1466251397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1467251269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1468251269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1469251269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1470251269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1471251141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1472251141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1473251141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1474251141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1475251013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1476251013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1477251013500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1478251013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1479250885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1480250885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1481250885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1482250885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1483250757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1484250757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1485250757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1486250757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1487250629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1488250629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1489250629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1490250629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1491250501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1492250501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1493250501500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1494250501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1495250373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1496250373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1497250373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1498250373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1499250245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1500250245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1501250245500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1502250245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1503250117500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1504250117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1505250117500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1506250117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1507249989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1508249989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1509249989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1510249989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1511249861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1512249861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1513249861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1514249861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1515249733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1516249733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1517249733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1518249733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1519249605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1520249605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1521249605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1522249605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1523249477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1524249477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1525249477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1526249477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1527249349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1528249349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1529249349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1530249349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1531249221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1532249221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1533249221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1534249221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1535249093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1536249093500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1537249093500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1538249093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1539248965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1540248965500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1541248965500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1542248965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1543248837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1544248837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1545248837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1546248837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1547248709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1548248709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1549248709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1550248709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1551248581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1552248581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1553248581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1554248581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1555248453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1556248453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1557248453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1558248453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1559248325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1560248325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1561248325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1562248325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1563248197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1564248197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1565248197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1566248197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1567248069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1568248069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1569248069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1570248069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1571247941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1572247941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1573247941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1574247941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1575247813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1576247813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1577247813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1578247813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1579247685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1580247685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1581247685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1582247685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1583247557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1584247557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1585247557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1586247557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1587247429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1588247429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1589247429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1590247429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1591247301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1592247301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1593247301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1594247301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1595247173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1596247173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1597247173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1598247173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1599247045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1600247045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1601247045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1602247045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1603246917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1604246917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1605246917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1606246917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1607246789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1608246789500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1609246789500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1610246789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1611246661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1612246661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1613246661500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1614246661500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1615246533500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1616246533500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1617246533500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1618246533500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1619246405500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1620246405500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1621246405500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1622246405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1623246277500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1624246277500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1625246277500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1626246277500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1627246149500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1628246149500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1629246149500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1630246149500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1631246021500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1632246021500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1633246021500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1634246021500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1635245893500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1636245893500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1637245893500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1638245893500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1639245765500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1640245765500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1641245765500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1642245765500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1643245637500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1644245637500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1645245637500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1646245637500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1647245509500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1648245509500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1649245509500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1650245509500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1651245381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1652245381500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1653245381500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1654245381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1655245253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1656245253500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1657245253500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1658245253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1659245125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1660245125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1661245125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1662245125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1663244997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1664244997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1665244997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1666244997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1667244869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1668244869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1669244869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1670244869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1671244741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1672244741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1673244741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1674244741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1675244613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1676244613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1677244613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1678244613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1679244485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1680244485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1681244485500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1682244485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1683244357500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1684244357500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1685244357500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1686244357500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1687244229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1688244229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1689244229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1690244229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1691244101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1692244101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1693244101500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1694244101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1695243973500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1696243973500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1697243973500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1698243973500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1699243845500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1700243845500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1701243845500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1702243845500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1703243717500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1704243717500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1705243717500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1706243717500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1707243589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1708243589500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1709243589500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1710243589500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1711243461500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1712243461500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1713243461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1714243461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1715243333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1716243333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1717243333500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1718243333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1719243205500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1720243205500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1721243205500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1722243205500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1723243077500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1724243077500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1725243077500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1726243077500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1727242949500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1728242949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1729242949500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1730242949500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1731242821500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1732242821500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1733242821500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1734242821500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1735242693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1736242693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1737242693500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1738242693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1739242565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1740242565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1741242565500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1742242565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1743242437500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1744242437500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1745242437500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1746242437500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1747242309500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1748242309500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1749242309500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1750242309500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1751242181500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1752242181500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1753242181500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1754242181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1755242053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1756242053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1757242053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1758242053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1759241925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1760241925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1761241925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1762241925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1763241797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1764241797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1765241797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1766241797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1767241669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1768241669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1769241669500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1770241669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1771241541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1772241541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1773241541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1774241541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1775241413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1776241413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1777241413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1778241413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1779241285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1780241285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1781241285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1782241285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1783241157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1784241157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1785241157500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1786241157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1787241029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1788241029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1789241029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1790241029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1791240901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1792240901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1793240901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1794240901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1795240773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1796240773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1797240773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1798240773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1799240645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1800240645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1801240645500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1802240645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1803240517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1804240517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1805240517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1806240517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1807240389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1808240389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1809240389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1810240389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1811240261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1812240261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1813240261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1814240261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1815240133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1816240133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1817240133500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1818240133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1819240005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1820240005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1821240005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1822240005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1823239877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1824239877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1825239877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1826239877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1827239749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1828239749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1829239749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1830239749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1831239621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1832239621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1833239621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1834239621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1835239493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1836239493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1837239493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1838239493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1839239365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1840239365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1841239365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1842239365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1843239237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1844239237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1845239237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1846239237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1847239109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1848239109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1849239109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1850239109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1851238981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1852238981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1853238981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1854238981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1855238853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1856238853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1857238853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1858238853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1859238725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1860238725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1861238725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1862238725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1863238597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1864238597500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1865238597500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1866238597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1867238469500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1868238469500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1869238469500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1870238469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1871238341500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1872238341500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1873238341500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1874238341500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1875238213500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1876238213500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1877238213500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1878238213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1879238085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1880238085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1881238085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1882238085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1883237957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1884237957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1885237957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1886237957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1887237829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1888237829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1889237829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1890237829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1891237701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1892237701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1893237701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1894237701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1895237573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1896237573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1897237573500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1898237573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1899237445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1900237445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1901237445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1902237445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1903237317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1904237317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1905237317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1906237317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1907237189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1908237189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1909237189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1910237189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1911237061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1912237061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1913237061500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1914237061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1915236933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1916236933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1917236933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1918236933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1919236805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1920236805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1921236805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1922236805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1923236677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1924236677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1925236677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1926236677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1927236549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1928236549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1929236549500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1930236549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1931236421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1932236421500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1933236421500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1934236421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1935236293500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1936236293500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1937236293500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1938236293500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1939236165500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1940236165500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1941236165500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1942236165500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1943236037500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1944236037500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1945236037500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1946236037500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1947235909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1948235909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1949235909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1950235909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1951235781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1952235781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1953235781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1954235781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1955235653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1956235653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1957235653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1958235653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1959235525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1960235525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1961235525500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1962235525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1963235397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1964235397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1965235397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1966235397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1967235269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1968235269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1969235269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1970235269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1971235141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1972235141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1973235141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1974235141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1975235013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1976235013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1977235013500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1978235013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1979234885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1980234885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1981234885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1982234885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1983234757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1984234757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1985234757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1986234757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1987234629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1988234629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1989234629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1990234629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1991234501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1992234501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1993234501500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1994234501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1995234373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 1996234373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 1997234373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 1998234373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 1999234245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2000234245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2001234245500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2002234245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2003234117500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2004234117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2005234117500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2006234117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2007233989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2008233989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2009233989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2010233989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2011233861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2012233861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2013233861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2014233861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2015233733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2016233733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2017233733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2018233733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2019233605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2020233605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2021233605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2022233605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2023233477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2024233477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2025233477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2026233477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2027233349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2028233349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2029233349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2030233349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2031233221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2032233221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2033233221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2034233221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2035233093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2036233093500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2037233093500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2038233093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2039232965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2040232965500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2041232965500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2042232965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2043232837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2044232837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2045232837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2046232837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2047232709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2048232709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2049232709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2050232709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2051232581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2052232581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2053232581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2054232581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2055232453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2056232453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2057232453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2058232453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2059232325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2060232325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2061232325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2062232325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2063232197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2064232197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2065232197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2066232197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2067232069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2068232069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2069232069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2070232069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2071231941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2072231941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2073231941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2074231941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2075231813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2076231813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2077231813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2078231813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2079231685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2080231685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2081231685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2082231685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2083231557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2084231557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2085231557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2086231557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2087231429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2088231429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2089231429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2090231429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2091231301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2092231301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2093231301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2094231301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2095231173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2096231173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2097231173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2098231173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2099231045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2100231045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2101231045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2102231045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2103230917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2104230917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2105230917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2106230917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2107230789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2108230789500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2109230789500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2110230789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2111230661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2112230661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2113230661500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2114230661500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2115230533500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2116230533500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2117230533500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2118230533500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2119230405500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2120230405500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2121230405500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2122230405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2123230277500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2124230277500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2125230277500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2126230277500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2127230149500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2128230149500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2129230149500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2130230149500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2131230021500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2132230021500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2133230021500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2134230021500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2135229893500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2136229893500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2137229893500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2138229893500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2139229765500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2140229765500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2141229765500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2142229765500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2143229637500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2144229637500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2145229637500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2146229637500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2147229509500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2148229509500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2149229509500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2150229509500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2151229381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2152229381500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2153229381500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2154229381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2155229253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2156229253500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2157229253500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2158229253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2159229125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2160229125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2161229125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2162229125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2163228997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2164228997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2165228997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2166228997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2167228869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2168228869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2169228869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2170228869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2171228741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2172228741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2173228741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2174228741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2175228613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2176228613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2177228613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2178228613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2179228485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2180228485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2181228485500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2182228485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2183228357500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2184228357500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2185228357500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2186228357500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2187228229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2188228229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2189228229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2190228229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2191228101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2192228101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2193228101500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2194228101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2195227973500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2196227973500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2197227973500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2198227973500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2199227845500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2200227845500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2201227845500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2202227845500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2203227717500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2204227717500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2205227717500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2206227717500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2207227589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2208227589500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2209227589500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2210227589500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2211227461500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2212227461500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2213227461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2214227461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2215227333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2216227333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2217227333500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2218227333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2219227205500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2220227205500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2221227205500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2222227205500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2223227077500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2224227077500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2225227077500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2226227077500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2227226949500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2228226949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2229226949500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2230226949500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2231226821500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2232226821500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2233226821500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2234226821500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2235226693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2236226693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2237226693500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2238226693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2239226565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2240226565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2241226565500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2242226565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2243226437500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2244226437500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2245226437500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2246226437500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2247226309500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2248226309500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2249226309500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2250226309500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2251226181500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2252226181500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2253226181500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2254226181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2255226053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2256226053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2257226053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2258226053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2259225925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2260225925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2261225925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2262225925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2263225797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2264225797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2265225797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2266225797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2267225669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2268225669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2269225669500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2270225669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2271225541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2272225541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2273225541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2274225541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2275225413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2276225413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2277225413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2278225413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2279225285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2280225285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2281225285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2282225285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2283225157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2284225157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2285225157500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2286225157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2287225029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2288225029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2289225029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2290225029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2291224901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2292224901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2293224901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2294224901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2295224773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2296224773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2297224773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2298224773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2299224645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2300224645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2301224645500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2302224645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2303224517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2304224517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2305224517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2306224517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2307224389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2308224389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2309224389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2310224389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2311224261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2312224261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2313224261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2314224261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2315224133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2316224133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2317224133500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2318224133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2319224005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2320224005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2321224005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2322224005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2323223877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2324223877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2325223877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2326223877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2327223749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2328223749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2329223749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2330223749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2331223621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2332223621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2333223621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2334223621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2335223493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2336223493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2337223493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2338223493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2339223365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2340223365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2341223365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2342223365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2343223237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2344223237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2345223237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2346223237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2347223109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2348223109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2349223109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2350223109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2351222981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2352222981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2353222981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2354222981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2355222853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2356222853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2357222853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2358222853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2359222725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2360222725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2361222725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2362222725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2363222597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2364222597500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2365222597500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2366222597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2367222469500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2368222469500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2369222469500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2370222469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2371222341500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2372222341500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2373222341500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2374222341500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2375222213500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2376222213500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2377222213500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2378222213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2379222085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2380222085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2381222085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2382222085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2383221957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2384221957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2385221957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2386221957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2387221829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2388221829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2389221829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2390221829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2391221701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2392221701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2393221701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2394221701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2395221573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2396221573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2397221573500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2398221573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2399221445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2400221445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2401221445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2402221445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2403221317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2404221317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2405221317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2406221317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2407221189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2408221189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2409221189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2410221189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2411221061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2412221061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2413221061500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2414221061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2415220933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2416220933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2417220933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2418220933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2419220805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2420220805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2421220805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2422220805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2423220677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2424220677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2425220677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2426220677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2427220549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2428220549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2429220549500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2430220549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2431220421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2432220421500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2433220421500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2434220421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2435220293500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2436220293500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2437220293500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2438220293500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2439220165500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2440220165500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2441220165500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2442220165500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2443220037500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2444220037500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2445220037500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2446220037500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2447219909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2448219909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2449219909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2450219909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2451219781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2452219781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2453219781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2454219781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2455219653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2456219653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2457219653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2458219653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2459219525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2460219525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2461219525500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2462219525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2463219397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2464219397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2465219397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2466219397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2467219269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2468219269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2469219269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2470219269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2471219141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2472219141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2473219141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2474219141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2475219013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2476219013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2477219013500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2478219013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2479218885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2480218885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2481218885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2482218885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2483218757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2484218757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2485218757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2486218757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2487218629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2488218629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2489218629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2490218629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2491218501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2492218501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2493218501500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2494218501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2495218373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2496218373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2497218373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2498218373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2499218245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2500218245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2501218245500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2502218245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2503218117500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2504218117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2505218117500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2506218117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2507217989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2508217989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2509217989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2510217989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2511217861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2512217861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2513217861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2514217861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2515217733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2516217733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2517217733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2518217733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2519217605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2520217605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2521217605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2522217605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2523217477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2524217477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2525217477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2526217477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2527217349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2528217349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2529217349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2530217349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2531217221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2532217221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2533217221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2534217221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2535217093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2536217093500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2537217093500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2538217093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2539216965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2540216965500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2541216965500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2542216965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2543216837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2544216837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2545216837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2546216837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2547216709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2548216709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2549216709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2550216709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2551216581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2552216581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2553216581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2554216581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2555216453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2556216453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2557216453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2558216453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2559216325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2560216325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2561216325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2562216325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2563216197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2564216197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2565216197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2566216197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2567216069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2568216069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2569216069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2570216069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2571215941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2572215941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2573215941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2574215941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2575215813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2576215813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2577215813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2578215813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2579215685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2580215685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2581215685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2582215685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2583215557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2584215557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2585215557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2586215557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2587215429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2588215429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2589215429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2590215429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2591215301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2592215301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2593215301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2594215301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2595215173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2596215173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2597215173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2598215173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2599215045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2600215045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2601215045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2602215045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2603214917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2604214917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2605214917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2606214917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2607214789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2608214789500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2609214789500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2610214789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2611214661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2612214661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2613214661500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2614214661500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2615214533500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2616214533500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2617214533500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2618214533500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2619214405500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2620214405500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2621214405500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2622214405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2623214277500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2624214277500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2625214277500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2626214277500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2627214149500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2628214149500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2629214149500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2630214149500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2631214021500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2632214021500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2633214021500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2634214021500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2635213893500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2636213893500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2637213893500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2638213893500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2639213765500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2640213765500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2641213765500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2642213765500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2643213637500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2644213637500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2645213637500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2646213637500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2647213509500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2648213509500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2649213509500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2650213509500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2651213381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2652213381500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2653213381500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2654213381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2655213253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2656213253500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2657213253500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2658213253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2659213125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2660213125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2661213125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2662213125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2663212997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2664212997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2665212997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2666212997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2667212869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2668212869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2669212869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2670212869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2671212741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2672212741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2673212741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2674212741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2675212613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2676212613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2677212613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2678212613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2679212485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2680212485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2681212485500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2682212485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2683212357500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2684212357500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2685212357500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2686212357500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2687212229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2688212229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2689212229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2690212229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2691212101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2692212101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2693212101500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2694212101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2695211973500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2696211973500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2697211973500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2698211973500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2699211845500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2700211845500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2701211845500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2702211845500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2703211717500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2704211717500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2705211717500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2706211717500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2707211589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2708211589500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2709211589500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2710211589500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2711211461500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2712211461500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2713211461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2714211461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2715211333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2716211333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2717211333500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2718211333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2719211205500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2720211205500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2721211205500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2722211205500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2723211077500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2724211077500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2725211077500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2726211077500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2727210949500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2728210949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2729210949500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2730210949500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2731210821500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2732210821500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2733210821500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2734210821500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2735210693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2736210693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2737210693500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2738210693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2739210565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2740210565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2741210565500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2742210565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2743210437500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2744210437500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2745210437500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2746210437500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2747210309500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2748210309500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2749210309500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2750210309500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2751210181500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2752210181500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2753210181500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2754210181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2755210053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2756210053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2757210053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2758210053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2759209925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2760209925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2761209925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2762209925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2763209797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2764209797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2765209797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2766209797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2767209669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2768209669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2769209669500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2770209669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2771209541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2772209541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2773209541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2774209541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2775209413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2776209413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2777209413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2778209413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2779209285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2780209285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2781209285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2782209285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2783209157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2784209157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2785209157500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2786209157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2787209029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2788209029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2789209029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2790209029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2791208901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2792208901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2793208901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2794208901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2795208773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2796208773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2797208773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2798208773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2799208645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2800208645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2801208645500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2802208645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2803208517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2804208517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2805208517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2806208517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2807208389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2808208389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2809208389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2810208389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2811208261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2812208261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2813208261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2814208261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2815208133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2816208133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2817208133500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2818208133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2819208005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2820208005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2821208005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2822208005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2823207877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2824207877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2825207877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2826207877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2827207749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2828207749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2829207749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2830207749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2831207621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2832207621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2833207621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2834207621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2835207493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2836207493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2837207493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2838207493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2839207365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2840207365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2841207365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2842207365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2843207237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2844207237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2845207237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2846207237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2847207109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2848207109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2849207109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2850207109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2851206981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2852206981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2853206981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2854206981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2855206853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2856206853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2857206853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2858206853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2859206725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2860206725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2861206725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2862206725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2863206597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2864206597500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2865206597500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2866206597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2867206469500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2868206469500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2869206469500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2870206469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2871206341500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2872206341500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2873206341500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2874206341500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2875206213500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2876206213500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2877206213500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2878206213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2879206085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2880206085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2881206085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2882206085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2883205957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2884205957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2885205957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2886205957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2887205829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2888205829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2889205829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2890205829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2891205701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2892205701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2893205701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2894205701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2895205573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2896205573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2897205573500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2898205573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2899205445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2900205445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2901205445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2902205445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2903205317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2904205317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2905205317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2906205317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2907205189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2908205189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2909205189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2910205189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2911205061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2912205061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2913205061500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2914205061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2915204933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2916204933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2917204933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2918204933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2919204805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2920204805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2921204805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2922204805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2923204677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2924204677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2925204677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2926204677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2927204549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2928204549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2929204549500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2930204549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2931204421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2932204421500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2933204421500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2934204421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2935204293500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2936204293500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2937204293500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2938204293500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2939204165500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2940204165500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2941204165500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2942204165500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2943204037500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2944204037500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2945204037500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2946204037500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2947203909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2948203909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2949203909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2950203909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2951203781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2952203781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2953203781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2954203781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2955203653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2956203653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2957203653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2958203653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2959203525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2960203525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2961203525500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2962203525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2963203397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2964203397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2965203397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2966203397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2967203269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2968203269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2969203269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2970203269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2971203141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2972203141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2973203141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2974203141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2975203013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2976203013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2977203013500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2978203013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2979202885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2980202885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2981202885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2982202885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2983202757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2984202757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2985202757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2986202757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2987202629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2988202629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2989202629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2990202629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2991202501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2992202501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2993202501500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2994202501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2995202373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 2996202373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 2997202373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2998202373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 2999202245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3000202245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3001202245500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3002202245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3003202117500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3004202117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3005202117500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3006202117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3007201989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3008201989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3009201989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3010201989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3011201861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3012201861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3013201861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3014201861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3015201733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3016201733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3017201733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3018201733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3019201605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3020201605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3021201605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3022201605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3023201477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3024201477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3025201477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3026201477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3027201349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3028201349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3029201349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3030201349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3031201221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3032201221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3033201221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3034201221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3035201093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3036201093500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3037201093500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3038201093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3039200965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3040200965500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3041200965500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3042200965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3043200837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3044200837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3045200837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3046200837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3047200709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3048200709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3049200709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3050200709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3051200581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3052200581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3053200581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3054200581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3055200453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3056200453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3057200453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3058200453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3059200325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3060200325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3061200325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3062200325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3063200197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3064200197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3065200197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3066200197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3067200069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3068200069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3069200069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3070200069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3071199941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3072199941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3073199941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3074199941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3075199813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3076199813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3077199813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3078199813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3079199685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3080199685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3081199685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3082199685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3083199557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3084199557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3085199557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3086199557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3087199429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3088199429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3089199429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3090199429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3091199301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3092199301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3093199301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3094199301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3095199173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3096199173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3097199173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3098199173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3099199045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3100199045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3101199045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3102199045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3103198917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3104198917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3105198917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3106198917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3107198789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3108198789500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3109198789500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3110198789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3111198661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3112198661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3113198661500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3114198661500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3115198533500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3116198533500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3117198533500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3118198533500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3119198405500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3120198405500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3121198405500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3122198405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3123198277500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3124198277500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3125198277500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3126198277500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3127198149500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3128198149500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3129198149500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3130198149500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3131198021500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3132198021500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3133198021500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3134198021500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3135197893500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3136197893500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3137197893500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3138197893500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3139197765500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3140197765500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3141197765500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3142197765500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3143197637500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3144197637500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3145197637500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3146197637500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3147197509500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3148197509500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3149197509500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3150197509500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3151197381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3152197381500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3153197381500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3154197381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3155197253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3156197253500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3157197253500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3158197253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3159197125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3160197125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3161197125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3162197125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3163196997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3164196997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3165196997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3166196997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3167196869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3168196869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3169196869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3170196869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3171196741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3172196741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3173196741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3174196741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3175196613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3176196613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3177196613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3178196613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3179196485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3180196485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3181196485500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3182196485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3183196357500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3184196357500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3185196357500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3186196357500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3187196229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3188196229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3189196229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3190196229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3191196101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3192196101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3193196101500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3194196101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3195195973500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3196195973500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3197195973500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3198195973500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3199195845500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3200195845500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3201195845500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3202195845500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3203195717500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3204195717500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3205195717500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3206195717500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3207195589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3208195589500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3209195589500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3210195589500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3211195461500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3212195461500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3213195461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3214195461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3215195333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3216195333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3217195333500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3218195333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3219195205500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3220195205500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3221195205500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3222195205500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3223195077500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3224195077500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3225195077500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3226195077500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3227194949500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3228194949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3229194949500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3230194949500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3231194821500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3232194821500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3233194821500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3234194821500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3235194693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3236194693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3237194693500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3238194693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3239194565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3240194565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 3241194565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3241194573000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3242194573000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3242194585000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3243194585000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 3244194585000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3244194592500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3245194592500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3245194600000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3246194600000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 3247194600000.  Starting simulation...
+info: Entering event queue @ 3247194611000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3247194613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3248194613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3248194621000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3249194621000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 3250194621000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3250194621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3251194621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3251194629000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3252194629000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3253194629000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3254194629000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3255194053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3256194053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3257194053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3258194053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3259193925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3260193925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3261193925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3262193925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3263193797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3264193797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3265193797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3266193797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3267193669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3268193669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3269193669500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3270193669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3271193541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3272193541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3273193541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3274193541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3275193413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3276193413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3277193413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3278193413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3279193285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3280193285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3281193285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3282193285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3283193157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3284193157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3285193157500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3286193157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3287193029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3288193029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3289193029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3290193029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3291192901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3292192901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3293192901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3294192901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3295192773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3296192773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3297192773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3298192773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3299192645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3300192645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3301192645500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3302192645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3303192517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3304192517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3305192517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3306192517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3307192389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3308192389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3309192389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3310192389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3311192261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3312192261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3313192261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3314192261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3315192133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3316192133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3317192133500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3318192133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3319192005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3320192005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3321192005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3322192005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3323191877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3324191877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3325191877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3326191877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3327191749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3328191749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3329191749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3330191749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3331191621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3332191621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3333191621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3334191621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3335191493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3336191493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3337191493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3338191493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3339191365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3340191365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3341191365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3342191365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3343191237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3344191237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3345191237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3346191237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3347191109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3348191109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3349191109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3350191109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3351190981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3352190981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3353190981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3354190981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3355190853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3356190853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3357190853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3358190853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3359190725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3360190725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3361190725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3362190725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3363190597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3364190597500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3365190597500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3366190597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3367190469500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3368190469500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3369190469500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3370190469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3371190341500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3372190341500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3373190341500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3374190341500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3375190213500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3376190213500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3377190213500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3378190213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3379190085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3380190085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3381190085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3382190085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3383189957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3384189957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3385189957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3386189957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3387189829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3388189829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3389189829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3390189829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3391189701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3392189701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3393189701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3394189701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3395189573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3396189573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3397189573500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3398189573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3399189445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3400189445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3401189445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3402189445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3403189317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3404189317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3405189317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3406189317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3407189189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3408189189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3409189189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3410189189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3411189061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3412189061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3413189061500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3414189061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3415188933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3416188933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3417188933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3418188933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3419188805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3420188805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3421188805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3422188805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3423188677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3424188677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3425188677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3426188677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3427188549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3428188549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3429188549500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3430188549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3431188421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3432188421500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3433188421500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3434188421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3435188293500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3436188293500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3437188293500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3438188293500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3439188165500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3440188165500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3441188165500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3442188165500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3443188037500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3444188037500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3445188037500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3446188037500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3447187909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3448187909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3449187909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3450187909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3451187781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3452187781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3453187781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3454187781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3455187653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3456187653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3457187653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3458187653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3459187525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3460187525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3461187525500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3462187525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3463187397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3464187397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3465187397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3466187397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3467187269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3468187269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3469187269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3470187269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3471187141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3472187141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3473187141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3474187141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3475187013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3476187013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3477187013500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3478187013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3479186885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3480186885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3481186885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3482186885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3483186757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3484186757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3485186757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3486186757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3487186629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3488186629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3489186629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3490186629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3491186501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3492186501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3493186501500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3494186501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3495186373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3496186373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3497186373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3498186373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3499186245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3500186245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3501186245500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3502186245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3503186117500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3504186117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3505186117500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3506186117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3507185989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3508185989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3509185989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3510185989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3511185861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3512185861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3513185861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3514185861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3515185733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3516185733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3517185733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3518185733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3519185605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3520185605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3521185605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3522185605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3523185477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3524185477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3525185477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3526185477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3527185349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3528185349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3529185349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3530185349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3531185221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3532185221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3533185221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3534185221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3535185093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3536185093500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3537185093500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3538185093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3539184965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3540184965500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3541184965500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3542184965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3543184837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3544184837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3545184837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3546184837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3547184709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3548184709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3549184709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3550184709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3551184581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3552184581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3553184581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3554184581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3555184453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3556184453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3557184453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3558184453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3559184325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3560184325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3561184325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3562184325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3563184197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3564184197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3565184197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3566184197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3567184069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3568184069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3569184069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3570184069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3571183941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3572183941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3573183941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3574183941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3575183813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3576183813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3577183813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3578183813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3579183685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3580183685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3581183685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3582183685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3583183557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3584183557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3585183557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3586183557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3587183429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3588183429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3589183429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3590183429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3591183301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3592183301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3593183301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3594183301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3595183173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3596183173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3597183173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3598183173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3599183045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3600183045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3601183045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3602183045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3603182917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3604182917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3605182917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3606182917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3607182789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3608182789500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3609182789500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3610182789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3611182661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3612182661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3613182661500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3614182661500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3615182533500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3616182533500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3617182533500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3618182533500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3619182405500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3620182405500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3621182405500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3622182405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3623182277500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3624182277500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3625182277500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3626182277500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3627182149500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3628182149500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3629182149500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3630182149500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3631182021500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3632182021500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3633182021500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3634182021500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3635181893500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3636181893500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3637181893500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3638181893500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3639181765500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3640181765500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3641181765500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3642181765500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3643181637500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3644181637500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3645181637500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3646181637500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3647181509500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3648181509500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3649181509500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3650181509500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3651181381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3652181381500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3653181381500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3654181381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3655181253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3656181253500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3657181253500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3658181253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3659181125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3660181125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3661181125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3662181125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3663180997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3664180997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3665180997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3666180997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3667180869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3668180869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3669180869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3670180869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3671180741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3672180741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3673180741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3674180741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3675180613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3676180613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3677180613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3678180613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3679180485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3680180485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3681180485500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3682180485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3683180357500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3684180357500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3685180357500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3686180357500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3687180229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3688180229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3689180229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3690180229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3691180101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3692180101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3693180101500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3694180101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3695179973500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3696179973500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3697179973500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3698179973500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3699179845500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3700179845500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3701179845500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3702179845500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3703179717500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3704179717500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3705179717500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3706179717500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3707179589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3708179589500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3709179589500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3710179589500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3711179461500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3712179461500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3713179461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3714179461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3715179333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3716179333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3717179333500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3718179333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3719179205500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3720179205500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3721179205500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3722179205500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3723179077500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3724179077500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3725179077500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3726179077500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3727178949500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3728178949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3729178949500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3730178949500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3731178821500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3732178821500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3733178821500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3734178821500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3735178693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3736178693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3737178693500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3738178693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3739178565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3740178565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3741178565500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3742178565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3743178437500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3744178437500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3745178437500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3746178437500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3747178309500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3748178309500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3749178309500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3750178309500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3751178181500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3752178181500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3753178181500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3754178181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3755178053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3756178053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3757178053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3758178053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3759177925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3760177925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3761177925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3762177925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3763177797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3764177797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3765177797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3766177797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3767177669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3768177669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3769177669500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3770177669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3771177541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3772177541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3773177541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3774177541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3775177413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3776177413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3777177413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3778177413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3779177285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3780177285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3781177285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3782177285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3783177157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3784177157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3785177157500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3786177157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3787177029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3788177029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3789177029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3790177029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3791176901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3792176901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3793176901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3794176901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3795176773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3796176773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3797176773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3798176773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3799176645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3800176645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3801176645500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3802176645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3803176517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3804176517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3805176517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3806176517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3807176389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3808176389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3809176389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3810176389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3811176261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3812176261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3813176261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3814176261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3815176133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3816176133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3817176133500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3818176133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3819176005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3820176005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3821176005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3822176005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3823175877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3824175877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3825175877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3826175877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3827175749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3828175749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3829175749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3830175749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3831175621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3832175621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3833175621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3834175621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3835175493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3836175493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3837175493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3838175493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3839175365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3840175365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3841175365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3842175365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3843175237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3844175237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3845175237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3846175237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3847175109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3848175109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3849175109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3850175109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3851174981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3852174981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3853174981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3854174981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3855174853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3856174853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3857174853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3858174853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3859174725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3860174725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3861174725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3862174725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3863174597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 3864174597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3864174598500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 3865174598500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3865174599000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3866174599000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3866174603000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3867174603000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 3868174603000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3868174604000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3869174604000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3869174608000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3870174608000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 3871174608000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3871174608500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3872174608500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3872174616000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3873174616000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3874174616000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3875174616000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3875174619500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3876174619500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3877174619500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3878174619500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3879174082000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3880174082000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3881174082000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3882174082000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3883173957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3884173957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3885173957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3886173957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3887173829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3888173829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3889173829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3890173829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3891173701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3892173701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3893173701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3894173701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3895173573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3896173573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3897173573500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3898173573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3899173445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3900173445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3901173445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3902173445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3903173317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3904173317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3905173317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3906173317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3907173189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3908173189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3909173189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3910173189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3911173061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3912173061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3913173061500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3914173061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3915172933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3916172933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3917172933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3918172933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3919172805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3920172805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3921172805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3922172805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3923172677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3924172677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3925172677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3926172677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3927172549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3928172549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3929172549500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3930172549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3931172421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3932172421500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3933172421500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3934172421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3935172293500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3936172293500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3937172293500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3938172293500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3939172165500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3940172165500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3941172165500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3942172165500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3943172037500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3944172037500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3945172037500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3946172037500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3947171909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3948171909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3949171909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3950171909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3951171781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3952171781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3953171781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3954171781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3955171653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3956171653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3957171653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3958171653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3959171525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3960171525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3961171525500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3962171525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3963171397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3964171397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3965171397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3966171397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3967171269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3968171269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3969171269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3970171269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3971171141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3972171141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3973171141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3974171141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3975171013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3976171013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3977171013500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3978171013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3979170885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3980170885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3981170885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3982170885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3983170757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3984170757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3985170757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3986170757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3987170629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3988170629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3989170629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3990170629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3991170501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3992170501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3993170501500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3994170501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3995170373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 3996170373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 3997170373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 3998170373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 3999170245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4000170245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4001170245500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4002170245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4003170117500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4004170117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4005170117500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4006170117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4007169989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4008169989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4009169989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4010169989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4011169861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4012169861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4013169861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4014169861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4015169733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4016169733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4017169733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4018169733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4019169605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4020169605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4021169605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4022169605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4023169477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4024169477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4025169477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4026169477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4027169349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4028169349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4029169349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4030169349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4031169221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4032169221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4033169221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4034169221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4035169093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4036169093500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4037169093500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4038169093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4039168965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4040168965500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4041168965500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4042168965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4043168837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4044168837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4045168837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4046168837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4047168709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4048168709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4049168709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4050168709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4051168581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4052168581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4053168581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4054168581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4055168453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4056168453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4057168453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4058168453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4059168325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4060168325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4061168325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4062168325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4063168197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4064168197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4065168197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4066168197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4067168069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4068168069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4069168069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4070168069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4071167941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4072167941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4073167941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4074167941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4075167813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4076167813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4077167813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4078167813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4079167685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4080167685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4081167685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4082167685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4083167557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4084167557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4085167557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4086167557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4087167429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4088167429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4089167429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4090167429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4091167301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4092167301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4093167301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4094167301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4095167173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4096167173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4097167173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4098167173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4099167045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4100167045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4101167045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4102167045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4103166917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4104166917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4105166917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4106166917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4107166789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4108166789500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4109166789500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4110166789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4111166661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4112166661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4113166661500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4114166661500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4115166533500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4116166533500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4117166533500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4118166533500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4119166405500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4120166405500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4121166405500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4122166405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4123166277500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4124166277500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4125166277500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4126166277500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4127166149500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4128166149500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4129166149500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4130166149500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4131166021500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4132166021500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4133166021500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4134166021500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4135165893500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4136165893500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4137165893500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4138165893500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4139165765500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4140165765500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4141165765500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4142165765500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4143165637500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4144165637500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4145165637500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4146165637500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4147165509500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4148165509500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4149165509500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4150165509500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4151165381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4152165381500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4153165381500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4154165381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4155165253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4156165253500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4157165253500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4158165253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4159165125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4160165125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4161165125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4162165125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4163164997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4164164997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4165164997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4166164997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4167164869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4168164869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4169164869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4170164869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4171164741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4172164741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4173164741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4174164741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4175164613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4176164613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4177164613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4178164613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4179164485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4180164485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4181164485500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4182164485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4183164357500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4184164357500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4185164357500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4186164357500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4187164229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4188164229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4189164229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4190164229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4191164101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4192164101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4193164101500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4194164101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4195163973500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4196163973500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4197163973500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4198163973500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4199163845500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4200163845500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4201163845500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4202163845500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4203163717500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4204163717500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4205163717500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4206163717500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4207163589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4208163589500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4209163589500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4210163589500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4211163461500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4212163461500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4213163461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4214163461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4215163333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4216163333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4217163333500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4218163333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4219163205500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4220163205500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4221163205500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4222163205500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4223163077500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4224163077500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4225163077500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4226163077500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4227162949500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4228162949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4229162949500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4230162949500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4231162821500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4232162821500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4233162821500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4234162821500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4235162693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4236162693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4237162693500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4238162693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4239162565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4240162565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4241162565500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4242162565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4243162437500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4244162437500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4245162437500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4246162437500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4247162309500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4248162309500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4249162309500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4250162309500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4251162181500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4252162181500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4253162181500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4254162181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4255162053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4256162053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4257162053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4258162053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4259161925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4260161925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4261161925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4262161925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4263161797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4264161797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4265161797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4266161797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4267161669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4268161669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4269161669500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4270161669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4271161541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4272161541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4273161541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4274161541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4275161413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4276161413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4277161413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4278161413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4279161285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4280161285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4281161285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4282161285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4283161157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4284161157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4285161157500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4286161157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4287161029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4288161029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4289161029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4290161029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4291160901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4292160901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4293160901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4294160901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4295160773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4296160773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4297160773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4298160773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4299160645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4300160645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4301160645500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4302160645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4303160517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4304160517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4305160517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4306160517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4307160389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4308160389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4309160389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4310160389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4311160261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4312160261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4313160261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4314160261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4315160133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4316160133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4317160133500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4318160133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4319160005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4320160005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4321160005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4322160005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4323159877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4324159877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4325159877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4326159877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4327159749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4328159749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4329159749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4330159749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4331159621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4332159621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4333159621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4334159621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4335159493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4336159493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4337159493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4338159493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4339159365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4340159365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4341159365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4342159365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4343159237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4344159237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4345159237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4346159237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4347159109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4348159109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4349159109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4350159109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4351158981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4352158981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4353158981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4354158981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4355158853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4356158853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4357158853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4358158853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4359158725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4360158725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4361158725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4362158725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4363158597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4364158597500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4365158597500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4366158597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4367158469500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4368158469500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4369158469500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4370158469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4371158341500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4372158341500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4373158341500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4374158341500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4375158213500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4376158213500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4377158213500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4378158213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4379158085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4380158085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4381158085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4382158085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4383157957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4384157957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4385157957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4386157957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4387157829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4388157829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4389157829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4390157829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4391157701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4392157701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4393157701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4394157701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4395157573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4396157573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4397157573500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4398157573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4399157445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4400157445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4401157445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4402157445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4403157317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4404157317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4405157317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4406157317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4407157189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4408157189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4409157189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4410157189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4411157061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4412157061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4413157061500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4414157061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4415156933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4416156933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4417156933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4418156933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4419156805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4420156805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4421156805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4422156805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4423156677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4424156677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4425156677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4426156677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4427156549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4428156549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4429156549500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4430156549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4431156421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 4432156421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4432156422500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 4433156422500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4433156423000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4434156423000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4434156427000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4435156427000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 4436156427000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4436156428000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4437156428000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4437156432000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4438156432000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 4439156432000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4439156432500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4440156432500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4440156440000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4441156440000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4442156440000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4443156440000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4443156443500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4444156443500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4445156443500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4446156443500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4447155909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4448155909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4449155909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4450155909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4451155781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4452155781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4453155781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4454155781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4455155653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4456155653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4457155653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4458155653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4459155525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4460155525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4461155525500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4462155525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4463155397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4464155397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4465155397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4466155397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4467155269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4468155269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4469155269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4470155269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4471155141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4472155141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4473155141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4474155141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4475155013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4476155013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4477155013500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4478155013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4479154885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4480154885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4481154885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4482154885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4483154757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4484154757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4485154757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4486154757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4487154629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4488154629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4489154629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4490154629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4491154501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4492154501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4493154501500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4494154501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4495154373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4496154373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4497154373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4498154373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4499154245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4500154245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4501154245500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4502154245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4503154117500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4504154117500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4505154117500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4506154117500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4507153989500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4508153989500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4509153989500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4510153989500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4511153861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4512153861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4513153861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4514153861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4515153733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4516153733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4517153733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4518153733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4519153605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4520153605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4521153605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4522153605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4523153477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4524153477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4525153477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4526153477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4527153349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4528153349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4529153349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4530153349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4531153221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4532153221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4533153221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4534153221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4535153093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4536153093500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4537153093500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4538153093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4539152965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4540152965500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4541152965500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4542152965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4543152837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4544152837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4545152837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4546152837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4547152709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4548152709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4549152709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4550152709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4551152581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4552152581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4553152581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4554152581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4555152453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4556152453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4557152453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4558152453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4559152325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4560152325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4561152325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4562152325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4563152197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4564152197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4565152197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4566152197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4567152069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4568152069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4569152069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4570152069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4571151941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4572151941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4573151941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4574151941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4575151813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4576151813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4577151813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4578151813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4579151685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4580151685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4581151685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4582151685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4583151557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4584151557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4585151557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4586151557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4587151429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4588151429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4589151429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4590151429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4591151301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4592151301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4593151301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4594151301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4595151173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4596151173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4597151173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4598151173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4599151045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4600151045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4601151045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4602151045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4603150917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4604150917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4605150917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4606150917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4607150789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4608150789500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4609150789500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4610150789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4611150661500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4612150661500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4613150661500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4614150661500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4615150533500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4616150533500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4617150533500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4618150533500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4619150405500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4620150405500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4621150405500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4622150405500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4623150277500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4624150277500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4625150277500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4626150277500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4627150149500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4628150149500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4629150149500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4630150149500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4631150021500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4632150021500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4633150021500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4634150021500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4635149893500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4636149893500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4637149893500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4638149893500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4639149765500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4640149765500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4641149765500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4642149765500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4643149637500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4644149637500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4645149637500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4646149637500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4647149509500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4648149509500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4649149509500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4650149509500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4651149381500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4652149381500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4653149381500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4654149381500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4655149253500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4656149253500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4657149253500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4658149253500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4659149125500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4660149125500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4661149125500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4662149125500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4663148997500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4664148997500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4665148997500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4666148997500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4667148869500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4668148869500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4669148869500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4670148869500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4671148741500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4672148741500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4673148741500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4674148741500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4675148613500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4676148613500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4677148613500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4678148613500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4679148485500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4680148485500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4681148485500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4682148485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4683148357500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4684148357500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4685148357500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4686148357500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4687148229500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4688148229500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4689148229500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4690148229500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4691148101500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4692148101500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4693148101500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4694148101500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4695147973500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4696147973500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4697147973500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4698147973500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4699147845500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4700147845500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4701147845500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4702147845500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4703147717500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4704147717500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4705147717500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4706147717500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4707147589500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4708147589500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4709147589500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4710147589500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4711147461500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4712147461500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4713147461500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4714147461500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4715147333500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4716147333500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4717147333500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4718147333500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4719147205500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4720147205500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4721147205500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4722147205500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4723147077500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4724147077500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4725147077500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4726147077500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4727146949500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4728146949500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4729146949500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4730146949500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4731146821500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4732146821500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4733146821500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4734146821500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4735146693500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4736146693500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4737146693500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4738146693500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4739146565500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4740146565500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4741146565500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4742146565500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4743146437500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4744146437500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4745146437500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4746146437500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4747146309500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4748146309500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4749146309500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4750146309500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4751146181500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4752146181500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4753146181500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4754146181500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4755146053500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4756146053500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4757146053500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4758146053500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4759145925500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4760145925500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4761145925500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4762145925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4763145797500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4764145797500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4765145797500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4766145797500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4767145669500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4768145669500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4769145669500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4770145669500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4771145541500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4772145541500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4773145541500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4774145541500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4775145413500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4776145413500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4777145413500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4778145413500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4779145285500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4780145285500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4781145285500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4782145285500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4783145157500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4784145157500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4785145157500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4786145157500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4787145029500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4788145029500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4789145029500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4790145029500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4791144901500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4792144901500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4793144901500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4794144901500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4795144773500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4796144773500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4797144773500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4798144773500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4799144645500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4800144645500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4801144645500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4802144645500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4803144517500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4804144517500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4805144517500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4806144517500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4807144389500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4808144389500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4809144389500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4810144389500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4811144261500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4812144261500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4813144261500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4814144261500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4815144133500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4816144133500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4817144133500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4818144133500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4819144005500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4820144005500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4821144005500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4822144005500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4823143877500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4824143877500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4825143877500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4826143877500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4827143749500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4828143749500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4829143749500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4830143749500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4831143621500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4832143621500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4833143621500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4834143621500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4835143493500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4836143493500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4837143493500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4838143493500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4839143365500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4840143365500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4841143365500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4842143365500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4843143237500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4844143237500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4845143237500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4846143237500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4847143109500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4848143109500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4849143109500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4850143109500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4851142981500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4852142981500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4853142981500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4854142981500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4855142853500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4856142853500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4857142853500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4858142853500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4859142725500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4860142725500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4861142725500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4862142725500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4863142597500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4864142597500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4865142597500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4866142597500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4867142469500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4868142469500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4869142469500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4870142469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4871142341500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4872142341500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4873142341500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4874142341500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4875142213500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4876142213500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4877142213500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4878142213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4879142085500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4880142085500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4881142085500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4882142085500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4883141957500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4884141957500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4885141957500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4886141957500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4887141829500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4888141829500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4889141829500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4890141829500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4891141701500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4892141701500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4893141701500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4894141701500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4895141573500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4896141573500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4897141573500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4898141573500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4899141445500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4900141445500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4901141445500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4902141445500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4903141317500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4904141317500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4905141317500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4906141317500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4907141189500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4908141189500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4909141189500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4910141189500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4911141061500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4912141061500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4913141061500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4914141061500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4915140933500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4916140933500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4917140933500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4918140933500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4919140805500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4920140805500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4921140805500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4922140805500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4923140677500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4924140677500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4925140677500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4926140677500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4927140549500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4928140549500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4929140549500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4930140549500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4931140421500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4932140421500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4933140421500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4934140421500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4935140293500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4936140293500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4937140293500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4938140293500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4939140165500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4940140165500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4941140165500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4942140165500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4943140037500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4944140037500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4945140037500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4946140037500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4947139909500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4948139909500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4949139909500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4950139909500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4951139781500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4952139781500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4953139781500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4954139781500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4955139653500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4956139653500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4957139653500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4958139653500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4959139525500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4960139525500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4961139525500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4962139525500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4963139397500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4964139397500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4965139397500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4966139397500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4967139269500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4968139269500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4969139269500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4970139269500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4971139141500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4972139141500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4973139141500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4974139141500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4975139013500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4976139013500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4977139013500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4978139013500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4979138885500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4980138885500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4981138885500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4982138885500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4983138757500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4984138757500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4985138757500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4986138757500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4987138629500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4988138629500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4989138629500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4990138629500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4991138501500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4992138501500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4993138501500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4994138501500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4995138373500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 4996138373500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 4997138373500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 4998138373500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 4999138245500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5000138245500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5001138245500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5001138253000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5002138253000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5002138262500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5003138262500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5004138262500.  Starting simulation...
+info: Entering event queue @ 5004138451000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5004138458500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5005138458500.  Starting simulation...
+info: Entering event queue @ 5007137924500.  Starting simulation...
+info: Entering event queue @ 5007137925500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5007137930000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5008137930000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5009137930000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5010137930000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5011137861500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5012137861500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5013137861500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5014137861500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5015137733500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5016137733500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5017137733500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5018137733500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5019137605500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5020137605500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5021137605500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5022137605500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5023137477500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5024137477500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5025137477500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5026137477500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5027137349500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5028137349500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5029137349500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5030137349500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5031137221500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5032137221500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5033137221500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5034137221500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5035137093500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5036137093500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5037137093500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5038137093500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5039136965500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5040136965500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5041136965500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5042136965500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5043136837500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5044136837500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5045136837500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5046136837500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5047136709500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5048136709500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5049136709500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5050136709500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5051136581500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5052136581500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5053136581500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5054136581500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5055136453500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5056136453500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5057136453500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5058136453500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5059136325500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5060136325500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5061136325500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5062136325500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5063136197500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5064136197500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5065136197500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5066136197500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5067136069500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5068136069500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5069136069500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5070136069500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5071135941500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5072135941500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5073135941500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5074135941500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5075135813500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5076135813500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5077135813500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5078135813500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5079135685500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5080135685500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5081135685500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5082135685500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5083135557500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5084135557500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5085135557500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5086135557500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5087135429500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5088135429500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5089135429500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5090135429500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5091135301500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5092135301500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5093135301500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5094135301500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5095135173500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5096135173500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5097135173500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5098135173500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5099135045500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5100135045500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5101135045500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5102135045500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5103134917500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5104134917500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5105134917500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5106134917500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5107134789500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 5108134789500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5108134791000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5109134791000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5109134798500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5110134798500.  Starting simulation...
+info: Entering event queue @ 5110134845250.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5110134982250.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5111134982250.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5112134982250.  Starting simulation...
+info: Entering event queue @ 5112135240000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5112135247500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5113135247500.  Starting simulation...
+info: Entering event queue @ 5115134468500.  Starting simulation...
+info: Entering event queue @ 5115134469500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5115134474000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 5116134474000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5116134474500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5117134474500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5117134482000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5118134482000.  Starting simulation...
+info: Entering event queue @ 5119134341500.  Starting simulation...
+info: Entering event queue @ 5119134342500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5119134347000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 5120134347000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5120134348500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5121134348500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5121134356000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5122134356000.  Starting simulation...
+info: Entering event queue @ 5123134212500.  Starting simulation...
+info: Entering event queue @ 5123134213500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5123134218000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5124134218000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+switching cpus
+info: Entering event queue @ 5125134218000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5126134218000.  Starting simulation...
+info: Entering event queue @ 5127134484500.  Starting simulation...
+info: Entering event queue @ 5127134485500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5127134490000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5128134490000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5129134490000.  Starting simulation...
+info: Entering event queue @ 5129134497500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5129134498000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5130134498000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5130134511000.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+switching cpus
+info: Entering event queue @ 5131134511000.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5132134511000.  Starting simulation...
+info: Entering event queue @ 5132134561000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5132134794500.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5133134794500.  Starting simulation...
+info: Entering event queue @ 5135133830000.  Starting simulation...
+info: Entering event queue @ 5135133831000.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5135133835500.  Starting simulation...
+Switching CPUs...
+Next CPU: TimingSimpleCPU
+info: Entering event queue @ 5136133835500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5136133836500.  Starting simulation...
+Switching CPUs...
+Next CPU: DerivO3CPU
+info: Entering event queue @ 5137133836500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5137133844000.  Starting simulation...
+Switching CPUs...
+Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 5138133844000.  Starting simulation...
+info: Entering event queue @ 5139134126500.  Starting simulation...
+info: Entering event queue @ 5139134127500.  Starting simulation...
+switching cpus
+info: Entering event queue @ 5139134132000.  Starting simulation...
diff --git a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
index eec6d9444..3b61c4c39 100644
--- a/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
+++ b/tests/long/fs/10.linux-boot/ref/x86/linux/pc-switcheroo-full/system.pc.com_1.terminal
@@ -27,7 +27,7 @@ Built 1 zonelists.  Total pages: 30613
 Kernel command line: earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1

 Initializing CPU#0

 PID hash table entries: 512 (order: 9, 4096 bytes)

-time.c: Detected 1999.988 MHz processor.

+time.c: Detected 1999.986 MHz processor.

 Console: colour dummy device 80x25

 console handover: boot [earlyser0] -> real [ttyS0]

 Dentry cache hash table entries: 16384 (order: 5, 131072 bytes)

@@ -43,7 +43,7 @@ ACPI: Core revision 20070126
 ACPI Exception (tbxface-0618): AE_NO_ACPI_TABLES, While loading namespace from ACPI tables [20070126]

 ACPI: Unable to load the System Description Tables

 Using local APIC timer interrupts.

-result 7812471

+result 7812464

 Detected 7.812 MHz APIC timer.

 NET: Registered protocol family 16

 PCI: Using configuration type 1

diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
index e058c4cd9..8dffb60f8 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/config.ini
@@ -13,28 +13,28 @@ boot_osflags=a
 cache_line_size=64
 clk_domain=system.clk_domain
 hypervisor_addr=1099243257856
-hypervisor_bin=/scratch/nilay/GEM5/system/binaries/q_new.bin
+hypervisor_bin=/dist/m5/system/binaries/q_new.bin
 hypervisor_desc=system.hypervisor_desc
 hypervisor_desc_addr=133446500352
-hypervisor_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-hv.bin
+hypervisor_desc_bin=/dist/m5/system/binaries/1up-hv.bin
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=1048576:68157439 2147483648:2415919103
-memories=system.hypervisor_desc system.nvram system.physmem1 system.physmem0 system.partition_desc system.rom
+memories=system.rom system.physmem1 system.hypervisor_desc system.physmem0 system.nvram system.partition_desc
 num_work_ids=16
 nvram=system.nvram
 nvram_addr=133429198848
-nvram_bin=/scratch/nilay/GEM5/system/binaries/nvram1
+nvram_bin=/dist/m5/system/binaries/nvram1
 openboot_addr=1099243716608
-openboot_bin=/scratch/nilay/GEM5/system/binaries/openboot_new.bin
+openboot_bin=/dist/m5/system/binaries/openboot_new.bin
 partition_desc=system.partition_desc
 partition_desc_addr=133445976064
-partition_desc_bin=/scratch/nilay/GEM5/system/binaries/1up-md.bin
+partition_desc_bin=/dist/m5/system/binaries/1up-md.bin
 readfile=tests/halt.sh
 reset_addr=1099243192320
-reset_bin=/scratch/nilay/GEM5/system/binaries/reset_new.bin
+reset_bin=/dist/m5/system/binaries/reset_new.bin
 rom=system.rom
 symbolfile=
 work_begin_ckpt_count=0
@@ -140,7 +140,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/disk.s10hw2
+image_file=/dist/m5/system/disks/disk.s10hw2
 read_only=true
 
 [system.hypervisor_desc]
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
index 49566b7e3..387f71a0d 100755
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simerr
@@ -14,6 +14,14 @@ warn: rounding error > tolerance
     0.145519 rounded to 0
 warn: rounding error > tolerance
     0.145519 rounded to 0
+warn: rounding error > tolerance
+    0.145519 rounded to 0
+warn: rounding error > tolerance
+    0.145519 rounded to 0
+warn: rounding error > tolerance
+    0.145519 rounded to 0
+warn: rounding error > tolerance
+    0.145519 rounded to 0
 warn: Sockets disabled, not accepting terminal connections
 warn: CoherentBus system.membus has no snooping ports attached!
 warn: Sockets disabled, not accepting gdb connections
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
index e5c65571f..e75f41d79 100755
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/simout
@@ -1,8 +1,10 @@
+Redirecting stdout to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simout
+Redirecting stderr to build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar  3 2013 21:18:30
-gem5 started Mar  3 2013 22:32:14
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:07:33
 gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic -re tests/run.py build/SPARC/tests/opt/long/fs/80.solaris-boot/sparc/solaris/t1000-simple-atomic
 Global frequency set at 2000000000 ticks per second
diff --git a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
index 51f3de6f4..be15ea4e1 100644
--- a/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
+++ b/tests/long/fs/80.solaris-boot/ref/sparc/solaris/t1000-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.233778                       # Nu
 sim_ticks                                  4467555024                       # Number of ticks simulated
 final_tick                                 4467555024                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   2000000000                       # Frequency of simulated ticks
-host_inst_rate                                1777607                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1778305                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                3563977                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 572484                       # Number of bytes of host memory used
-host_seconds                                  1253.53                       # Real time elapsed on the host
+host_inst_rate                                3036891                       # Simulator instruction rate (inst/s)
+host_op_rate                                  3038085                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                6088754                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 524036                       # Number of bytes of host memory used
+host_seconds                                   733.74                       # Real time elapsed on the host
 sim_insts                                  2228284650                       # Number of instructions simulated
 sim_ops                                    2229160714                       # Number of ops (including micro ops) simulated
 system.hypervisor_desc.bytes_read::cpu.data        16792                       # Number of bytes read from this memory
@@ -19,20 +19,22 @@ system.hypervisor_desc.bw_read::cpu.data         7517                       # To
 system.hypervisor_desc.bw_read::total            7517                       # Total read bandwidth from this memory (bytes/s)
 system.hypervisor_desc.bw_total::cpu.data         7517                       # Total bandwidth to/from this memory (bytes/s)
 system.hypervisor_desc.bw_total::total           7517                       # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bytes_read::cpu.data                 284                       # Number of bytes read from this memory
-system.nvram.bytes_read::total                    284                       # Number of bytes read from this memory
-system.nvram.bytes_written::cpu.data               92                       # Number of bytes written to this memory
-system.nvram.bytes_written::total                  92                       # Number of bytes written to this memory
-system.nvram.num_reads::cpu.data                  284                       # Number of read requests responded to by this memory
-system.nvram.num_reads::total                     284                       # Number of read requests responded to by this memory
-system.nvram.num_writes::cpu.data                  92                       # Number of write requests responded to by this memory
-system.nvram.num_writes::total                     92                       # Number of write requests responded to by this memory
-system.nvram.bw_read::cpu.data                    127                       # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_read::total                       127                       # Total read bandwidth from this memory (bytes/s)
-system.nvram.bw_write::cpu.data                    41                       # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_write::total                       41                       # Write bandwidth from this memory (bytes/s)
-system.nvram.bw_total::cpu.data                   168                       # Total bandwidth to/from this memory (bytes/s)
-system.nvram.bw_total::total                      168                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.bytes_read::cpu.inst                432296                       # Number of bytes read from this memory
+system.rom.bytes_read::cpu.data                696392                       # Number of bytes read from this memory
+system.rom.bytes_read::total                  1128688                       # Number of bytes read from this memory
+system.rom.bytes_inst_read::cpu.inst           432296                       # Number of instructions bytes read from this memory
+system.rom.bytes_inst_read::total              432296                       # Number of instructions bytes read from this memory
+system.rom.num_reads::cpu.inst                 108074                       # Number of read requests responded to by this memory
+system.rom.num_reads::cpu.data                  87049                       # Number of read requests responded to by this memory
+system.rom.num_reads::total                    195123                       # Number of read requests responded to by this memory
+system.rom.bw_read::cpu.inst                   193527                       # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_read::cpu.data                   311755                       # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_read::total                      505282                       # Total read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read::cpu.inst              193527                       # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_inst_read::total                 193527                       # Instruction read bandwidth from this memory (bytes/s)
+system.rom.bw_total::cpu.inst                  193527                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.bw_total::cpu.data                  311755                       # Total bandwidth to/from this memory (bytes/s)
+system.rom.bw_total::total                     505282                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem1.bytes_read::cpu.inst       8318106840                       # Number of bytes read from this memory
 system.physmem1.bytes_read::cpu.data       1495885127                       # Number of bytes read from this memory
 system.physmem1.bytes_read::total          9813991967                       # Number of bytes read from this memory
@@ -81,6 +83,20 @@ system.physmem0.bw_write::total               6894251                       # Wr
 system.physmem0.bw_total::cpu.inst          274105779                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem0.bw_total::cpu.data           50557518                       # Total bandwidth to/from this memory (bytes/s)
 system.physmem0.bw_total::total             324663297                       # Total bandwidth to/from this memory (bytes/s)
+system.nvram.bytes_read::cpu.data                 284                       # Number of bytes read from this memory
+system.nvram.bytes_read::total                    284                       # Number of bytes read from this memory
+system.nvram.bytes_written::cpu.data               92                       # Number of bytes written to this memory
+system.nvram.bytes_written::total                  92                       # Number of bytes written to this memory
+system.nvram.num_reads::cpu.data                  284                       # Number of read requests responded to by this memory
+system.nvram.num_reads::total                     284                       # Number of read requests responded to by this memory
+system.nvram.num_writes::cpu.data                  92                       # Number of write requests responded to by this memory
+system.nvram.num_writes::total                     92                       # Number of write requests responded to by this memory
+system.nvram.bw_read::cpu.data                    127                       # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_read::total                       127                       # Total read bandwidth from this memory (bytes/s)
+system.nvram.bw_write::cpu.data                    41                       # Write bandwidth from this memory (bytes/s)
+system.nvram.bw_write::total                       41                       # Write bandwidth from this memory (bytes/s)
+system.nvram.bw_total::cpu.data                   168                       # Total bandwidth to/from this memory (bytes/s)
+system.nvram.bw_total::total                      168                       # Total bandwidth to/from this memory (bytes/s)
 system.partition_desc.bytes_read::cpu.data         4846                       # Number of bytes read from this memory
 system.partition_desc.bytes_read::total          4846                       # Number of bytes read from this memory
 system.partition_desc.num_reads::cpu.data          608                       # Number of read requests responded to by this memory
@@ -89,22 +105,6 @@ system.partition_desc.bw_read::cpu.data          2169                       # To
 system.partition_desc.bw_read::total             2169                       # Total read bandwidth from this memory (bytes/s)
 system.partition_desc.bw_total::cpu.data         2169                       # Total bandwidth to/from this memory (bytes/s)
 system.partition_desc.bw_total::total            2169                       # Total bandwidth to/from this memory (bytes/s)
-system.rom.bytes_read::cpu.inst                432296                       # Number of bytes read from this memory
-system.rom.bytes_read::cpu.data                696392                       # Number of bytes read from this memory
-system.rom.bytes_read::total                  1128688                       # Number of bytes read from this memory
-system.rom.bytes_inst_read::cpu.inst           432296                       # Number of instructions bytes read from this memory
-system.rom.bytes_inst_read::total              432296                       # Number of instructions bytes read from this memory
-system.rom.num_reads::cpu.inst                 108074                       # Number of read requests responded to by this memory
-system.rom.num_reads::cpu.data                  87049                       # Number of read requests responded to by this memory
-system.rom.num_reads::total                    195123                       # Number of read requests responded to by this memory
-system.rom.bw_read::cpu.inst                   193527                       # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::cpu.data                   311755                       # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_read::total                      505282                       # Total read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::cpu.inst              193527                       # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_inst_read::total                 193527                       # Instruction read bandwidth from this memory (bytes/s)
-system.rom.bw_total::cpu.inst                  193527                       # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::cpu.data                  311755                       # Total bandwidth to/from this memory (bytes/s)
-system.rom.bw_total::total                     505282                       # Total bandwidth to/from this memory (bytes/s)
 system.membus.throughput                   5163367605                       # Throughput (bytes/s)
 system.membus.data_through_bus            11533814443                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
index c6185ffda..108881308 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +445,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -445,12 +459,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -500,16 +523,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -528,9 +559,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -539,10 +570,14 @@ simpoint=55300000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:268435455
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -576,6 +616,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
index 276747f08..9be633e93 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing/sim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 01:31:22
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:20:51
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -25,4 +25,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 26780899500 because target called exit()
+Exiting @ tick 26877484000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
index 4ab5b0af3..e8dafcae9 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -120,9 +129,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -131,11 +140,16 @@ simpoint=55300000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
index 6c1085aa7..a5dbe98d0 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:04:57
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:18:17
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
index 75d632a3d..08fdda12e 100644
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +81,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,12 +125,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -165,17 +189,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -192,9 +225,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/mcf
+executable=/dist/m5/cpu2000/binaries/arm/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -203,11 +236,16 @@ simpoint=55300000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
index ceb59a6aa..c84bc1d04 100755
--- a/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/arm/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:06:05
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:24:43
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/10.mcf/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
index d22bba3b1..de11b33de 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,9 +97,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -99,11 +108,16 @@ simpoint=55300000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
index ba77eb012..db2db18f1 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-at
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:10:07
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:07:55
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
index 2ea824e22..882273887 100644
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -119,10 +143,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,9 +193,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/mcf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -171,11 +204,16 @@ simpoint=55300000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
index c9bc4a594..1e103dc44 100755
--- a/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/sparc/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-ti
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:04:08
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:07:47
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/10.mcf/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
index 4e8c5ef6c..5b842e86b 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,9 +30,14 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -113,6 +120,11 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.branchPred]
 type=BranchPredictor
 BTBEntries=4096
@@ -121,11 +133,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +143,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +157,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -161,7 +180,8 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -430,10 +450,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -444,15 +464,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -472,16 +501,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -492,16 +522,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -520,9 +558,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -531,10 +569,14 @@ simpoint=55300000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -545,19 +587,24 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:268435455
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -568,6 +615,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
index 989d45db0..14639c3c6 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing/sim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:13:59
-gem5 started Mar 27 2013 00:35:52
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:21:35
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -18,6 +18,7 @@ All Rights Reserved.
 nodes                      : 500
 active arcs                : 1905
 simplex iterations         : 1502
+info: Increasing stack size by one page.
 flow value                 : 4990014995
 new implicit arcs          : 23867
 active arcs                : 25772
@@ -25,4 +26,4 @@ simplex iterations         : 2663
 flow value                 : 3080014995
 checksum                   : 68389
 optimal
-Exiting @ tick 66015916000 because target called exit()
+Exiting @ tick 65501881000 because target called exit()
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
index 4a41d87f1..433f51b0f 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
+children=apic_clk_domain dtb interrupts isa itb tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -63,6 +72,11 @@ workload=system.cpu.workload
 dcache_port=system.membus.slave[2]
 icache_port=system.membus.slave[1]
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -71,13 +85,14 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -97,7 +112,8 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
@@ -112,9 +128,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -123,10 +139,14 @@ simpoint=55300000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -137,13 +157,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
index b233b4d5d..670a5ba2d 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:52:30
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
index 5da614d68..ffd9b2f5e 100644
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
+children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -59,12 +65,17 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +86,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -89,16 +109,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -109,15 +130,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -137,16 +167,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -157,16 +188,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -185,9 +224,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/mcf
+executable=/dist/m5/cpu2000/binaries/x86/linux/mcf
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
+input=/dist/m5/cpu2000/data/mcf/smred/input/mcf.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -196,10 +235,14 @@ simpoint=55300000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -210,13 +253,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:268435455
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
index 5ba351c70..2c70ca6cf 100755
--- a/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/10.mcf/ref/x86/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:32:00
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/10.mcf/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
index 2763bfff6..7756821bd 100644
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +445,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -445,12 +459,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -500,16 +523,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -528,9 +559,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -539,10 +570,14 @@ simpoint=114600000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -576,6 +616,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
index 374965c0a..b4d96e4ea 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simerr
@@ -1,4 +1,3 @@
 warn: Sockets disabled, not accepting gdb connections
 warn: CP14 unimplemented crn[8], opc1[2], crm[9], opc2[4]
-warn: CP14 unimplemented crn[15], opc1[7], crm[5], opc2[7]
 hack: be nice to actually delete the event here
diff --git a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
index 601f6c5a6..27bb412f8 100755
--- a/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 01:41:39
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 07:58:36
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -69,4 +69,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 199986318000 because target called exit()
+Exiting @ tick 202349747500 because target called exit()
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
index 50301a571..7b35bd3ad 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -120,9 +129,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -131,11 +140,16 @@ simpoint=114600000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
index 0dc087363..b9241b523 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-ato
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:09:03
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:00:02
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
index a0662150c..d125ef04b 100644
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +81,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,12 +125,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -165,17 +189,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -192,9 +225,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/parser
+executable=/dist/m5/cpu2000/binaries/arm/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -203,11 +236,16 @@ simpoint=114600000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
index 1864fc9ed..0a37362e8 100755
--- a/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/arm/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:10:40
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:48:54
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/20.parser/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
index 448cff052..6ab0a9e51 100644
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,9 +30,14 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -113,6 +120,11 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.branchPred]
 type=BranchPredictor
 BTBEntries=4096
@@ -121,11 +133,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +143,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +157,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -161,7 +180,8 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -430,10 +450,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -444,15 +464,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -472,16 +501,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -492,16 +522,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -520,9 +558,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -531,10 +569,14 @@ simpoint=114600000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -545,19 +587,24 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -568,6 +615,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
index 665c3f4ff..983df26b6 100755
--- a/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/o3-timing/simout
@@ -3,15 +3,14 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 18 2013 13:37:41
-gem5 started Apr 18 2013 14:16:02
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 07:10:19
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 
  Reading the dictionary files: *********info: Increasing stack size by one page.
-info: Increasing stack size by one page.
 ****************************************
  58924 words stored in 3784810 bytes
 
@@ -25,6 +24,7 @@ Processing sentences in batch mode
 Echoing of input sentence turned on.
 * as had expected the party to be a success , it was a success 
 info: Increasing stack size by one page.
+info: Increasing stack size by one page.
 * do you know where John 's 
 * he said that , finding that it was impossible to get work as a waiter , he would work as a janitor 
 info: Increasing stack size by one page.
@@ -81,4 +81,4 @@ info: Increasing stack size by one page.
   about 2 million people attended 
   the five best costumes got prizes 
 No errors!
-Exiting @ tick 434543595000 because target called exit()
+Exiting @ tick 458201684000 because target called exit()
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
index 3ae684a0d..397d5a34d 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
+children=apic_clk_domain dtb interrupts isa itb tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -63,6 +72,11 @@ workload=system.cpu.workload
 dcache_port=system.membus.slave[2]
 icache_port=system.membus.slave[1]
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -71,13 +85,14 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -97,7 +112,8 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
@@ -112,9 +128,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -123,10 +139,14 @@ simpoint=114600000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -137,13 +157,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
index 1169e7228..7a734044e 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-ato
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:21:35
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
index e9b7f5ea7..3a3bc324c 100644
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
+children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -59,12 +65,17 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +86,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -89,16 +109,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -109,15 +130,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -137,16 +167,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -157,16 +188,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -185,9 +224,9 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/parser
+executable=/dist/m5/cpu2000/binaries/x86/linux/parser
 gid=100
-input=/scratch/nilay/GEM5/dist/m5/cpu2000/data/parser/mdred/input/parser.in
+input=/dist/m5/cpu2000/data/parser/mdred/input/parser.in
 max_stack_size=67108864
 output=cout
 pid=100
@@ -196,10 +235,14 @@ simpoint=114600000000
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -210,13 +253,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
index d05acb658..5ef733649 100755
--- a/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/20.parser/ref/x86/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/20.parser/x86/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:48:16
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/20.parser/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
index 9ca2ce67b..a92131062 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +42,7 @@ activity=0
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +72,7 @@ multRepeatRate=1
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +91,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +101,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +115,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -154,10 +177,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,17 +191,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -195,7 +227,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -206,11 +238,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -218,27 +255,38 @@ slave=system.system_port system.cpu.l2cache.mem_side
 
 [system.physmem]
 type=SimpleDRAM
-addr_mapping=openmap
+activation_limit=4
+addr_mapping=RaBaChCo
 banks_per_rank=8
-clock=1000
-conf_table_reported=false
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRCD=13750
 tREFI=7800000
 tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
index 21846ca98..3f1389dac 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:33:34
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 09:53:14
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -13,4 +11,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.133333
-Exiting @ tick 139846906500 because target called exit()
+Exiting @ tick 139916242500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
index 1fb09b246..dfa123161 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -454,10 +477,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +491,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -496,7 +527,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -507,10 +538,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +584,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
index f0252d6b4..dc6d59bdf 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 22:56:39
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 09:53:14
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -13,4 +11,4 @@ info: Increasing stack size by one page.
 Eon, Version 1.1
 info: Increasing stack size by one page.
 OO-style eon Time= 0.066667
-Exiting @ tick 77333664500 because target called exit()
+Exiting @ tick 77521581000 because target called exit()
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
index e04d3a419..9894abc48 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
index 1bc520ee3..b09a5533b 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:04:20
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 09:53:14
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
index a2dc77128..17feee0a3 100644
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -119,10 +143,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
index b077bccfc..b94ac7377 100755
--- a/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/alpha/tru64/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:49:24
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 09:53:14
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
index aa8b8d316..c6c5b71d8 100644
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +445,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -445,12 +459,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -500,16 +523,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -528,7 +559,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -539,10 +570,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -576,6 +616,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
index fab84fa34..d9d67c53c 100755
--- a/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing/sim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 03:18:38
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:27:24
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -15,4 +15,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 OO-style eon Time= 0.060000
-Exiting @ tick 68258363000 because target called exit()
+Exiting @ tick 68375005500 because target called exit()
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
index df103243c..1c8f49cef 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -120,7 +129,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -131,11 +140,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
index 144aa8e04..9c8ccea96 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:20:38
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:21:07
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
index 93ad8536f..f3f7cd9b4 100644
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +81,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,12 +125,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -165,17 +189,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -192,7 +225,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/eon
+executable=/dist/m5/cpu2000/binaries/arm/linux/eon
 gid=100
 input=cin
 max_stack_size=67108864
@@ -203,11 +236,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
index 9d9130208..b54aa45d0 100755
--- a/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/30.eon/ref/arm/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:24:50
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:19:15
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/30.eon/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
index 11091dc51..cb1d4f78d 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -454,10 +477,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +491,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -496,7 +527,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -507,10 +538,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +584,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
index 40a764ff6..6fa75b847 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 22:56:38
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 09:53:14
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1387,4 +1385,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 626014950000 because target called exit()
+Exiting @ tick 631883288500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
index 98e511e60..d4071b647 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
index 76e77727d..0011f9cf8 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:44:11
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 09:53:14
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
index be88a9856..d6223b426 100644
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -119,10 +143,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
index c7b42c8e2..a19734d3d 100755
--- a/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/alpha/tru64/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:29:25
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 09:53:14
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/40.perlbmk/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
index 046e463df..f5cd82b95 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +445,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -445,12 +459,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -500,16 +523,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -528,7 +559,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -539,10 +570,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -576,6 +616,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
index 7e27488e7..6bce28421 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 02:55:03
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:57:23
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -1387,4 +1387,4 @@ info: Increasing stack size by one page.
 2000: 760651391
 1000: 4031656975
 0: 2206428413
-Exiting @ tick 627426486000 because target called exit()
+Exiting @ tick 640648369500 because target called exit()
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
index 821ff54be..583a974bb 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -120,7 +129,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -131,11 +140,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
index 542af2be2..2dca8a365 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-at
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:32:44
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:31:40
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
index 28c3943fd..e7d15bd7c 100644
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +81,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,12 +125,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -165,17 +189,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -192,7 +225,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/perlbmk
+executable=/dist/m5/cpu2000/binaries/arm/linux/perlbmk
 gid=100
 input=cin
 max_stack_size=67108864
@@ -203,11 +236,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
index 32f62cb45..15b548e96 100755
--- a/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-ti
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 20:51:04
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:11:37
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/40.perlbmk/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
index b0d1b1795..dd99e1fcc 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +42,7 @@ activity=0
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +72,7 @@ multRepeatRate=1
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +91,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +101,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +115,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -154,10 +177,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,16 +191,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -196,7 +227,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,10 +238,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -221,19 +256,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -244,6 +284,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
index 2573c0d57..f56fe9b31 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 22:56:38
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 09:55:43
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 42725646500 because target called exit()
+Exiting @ tick 43769191000 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
index d2c7ef690..7b8dd0790 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -454,10 +477,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +491,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -496,7 +527,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -507,10 +538,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +584,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
index dfc94d274..0840178d9 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/o3-timing/simout
@@ -1,13 +1,11 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 22:56:39
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 09:57:43
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 23931821000 because target called exit()
+Exiting @ tick 24977022500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
index 565b787c0..c0c8f0dec 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
index dcabfa4e7..6c7ff5465 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:34:02
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:03:40
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
index 3b759a9fa..b1fb247dd 100644
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -119,10 +143,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
index e6bb386fa..f89175182 100755
--- a/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/alpha/tru64/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:15:43
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:04:18
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
index 9ae4cf5ba..19517f85f 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +445,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -445,12 +459,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -500,16 +523,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -528,7 +559,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -539,10 +570,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -576,6 +616,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
index 862f6a349..b38f95469 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/o3-timing/simout
@@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 02:50:34
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:04:25
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
-Exiting @ tick 25534556000 because target called exit()
+Exiting @ tick 26765004500 because target called exit()
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
index d64046cb9..6172e5c1a 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -120,7 +129,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -131,11 +140,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
index c3ccf1541..cdf0f47ec 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-ato
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:10:40
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:45:30
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
index 358ede026..5e9534bc1 100644
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +81,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,12 +125,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -165,17 +189,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -192,7 +225,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/vortex
+executable=/dist/m5/cpu2000/binaries/arm/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -203,11 +236,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
index b9e94a32f..67309511e 100755
--- a/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/arm/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:11:48
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:31:35
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/50.vortex/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
index 1bc84354f..0f57053cc 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
index 806d3e418..c44643a8d 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:08:27
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:07:56
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
index 6398f17b7..e7e0ce2f8 100644
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -119,10 +143,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/vortex
+executable=/dist/m5/cpu2000/binaries/sparc/linux/vortex
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
index 1ed94a2b4..7747f2ffd 100755
--- a/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/50.vortex/ref/sparc/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:01:47
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:10:51
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/50.vortex/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
index 4253e4098..49239c031 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +42,7 @@ activity=0
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +72,7 @@ multRepeatRate=1
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +91,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +101,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +115,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -154,10 +177,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,16 +191,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -196,7 +227,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,10 +238,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -221,19 +256,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -244,6 +284,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
index 59f36663a..037bfdea9 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 22:56:38
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:05:17
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -25,4 +23,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 993429839500 because target called exit()
+Exiting @ tick 1017016979500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
index 0b5fae7fe..5c873ae8a 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -454,10 +477,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +491,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -496,7 +527,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -507,10 +538,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +584,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
index 2ef92f817..a9e5ff044 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/o3-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 22:58:12
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:05:25
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -25,4 +23,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 665534636500 because target called exit()
+Exiting @ tick 694171131000 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
index fd8132952..86a7050c2 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
index 0658af7d4..33b8f7ad8 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-atomic/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:47:45
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:09:10
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
index ea6dff7f2..482b126d1 100644
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -119,10 +143,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
index 167c61e46..154161af5 100755
--- a/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/alpha/tru64/simple-timing/simout
@@ -1,11 +1,9 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:15:18
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:14:34
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
index a8a560c2e..67c7195c6 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +445,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -445,12 +459,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -500,16 +523,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -528,7 +559,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -539,10 +570,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -576,6 +616,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
index 0e28a571f..4c68e7cbb 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing/s
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 01:49:26
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:11:07
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -26,4 +26,4 @@ Uncompressing Data
 Uncompressed data 1048576 bytes in length
 Uncompressed data compared correctly
 Tested 1MB buffer: OK!
-Exiting @ tick 517355353500 because target called exit()
+Exiting @ tick 541686426500 because target called exit()
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
index c0c32553c..4c52e043e 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -120,7 +129,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -131,11 +140,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
index ad5616590..836ec0832 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atom
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:13:46
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:33:02
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
index 15930e421..0b3714a01 100644
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +81,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,12 +125,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -165,17 +189,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -192,7 +225,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/arm/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -203,11 +236,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
index f67b33f3c..8e102e919 100755
--- a/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:25:52
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:46:27
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/60.bzip2/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
index 64ac15724..593d636da 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
+children=apic_clk_domain dtb interrupts isa itb tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -63,6 +72,11 @@ workload=system.cpu.workload
 dcache_port=system.membus.slave[2]
 icache_port=system.membus.slave[1]
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -71,13 +85,14 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -97,7 +112,8 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
@@ -112,7 +128,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,10 +139,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -137,13 +157,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
index 654ed6b82..09e2cbd6f 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atom
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 07:00:18
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
index dfbf80a27..8de21ec08 100644
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
+children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -59,12 +65,17 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +86,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -89,16 +109,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -109,15 +130,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -137,16 +167,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -157,16 +188,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -185,7 +224,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/bzip2
+executable=/dist/m5/cpu2000/binaries/x86/linux/bzip2
 gid=100
 input=cin
 max_stack_size=67108864
@@ -196,10 +235,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -210,13 +253,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
index 88a0bc2fc..842f4ca6e 100755
--- a/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/60.bzip2/ref/x86/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:22:01
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/60.bzip2/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
index 9b4ab11e5..c08f958c6 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +42,7 @@ activity=0
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +72,7 @@ multRepeatRate=1
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +91,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +101,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +115,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -154,10 +177,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,16 +191,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -196,7 +227,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,10 +238,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -221,19 +256,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -244,6 +284,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
index eac5f6715..27c876af5 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
@@ -1,14 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 23:05:23
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:18:38
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -25,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 41622221000 because target called exit()
+122 123 124 Exiting @ tick 41671895000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
index e01df0c34..8c9cfc594 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -454,10 +477,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +491,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -496,7 +527,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -507,10 +538,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +584,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
index 00c3eaf77..f8802d4f7 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/o3-timing/simout
@@ -1,14 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 23:10:12
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:24:35
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sav
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/o3-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
@@ -25,4 +21,4 @@ Authors: Carl Sechen, Bill Swartz
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 23379948000 because target called exit()
+122 123 124 Exiting @ tick 23492267500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
index 27f048879..04249e1da 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
index b0e6a9854..508377532 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-atomic/simout
@@ -1,14 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:46:14
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:32:22
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sav
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-atomic/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
index 8de838008..2ef8f2342 100644
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -119,10 +143,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
+executable=/dist/m5/cpu2000/binaries/alpha/tru64/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
index e6fe2a9db..b809995e1 100755
--- a/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/alpha/tru64/simple-timing/simout
@@ -1,14 +1,10 @@
-Redirecting stdout to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/simout
-Redirecting stderr to build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:17:33
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 10:32:58
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sav
-Couldn't unlink  build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/simple-timing/smred.sv2
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
index f27c400f3..271729e48 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +445,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -445,12 +459,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -500,16 +523,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -528,7 +559,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -539,10 +570,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -576,6 +616,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
index 7ea8b22e4..000af632b 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/s
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 03:01:21
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:14:29
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sav
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/o3-timing/smred.sv2
@@ -25,4 +25,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 74157495500 because target called exit()
+122 123 124 Exiting @ tick 74201024500 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
index 19646e5c5..46e3b79d7 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -120,7 +129,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -131,11 +140,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
index 0d1d50648..debc9398c 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atom
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:36:32
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:16:29
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sav
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
index 4b7535a34..beab37699 100644
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +81,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,12 +125,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -165,17 +189,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -192,7 +225,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/arm/linux/twolf
+executable=/dist/m5/cpu2000/binaries/arm/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -203,11 +236,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
index a57db40a7..559353937 100755
--- a/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/arm/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 21:38:40
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:33:12
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sav
 Couldn't unlink  build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
index 561079b2c..450711784 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
index 3551a28b3..1f1c88e44 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 15:49:57
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:10:38
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sav
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
index 5a2c83658..bac902cb5 100644
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -119,10 +143,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/sparc/linux/twolf
+executable=/dist/m5/cpu2000/binaries/sparc/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
index e4c331210..139366506 100755
--- a/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/sparc/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:12:46
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:08:55
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sav
 Couldn't unlink  build/SPARC/tests/opt/long/se/70.twolf/sparc/linux/simple-timing/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
index 32480c302..078b2c3e8 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,9 +30,14 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -113,6 +120,11 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.branchPred]
 type=BranchPredictor
 BTBEntries=4096
@@ -121,11 +133,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +143,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +157,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -161,7 +180,8 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -430,10 +450,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -444,15 +464,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -472,16 +501,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -492,16 +522,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -520,7 +558,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -531,10 +569,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -545,19 +587,24 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -568,6 +615,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
index 7157fcc8e..23eb40269 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/s
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:13:59
-gem5 started Mar 26 2013 23:44:56
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:27:45
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sav
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/o3-timing/smred.sv2
@@ -26,4 +26,4 @@ info: Increasing stack size by one page.
  76  77  78  79  80  81  82  83  84  85  86  87  88  89  90 
  91  92  93  94  95  96  97  98  99 100 101 102 103 104 105 
 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 
-122 123 124 Exiting @ tick 82784332500 because target called exit()
+122 123 124 Exiting @ tick 144470654000 because target called exit()
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
index ce16e921c..a8660b22e 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
+children=apic_clk_domain dtb interrupts isa itb tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -63,6 +72,11 @@ workload=system.cpu.workload
 dcache_port=system.membus.slave[2]
 icache_port=system.membus.slave[1]
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -71,13 +85,14 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -97,7 +112,8 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
@@ -112,7 +128,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,10 +139,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -137,13 +157,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
index 0a35f8c74..9ce3bb0d1 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atom
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:35
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:58:25
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sav
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-atomic/smred.sv2
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
index 93ab42722..00a43a175 100644
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
+children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -59,12 +65,17 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +86,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -89,16 +109,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -109,15 +130,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -137,16 +167,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -157,16 +188,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -185,7 +224,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/x86/linux/twolf
+executable=/dist/m5/cpu2000/binaries/x86/linux/twolf
 gid=100
 input=cin
 max_stack_size=67108864
@@ -196,10 +235,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -210,13 +253,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
index 4e4920ac0..4f73957c8 100755
--- a/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
+++ b/tests/long/se/70.twolf/ref/x86/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timi
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:30:24
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:21:36
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sav
 Couldn't unlink  build/X86/tests/opt/long/se/70.twolf/x86/linux/simple-timing/smred.sv2
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
index 573c7933c..f697c291f 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini
@@ -8,19 +8,20 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-clock=1000
-console=/scratch/nilay/GEM5/system/binaries/console
+cache_line_size=64
+clk_domain=system.clk_domain
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=8796093022208:18446744073709551615
 req_size=16
@@ -44,12 +45,16 @@ resp_size=16
 master=system.iobus.slave[0]
 slave=system.membus.master[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -68,6 +73,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -80,10 +89,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -94,22 +103,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -120,12 +138,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=AlphaInterrupts
 
@@ -142,9 +169,8 @@ type=ExeTracer
 [system.cpu1]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=1
 do_checkpoint_insts=true
 do_quiesce=true
@@ -163,6 +189,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -175,10 +205,10 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -189,22 +219,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -215,12 +254,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=AlphaInterrupts
 
@@ -234,6 +282,11 @@ size=48
 [system.cpu1.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.disk0]
 type=IdeDisk
 children=image
@@ -251,7 +304,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -271,7 +324,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -280,8 +333,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -291,10 +343,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -305,18 +357,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -327,18 +388,27 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
@@ -347,7 +417,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -364,28 +434,35 @@ pio=system.membus.default
 
 [system.physmem]
 type=SimpleDRAM
-addr_mapping=openmap
+activation_limit=4
+addr_mapping=RaBaChCo
 banks_per_rank=8
-clock=1000
-conf_table_reported=false
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRCD=13750
 tREFI=7800000
 tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[1]
 
 [system.simple_disk]
@@ -396,7 +473,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -408,9 +485,9 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.l2c.cpu_side
@@ -424,7 +501,7 @@ system=system
 
 [system.tsunami.backdoor]
 type=AlphaBackdoor
-clock=1000
+clk_domain=system.clk_domain
 cpu=system.cpu0
 disk=system.simple_disk
 pio_addr=8804682956800
@@ -436,7 +513,7 @@ pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8803072344064
 pio_latency=100000
 system=system
@@ -483,7 +560,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=2000
+clk_domain=system.clk_domain
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -514,7 +591,7 @@ pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -531,7 +608,7 @@ pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -548,7 +625,7 @@ pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -565,7 +642,7 @@ pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -582,7 +659,7 @@ pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -599,7 +676,7 @@ pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -616,7 +693,7 @@ pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -633,7 +710,7 @@ pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -650,7 +727,7 @@ pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -667,7 +744,7 @@ pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -684,7 +761,7 @@ pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -701,7 +778,7 @@ pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -718,7 +795,7 @@ pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -735,7 +812,7 @@ pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -752,7 +829,7 @@ pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -769,7 +846,7 @@ pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -786,7 +863,7 @@ pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -803,7 +880,7 @@ pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -820,7 +897,7 @@ pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -837,7 +914,7 @@ pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
-clock=1000
+clk_domain=system.clk_domain
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=100000
@@ -884,7 +961,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
@@ -901,7 +978,7 @@ pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
-clock=1000
+clk_domain=system.clk_domain
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -913,7 +990,7 @@ pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8802535473152
 pio_latency=100000
 system=system
@@ -923,7 +1000,8 @@ pio=system.iobus.master[1]
 [system.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.tsunami
 size=16777216
@@ -932,7 +1010,7 @@ pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8804615848952
 pio_latency=100000
 platform=system.tsunami
@@ -940,3 +1018,7 @@ system=system
 terminal=system.terminal
 pio=system.iobus.master[23]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
index a62617d01..410351310 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:01:11
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:50
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
 info: Launching CPU 1 @ 97861500
-Exiting @ tick 1870325497500 because m5_exit instruction encountered
+Exiting @ tick 1870335643500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
index 101a67dc8..1e009881b 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.870336                       # Nu
 sim_ticks                                1870335643500                       # Number of ticks simulated
 final_tick                               1870335643500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1417566                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1417565                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            41981821830                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 308248                       # Number of bytes of host memory used
-host_seconds                                    44.55                       # Real time elapsed on the host
+host_inst_rate                                2937220                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2937218                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            86986978503                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 308008                       # Number of bytes of host memory used
+host_seconds                                    21.50                       # Real time elapsed on the host
 sim_insts                                    63154034                       # Number of instructions simulated
 sim_ops                                      63154034                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu0.inst           761216                       # Number of bytes read from this memory
@@ -198,23 +198,23 @@ system.physmem.avgGap                             nan                       # Av
 system.membus.throughput                     42160246                       # Throughput (bytes/s)
 system.membus.data_through_bus               78853810                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.l2c.tags.replacements                       1000626                       # number of replacements
-system.l2c.tags.tagsinuse                     65381.922487                       # Cycle average of tags in use
-system.l2c.tags.total_refs                         2464723                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                       1065768                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          2.312626                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                     838081000                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks        56158.706931                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst          4894.235246                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data          4134.598984                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst           174.423126                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data            19.958201                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.856914                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.074680                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.063089                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.002661                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.000305                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.997649                       # Average percentage of cache occupancy
+system.l2c.tags.replacements                  1000626                       # number of replacements
+system.l2c.tags.tagsinuse                65381.922487                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    2464723                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                  1065768                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.312626                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                838081000                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   56158.706931                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4894.235246                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     4134.598984                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      174.423126                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data       19.958201                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.856914                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.074680                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.063089                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.002661                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.000305                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.997649                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::cpu0.inst             873088                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.data             763068                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu1.inst             101908                       # number of ReadReq hits
@@ -326,15 +326,15 @@ system.l2c.cache_copies                             0                       # nu
 system.l2c.writebacks::writebacks               81316                       # number of writebacks
 system.l2c.writebacks::total                    81316                       # number of writebacks
 system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                     41695                       # number of replacements
-system.iocache.tags.tagsinuse                     0.435438                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                     41711                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle              1685787165017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide       0.435438                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide      0.027215                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total            0.027215                       # Average percentage of cache occupancy
+system.iocache.tags.replacements                41695                       # number of replacements
+system.iocache.tags.tagsinuse                0.435438                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41711                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1685787165017                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     0.435438                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.027215                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.027215                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          175                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              175                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -562,15 +562,15 @@ system.toL2Bus.data_through_bus             246743154                       # To
 system.toL2Bus.snoop_data_through_bus           10368                       # Total snoop data (bytes)
 system.iobus.throughput                       1460500                       # Throughput (bytes/s)
 system.iobus.data_through_bus                 2731626                       # Total data (bytes)
-system.cpu0.icache.tags.replacements                884406                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               511.244754                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                56345130                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                884918                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                 63.672713                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle            9786576500                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.replacements           884406                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.244754                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           56345130                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           884918                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            63.672713                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle       9786576500                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.244754                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998525                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.998525                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998525                       # Average percentage of cache occupancy
 system.cpu0.icache.ReadReq_hits::cpu0.inst     56345130                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       56345130                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst     56345130                       # number of demand (read+write) hits
@@ -604,15 +604,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements               1978683                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               507.129817                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                13123756                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs               1979195                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                  6.630855                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle              10840000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.replacements          1978683                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          507.129817                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           13123756                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs          1979195                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs             6.630855                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         10840000                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   507.129817                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.990488                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.990488                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.990488                       # Average percentage of cache occupancy
 system.cpu0.dcache.ReadReq_hits::cpu0.data      7298341                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        7298341                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data      5462261                       # number of WriteReq hits
@@ -799,15 +799,15 @@ system.cpu1.kern.mode_ticks::kernel        1373906500      0.07%      0.07% # nu
 system.cpu1.kern.mode_ticks::user           508289000      0.03%      0.10% # number of ticks spent at the given mode
 system.cpu1.kern.mode_ticks::idle        1868002681000     99.90%    100.00% # number of ticks spent at the given mode
 system.cpu1.kern.swap_context                     471                       # number of times the context was actually changed
-system.cpu1.icache.tags.replacements                103103                       # number of replacements
-system.cpu1.icache.tags.tagsinuse               427.126317                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                 5832124                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                103615                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                 56.286484                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle          1868933191000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.replacements           103103                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          427.126317                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs            5832124                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           103615                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            56.286484                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle     1868933191000                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.tags.occ_blocks::cpu1.inst   427.126317                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.834231                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.834231                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.834231                       # Average percentage of cache occupancy
 system.cpu1.icache.ReadReq_hits::cpu1.inst      5832124                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total        5832124                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst      5832124                       # number of demand (read+write) hits
@@ -841,15 +841,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets          nan
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                 62052                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse               421.569557                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                 1836045                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                 62390                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                 29.428514                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle          1851115695500                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.replacements            62052                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          421.569557                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs            1836045                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs            62390                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            29.428514                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle     1851115695500                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.tags.occ_blocks::cpu1.data   421.569557                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.823378                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.823378                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.823378                       # Average percentage of cache occupancy
 system.cpu1.dcache.ReadReq_hits::cpu1.data      1109514                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        1109514                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data       707455                       # number of WriteReq hits
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
index 50088b4ab..ac72e998f 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini
@@ -8,19 +8,20 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
+children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-clock=1000
-console=/scratch/nilay/GEM5/system/binaries/console
+cache_line_size=64
+clk_domain=system.clk_domain
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=8796093022208:18446744073709551615
 req_size=16
@@ -44,12 +45,16 @@ resp_size=16
 master=system.iobus.slave[0]
 slave=system.membus.master[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -68,6 +73,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -80,10 +89,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -94,22 +103,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -120,12 +138,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -138,10 +165,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -152,17 +179,26 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -171,6 +207,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.disk0]
 type=IdeDisk
 children=image
@@ -188,7 +229,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -208,7 +249,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -217,8 +258,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -228,10 +268,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -242,18 +282,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
@@ -262,7 +311,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -279,28 +328,35 @@ pio=system.membus.default
 
 [system.physmem]
 type=SimpleDRAM
-addr_mapping=openmap
+activation_limit=4
+addr_mapping=RaBaChCo
 banks_per_rank=8
-clock=1000
-conf_table_reported=false
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRCD=13750
 tREFI=7800000
 tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[1]
 
 [system.simple_disk]
@@ -311,7 +367,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -329,7 +385,7 @@ system=system
 
 [system.tsunami.backdoor]
 type=AlphaBackdoor
-clock=1000
+clk_domain=system.clk_domain
 cpu=system.cpu
 disk=system.simple_disk
 pio_addr=8804682956800
@@ -341,7 +397,7 @@ pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8803072344064
 pio_latency=100000
 system=system
@@ -388,7 +444,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=2000
+clk_domain=system.clk_domain
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -419,7 +475,7 @@ pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -436,7 +492,7 @@ pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -453,7 +509,7 @@ pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -470,7 +526,7 @@ pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -487,7 +543,7 @@ pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -504,7 +560,7 @@ pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -521,7 +577,7 @@ pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -538,7 +594,7 @@ pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -555,7 +611,7 @@ pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -572,7 +628,7 @@ pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -589,7 +645,7 @@ pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -606,7 +662,7 @@ pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -623,7 +679,7 @@ pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -640,7 +696,7 @@ pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -657,7 +713,7 @@ pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -674,7 +730,7 @@ pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -691,7 +747,7 @@ pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -708,7 +764,7 @@ pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -725,7 +781,7 @@ pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -742,7 +798,7 @@ pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
-clock=1000
+clk_domain=system.clk_domain
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=100000
@@ -789,7 +845,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
@@ -806,7 +862,7 @@ pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
-clock=1000
+clk_domain=system.clk_domain
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -818,7 +874,7 @@ pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8802535473152
 pio_latency=100000
 system=system
@@ -828,7 +884,8 @@ pio=system.iobus.master[1]
 [system.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.tsunami
 size=16777216
@@ -837,7 +894,7 @@ pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8804615848952
 pio_latency=100000
 platform=system.tsunami
@@ -845,3 +902,7 @@ system=system
 terminal=system.terminal
 pio=system.iobus.master[23]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
index c4aa2f920..b63c77b44 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:01:49
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:50
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1829330593000 because m5_exit instruction encountered
+Exiting @ tick 1829332269000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
index ee54d11d9..d5ea0605d 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  1.829332                       # Nu
 sim_ticks                                1829332269000                       # Number of ticks simulated
 final_tick                               1829332269000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1710493                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1710492                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            52117657653                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306192                       # Number of bytes of host memory used
-host_seconds                                    35.10                       # Real time elapsed on the host
+host_inst_rate                                2947908                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2947905                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            89820884398                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 305960                       # Number of bytes of host memory used
+host_seconds                                    20.37                       # Real time elapsed on the host
 sim_insts                                    60038305                       # Number of instructions simulated
 sim_ops                                      60038305                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu.inst            857984                       # Number of bytes read from this memory
@@ -188,15 +188,15 @@ system.physmem.avgGap                             nan                       # Av
 system.membus.throughput                     42552540                       # Throughput (bytes/s)
 system.membus.data_through_bus               77842734                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.iocache.tags.replacements                     41686                       # number of replacements
-system.iocache.tags.tagsinuse                     1.225570                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                     41702                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                             0                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle              1685780659017                       # Cycle when the warmup percentage was hit.
-system.iocache.tags.occ_blocks::tsunami.ide       1.225570                       # Average occupied blocks per requestor
-system.iocache.tags.occ_percent::tsunami.ide      0.076598                       # Average percentage of cache occupancy
-system.iocache.tags.occ_percent::total            0.076598                       # Average percentage of cache occupancy
+system.iocache.tags.replacements                41686                       # number of replacements
+system.iocache.tags.tagsinuse                1.225570                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                41702                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                        0                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle         1685780659017                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.occ_blocks::tsunami.ide     1.225570                       # Average occupied blocks per requestor
+system.iocache.tags.occ_percent::tsunami.ide     0.076598                       # Average percentage of cache occupancy
+system.iocache.tags.occ_percent::total       0.076598                       # Average percentage of cache occupancy
 system.iocache.ReadReq_misses::tsunami.ide          174                       # number of ReadReq misses
 system.iocache.ReadReq_misses::total              174                       # number of ReadReq misses
 system.iocache.WriteReq_misses::tsunami.ide        41552                       # number of WriteReq misses
@@ -416,15 +416,15 @@ system.tsunami.ethernet.postedInterrupts            0                       # nu
 system.tsunami.ethernet.droppedPackets              0                       # number of packets dropped
 system.iobus.throughput                       1480181                       # Throughput (bytes/s)
 system.iobus.data_through_bus                 2707742                       # Total data (bytes)
-system.cpu.icache.tags.replacements                 919609                       # number of replacements
-system.cpu.icache.tags.tagsinuse                511.215244                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 59129907                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                 920121                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  64.263186                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle             9686972500                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     511.215244                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.998467                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.998467                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            919609                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.215244                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            59129907                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            920121                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             64.263186                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        9686972500                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.215244                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.998467                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.998467                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst     59129907                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        59129907                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      59129907                       # number of demand (read+write) hits
@@ -458,19 +458,19 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                992301                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse             65424.374219                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 2433263                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs               1057464                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                  2.301036                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle             614754000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements           992301                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        65424.374219                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            2433263                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs          1057464                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs             2.301036                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle        614754000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks 56309.127841                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   4867.327126                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   4247.919252                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  4867.327126                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  4247.919252                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.859209                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.074270                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.064818                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.998297                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.998297                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.inst       906812                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.data       811232                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::total        1718044                       # number of ReadReq hits
@@ -538,15 +538,15 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks::writebacks        74291                       # number of writebacks
 system.cpu.l2cache.writebacks::total            74291                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                2042706                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                511.997802                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 14038427                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                2043218                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                   6.870744                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle               10840000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     511.997802                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.999996                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements           2042706                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997802                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            14038427                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs           2043218                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs              6.870744                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          10840000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997802                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999996                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999996                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data      7807777                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total         7807777                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      5848211                       # number of WriteReq hits
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
index 007c56f0a..4764f4e77 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini
@@ -8,19 +8,20 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
+children=bridge clk_domain cpu0 cpu1 cpu_clk_domain disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami voltage_domain
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-clock=1000
-console=/scratch/nilay/GEM5/system/binaries/console
+cache_line_size=64
+clk_domain=system.clk_domain
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=8796093022208:18446744073709551615
 req_size=16
@@ -44,12 +45,16 @@ resp_size=16
 master=system.iobus.slave[0]
 slave=system.membus.master[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -67,6 +72,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu0.tracer
@@ -76,10 +82,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -90,22 +96,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -116,12 +131,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=AlphaInterrupts
 
@@ -138,9 +162,8 @@ type=ExeTracer
 [system.cpu1]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=1
 do_checkpoint_insts=true
 do_quiesce=true
@@ -158,6 +181,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu1.tracer
@@ -167,10 +191,10 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -181,22 +205,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -207,12 +240,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=AlphaInterrupts
 
@@ -226,6 +268,11 @@ size=48
 [system.cpu1.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.disk0]
 type=IdeDisk
 children=image
@@ -243,7 +290,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -263,7 +310,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -272,8 +319,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -283,10 +329,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -297,18 +343,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -319,17 +374,25 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -340,7 +403,7 @@ slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -358,19 +421,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -381,7 +449,6 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[1]
 
 [system.simple_disk]
@@ -392,7 +459,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -404,8 +471,7 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -421,7 +487,7 @@ system=system
 
 [system.tsunami.backdoor]
 type=AlphaBackdoor
-clock=1000
+clk_domain=system.clk_domain
 cpu=system.cpu0
 disk=system.simple_disk
 pio_addr=8804682956800
@@ -433,7 +499,7 @@ pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8803072344064
 pio_latency=100000
 system=system
@@ -480,7 +546,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=2000
+clk_domain=system.clk_domain
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -511,7 +577,7 @@ pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -528,7 +594,7 @@ pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -545,7 +611,7 @@ pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -562,7 +628,7 @@ pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -579,7 +645,7 @@ pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -596,7 +662,7 @@ pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -613,7 +679,7 @@ pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -630,7 +696,7 @@ pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -647,7 +713,7 @@ pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -664,7 +730,7 @@ pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -681,7 +747,7 @@ pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -698,7 +764,7 @@ pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -715,7 +781,7 @@ pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -732,7 +798,7 @@ pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -749,7 +815,7 @@ pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -766,7 +832,7 @@ pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -783,7 +849,7 @@ pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -800,7 +866,7 @@ pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -817,7 +883,7 @@ pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -834,7 +900,7 @@ pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
-clock=1000
+clk_domain=system.clk_domain
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=100000
@@ -881,7 +947,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
@@ -898,7 +964,7 @@ pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
-clock=1000
+clk_domain=system.clk_domain
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -910,7 +976,7 @@ pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8802535473152
 pio_latency=100000
 system=system
@@ -920,7 +986,8 @@ pio=system.iobus.master[1]
 [system.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.tsunami
 size=16777216
@@ -929,7 +996,7 @@ pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8804615848952
 pio_latency=100000
 platform=system.tsunami
@@ -937,3 +1004,7 @@ system=system
 terminal=system.terminal
 pio=system.iobus.master[23]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
index 117d6c541..a33dd389d 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
@@ -3,13 +3,13 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:13
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:51
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-info: Launching CPU 1 @ 614109000
-Exiting @ tick 1955749107000 because m5_exit instruction encountered
+info: Launching CPU 1 @ 675287000
+Exiting @ tick 1961841175000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
index aa80e0b5e..0d754b641 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/system.terminal
@@ -17,8 +17,8 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
unix_boot_mem ends at FFFFFC0000078000 
 
k_argc = 0 
 
jumping to kernel at 0xFFFFFC0000310000, (PCBB 0xFFFFFC0000018180 pfn 1067)
-
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
 
CallbackFixup 0 18000, t7=FFFFFC000070C000
+
Entering slaveloop for cpu 1 my_rpb=FFFFFC0000018400
 
Linux version 2.6.13 (hsul@zed.eecs.umich.edu) (gcc version 3.4.3) #1 SMP Sun Oct 8 19:52:07 EDT 2006
 
Booting GENERIC on Tsunami variation DP264 using machine vector DP264 from SRM
 
Major Options: SMP LEGACY_START VERBOSE_MCHECK 
@@ -27,7 +27,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 40 cycles, load miss latency 123 cycles
+
4096K Bcache detected; load hit latency 38 cycles, load miss latency 142 cycles
 
SMP: 2 CPUs probed -- cpu_present_mask = 3
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
index d8f41ddb0..54bf6e928 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini
@@ -8,19 +8,20 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami
+children=bridge clk_domain cpu cpu_clk_domain disk0 disk2 intrctrl iobus iocache membus physmem simple_disk terminal tsunami voltage_domain
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-clock=1000
-console=/scratch/nilay/GEM5/system/binaries/console
+cache_line_size=64
+clk_domain=system.clk_domain
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:134217727
 memories=system.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
+pal=/dist/m5/system/binaries/ts_osfpal
 readfile=tests/halt.sh
 symbolfile=
 system_rev=1024
@@ -36,7 +37,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=8796093022208:18446744073709551615
 req_size=16
@@ -44,12 +45,16 @@ resp_size=16
 master=system.iobus.slave[0]
 slave=system.membus.master[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -67,6 +72,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -76,10 +82,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -90,22 +96,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -116,12 +131,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -134,10 +158,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -148,17 +172,26 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -167,6 +200,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.disk0]
 type=IdeDisk
 children=image
@@ -184,7 +222,7 @@ table_size=65536
 
 [system.disk0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.disk2]
@@ -204,7 +242,7 @@ table_size=65536
 
 [system.disk2.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.intrctrl]
@@ -213,8 +251,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -224,10 +261,10 @@ slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -238,18 +275,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[29]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
@@ -258,7 +304,7 @@ slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -275,28 +321,35 @@ pio=system.membus.default
 
 [system.physmem]
 type=SimpleDRAM
-addr_mapping=openmap
+activation_limit=4
+addr_mapping=RaBaChCo
 banks_per_rank=8
-clock=1000
-conf_table_reported=false
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRCD=13750
 tREFI=7800000
 tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[1]
 
 [system.simple_disk]
@@ -307,7 +360,7 @@ system=system
 
 [system.simple_disk.disk]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [system.terminal]
@@ -325,7 +378,7 @@ system=system
 
 [system.tsunami.backdoor]
 type=AlphaBackdoor
-clock=1000
+clk_domain=system.clk_domain
 cpu=system.cpu
 disk=system.simple_disk
 pio_addr=8804682956800
@@ -337,7 +390,7 @@ pio=system.iobus.master[24]
 
 [system.tsunami.cchip]
 type=TsunamiCChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8803072344064
 pio_latency=100000
 system=system
@@ -384,7 +437,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=2000
+clk_domain=system.clk_domain
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -415,7 +468,7 @@ pio=system.iobus.master[27]
 
 [system.tsunami.fake_OROM]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -432,7 +485,7 @@ pio=system.iobus.master[8]
 
 [system.tsunami.fake_ata0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -449,7 +502,7 @@ pio=system.iobus.master[19]
 
 [system.tsunami.fake_ata1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -466,7 +519,7 @@ pio=system.iobus.master[20]
 
 [system.tsunami.fake_pnp_addr]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -483,7 +536,7 @@ pio=system.iobus.master[9]
 
 [system.tsunami.fake_pnp_read0]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -500,7 +553,7 @@ pio=system.iobus.master[11]
 
 [system.tsunami.fake_pnp_read1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -517,7 +570,7 @@ pio=system.iobus.master[12]
 
 [system.tsunami.fake_pnp_read2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -534,7 +587,7 @@ pio=system.iobus.master[13]
 
 [system.tsunami.fake_pnp_read3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -551,7 +604,7 @@ pio=system.iobus.master[14]
 
 [system.tsunami.fake_pnp_read4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -568,7 +621,7 @@ pio=system.iobus.master[15]
 
 [system.tsunami.fake_pnp_read5]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -585,7 +638,7 @@ pio=system.iobus.master[16]
 
 [system.tsunami.fake_pnp_read6]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -602,7 +655,7 @@ pio=system.iobus.master[17]
 
 [system.tsunami.fake_pnp_read7]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -619,7 +672,7 @@ pio=system.iobus.master[18]
 
 [system.tsunami.fake_pnp_write]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -636,7 +689,7 @@ pio=system.iobus.master[10]
 
 [system.tsunami.fake_ppc]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -653,7 +706,7 @@ pio=system.iobus.master[7]
 
 [system.tsunami.fake_sm_chip]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -670,7 +723,7 @@ pio=system.iobus.master[2]
 
 [system.tsunami.fake_uart1]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -687,7 +740,7 @@ pio=system.iobus.master[3]
 
 [system.tsunami.fake_uart2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -704,7 +757,7 @@ pio=system.iobus.master[4]
 
 [system.tsunami.fake_uart3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -721,7 +774,7 @@ pio=system.iobus.master[5]
 
 [system.tsunami.fake_uart4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -738,7 +791,7 @@ pio=system.iobus.master[6]
 
 [system.tsunami.fb]
 type=BadDevice
-clock=1000
+clk_domain=system.clk_domain
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=100000
@@ -785,7 +838,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.disk0 system.disk2
@@ -802,7 +855,7 @@ pio=system.iobus.master[25]
 
 [system.tsunami.io]
 type=TsunamiIO
-clock=1000
+clk_domain=system.clk_domain
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -814,7 +867,7 @@ pio=system.iobus.master[22]
 
 [system.tsunami.pchip]
 type=TsunamiPChip
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8802535473152
 pio_latency=100000
 system=system
@@ -824,7 +877,8 @@ pio=system.iobus.master[1]
 [system.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.tsunami
 size=16777216
@@ -833,7 +887,7 @@ pio=system.iobus.default
 
 [system.tsunami.uart]
 type=Uart8250
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=8804615848952
 pio_latency=100000
 platform=system.tsunami
@@ -841,3 +895,7 @@ system=system
 terminal=system.terminal
 pio=system.iobus.master[23]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
index 229260842..cabc90a11 100755
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:32:52
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:50
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/fs/10.linux-boot/alpha/linux/tsunami-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: system.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1910582068000 because m5_exit instruction encountered
+Exiting @ tick 1918473094000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
index ff644ed3f..0d89ac053 100644
--- a/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/system.terminal
@@ -24,7 +24,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
memcluster 1, usage 0, start      392, end    16384
 
freeing pages 1069:16384
 
reserving pages 1069:1070
-
4096K Bcache detected; load hit latency 40 cycles, load miss latency 124 cycles
+
4096K Bcache detected; load hit latency 38 cycles, load miss latency 142 cycles
 
SMP: 1 CPUs probed -- cpu_present_mask = 1
 
Built 1 zonelists
 
Kernel command line: root=/dev/hda1 console=ttyS0
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
index 25f4e376e..b499d5442 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/config.ini
@@ -8,18 +8,19 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
-dtb_filename=
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
@@ -27,6 +28,8 @@ mem_ranges=0:134217727
 memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -40,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -65,15 +68,19 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -92,6 +99,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -104,10 +115,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -118,12 +129,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=ArmTLB
 children=walker
@@ -132,17 +152,17 @@ walker=system.cpu0.dtb.walker
 
 [system.cpu0.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -153,12 +173,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=ArmInterrupts
 
@@ -187,7 +216,7 @@ walker=system.cpu0.itb.walker
 
 [system.cpu0.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[2]
@@ -198,9 +227,8 @@ type=ExeTracer
 [system.cpu1]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=1
 do_checkpoint_insts=true
 do_quiesce=true
@@ -219,6 +247,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -231,10 +263,10 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -245,12 +277,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=ArmTLB
 children=walker
@@ -259,17 +300,17 @@ walker=system.cpu1.dtb.walker
 
 [system.cpu1.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[7]
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -280,12 +321,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=ArmInterrupts
 
@@ -314,7 +364,7 @@ walker=system.cpu1.itb.walker
 
 [system.cpu1.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[6]
@@ -322,14 +372,18 @@ port=system.toL2Bus.slave[6]
 [system.cpu1.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -338,10 +392,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -352,18 +406,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -374,27 +437,36 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -411,29 +483,36 @@ pio=system.membus.default
 
 [system.physmem]
 type=SimpleDRAM
-addr_mapping=openmap
+activation_limit=4
+addr_mapping=RaBaChCo
 banks_per_rank=8
-clock=1000
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRCD=13750
 tREFI=7800000
 tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -446,16 +525,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -502,7 +581,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -520,7 +599,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -534,7 +613,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -543,7 +622,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -559,8 +638,8 @@ warn_access=
 pio=system.iobus.master[24]
 
 [system.realview.gic]
-type=Gic
-clock=1000
+type=Pl390
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -569,12 +648,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -584,7 +663,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -594,7 +673,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -604,7 +683,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -618,7 +697,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -631,7 +710,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -644,23 +723,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -670,19 +749,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -694,7 +772,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -707,7 +785,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -717,7 +795,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -727,7 +805,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -737,7 +815,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -747,7 +825,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -761,7 +839,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -774,7 +852,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -789,7 +867,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -799,7 +877,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -809,7 +887,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -819,7 +897,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -835,9 +913,9 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.l2c.cpu_side
@@ -849,3 +927,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
index e8e271d58..4ccac5e7b 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simerr
@@ -1,6 +1,7 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
+warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
index c2890e671..789ceb651 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:45:38
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:04:45
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 912096763500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
index ee810dcc9..1f4c71309 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.912097                       # Nu
 sim_ticks                                912096763500                       # Number of ticks simulated
 final_tick                               912096763500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 749434                       # Simulator instruction rate (inst/s)
-host_op_rate                                   964895                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            11092016800                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 399496                       # Number of bytes of host memory used
-host_seconds                                    82.23                       # Real time elapsed on the host
+host_inst_rate                                1616966                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2081841                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            23931929912                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 396248                       # Number of bytes of host memory used
+host_seconds                                    38.11                       # Real time elapsed on the host
 sim_insts                                    61625970                       # Number of instructions simulated
 sim_ops                                      79343340                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::realview.clcd     39321600                       # Number of bytes read from this memory
@@ -234,29 +234,29 @@ system.realview.nvmem.bw_total::total              75                       # To
 system.membus.throughput                     64986577                       # Throughput (bytes/s)
 system.membus.data_through_bus               59274047                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
-system.l2c.tags.replacements                         70658                       # number of replacements
-system.l2c.tags.tagsinuse                     51560.149653                       # Cycle average of tags in use
-system.l2c.tags.total_refs                         1623339                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                        135810                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                         11.953015                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks        39278.694978                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.dtb.walker       0.000049                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.itb.walker       0.001108                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst          4358.955639                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data          2482.445004                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.dtb.walker       2.678940                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst          2126.451282                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data          3310.922653                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.599345                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.dtb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.itb.walker      0.000000                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.066512                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.037879                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.dtb.walker      0.000041                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.032447                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.050521                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.786745                       # Average percentage of cache occupancy
+system.l2c.tags.replacements                    70658                       # number of replacements
+system.l2c.tags.tagsinuse                51560.149653                       # Cycle average of tags in use
+system.l2c.tags.total_refs                    1623339                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                   135810                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                    11.953015                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks   39278.694978                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.dtb.walker     0.000049                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.itb.walker     0.001108                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst     4358.955639                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data     2482.445004                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.dtb.walker     2.678940                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst     2126.451282                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data     3310.922653                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.599345                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.dtb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.itb.walker     0.000000                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.066512                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.037879                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.dtb.walker     0.000041                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.032447                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.050521                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.786745                       # Average percentage of cache occupancy
 system.l2c.ReadReq_hits::cpu0.dtb.walker         3874                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.itb.walker         1919                       # number of ReadReq hits
 system.l2c.ReadReq_hits::cpu0.inst             421038                       # number of ReadReq hits
@@ -487,15 +487,15 @@ system.cpu0.not_idle_fraction                0.021750                       # Pe
 system.cpu0.idle_fraction                    0.978250                       # Percentage of idle cycles
 system.cpu0.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu0.kern.inst.quiesce                   49966                       # number of quiesce instructions executed
-system.cpu0.icache.tags.replacements                428546                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               511.015216                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                29811115                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                429058                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                 69.480385                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle           64537139000                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.replacements           428546                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          511.015216                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs           29811115                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs           429058                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs            69.480385                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle      64537139000                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   511.015216                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.998077                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.998077                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.998077                       # Average percentage of cache occupancy
 system.cpu0.icache.ReadReq_hits::cpu0.inst     29811115                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total       29811115                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst     29811115                       # number of demand (read+write) hits
@@ -529,15 +529,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                323609                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               494.763091                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                12467604                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                323981                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                 38.482516                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle              22115000                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.replacements           323609                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          494.763091                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs           12467604                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs           323981                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs            38.482516                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle         22115000                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   494.763091                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.966334                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.966334                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.966334                       # Average percentage of cache occupancy
 system.cpu0.dcache.ReadReq_hits::cpu0.data      6512305                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total        6512305                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data      5630881                       # number of WriteReq hits
@@ -663,15 +663,15 @@ system.cpu1.not_idle_fraction                0.022362                       # Pe
 system.cpu1.idle_fraction                    0.977638                       # Percentage of idle cycles
 system.cpu1.kern.inst.arm                           0                       # number of arm instructions executed
 system.cpu1.kern.inst.quiesce                   40379                       # number of quiesce instructions executed
-system.cpu1.icache.tags.replacements                433942                       # number of replacements
-system.cpu1.icache.tags.tagsinuse               475.447912                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                31979125                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                434454                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                 73.607620                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle           69967763000                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.replacements           433942                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          475.447912                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs           31979125                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs           434454                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs            73.607620                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle      69967763000                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.tags.occ_blocks::cpu1.inst   475.447912                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.928609                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.928609                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.928609                       # Average percentage of cache occupancy
 system.cpu1.icache.ReadReq_hits::cpu1.inst     31979125                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total       31979125                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst     31979125                       # number of demand (read+write) hits
@@ -705,15 +705,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets          nan
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                294289                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse               447.573682                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                11707745                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                294801                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                 39.714061                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle           67293493000                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.replacements           294289                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          447.573682                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs           11707745                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs           294801                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs            39.714061                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle      67293493000                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.tags.occ_blocks::cpu1.data   447.573682                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.874167                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.874167                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.874167                       # Average percentage of cache occupancy
 system.cpu1.dcache.ReadReq_hits::cpu1.data      7002209                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total        7002209                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data      4520313                       # number of WriteReq hits
@@ -773,12 +773,12 @@ system.cpu1.dcache.cache_copies                     0                       # nu
 system.cpu1.dcache.writebacks::writebacks       266849                       # number of writebacks
 system.cpu1.dcache.writebacks::total           266849                       # number of writebacks
 system.cpu1.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.iocache.tags.replacements                         0                       # number of replacements
-system.iocache.tags.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                           nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements                    0                       # number of replacements
+system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
deleted file mode 100644
index 7edf5b1c7..000000000
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/status
+++ /dev/null
@@ -1 +0,0 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic-dual FAILED!
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
index 17e9c9abf..f2f53421d 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic-dual/system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
index 687db2fa1..4246eb19f 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/config.ini
@@ -8,18 +8,19 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
+children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
-dtb_filename=
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
@@ -27,6 +28,8 @@ mem_ranges=0:134217727
 memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -40,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -65,15 +68,19 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -92,6 +99,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -104,10 +115,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -118,12 +129,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -132,17 +152,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -153,12 +173,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -187,17 +216,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -208,17 +237,26 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -227,14 +265,18 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -243,10 +285,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -257,27 +299,36 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -294,29 +345,36 @@ pio=system.membus.default
 
 [system.physmem]
 type=SimpleDRAM
-addr_mapping=openmap
+activation_limit=4
+addr_mapping=RaBaChCo
 banks_per_rank=8
-clock=1000
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRCD=13750
 tREFI=7800000
 tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -329,16 +387,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -385,7 +443,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -403,7 +461,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -417,7 +475,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -426,7 +484,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -442,8 +500,8 @@ warn_access=
 pio=system.iobus.master[24]
 
 [system.realview.gic]
-type=Gic
-clock=1000
+type=Pl390
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -452,12 +510,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -467,7 +525,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -477,7 +535,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -487,7 +545,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -501,7 +559,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -514,7 +572,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -527,23 +585,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -553,19 +611,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -577,7 +634,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -590,7 +647,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -600,7 +657,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -610,7 +667,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -620,7 +677,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -630,7 +687,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -644,7 +701,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -657,7 +714,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -672,7 +729,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -682,7 +739,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -692,7 +749,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -702,7 +759,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -722,3 +779,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
index 3ee89fc27..eda827fb8 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simerr
@@ -1,6 +1,7 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
+warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
index ec6b1ae21..0ff7b53a5 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:44:32
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:30:49
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 2332810264000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
index 44e286527..a865904c2 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  2.332810                       # Nu
 sim_ticks                                2332810264000                       # Number of ticks simulated
 final_tick                               2332810264000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                 692273                       # Simulator instruction rate (inst/s)
-host_op_rate                                   890221                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                            26733610702                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 396420                       # Number of bytes of host memory used
-host_seconds                                    87.26                       # Real time elapsed on the host
+host_inst_rate                                1522133                       # Simulator instruction rate (inst/s)
+host_op_rate                                  1957369                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                            58780416325                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 396116                       # Number of bytes of host memory used
+host_seconds                                    39.70                       # Real time elapsed on the host
 sim_insts                                    60408639                       # Number of instructions simulated
 sim_ops                                      77681819                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::realview.clcd    111673344                       # Number of bytes read from this memory
@@ -285,15 +285,15 @@ system.cpu.not_idle_fraction                 0.016889                       # Pe
 system.cpu.idle_fraction                     0.983111                       # Percentage of idle cycles
 system.cpu.kern.inst.arm                            0                       # number of arm instructions executed
 system.cpu.kern.inst.quiesce                    82795                       # number of quiesce instructions executed
-system.cpu.icache.tags.replacements                 850590                       # number of replacements
-system.cpu.icache.tags.tagsinuse                511.678593                       # Cycle average of tags in use
-system.cpu.icache.tags.total_refs                 60583498                       # Total number of references to valid blocks.
-system.cpu.icache.tags.sampled_refs                 851102                       # Sample count of references to valid blocks.
-system.cpu.icache.tags.avg_refs                  71.182418                       # Average number of references to valid blocks.
-system.cpu.icache.tags.warmup_cycle             5709383000                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.tags.occ_blocks::cpu.inst     511.678593                       # Average occupied blocks per requestor
-system.cpu.icache.tags.occ_percent::cpu.inst      0.999372                       # Average percentage of cache occupancy
-system.cpu.icache.tags.occ_percent::total         0.999372                       # Average percentage of cache occupancy
+system.cpu.icache.tags.replacements            850590                       # number of replacements
+system.cpu.icache.tags.tagsinuse           511.678593                       # Cycle average of tags in use
+system.cpu.icache.tags.total_refs            60583498                       # Total number of references to valid blocks.
+system.cpu.icache.tags.sampled_refs            851102                       # Sample count of references to valid blocks.
+system.cpu.icache.tags.avg_refs             71.182418                       # Average number of references to valid blocks.
+system.cpu.icache.tags.warmup_cycle        5709383000                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.tags.occ_blocks::cpu.inst   511.678593                       # Average occupied blocks per requestor
+system.cpu.icache.tags.occ_percent::cpu.inst     0.999372                       # Average percentage of cache occupancy
+system.cpu.icache.tags.occ_percent::total     0.999372                       # Average percentage of cache occupancy
 system.cpu.icache.ReadReq_hits::cpu.inst     60583498                       # number of ReadReq hits
 system.cpu.icache.ReadReq_hits::total        60583498                       # number of ReadReq hits
 system.cpu.icache.demand_hits::cpu.inst      60583498                       # number of demand (read+write) hits
@@ -327,23 +327,23 @@ system.cpu.icache.avg_blocked_cycles::no_targets          nan
 system.cpu.icache.fast_writes                       0                       # number of fast writes performed
 system.cpu.icache.cache_copies                      0                       # number of cache copies performed
 system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.l2cache.tags.replacements                 62243                       # number of replacements
-system.cpu.l2cache.tags.tagsinuse             50007.272909                       # Cycle average of tags in use
-system.cpu.l2cache.tags.total_refs                 1669922                       # Total number of references to valid blocks.
-system.cpu.l2cache.tags.sampled_refs                127628                       # Sample count of references to valid blocks.
-system.cpu.l2cache.tags.avg_refs                 13.084292                       # Average number of references to valid blocks.
-system.cpu.l2cache.tags.warmup_cycle          2316901489000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.tags.replacements            62243                       # number of replacements
+system.cpu.l2cache.tags.tagsinuse        50007.272909                       # Cycle average of tags in use
+system.cpu.l2cache.tags.total_refs            1669922                       # Total number of references to valid blocks.
+system.cpu.l2cache.tags.sampled_refs           127628                       # Sample count of references to valid blocks.
+system.cpu.l2cache.tags.avg_refs            13.084292                       # Average number of references to valid blocks.
+system.cpu.l2cache.tags.warmup_cycle     2316901489000                       # Cycle when the warmup percentage was hit.
 system.cpu.l2cache.tags.occ_blocks::writebacks 36899.582990                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker     2.960148                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker     0.993931                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.inst   7014.720482                       # Average occupied blocks per requestor
-system.cpu.l2cache.tags.occ_blocks::cpu.data   6089.015357                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.inst  7014.720482                       # Average occupied blocks per requestor
+system.cpu.l2cache.tags.occ_blocks::cpu.data  6089.015357                       # Average occupied blocks per requestor
 system.cpu.l2cache.tags.occ_percent::writebacks     0.563043                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker     0.000045                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.itb.walker     0.000015                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.inst     0.107036                       # Average percentage of cache occupancy
 system.cpu.l2cache.tags.occ_percent::cpu.data     0.092911                       # Average percentage of cache occupancy
-system.cpu.l2cache.tags.occ_percent::total        0.763050                       # Average percentage of cache occupancy
+system.cpu.l2cache.tags.occ_percent::total     0.763050                       # Average percentage of cache occupancy
 system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker         7507                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.itb.walker         3129                       # number of ReadReq hits
 system.cpu.l2cache.ReadReq_hits::cpu.inst       838871                       # number of ReadReq hits
@@ -435,15 +435,15 @@ system.cpu.l2cache.cache_copies                     0                       # nu
 system.cpu.l2cache.writebacks::writebacks        57863                       # number of writebacks
 system.cpu.l2cache.writebacks::total            57863                       # number of writebacks
 system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.dcache.tags.replacements                 623337                       # number of replacements
-system.cpu.dcache.tags.tagsinuse                511.997031                       # Cycle average of tags in use
-system.cpu.dcache.tags.total_refs                 23628343                       # Total number of references to valid blocks.
-system.cpu.dcache.tags.sampled_refs                 623849                       # Sample count of references to valid blocks.
-system.cpu.dcache.tags.avg_refs                  37.875100                       # Average number of references to valid blocks.
-system.cpu.dcache.tags.warmup_cycle               21763000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.tags.occ_blocks::cpu.data     511.997031                       # Average occupied blocks per requestor
-system.cpu.dcache.tags.occ_percent::cpu.data      0.999994                       # Average percentage of cache occupancy
-system.cpu.dcache.tags.occ_percent::total         0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.replacements            623337                       # number of replacements
+system.cpu.dcache.tags.tagsinuse           511.997031                       # Cycle average of tags in use
+system.cpu.dcache.tags.total_refs            23628343                       # Total number of references to valid blocks.
+system.cpu.dcache.tags.sampled_refs            623849                       # Sample count of references to valid blocks.
+system.cpu.dcache.tags.avg_refs             37.875100                       # Average number of references to valid blocks.
+system.cpu.dcache.tags.warmup_cycle          21763000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.tags.occ_blocks::cpu.data   511.997031                       # Average occupied blocks per requestor
+system.cpu.dcache.tags.occ_percent::cpu.data     0.999994                       # Average percentage of cache occupancy
+system.cpu.dcache.tags.occ_percent::total     0.999994                       # Average percentage of cache occupancy
 system.cpu.dcache.ReadReq_hits::cpu.data     13180066                       # number of ReadReq hits
 system.cpu.dcache.ReadReq_hits::total        13180066                       # number of ReadReq hits
 system.cpu.dcache.WriteReq_hits::cpu.data      9962072                       # number of WriteReq hits
@@ -502,12 +502,12 @@ system.cpu.dcache.no_allocate_misses                0                       # Nu
 system.cpu.toL2Bus.throughput                59102649                       # Throughput (bytes/s)
 system.cpu.toL2Bus.data_through_bus         137875266                       # Total data (bytes)
 system.cpu.toL2Bus.snoop_data_through_bus            0                       # Total snoop data (bytes)
-system.iocache.tags.replacements                         0                       # number of replacements
-system.iocache.tags.tagsinuse                            0                       # Cycle average of tags in use
-system.iocache.tags.total_refs                           0                       # Total number of references to valid blocks.
-system.iocache.tags.sampled_refs                         0                       # Sample count of references to valid blocks.
-system.iocache.tags.avg_refs                           nan                       # Average number of references to valid blocks.
-system.iocache.tags.warmup_cycle                         0                       # Cycle when the warmup percentage was hit.
+system.iocache.tags.replacements                    0                       # number of replacements
+system.iocache.tags.tagsinuse                       0                       # Cycle average of tags in use
+system.iocache.tags.total_refs                      0                       # Total number of references to valid blocks.
+system.iocache.tags.sampled_refs                    0                       # Sample count of references to valid blocks.
+system.iocache.tags.avg_refs                      nan                       # Average number of references to valid blocks.
+system.iocache.tags.warmup_cycle                    0                       # Cycle when the warmup percentage was hit.
 system.iocache.blocked_cycles::no_mshrs             0                       # number of cycles access was blocked
 system.iocache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
 system.iocache.blocked::no_mshrs                    0                       # number of cycles access was blocked
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
deleted file mode 100644
index 5d3e81846..000000000
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/status
+++ /dev/null
@@ -1 +0,0 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-atomic FAILED!
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
index c810346c6..d321164ca 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-atomic/system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
index 2d5c88739..6e5d183fa 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/config.ini
@@ -8,18 +8,19 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -27,6 +28,8 @@ mem_ranges=0:134217727
 memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -40,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -65,15 +68,19 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -91,6 +98,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu0.tracer
@@ -100,10 +108,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,12 +122,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=ArmTLB
 children=walker
@@ -128,17 +145,17 @@ walker=system.cpu0.dtb.walker
 
 [system.cpu0.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -149,12 +166,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=ArmInterrupts
 
@@ -183,7 +209,7 @@ walker=system.cpu0.itb.walker
 
 [system.cpu0.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[2]
@@ -194,9 +220,8 @@ type=ExeTracer
 [system.cpu1]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=1
 do_checkpoint_insts=true
 do_quiesce=true
@@ -214,6 +239,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu1.tracer
@@ -223,10 +249,10 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -237,12 +263,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=ArmTLB
 children=walker
@@ -251,17 +286,17 @@ walker=system.cpu1.dtb.walker
 
 [system.cpu1.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[7]
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -272,12 +307,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=ArmInterrupts
 
@@ -306,7 +350,7 @@ walker=system.cpu1.itb.walker
 
 [system.cpu1.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[6]
@@ -314,14 +358,18 @@ port=system.toL2Bus.slave[6]
 [system.cpu1.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -330,10 +378,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -344,18 +392,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -366,28 +423,36 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -405,19 +470,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -428,8 +498,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -442,16 +511,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -498,7 +567,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -516,7 +585,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -530,7 +599,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -539,7 +608,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -556,7 +625,7 @@ pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
-clock=1000
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -565,12 +634,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -580,7 +649,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -590,7 +659,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -600,7 +669,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -614,7 +683,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -627,7 +696,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -640,23 +709,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -666,19 +735,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -690,7 +758,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -703,7 +771,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -713,7 +781,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -723,7 +791,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -733,7 +801,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -743,7 +811,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -757,7 +825,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -770,7 +838,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -785,7 +853,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -795,7 +863,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -805,7 +873,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -815,7 +883,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -831,8 +899,7 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -846,3 +913,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
index a21ab0771..c328b3227 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 26 2013 15:15:53
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:25:29
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 1183437503500 because m5_exit instruction encountered
+Exiting @ tick 1194883580500 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
deleted file mode 100644
index 8ae0da5a8..000000000
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/status
+++ /dev/null
@@ -1 +0,0 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing-dual FAILED!
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
index 4f02e6414..69edb0827 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing-dual/system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
index f1513514e..01d95ba19 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/config.ini
@@ -8,18 +8,19 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu intrctrl iobus iocache membus physmem realview terminal vncserver
+children=bridge cf0 clk_domain cpu cpu_clk_domain intrctrl iobus iocache membus physmem realview terminal vncserver voltage_domain
 atags_addr=256
-boot_loader=/scratch/nilay/GEM5/system/binaries/boot.arm
+boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
-dtb_filename=
+cache_line_size=64
+clk_domain=system.clk_domain
+dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
 flags_addr=268435504
 gic_cpu_addr=520093952
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+kernel=/dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=timing
@@ -27,6 +28,8 @@ mem_ranges=0:134217727
 memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
+panic_on_oops=true
+panic_on_panic=true
 readfile=tests/halt.sh
 symbolfile=
 work_begin_ckpt_count=0
@@ -40,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -65,15 +68,19 @@ table_size=65536
 
 [system.cf0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-arm-ael.img
+image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -91,6 +98,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -100,10 +108,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -114,12 +122,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -128,17 +145,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -149,12 +166,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -183,17 +209,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -204,17 +230,26 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -223,14 +258,18 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walke
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -239,10 +278,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -253,27 +292,36 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.cpu.l2cache.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -290,29 +338,36 @@ pio=system.membus.default
 
 [system.physmem]
 type=SimpleDRAM
-addr_mapping=openmap
+activation_limit=4
+addr_mapping=RaBaChCo
 banks_per_rank=8
-clock=1000
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRCD=13750
 tREFI=7800000
 tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -325,16 +380,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -381,7 +436,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -399,7 +454,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -413,7 +468,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -422,7 +477,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -438,8 +493,8 @@ warn_access=
 pio=system.iobus.master[24]
 
 [system.realview.gic]
-type=Gic
-clock=1000
+type=Pl390
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -448,12 +503,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -463,7 +518,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -473,7 +528,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -483,7 +538,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -497,7 +552,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -510,7 +565,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -523,23 +578,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -549,19 +604,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -573,7 +627,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -586,7 +640,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -596,7 +650,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -606,7 +660,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -616,7 +670,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -626,7 +680,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -640,7 +694,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -653,7 +707,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -668,7 +722,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -678,7 +732,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -688,7 +742,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -698,7 +752,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -718,3 +772,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
index 3ee89fc27..eda827fb8 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simerr
@@ -1,6 +1,7 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
+warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
index a83c8cf44..b95a8c30f 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:45:50
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:14:19
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 2603634694000 because m5_exit instruction encountered
+Exiting @ tick 2615716222000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
deleted file mode 100644
index 4523c3c36..000000000
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/status
+++ /dev/null
@@ -1 +0,0 @@
-build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-simple-timing FAILED!
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
index 3191ccab8..ca0537849 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/system.terminal
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
index 7bfde3940..d251aac9e 100644
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/config.ini
@@ -8,11 +8,12 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxArmSystem
-children=bridge cf0 cpu0 cpu1 intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver
+children=bridge cf0 clk_domain cpu0 cpu1 cpu_clk_domain intrctrl iobus iocache l2c membus physmem realview terminal toL2Bus vncserver voltage_domain
 atags_addr=256
 boot_loader=/dist/m5/system/binaries/boot.arm
 boot_osflags=earlyprintk console=ttyAMA0 lpj=19988480 norandmaps rw loglevel=8 mem=128MB root=/dev/sda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 dtb_filename=False
 early_kernel_symbols=false
 enable_context_switch_stats_dump=false
@@ -24,7 +25,7 @@ load_addr_mask=268435455
 machine_type=RealView_PBX
 mem_mode=atomic
 mem_ranges=0:134217727
-memories=system.realview.nvmem system.physmem
+memories=system.physmem system.realview.nvmem
 multi_proc=true
 num_work_ids=16
 panic_on_oops=true
@@ -42,7 +43,7 @@ system_port=system.membus.slave[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=268435456:520093695 1073741824:1610612735
 req_size=16
@@ -70,12 +71,16 @@ type=RawDiskImage
 image_file=/dist/m5/system/disks/linux-arm-ael.img
 read_only=true
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -110,10 +115,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -124,12 +129,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=ArmTLB
 children=walker
@@ -138,17 +152,17 @@ walker=system.cpu0.dtb.walker
 
 [system.cpu0.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[3]
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -159,12 +173,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=ArmInterrupts
 
@@ -193,7 +216,7 @@ walker=system.cpu0.itb.walker
 
 [system.cpu0.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.toL2Bus.slave[2]
@@ -203,10 +226,9 @@ type=ExeTracer
 
 [system.cpu1]
 type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer
-branchPred=Null
+children=dtb isa itb tracer
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -215,7 +237,7 @@ dtb=system.cpu1.dtb
 fastmem=false
 function_trace=false
 function_trace_start=0
-interrupts=system.cpu1.interrupts
+interrupts=Null
 isa=system.cpu1.isa
 itb=system.cpu1.itb
 max_insts_all_threads=0
@@ -245,13 +267,10 @@ walker=system.cpu1.dtb.walker
 
 [system.cpu1.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
-[system.cpu1.interrupts]
-type=ArmInterrupts
-
 [system.cpu1.isa]
 type=ArmISA
 fpsid=1090793632
@@ -277,21 +296,25 @@ walker=system.cpu1.itb.walker
 
 [system.cpu1.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
 [system.cpu1.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.intrctrl]
 type=IntrControl
 sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -300,10 +323,10 @@ slave=system.bridge.master system.realview.clcd.dma system.realview.cf_ctrl.dma
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -314,18 +337,27 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[25]
 mem_side=system.membus.slave[2]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -336,28 +368,36 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.bridge.slave system.realview.nvmem.port system.physmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio
+master=system.bridge.slave system.realview.nvmem.port system.realview.gic.pio system.realview.l2x0_fake.pio system.realview.a9scu.pio system.realview.local_cpu_timer.pio system.physmem.port
 slave=system.system_port system.l2c.mem_side system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -375,19 +415,24 @@ pio=system.membus.default
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -398,8 +443,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[2]
+port=system.membus.master[6]
 
 [system.realview]
 type=RealView
@@ -412,16 +456,16 @@ system=system
 
 [system.realview.a9scu]
 type=A9SCU
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=520093696
 pio_latency=100000
 system=system
-pio=system.membus.master[5]
+pio=system.membus.master[4]
 
 [system.realview.aaci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268451840
 pio_latency=100000
@@ -468,7 +512,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=2
 disks=system.cf0
@@ -486,7 +530,7 @@ pio=system.iobus.master[7]
 [system.realview.clcd]
 type=Pl111
 amba_id=1315089
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num=55
 pio_addr=268566528
@@ -500,7 +544,7 @@ pio=system.iobus.master[4]
 [system.realview.dmac_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268632064
 pio_latency=100000
@@ -509,7 +553,7 @@ pio=system.iobus.master[9]
 
 [system.realview.flash_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=true
 pio_addr=1073741824
 pio_latency=100000
@@ -526,7 +570,7 @@ pio=system.iobus.master[24]
 
 [system.realview.gic]
 type=Pl390
-clock=1000
+clk_domain=system.clk_domain
 cpu_addr=520093952
 cpu_pio_delay=10000
 dist_addr=520097792
@@ -535,12 +579,12 @@ int_latency=10000
 it_lines=128
 platform=system.realview
 system=system
-pio=system.membus.master[3]
+pio=system.membus.master[2]
 
 [system.realview.gpio0_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268513280
 pio_latency=100000
@@ -550,7 +594,7 @@ pio=system.iobus.master[16]
 [system.realview.gpio1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268517376
 pio_latency=100000
@@ -560,7 +604,7 @@ pio=system.iobus.master[17]
 [system.realview.gpio2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268521472
 pio_latency=100000
@@ -570,7 +614,7 @@ pio=system.iobus.master[18]
 [system.realview.kmi0]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=52
@@ -584,7 +628,7 @@ pio=system.iobus.master[5]
 [system.realview.kmi1]
 type=Pl050
 amba_id=1314896
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=1000000
 int_num=53
@@ -597,7 +641,7 @@ pio=system.iobus.master[6]
 
 [system.realview.l2x0_fake]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=520101888
 pio_latency=100000
@@ -610,23 +654,23 @@ ret_data8=255
 system=system
 update_data=false
 warn_access=
-pio=system.membus.master[4]
+pio=system.membus.master[3]
 
 [system.realview.local_cpu_timer]
 type=CpuLocalTimer
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_num_timer=29
 int_num_watchdog=30
 pio_addr=520095232
 pio_latency=100000
 system=system
-pio=system.membus.master[6]
+pio=system.membus.master[5]
 
 [system.realview.mmc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268455936
 pio_latency=100000
@@ -636,19 +680,18 @@ pio=system.iobus.master[22]
 [system.realview.nvmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
+clk_domain=system.clk_domain
 conf_table_reported=false
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=2147483648:2214592511
-zero=true
 port=system.membus.master[1]
 
 [system.realview.realview_io]
 type=RealViewCtrl
-clock=1000
+clk_domain=system.clk_domain
 idreg=0
 pio_addr=268435456
 pio_latency=100000
@@ -660,7 +703,7 @@ pio=system.iobus.master[1]
 [system.realview.rtc]
 type=PL031
 amba_id=3412017
-clock=1000
+clk_domain=system.clk_domain
 gic=system.realview.gic
 int_delay=100000
 int_num=42
@@ -673,7 +716,7 @@ pio=system.iobus.master[23]
 [system.realview.sci_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268492800
 pio_latency=100000
@@ -683,7 +726,7 @@ pio=system.iobus.master[20]
 [system.realview.smc_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=269357056
 pio_latency=100000
@@ -693,7 +736,7 @@ pio=system.iobus.master[13]
 [system.realview.sp810_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=true
 pio_addr=268439552
 pio_latency=100000
@@ -703,7 +746,7 @@ pio=system.iobus.master[14]
 [system.realview.ssp_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268488704
 pio_latency=100000
@@ -713,7 +756,7 @@ pio=system.iobus.master[19]
 [system.realview.timer0]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -727,7 +770,7 @@ pio=system.iobus.master[2]
 [system.realview.timer1]
 type=Sp804
 amba_id=1316868
-clock=1000
+clk_domain=system.clk_domain
 clock0=1000000
 clock1=1000000
 gic=system.realview.gic
@@ -740,7 +783,7 @@ pio=system.iobus.master[3]
 
 [system.realview.uart]
 type=Pl011
-clock=1000
+clk_domain=system.clk_domain
 end_on_eot=false
 gic=system.realview.gic
 int_delay=100000
@@ -755,7 +798,7 @@ pio=system.iobus.master[0]
 [system.realview.uart1_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268476416
 pio_latency=100000
@@ -765,7 +808,7 @@ pio=system.iobus.master[10]
 [system.realview.uart2_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268480512
 pio_latency=100000
@@ -775,7 +818,7 @@ pio=system.iobus.master[11]
 [system.realview.uart3_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268484608
 pio_latency=100000
@@ -785,7 +828,7 @@ pio=system.iobus.master[12]
 [system.realview.watchdog_fake]
 type=AmbaFake
 amba_id=0
-clock=1000
+clk_domain=system.clk_domain
 ignore_access=false
 pio_addr=268500992
 pio_latency=100000
@@ -801,8 +844,7 @@ port=3456
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -816,3 +858,7 @@ frame_capture=false
 number=0
 port=5900
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
index 083c63715..06edbeba7 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simerr
@@ -1,6 +1,7 @@
 warn: Sockets disabled, not accepting vnc client connections
 warn: Sockets disabled, not accepting terminal connections
 warn: Sockets disabled, not accepting gdb connections
+warn: DTB file specified, but no device tree support in kernel
 warn: The clidr register always reports 0 caches.
 warn: clidr LoUIS field of 0b001 to match current ARM implementations.
 warn: The csselr register isn't implemented.
diff --git a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
index ac14d4997..9b6e36065 100755
--- a/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-atomic/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realv
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:48:26
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 07:58:36
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic -re tests/run.py build/ARM/tests/opt/quick/fs/10.linux-boot/arm/linux/realview-switcheroo-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
+info: kernel located at: /dist/m5/system/binaries/vmlinux.arm.smp.fb.2.6.38.8
 info: Using bootloader at address 0x80000000
 info: Entering event queue @ 0.  Starting simulation...
 Switching CPUs...
@@ -35,9312 +35,9315 @@ Switching CPUs...
 Next CPU: AtomicSimpleCPU
 info: Entering event queue @ 6000000000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 6000001000.  Starting simulation...
+info: Entering event queue @ 6000003500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 7000001000.  Starting simulation...
+info: Entering event queue @ 7000003500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 8000001000.  Starting simulation...
+info: Entering event queue @ 8000003500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 9000001000.  Starting simulation...
+info: Entering event queue @ 9000003500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 9000002500.  Starting simulation...
+info: Entering event queue @ 9000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 10000002500.  Starting simulation...
+info: Entering event queue @ 10000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 11000002500.  Starting simulation...
+info: Entering event queue @ 11000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 12000002500.  Starting simulation...
+info: Entering event queue @ 12000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 13000002500.  Starting simulation...
+info: Entering event queue @ 13000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 14000002500.  Starting simulation...
+info: Entering event queue @ 14000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 15000002500.  Starting simulation...
+info: Entering event queue @ 15000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 16000002500.  Starting simulation...
+info: Entering event queue @ 16000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 17000002500.  Starting simulation...
+info: Entering event queue @ 17000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 18000002500.  Starting simulation...
+info: Entering event queue @ 18000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 19000002500.  Starting simulation...
+info: Entering event queue @ 19000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 20000002500.  Starting simulation...
+info: Entering event queue @ 20000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 21000002500.  Starting simulation...
+info: Entering event queue @ 21000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 22000002500.  Starting simulation...
+info: Entering event queue @ 22000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 23000002500.  Starting simulation...
+info: Entering event queue @ 23000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 24000002500.  Starting simulation...
+info: Entering event queue @ 24000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 25000002500.  Starting simulation...
+info: Entering event queue @ 25000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 26000002500.  Starting simulation...
+info: Entering event queue @ 26000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 27000002500.  Starting simulation...
+info: Entering event queue @ 27000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 28000002500.  Starting simulation...
+info: Entering event queue @ 28000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 29000002500.  Starting simulation...
+info: Entering event queue @ 29000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 30000002500.  Starting simulation...
+info: Entering event queue @ 30000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 31000002500.  Starting simulation...
+info: Entering event queue @ 31000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 32000002500.  Starting simulation...
+info: Entering event queue @ 32000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 33000002500.  Starting simulation...
+info: Entering event queue @ 33000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 34000002500.  Starting simulation...
+info: Entering event queue @ 34000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 35000002500.  Starting simulation...
+info: Entering event queue @ 35000006500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 36000006500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 36000002500.  Starting simulation...
+info: Entering event queue @ 36000007000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 37000002500.  Starting simulation...
+info: Entering event queue @ 37000007000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 38000002500.  Starting simulation...
+info: Entering event queue @ 38000007000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 39000002500.  Starting simulation...
+info: Entering event queue @ 39000007000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 40000002500.  Starting simulation...
+info: Entering event queue @ 40000007000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 41000002500.  Starting simulation...
+info: Entering event queue @ 41000007000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 42000002500.  Starting simulation...
+info: Entering event queue @ 42000007000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 43000002500.  Starting simulation...
+info: Entering event queue @ 43000007000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 44000002500.  Starting simulation...
+info: Entering event queue @ 44000007000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 44000004000.  Starting simulation...
+info: Entering event queue @ 44000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 45000004000.  Starting simulation...
+info: Entering event queue @ 45000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 46000004000.  Starting simulation...
+info: Entering event queue @ 46000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 47000004000.  Starting simulation...
+info: Entering event queue @ 47000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 48000004000.  Starting simulation...
+info: Entering event queue @ 48000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 49000004000.  Starting simulation...
+info: Entering event queue @ 49000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 50000004000.  Starting simulation...
+info: Entering event queue @ 50000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 51000004000.  Starting simulation...
+info: Entering event queue @ 51000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 52000004000.  Starting simulation...
+info: Entering event queue @ 52000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 53000004000.  Starting simulation...
+info: Entering event queue @ 53000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 54000004000.  Starting simulation...
+info: Entering event queue @ 54000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 55000004000.  Starting simulation...
+info: Entering event queue @ 55000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 56000004000.  Starting simulation...
+info: Entering event queue @ 56000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 57000004000.  Starting simulation...
+info: Entering event queue @ 57000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 58000004000.  Starting simulation...
+info: Entering event queue @ 58000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 59000004000.  Starting simulation...
+info: Entering event queue @ 59000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 60000004000.  Starting simulation...
+info: Entering event queue @ 60000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 61000004000.  Starting simulation...
+info: Entering event queue @ 61000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 62000004000.  Starting simulation...
+info: Entering event queue @ 62000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 63000004000.  Starting simulation...
+info: Entering event queue @ 63000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 64000004000.  Starting simulation...
+info: Entering event queue @ 64000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 65000004000.  Starting simulation...
+info: Entering event queue @ 65000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 66000004000.  Starting simulation...
+info: Entering event queue @ 66000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 67000004000.  Starting simulation...
+info: Entering event queue @ 67000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 68000004000.  Starting simulation...
+info: Entering event queue @ 68000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 69000004000.  Starting simulation...
+info: Entering event queue @ 69000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 70000004000.  Starting simulation...
+info: Entering event queue @ 70000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 71000004000.  Starting simulation...
+info: Entering event queue @ 71000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 72000004000.  Starting simulation...
+info: Entering event queue @ 72000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 73000004000.  Starting simulation...
+info: Entering event queue @ 73000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 74000004000.  Starting simulation...
+info: Entering event queue @ 74000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 75000004000.  Starting simulation...
+info: Entering event queue @ 75000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 76000004000.  Starting simulation...
+info: Entering event queue @ 76000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 77000004000.  Starting simulation...
+info: Entering event queue @ 77000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 78000004000.  Starting simulation...
+info: Entering event queue @ 78000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 79000004000.  Starting simulation...
+info: Entering event queue @ 79000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 80000004000.  Starting simulation...
+info: Entering event queue @ 80000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 81000004000.  Starting simulation...
+info: Entering event queue @ 81000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 82000004000.  Starting simulation...
+info: Entering event queue @ 82000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 83000004000.  Starting simulation...
+info: Entering event queue @ 83000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 84000004000.  Starting simulation...
+info: Entering event queue @ 84000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 85000004000.  Starting simulation...
+info: Entering event queue @ 85000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 86000004000.  Starting simulation...
+info: Entering event queue @ 86000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 87000004000.  Starting simulation...
+info: Entering event queue @ 87000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 88000004000.  Starting simulation...
+info: Entering event queue @ 88000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 89000004000.  Starting simulation...
+info: Entering event queue @ 89000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 90000004000.  Starting simulation...
+info: Entering event queue @ 90000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 91000004000.  Starting simulation...
+info: Entering event queue @ 91000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 92000004000.  Starting simulation...
+info: Entering event queue @ 92000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 93000004000.  Starting simulation...
+info: Entering event queue @ 93000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 94000004000.  Starting simulation...
+info: Entering event queue @ 94000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 95000004000.  Starting simulation...
+info: Entering event queue @ 95000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 96000004000.  Starting simulation...
+info: Entering event queue @ 96000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 97000004000.  Starting simulation...
+info: Entering event queue @ 97000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 98000004000.  Starting simulation...
+info: Entering event queue @ 98000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 99000004000.  Starting simulation...
+info: Entering event queue @ 99000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 100000004000.  Starting simulation...
+info: Entering event queue @ 100000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 101000004000.  Starting simulation...
+info: Entering event queue @ 101000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 102000004000.  Starting simulation...
+info: Entering event queue @ 102000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 103000004000.  Starting simulation...
+info: Entering event queue @ 103000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 104000004000.  Starting simulation...
+info: Entering event queue @ 104000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 105000004000.  Starting simulation...
+info: Entering event queue @ 105000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 106000004000.  Starting simulation...
+info: Entering event queue @ 106000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 107000004000.  Starting simulation...
+info: Entering event queue @ 107000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 108000004000.  Starting simulation...
+info: Entering event queue @ 108000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 109000004000.  Starting simulation...
+info: Entering event queue @ 109000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 110000004000.  Starting simulation...
+info: Entering event queue @ 110000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 111000004000.  Starting simulation...
+info: Entering event queue @ 111000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 112000004000.  Starting simulation...
+info: Entering event queue @ 112000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 113000004000.  Starting simulation...
+info: Entering event queue @ 113000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 114000004000.  Starting simulation...
+info: Entering event queue @ 114000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 115000004000.  Starting simulation...
+info: Entering event queue @ 115000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 116000004000.  Starting simulation...
+info: Entering event queue @ 116000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 117000004000.  Starting simulation...
+info: Entering event queue @ 117000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 118000004000.  Starting simulation...
+info: Entering event queue @ 118000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 119000004000.  Starting simulation...
+info: Entering event queue @ 119000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 120000004000.  Starting simulation...
+info: Entering event queue @ 120000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 121000004000.  Starting simulation...
+info: Entering event queue @ 121000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 122000004000.  Starting simulation...
+info: Entering event queue @ 122000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 123000004000.  Starting simulation...
+info: Entering event queue @ 123000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 124000004000.  Starting simulation...
+info: Entering event queue @ 124000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 125000004000.  Starting simulation...
+info: Entering event queue @ 125000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 126000004000.  Starting simulation...
+info: Entering event queue @ 126000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 127000004000.  Starting simulation...
+info: Entering event queue @ 127000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 128000004000.  Starting simulation...
+info: Entering event queue @ 128000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 129000004000.  Starting simulation...
+info: Entering event queue @ 129000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 130000004000.  Starting simulation...
+info: Entering event queue @ 130000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 131000004000.  Starting simulation...
+info: Entering event queue @ 131000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 132000004000.  Starting simulation...
+info: Entering event queue @ 132000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 133000004000.  Starting simulation...
+info: Entering event queue @ 133000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 134000004000.  Starting simulation...
+info: Entering event queue @ 134000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 135000004000.  Starting simulation...
+info: Entering event queue @ 135000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 136000004000.  Starting simulation...
+info: Entering event queue @ 136000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 137000004000.  Starting simulation...
+info: Entering event queue @ 137000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 138000004000.  Starting simulation...
+info: Entering event queue @ 138000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 139000004000.  Starting simulation...
+info: Entering event queue @ 139000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 140000004000.  Starting simulation...
+info: Entering event queue @ 140000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 141000004000.  Starting simulation...
+info: Entering event queue @ 141000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 142000004000.  Starting simulation...
+info: Entering event queue @ 142000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 143000004000.  Starting simulation...
+info: Entering event queue @ 143000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 144000004000.  Starting simulation...
+info: Entering event queue @ 144000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 145000004000.  Starting simulation...
+info: Entering event queue @ 145000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 146000004000.  Starting simulation...
+info: Entering event queue @ 146000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 147000004000.  Starting simulation...
+info: Entering event queue @ 147000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 148000004000.  Starting simulation...
+info: Entering event queue @ 148000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 149000004000.  Starting simulation...
+info: Entering event queue @ 149000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 150000004000.  Starting simulation...
+info: Entering event queue @ 150000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 151000004000.  Starting simulation...
+info: Entering event queue @ 151000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 152000004000.  Starting simulation...
+info: Entering event queue @ 152000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 153000004000.  Starting simulation...
+info: Entering event queue @ 153000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 154000004000.  Starting simulation...
+info: Entering event queue @ 154000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 155000004000.  Starting simulation...
+info: Entering event queue @ 155000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 156000004000.  Starting simulation...
+info: Entering event queue @ 156000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 157000004000.  Starting simulation...
+info: Entering event queue @ 157000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 158000004000.  Starting simulation...
+info: Entering event queue @ 158000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 159000004000.  Starting simulation...
+info: Entering event queue @ 159000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 160000004000.  Starting simulation...
+info: Entering event queue @ 160000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 161000004000.  Starting simulation...
+info: Entering event queue @ 161000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 162000004000.  Starting simulation...
+info: Entering event queue @ 162000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 163000004000.  Starting simulation...
+info: Entering event queue @ 163000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 164000004000.  Starting simulation...
+info: Entering event queue @ 164000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 165000004000.  Starting simulation...
+info: Entering event queue @ 165000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 166000004000.  Starting simulation...
+info: Entering event queue @ 166000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 167000004000.  Starting simulation...
+info: Entering event queue @ 167000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 168000004000.  Starting simulation...
+info: Entering event queue @ 168000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 169000004000.  Starting simulation...
+info: Entering event queue @ 169000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 170000004000.  Starting simulation...
+info: Entering event queue @ 170000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 171000004000.  Starting simulation...
+info: Entering event queue @ 171000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 172000004000.  Starting simulation...
+info: Entering event queue @ 172000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 173000004000.  Starting simulation...
+info: Entering event queue @ 173000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 174000004000.  Starting simulation...
+info: Entering event queue @ 174000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 175000004000.  Starting simulation...
+info: Entering event queue @ 175000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 176000004000.  Starting simulation...
+info: Entering event queue @ 176000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 177000004000.  Starting simulation...
+info: Entering event queue @ 177000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 178000004000.  Starting simulation...
+info: Entering event queue @ 178000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 179000004000.  Starting simulation...
+info: Entering event queue @ 179000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 180000004000.  Starting simulation...
+info: Entering event queue @ 180000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 181000004000.  Starting simulation...
+info: Entering event queue @ 181000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 182000004000.  Starting simulation...
+info: Entering event queue @ 182000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 183000004000.  Starting simulation...
+info: Entering event queue @ 183000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 184000004000.  Starting simulation...
+info: Entering event queue @ 184000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 185000004000.  Starting simulation...
+info: Entering event queue @ 185000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 186000004000.  Starting simulation...
+info: Entering event queue @ 186000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 187000004000.  Starting simulation...
+info: Entering event queue @ 187000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 188000004000.  Starting simulation...
+info: Entering event queue @ 188000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 189000004000.  Starting simulation...
+info: Entering event queue @ 189000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 190000004000.  Starting simulation...
+info: Entering event queue @ 190000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 191000004000.  Starting simulation...
+info: Entering event queue @ 191000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 192000004000.  Starting simulation...
+info: Entering event queue @ 192000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 193000004000.  Starting simulation...
+info: Entering event queue @ 193000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 194000004000.  Starting simulation...
+info: Entering event queue @ 194000010500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 195000010500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 195000004000.  Starting simulation...
+info: Entering event queue @ 195000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 196000004000.  Starting simulation...
+info: Entering event queue @ 196000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 197000004000.  Starting simulation...
+info: Entering event queue @ 197000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 198000004000.  Starting simulation...
+info: Entering event queue @ 198000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 199000004000.  Starting simulation...
+info: Entering event queue @ 199000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 200000004000.  Starting simulation...
+info: Entering event queue @ 200000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 201000004000.  Starting simulation...
+info: Entering event queue @ 201000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 202000004000.  Starting simulation...
+info: Entering event queue @ 202000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 203000004000.  Starting simulation...
+info: Entering event queue @ 203000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 204000004000.  Starting simulation...
+info: Entering event queue @ 204000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 205000004000.  Starting simulation...
+info: Entering event queue @ 205000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 206000004000.  Starting simulation...
+info: Entering event queue @ 206000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 207000004000.  Starting simulation...
+info: Entering event queue @ 207000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 208000004000.  Starting simulation...
+info: Entering event queue @ 208000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 209000004000.  Starting simulation...
+info: Entering event queue @ 209000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 210000004000.  Starting simulation...
+info: Entering event queue @ 210000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 211000004000.  Starting simulation...
+info: Entering event queue @ 211000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 212000004000.  Starting simulation...
+info: Entering event queue @ 212000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 213000004000.  Starting simulation...
+info: Entering event queue @ 213000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 214000004000.  Starting simulation...
+info: Entering event queue @ 214000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 215000004000.  Starting simulation...
+info: Entering event queue @ 215000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 216000004000.  Starting simulation...
+info: Entering event queue @ 216000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 217000004000.  Starting simulation...
+info: Entering event queue @ 217000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 218000004000.  Starting simulation...
+info: Entering event queue @ 218000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 219000004000.  Starting simulation...
+info: Entering event queue @ 219000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 220000004000.  Starting simulation...
+info: Entering event queue @ 220000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 221000004000.  Starting simulation...
+info: Entering event queue @ 221000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 222000004000.  Starting simulation...
+info: Entering event queue @ 222000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 223000004000.  Starting simulation...
+info: Entering event queue @ 223000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 224000004000.  Starting simulation...
+info: Entering event queue @ 224000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 225000004000.  Starting simulation...
+info: Entering event queue @ 225000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 226000004000.  Starting simulation...
+info: Entering event queue @ 226000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 227000004000.  Starting simulation...
+info: Entering event queue @ 227000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 228000004000.  Starting simulation...
+info: Entering event queue @ 228000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 229000004000.  Starting simulation...
+info: Entering event queue @ 229000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 230000004000.  Starting simulation...
+info: Entering event queue @ 230000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 231000004000.  Starting simulation...
+info: Entering event queue @ 231000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 232000004000.  Starting simulation...
+info: Entering event queue @ 232000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 233000004000.  Starting simulation...
+info: Entering event queue @ 233000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 234000004000.  Starting simulation...
+info: Entering event queue @ 234000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 235000004000.  Starting simulation...
+info: Entering event queue @ 235000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 236000004000.  Starting simulation...
+info: Entering event queue @ 236000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 237000004000.  Starting simulation...
+info: Entering event queue @ 237000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 238000004000.  Starting simulation...
+info: Entering event queue @ 238000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 239000004000.  Starting simulation...
+info: Entering event queue @ 239000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 240000004000.  Starting simulation...
+info: Entering event queue @ 240000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 241000004000.  Starting simulation...
+info: Entering event queue @ 241000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 242000004000.  Starting simulation...
+info: Entering event queue @ 242000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 243000004000.  Starting simulation...
+info: Entering event queue @ 243000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 244000004000.  Starting simulation...
+info: Entering event queue @ 244000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 245000004000.  Starting simulation...
+info: Entering event queue @ 245000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 246000004000.  Starting simulation...
+info: Entering event queue @ 246000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 247000004000.  Starting simulation...
+info: Entering event queue @ 247000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 248000004000.  Starting simulation...
+info: Entering event queue @ 248000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 249000004000.  Starting simulation...
+info: Entering event queue @ 249000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 250000004000.  Starting simulation...
+info: Entering event queue @ 250000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 251000004000.  Starting simulation...
+info: Entering event queue @ 251000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 252000004000.  Starting simulation...
+info: Entering event queue @ 252000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 253000004000.  Starting simulation...
+info: Entering event queue @ 253000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 254000004000.  Starting simulation...
+info: Entering event queue @ 254000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 255000004000.  Starting simulation...
+info: Entering event queue @ 255000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 256000004000.  Starting simulation...
+info: Entering event queue @ 256000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 257000004000.  Starting simulation...
+info: Entering event queue @ 257000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 258000004000.  Starting simulation...
+info: Entering event queue @ 258000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 259000004000.  Starting simulation...
+info: Entering event queue @ 259000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 260000004000.  Starting simulation...
+info: Entering event queue @ 260000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 261000004000.  Starting simulation...
+info: Entering event queue @ 261000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 262000004000.  Starting simulation...
+info: Entering event queue @ 262000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 263000004000.  Starting simulation...
+info: Entering event queue @ 263000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 264000004000.  Starting simulation...
+info: Entering event queue @ 264000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 265000004000.  Starting simulation...
+info: Entering event queue @ 265000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 266000004000.  Starting simulation...
+info: Entering event queue @ 266000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 267000004000.  Starting simulation...
+info: Entering event queue @ 267000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 268000004000.  Starting simulation...
+info: Entering event queue @ 268000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 269000004000.  Starting simulation...
+info: Entering event queue @ 269000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 270000004000.  Starting simulation...
+info: Entering event queue @ 270000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 271000004000.  Starting simulation...
+info: Entering event queue @ 271000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 272000004000.  Starting simulation...
+info: Entering event queue @ 272000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 273000004000.  Starting simulation...
+info: Entering event queue @ 273000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 274000004000.  Starting simulation...
+info: Entering event queue @ 274000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 275000004000.  Starting simulation...
+info: Entering event queue @ 275000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 276000004000.  Starting simulation...
+info: Entering event queue @ 276000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 277000004000.  Starting simulation...
+info: Entering event queue @ 277000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 278000004000.  Starting simulation...
+info: Entering event queue @ 278000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 279000004000.  Starting simulation...
+info: Entering event queue @ 279000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 280000004000.  Starting simulation...
+info: Entering event queue @ 280000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 281000004000.  Starting simulation...
+info: Entering event queue @ 281000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 282000004000.  Starting simulation...
+info: Entering event queue @ 282000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 283000004000.  Starting simulation...
+info: Entering event queue @ 283000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 284000004000.  Starting simulation...
+info: Entering event queue @ 284000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 285000004000.  Starting simulation...
+info: Entering event queue @ 285000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 286000004000.  Starting simulation...
+info: Entering event queue @ 286000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 287000004000.  Starting simulation...
+info: Entering event queue @ 287000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 288000004000.  Starting simulation...
+info: Entering event queue @ 288000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 289000004000.  Starting simulation...
+info: Entering event queue @ 289000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 290000004000.  Starting simulation...
+info: Entering event queue @ 290000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 291000004000.  Starting simulation...
+info: Entering event queue @ 291000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 292000004000.  Starting simulation...
+info: Entering event queue @ 292000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 293000004000.  Starting simulation...
+info: Entering event queue @ 293000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 294000004000.  Starting simulation...
+info: Entering event queue @ 294000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 295000004000.  Starting simulation...
+info: Entering event queue @ 295000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 296000004000.  Starting simulation...
+info: Entering event queue @ 296000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 297000004000.  Starting simulation...
+info: Entering event queue @ 297000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 298000004000.  Starting simulation...
+info: Entering event queue @ 298000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 299000004000.  Starting simulation...
+info: Entering event queue @ 299000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 300000004000.  Starting simulation...
+info: Entering event queue @ 300000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 301000004000.  Starting simulation...
+info: Entering event queue @ 301000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 302000004000.  Starting simulation...
+info: Entering event queue @ 302000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 303000004000.  Starting simulation...
+info: Entering event queue @ 303000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 304000004000.  Starting simulation...
+info: Entering event queue @ 304000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 305000004000.  Starting simulation...
+info: Entering event queue @ 305000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 306000004000.  Starting simulation...
+info: Entering event queue @ 306000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 307000004000.  Starting simulation...
+info: Entering event queue @ 307000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 308000004000.  Starting simulation...
+info: Entering event queue @ 308000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 309000004000.  Starting simulation...
+info: Entering event queue @ 309000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 310000004000.  Starting simulation...
+info: Entering event queue @ 310000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 311000004000.  Starting simulation...
+info: Entering event queue @ 311000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 312000004000.  Starting simulation...
+info: Entering event queue @ 312000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 313000004000.  Starting simulation...
+info: Entering event queue @ 313000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 314000004000.  Starting simulation...
+info: Entering event queue @ 314000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 315000004000.  Starting simulation...
+info: Entering event queue @ 315000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 316000004000.  Starting simulation...
+info: Entering event queue @ 316000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 317000004000.  Starting simulation...
+info: Entering event queue @ 317000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 318000004000.  Starting simulation...
+info: Entering event queue @ 318000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 319000004000.  Starting simulation...
+info: Entering event queue @ 319000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 320000004000.  Starting simulation...
+info: Entering event queue @ 320000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 321000004000.  Starting simulation...
+info: Entering event queue @ 321000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 322000004000.  Starting simulation...
+info: Entering event queue @ 322000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 323000004000.  Starting simulation...
+info: Entering event queue @ 323000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 324000004000.  Starting simulation...
+info: Entering event queue @ 324000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 325000004000.  Starting simulation...
+info: Entering event queue @ 325000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 326000004000.  Starting simulation...
+info: Entering event queue @ 326000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 327000004000.  Starting simulation...
+info: Entering event queue @ 327000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 328000004000.  Starting simulation...
+info: Entering event queue @ 328000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 329000004000.  Starting simulation...
+info: Entering event queue @ 329000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 330000004000.  Starting simulation...
+info: Entering event queue @ 330000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 331000004000.  Starting simulation...
+info: Entering event queue @ 331000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 332000004000.  Starting simulation...
+info: Entering event queue @ 332000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 333000004000.  Starting simulation...
+info: Entering event queue @ 333000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 334000004000.  Starting simulation...
+info: Entering event queue @ 334000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 335000004000.  Starting simulation...
+info: Entering event queue @ 335000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 336000004000.  Starting simulation...
+info: Entering event queue @ 336000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 337000004000.  Starting simulation...
+info: Entering event queue @ 337000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 338000004000.  Starting simulation...
+info: Entering event queue @ 338000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 339000004000.  Starting simulation...
+info: Entering event queue @ 339000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 340000004000.  Starting simulation...
+info: Entering event queue @ 340000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 341000004000.  Starting simulation...
+info: Entering event queue @ 341000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 342000004000.  Starting simulation...
+info: Entering event queue @ 342000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 343000004000.  Starting simulation...
+info: Entering event queue @ 343000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 344000004000.  Starting simulation...
+info: Entering event queue @ 344000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 345000004000.  Starting simulation...
+info: Entering event queue @ 345000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 346000004000.  Starting simulation...
+info: Entering event queue @ 346000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 347000004000.  Starting simulation...
+info: Entering event queue @ 347000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 348000004000.  Starting simulation...
+info: Entering event queue @ 348000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 349000004000.  Starting simulation...
+info: Entering event queue @ 349000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 350000004000.  Starting simulation...
+info: Entering event queue @ 350000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 351000004000.  Starting simulation...
+info: Entering event queue @ 351000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 352000004000.  Starting simulation...
+info: Entering event queue @ 352000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 353000004000.  Starting simulation...
+info: Entering event queue @ 353000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 354000004000.  Starting simulation...
+info: Entering event queue @ 354000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 355000004000.  Starting simulation...
+info: Entering event queue @ 355000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 356000004000.  Starting simulation...
+info: Entering event queue @ 356000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 357000004000.  Starting simulation...
+info: Entering event queue @ 357000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 358000004000.  Starting simulation...
+info: Entering event queue @ 358000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 359000004000.  Starting simulation...
+info: Entering event queue @ 359000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 360000004000.  Starting simulation...
+info: Entering event queue @ 360000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 361000004000.  Starting simulation...
+info: Entering event queue @ 361000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 362000004000.  Starting simulation...
+info: Entering event queue @ 362000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 363000004000.  Starting simulation...
+info: Entering event queue @ 363000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 364000004000.  Starting simulation...
+info: Entering event queue @ 364000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 365000004000.  Starting simulation...
+info: Entering event queue @ 365000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 366000004000.  Starting simulation...
+info: Entering event queue @ 366000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 367000004000.  Starting simulation...
+info: Entering event queue @ 367000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 368000004000.  Starting simulation...
+info: Entering event queue @ 368000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 369000004000.  Starting simulation...
+info: Entering event queue @ 369000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 370000004000.  Starting simulation...
+info: Entering event queue @ 370000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 371000004000.  Starting simulation...
+info: Entering event queue @ 371000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 372000004000.  Starting simulation...
+info: Entering event queue @ 372000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 373000004000.  Starting simulation...
+info: Entering event queue @ 373000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 374000004000.  Starting simulation...
+info: Entering event queue @ 374000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 375000004000.  Starting simulation...
+info: Entering event queue @ 375000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 376000004000.  Starting simulation...
+info: Entering event queue @ 376000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 377000004000.  Starting simulation...
+info: Entering event queue @ 377000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 378000004000.  Starting simulation...
+info: Entering event queue @ 378000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 379000004000.  Starting simulation...
+info: Entering event queue @ 379000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 380000004000.  Starting simulation...
+info: Entering event queue @ 380000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 381000004000.  Starting simulation...
+info: Entering event queue @ 381000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 382000004000.  Starting simulation...
+info: Entering event queue @ 382000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 383000004000.  Starting simulation...
+info: Entering event queue @ 383000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 384000004000.  Starting simulation...
+info: Entering event queue @ 384000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 385000004000.  Starting simulation...
+info: Entering event queue @ 385000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 386000004000.  Starting simulation...
+info: Entering event queue @ 386000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 387000004000.  Starting simulation...
+info: Entering event queue @ 387000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 388000004000.  Starting simulation...
+info: Entering event queue @ 388000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 389000004000.  Starting simulation...
+info: Entering event queue @ 389000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 390000004000.  Starting simulation...
+info: Entering event queue @ 390000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 391000004000.  Starting simulation...
+info: Entering event queue @ 391000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 392000004000.  Starting simulation...
+info: Entering event queue @ 392000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 393000004000.  Starting simulation...
+info: Entering event queue @ 393000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 394000004000.  Starting simulation...
+info: Entering event queue @ 394000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 395000004000.  Starting simulation...
+info: Entering event queue @ 395000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 396000004000.  Starting simulation...
+info: Entering event queue @ 396000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 397000004000.  Starting simulation...
+info: Entering event queue @ 397000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 398000004000.  Starting simulation...
+info: Entering event queue @ 398000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 399000004000.  Starting simulation...
+info: Entering event queue @ 399000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 400000004000.  Starting simulation...
+info: Entering event queue @ 400000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 401000004000.  Starting simulation...
+info: Entering event queue @ 401000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 402000004000.  Starting simulation...
+info: Entering event queue @ 402000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 403000004000.  Starting simulation...
+info: Entering event queue @ 403000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 404000004000.  Starting simulation...
+info: Entering event queue @ 404000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 405000004000.  Starting simulation...
+info: Entering event queue @ 405000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 406000004000.  Starting simulation...
+info: Entering event queue @ 406000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 407000004000.  Starting simulation...
+info: Entering event queue @ 407000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 408000004000.  Starting simulation...
+info: Entering event queue @ 408000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 409000004000.  Starting simulation...
+info: Entering event queue @ 409000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 410000004000.  Starting simulation...
+info: Entering event queue @ 410000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 411000004000.  Starting simulation...
+info: Entering event queue @ 411000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 412000004000.  Starting simulation...
+info: Entering event queue @ 412000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 413000004000.  Starting simulation...
+info: Entering event queue @ 413000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 414000004000.  Starting simulation...
+info: Entering event queue @ 414000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 415000004000.  Starting simulation...
+info: Entering event queue @ 415000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 416000004000.  Starting simulation...
+info: Entering event queue @ 416000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 417000004000.  Starting simulation...
+info: Entering event queue @ 417000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 418000004000.  Starting simulation...
+info: Entering event queue @ 418000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 419000004000.  Starting simulation...
+info: Entering event queue @ 419000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 420000004000.  Starting simulation...
+info: Entering event queue @ 420000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 421000004000.  Starting simulation...
+info: Entering event queue @ 421000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 422000004000.  Starting simulation...
+info: Entering event queue @ 422000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 423000004000.  Starting simulation...
+info: Entering event queue @ 423000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 424000004000.  Starting simulation...
+info: Entering event queue @ 424000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 425000004000.  Starting simulation...
+info: Entering event queue @ 425000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 426000004000.  Starting simulation...
+info: Entering event queue @ 426000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 427000004000.  Starting simulation...
+info: Entering event queue @ 427000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 428000004000.  Starting simulation...
+info: Entering event queue @ 428000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 429000004000.  Starting simulation...
+info: Entering event queue @ 429000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 430000004000.  Starting simulation...
+info: Entering event queue @ 430000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 431000004000.  Starting simulation...
+info: Entering event queue @ 431000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 432000004000.  Starting simulation...
+info: Entering event queue @ 432000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 433000004000.  Starting simulation...
+info: Entering event queue @ 433000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 434000004000.  Starting simulation...
+info: Entering event queue @ 434000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 435000004000.  Starting simulation...
+info: Entering event queue @ 435000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 436000004000.  Starting simulation...
+info: Entering event queue @ 436000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 437000004000.  Starting simulation...
+info: Entering event queue @ 437000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 438000004000.  Starting simulation...
+info: Entering event queue @ 438000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 439000004000.  Starting simulation...
+info: Entering event queue @ 439000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 440000004000.  Starting simulation...
+info: Entering event queue @ 440000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 441000004000.  Starting simulation...
+info: Entering event queue @ 441000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 442000004000.  Starting simulation...
+info: Entering event queue @ 442000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 443000004000.  Starting simulation...
+info: Entering event queue @ 443000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 444000004000.  Starting simulation...
+info: Entering event queue @ 444000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 445000004000.  Starting simulation...
+info: Entering event queue @ 445000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 446000004000.  Starting simulation...
+info: Entering event queue @ 446000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 447000004000.  Starting simulation...
+info: Entering event queue @ 447000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 448000004000.  Starting simulation...
+info: Entering event queue @ 448000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 449000004000.  Starting simulation...
+info: Entering event queue @ 449000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 450000004000.  Starting simulation...
+info: Entering event queue @ 450000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 451000004000.  Starting simulation...
+info: Entering event queue @ 451000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 452000004000.  Starting simulation...
+info: Entering event queue @ 452000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 453000004000.  Starting simulation...
+info: Entering event queue @ 453000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 454000004000.  Starting simulation...
+info: Entering event queue @ 454000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 455000004000.  Starting simulation...
+info: Entering event queue @ 455000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 456000004000.  Starting simulation...
+info: Entering event queue @ 456000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 457000004000.  Starting simulation...
+info: Entering event queue @ 457000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 458000004000.  Starting simulation...
+info: Entering event queue @ 458000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 459000004000.  Starting simulation...
+info: Entering event queue @ 459000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 460000004000.  Starting simulation...
+info: Entering event queue @ 460000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 461000004000.  Starting simulation...
+info: Entering event queue @ 461000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 462000004000.  Starting simulation...
+info: Entering event queue @ 462000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 463000004000.  Starting simulation...
+info: Entering event queue @ 463000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 464000004000.  Starting simulation...
+info: Entering event queue @ 464000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 465000004000.  Starting simulation...
+info: Entering event queue @ 465000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 466000004000.  Starting simulation...
+info: Entering event queue @ 466000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 467000004000.  Starting simulation...
+info: Entering event queue @ 467000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 468000004000.  Starting simulation...
+info: Entering event queue @ 468000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 469000004000.  Starting simulation...
+info: Entering event queue @ 469000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 470000004000.  Starting simulation...
+info: Entering event queue @ 470000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 471000004000.  Starting simulation...
+info: Entering event queue @ 471000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 472000004000.  Starting simulation...
+info: Entering event queue @ 472000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 473000004000.  Starting simulation...
+info: Entering event queue @ 473000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 474000004000.  Starting simulation...
+info: Entering event queue @ 474000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 475000004000.  Starting simulation...
+info: Entering event queue @ 475000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 476000004000.  Starting simulation...
+info: Entering event queue @ 476000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 477000004000.  Starting simulation...
+info: Entering event queue @ 477000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 478000004000.  Starting simulation...
+info: Entering event queue @ 478000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 479000004000.  Starting simulation...
+info: Entering event queue @ 479000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 480000004000.  Starting simulation...
+info: Entering event queue @ 480000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 481000004000.  Starting simulation...
+info: Entering event queue @ 481000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 482000004000.  Starting simulation...
+info: Entering event queue @ 482000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 483000004000.  Starting simulation...
+info: Entering event queue @ 483000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 484000004000.  Starting simulation...
+info: Entering event queue @ 484000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 485000004000.  Starting simulation...
+info: Entering event queue @ 485000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 486000004000.  Starting simulation...
+info: Entering event queue @ 486000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 487000004000.  Starting simulation...
+info: Entering event queue @ 487000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 488000004000.  Starting simulation...
+info: Entering event queue @ 488000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 489000004000.  Starting simulation...
+info: Entering event queue @ 489000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 490000004000.  Starting simulation...
+info: Entering event queue @ 490000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 491000004000.  Starting simulation...
+info: Entering event queue @ 491000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 492000004000.  Starting simulation...
+info: Entering event queue @ 492000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 493000004000.  Starting simulation...
+info: Entering event queue @ 493000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 494000004000.  Starting simulation...
+info: Entering event queue @ 494000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 495000004000.  Starting simulation...
+info: Entering event queue @ 495000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 496000004000.  Starting simulation...
+info: Entering event queue @ 496000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 497000004000.  Starting simulation...
+info: Entering event queue @ 497000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 498000004000.  Starting simulation...
+info: Entering event queue @ 498000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 499000004000.  Starting simulation...
+info: Entering event queue @ 499000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 500000004000.  Starting simulation...
+info: Entering event queue @ 500000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 501000004000.  Starting simulation...
+info: Entering event queue @ 501000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 502000004000.  Starting simulation...
+info: Entering event queue @ 502000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 503000004000.  Starting simulation...
+info: Entering event queue @ 503000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 504000004000.  Starting simulation...
+info: Entering event queue @ 504000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 505000004000.  Starting simulation...
+info: Entering event queue @ 505000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 506000004000.  Starting simulation...
+info: Entering event queue @ 506000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 507000004000.  Starting simulation...
+info: Entering event queue @ 507000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 508000004000.  Starting simulation...
+info: Entering event queue @ 508000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 509000004000.  Starting simulation...
+info: Entering event queue @ 509000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 510000004000.  Starting simulation...
+info: Entering event queue @ 510000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 511000004000.  Starting simulation...
+info: Entering event queue @ 511000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 512000004000.  Starting simulation...
+info: Entering event queue @ 512000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 513000004000.  Starting simulation...
+info: Entering event queue @ 513000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 514000004000.  Starting simulation...
+info: Entering event queue @ 514000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 515000004000.  Starting simulation...
+info: Entering event queue @ 515000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 516000004000.  Starting simulation...
+info: Entering event queue @ 516000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 517000004000.  Starting simulation...
+info: Entering event queue @ 517000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 518000004000.  Starting simulation...
+info: Entering event queue @ 518000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 519000004000.  Starting simulation...
+info: Entering event queue @ 519000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 520000004000.  Starting simulation...
+info: Entering event queue @ 520000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 521000004000.  Starting simulation...
+info: Entering event queue @ 521000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 522000004000.  Starting simulation...
+info: Entering event queue @ 522000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 523000004000.  Starting simulation...
+info: Entering event queue @ 523000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 524000004000.  Starting simulation...
+info: Entering event queue @ 524000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 525000004000.  Starting simulation...
+info: Entering event queue @ 525000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 526000004000.  Starting simulation...
+info: Entering event queue @ 526000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 527000004000.  Starting simulation...
+info: Entering event queue @ 527000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 528000004000.  Starting simulation...
+info: Entering event queue @ 528000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 529000004000.  Starting simulation...
+info: Entering event queue @ 529000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 530000004000.  Starting simulation...
+info: Entering event queue @ 530000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 531000004000.  Starting simulation...
+info: Entering event queue @ 531000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 532000004000.  Starting simulation...
+info: Entering event queue @ 532000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 533000004000.  Starting simulation...
+info: Entering event queue @ 533000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 534000004000.  Starting simulation...
+info: Entering event queue @ 534000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 535000004000.  Starting simulation...
+info: Entering event queue @ 535000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 536000004000.  Starting simulation...
+info: Entering event queue @ 536000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 537000004000.  Starting simulation...
+info: Entering event queue @ 537000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 538000004000.  Starting simulation...
+info: Entering event queue @ 538000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 539000004000.  Starting simulation...
+info: Entering event queue @ 539000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 540000004000.  Starting simulation...
+info: Entering event queue @ 540000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 541000004000.  Starting simulation...
+info: Entering event queue @ 541000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 542000004000.  Starting simulation...
+info: Entering event queue @ 542000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 543000004000.  Starting simulation...
+info: Entering event queue @ 543000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 544000004000.  Starting simulation...
+info: Entering event queue @ 544000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 545000004000.  Starting simulation...
+info: Entering event queue @ 545000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 546000004000.  Starting simulation...
+info: Entering event queue @ 546000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 547000004000.  Starting simulation...
+info: Entering event queue @ 547000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 548000004000.  Starting simulation...
+info: Entering event queue @ 548000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 549000004000.  Starting simulation...
+info: Entering event queue @ 549000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 550000004000.  Starting simulation...
+info: Entering event queue @ 550000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 551000004000.  Starting simulation...
+info: Entering event queue @ 551000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 552000004000.  Starting simulation...
+info: Entering event queue @ 552000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 553000004000.  Starting simulation...
+info: Entering event queue @ 553000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 554000004000.  Starting simulation...
+info: Entering event queue @ 554000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 555000004000.  Starting simulation...
+info: Entering event queue @ 555000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 556000004000.  Starting simulation...
+info: Entering event queue @ 556000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 557000004000.  Starting simulation...
+info: Entering event queue @ 557000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 558000004000.  Starting simulation...
+info: Entering event queue @ 558000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 559000004000.  Starting simulation...
+info: Entering event queue @ 559000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 560000004000.  Starting simulation...
+info: Entering event queue @ 560000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 561000004000.  Starting simulation...
+info: Entering event queue @ 561000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 562000004000.  Starting simulation...
+info: Entering event queue @ 562000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 563000004000.  Starting simulation...
+info: Entering event queue @ 563000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 564000004000.  Starting simulation...
+info: Entering event queue @ 564000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 565000004000.  Starting simulation...
+info: Entering event queue @ 565000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 566000004000.  Starting simulation...
+info: Entering event queue @ 566000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 567000004000.  Starting simulation...
+info: Entering event queue @ 567000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 568000004000.  Starting simulation...
+info: Entering event queue @ 568000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 569000004000.  Starting simulation...
+info: Entering event queue @ 569000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 570000004000.  Starting simulation...
+info: Entering event queue @ 570000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 571000004000.  Starting simulation...
+info: Entering event queue @ 571000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 572000004000.  Starting simulation...
+info: Entering event queue @ 572000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 573000004000.  Starting simulation...
+info: Entering event queue @ 573000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 574000004000.  Starting simulation...
+info: Entering event queue @ 574000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 575000004000.  Starting simulation...
+info: Entering event queue @ 575000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 576000004000.  Starting simulation...
+info: Entering event queue @ 576000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 577000004000.  Starting simulation...
+info: Entering event queue @ 577000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 578000004000.  Starting simulation...
+info: Entering event queue @ 578000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 579000004000.  Starting simulation...
+info: Entering event queue @ 579000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 580000004000.  Starting simulation...
+info: Entering event queue @ 580000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 581000004000.  Starting simulation...
+info: Entering event queue @ 581000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 582000004000.  Starting simulation...
+info: Entering event queue @ 582000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 583000004000.  Starting simulation...
+info: Entering event queue @ 583000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 584000004000.  Starting simulation...
+info: Entering event queue @ 584000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 585000004000.  Starting simulation...
+info: Entering event queue @ 585000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 586000004000.  Starting simulation...
+info: Entering event queue @ 586000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 587000004000.  Starting simulation...
+info: Entering event queue @ 587000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 588000004000.  Starting simulation...
+info: Entering event queue @ 588000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 589000004000.  Starting simulation...
+info: Entering event queue @ 589000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 590000004000.  Starting simulation...
+info: Entering event queue @ 590000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 591000004000.  Starting simulation...
+info: Entering event queue @ 591000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 592000004000.  Starting simulation...
+info: Entering event queue @ 592000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 593000004000.  Starting simulation...
+info: Entering event queue @ 593000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 594000004000.  Starting simulation...
+info: Entering event queue @ 594000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 595000004000.  Starting simulation...
+info: Entering event queue @ 595000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 596000004000.  Starting simulation...
+info: Entering event queue @ 596000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 597000004000.  Starting simulation...
+info: Entering event queue @ 597000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 598000004000.  Starting simulation...
+info: Entering event queue @ 598000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 599000004000.  Starting simulation...
+info: Entering event queue @ 599000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 600000004000.  Starting simulation...
+info: Entering event queue @ 600000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 601000004000.  Starting simulation...
+info: Entering event queue @ 601000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 602000004000.  Starting simulation...
+info: Entering event queue @ 602000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 603000004000.  Starting simulation...
+info: Entering event queue @ 603000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 604000004000.  Starting simulation...
+info: Entering event queue @ 604000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 605000004000.  Starting simulation...
+info: Entering event queue @ 605000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 606000004000.  Starting simulation...
+info: Entering event queue @ 606000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 607000004000.  Starting simulation...
+info: Entering event queue @ 607000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 608000004000.  Starting simulation...
+info: Entering event queue @ 608000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 609000004000.  Starting simulation...
+info: Entering event queue @ 609000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 610000004000.  Starting simulation...
+info: Entering event queue @ 610000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 611000004000.  Starting simulation...
+info: Entering event queue @ 611000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 612000004000.  Starting simulation...
+info: Entering event queue @ 612000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 613000004000.  Starting simulation...
+info: Entering event queue @ 613000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 614000004000.  Starting simulation...
+info: Entering event queue @ 614000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 615000004000.  Starting simulation...
+info: Entering event queue @ 615000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 616000004000.  Starting simulation...
+info: Entering event queue @ 616000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 617000004000.  Starting simulation...
+info: Entering event queue @ 617000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 618000004000.  Starting simulation...
+info: Entering event queue @ 618000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 619000004000.  Starting simulation...
+info: Entering event queue @ 619000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 620000004000.  Starting simulation...
+info: Entering event queue @ 620000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 621000004000.  Starting simulation...
+info: Entering event queue @ 621000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 622000004000.  Starting simulation...
+info: Entering event queue @ 622000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 623000004000.  Starting simulation...
+info: Entering event queue @ 623000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 624000004000.  Starting simulation...
+info: Entering event queue @ 624000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 625000004000.  Starting simulation...
+info: Entering event queue @ 625000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 626000004000.  Starting simulation...
+info: Entering event queue @ 626000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 627000004000.  Starting simulation...
+info: Entering event queue @ 627000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 628000004000.  Starting simulation...
+info: Entering event queue @ 628000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 629000004000.  Starting simulation...
+info: Entering event queue @ 629000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 630000004000.  Starting simulation...
+info: Entering event queue @ 630000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 631000004000.  Starting simulation...
+info: Entering event queue @ 631000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 632000004000.  Starting simulation...
+info: Entering event queue @ 632000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 633000004000.  Starting simulation...
+info: Entering event queue @ 633000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 634000004000.  Starting simulation...
+info: Entering event queue @ 634000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 635000004000.  Starting simulation...
+info: Entering event queue @ 635000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 636000004000.  Starting simulation...
+info: Entering event queue @ 636000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 637000004000.  Starting simulation...
+info: Entering event queue @ 637000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 638000004000.  Starting simulation...
+info: Entering event queue @ 638000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 639000004000.  Starting simulation...
+info: Entering event queue @ 639000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 640000004000.  Starting simulation...
+info: Entering event queue @ 640000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 641000004000.  Starting simulation...
+info: Entering event queue @ 641000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 642000004000.  Starting simulation...
+info: Entering event queue @ 642000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 643000004000.  Starting simulation...
+info: Entering event queue @ 643000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 644000004000.  Starting simulation...
+info: Entering event queue @ 644000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 645000004000.  Starting simulation...
+info: Entering event queue @ 645000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 646000004000.  Starting simulation...
+info: Entering event queue @ 646000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 647000004000.  Starting simulation...
+info: Entering event queue @ 647000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 648000004000.  Starting simulation...
+info: Entering event queue @ 648000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 649000004000.  Starting simulation...
+info: Entering event queue @ 649000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 650000004000.  Starting simulation...
+info: Entering event queue @ 650000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 651000004000.  Starting simulation...
+info: Entering event queue @ 651000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 652000004000.  Starting simulation...
+info: Entering event queue @ 652000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 653000004000.  Starting simulation...
+info: Entering event queue @ 653000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 654000004000.  Starting simulation...
+info: Entering event queue @ 654000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 655000004000.  Starting simulation...
+info: Entering event queue @ 655000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 656000004000.  Starting simulation...
+info: Entering event queue @ 656000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 657000004000.  Starting simulation...
+info: Entering event queue @ 657000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 658000004000.  Starting simulation...
+info: Entering event queue @ 658000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 659000004000.  Starting simulation...
+info: Entering event queue @ 659000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 660000004000.  Starting simulation...
+info: Entering event queue @ 660000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 661000004000.  Starting simulation...
+info: Entering event queue @ 661000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 662000004000.  Starting simulation...
+info: Entering event queue @ 662000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 663000004000.  Starting simulation...
+info: Entering event queue @ 663000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 664000004000.  Starting simulation...
+info: Entering event queue @ 664000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 665000004000.  Starting simulation...
+info: Entering event queue @ 665000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 666000004000.  Starting simulation...
+info: Entering event queue @ 666000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 667000004000.  Starting simulation...
+info: Entering event queue @ 667000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 668000004000.  Starting simulation...
+info: Entering event queue @ 668000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 669000004000.  Starting simulation...
+info: Entering event queue @ 669000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 670000004000.  Starting simulation...
+info: Entering event queue @ 670000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 671000004000.  Starting simulation...
+info: Entering event queue @ 671000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 672000004000.  Starting simulation...
+info: Entering event queue @ 672000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 673000004000.  Starting simulation...
+info: Entering event queue @ 673000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 674000004000.  Starting simulation...
+info: Entering event queue @ 674000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 675000004000.  Starting simulation...
+info: Entering event queue @ 675000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 676000004000.  Starting simulation...
+info: Entering event queue @ 676000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 677000004000.  Starting simulation...
+info: Entering event queue @ 677000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 678000004000.  Starting simulation...
+info: Entering event queue @ 678000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 679000004000.  Starting simulation...
+info: Entering event queue @ 679000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 680000004000.  Starting simulation...
+info: Entering event queue @ 680000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 681000004000.  Starting simulation...
+info: Entering event queue @ 681000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 682000004000.  Starting simulation...
+info: Entering event queue @ 682000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 683000004000.  Starting simulation...
+info: Entering event queue @ 683000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 684000004000.  Starting simulation...
+info: Entering event queue @ 684000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 685000004000.  Starting simulation...
+info: Entering event queue @ 685000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 686000004000.  Starting simulation...
+info: Entering event queue @ 686000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 687000004000.  Starting simulation...
+info: Entering event queue @ 687000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 688000004000.  Starting simulation...
+info: Entering event queue @ 688000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 689000004000.  Starting simulation...
+info: Entering event queue @ 689000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 690000004000.  Starting simulation...
+info: Entering event queue @ 690000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 691000004000.  Starting simulation...
+info: Entering event queue @ 691000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 692000004000.  Starting simulation...
+info: Entering event queue @ 692000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 693000004000.  Starting simulation...
+info: Entering event queue @ 693000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 694000004000.  Starting simulation...
+info: Entering event queue @ 694000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 695000004000.  Starting simulation...
+info: Entering event queue @ 695000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 696000004000.  Starting simulation...
+info: Entering event queue @ 696000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 697000004000.  Starting simulation...
+info: Entering event queue @ 697000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 698000004000.  Starting simulation...
+info: Entering event queue @ 698000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 699000004000.  Starting simulation...
+info: Entering event queue @ 699000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 700000004000.  Starting simulation...
+info: Entering event queue @ 700000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 701000004000.  Starting simulation...
+info: Entering event queue @ 701000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 702000004000.  Starting simulation...
+info: Entering event queue @ 702000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 703000004000.  Starting simulation...
+info: Entering event queue @ 703000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 704000004000.  Starting simulation...
+info: Entering event queue @ 704000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 705000004000.  Starting simulation...
+info: Entering event queue @ 705000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 706000004000.  Starting simulation...
+info: Entering event queue @ 706000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 707000004000.  Starting simulation...
+info: Entering event queue @ 707000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 708000004000.  Starting simulation...
+info: Entering event queue @ 708000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 709000004000.  Starting simulation...
+info: Entering event queue @ 709000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 710000004000.  Starting simulation...
+info: Entering event queue @ 710000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 711000004000.  Starting simulation...
+info: Entering event queue @ 711000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 712000004000.  Starting simulation...
+info: Entering event queue @ 712000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 713000004000.  Starting simulation...
+info: Entering event queue @ 713000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 714000004000.  Starting simulation...
+info: Entering event queue @ 714000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 715000004000.  Starting simulation...
+info: Entering event queue @ 715000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 716000004000.  Starting simulation...
+info: Entering event queue @ 716000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 717000004000.  Starting simulation...
+info: Entering event queue @ 717000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 718000004000.  Starting simulation...
+info: Entering event queue @ 718000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 719000004000.  Starting simulation...
+info: Entering event queue @ 719000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 720000004000.  Starting simulation...
+info: Entering event queue @ 720000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 721000004000.  Starting simulation...
+info: Entering event queue @ 721000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 722000004000.  Starting simulation...
+info: Entering event queue @ 722000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 723000004000.  Starting simulation...
+info: Entering event queue @ 723000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 724000004000.  Starting simulation...
+info: Entering event queue @ 724000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 725000004000.  Starting simulation...
+info: Entering event queue @ 725000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 726000004000.  Starting simulation...
+info: Entering event queue @ 726000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 727000004000.  Starting simulation...
+info: Entering event queue @ 727000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 728000004000.  Starting simulation...
+info: Entering event queue @ 728000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 729000004000.  Starting simulation...
+info: Entering event queue @ 729000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 730000004000.  Starting simulation...
+info: Entering event queue @ 730000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 731000004000.  Starting simulation...
+info: Entering event queue @ 731000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 732000004000.  Starting simulation...
+info: Entering event queue @ 732000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 733000004000.  Starting simulation...
+info: Entering event queue @ 733000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 734000004000.  Starting simulation...
+info: Entering event queue @ 734000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 735000004000.  Starting simulation...
+info: Entering event queue @ 735000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 736000004000.  Starting simulation...
+info: Entering event queue @ 736000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 737000004000.  Starting simulation...
+info: Entering event queue @ 737000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 738000004000.  Starting simulation...
+info: Entering event queue @ 738000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 739000004000.  Starting simulation...
+info: Entering event queue @ 739000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 740000004000.  Starting simulation...
+info: Entering event queue @ 740000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 741000004000.  Starting simulation...
+info: Entering event queue @ 741000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 742000004000.  Starting simulation...
+info: Entering event queue @ 742000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 743000004000.  Starting simulation...
+info: Entering event queue @ 743000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 744000004000.  Starting simulation...
+info: Entering event queue @ 744000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 745000004000.  Starting simulation...
+info: Entering event queue @ 745000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 746000004000.  Starting simulation...
+info: Entering event queue @ 746000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 747000004000.  Starting simulation...
+info: Entering event queue @ 747000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 748000004000.  Starting simulation...
+info: Entering event queue @ 748000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 749000004000.  Starting simulation...
+info: Entering event queue @ 749000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 750000004000.  Starting simulation...
+info: Entering event queue @ 750000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 751000004000.  Starting simulation...
+info: Entering event queue @ 751000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 752000004000.  Starting simulation...
+info: Entering event queue @ 752000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 753000004000.  Starting simulation...
+info: Entering event queue @ 753000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 754000004000.  Starting simulation...
+info: Entering event queue @ 754000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 755000004000.  Starting simulation...
+info: Entering event queue @ 755000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 756000004000.  Starting simulation...
+info: Entering event queue @ 756000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 757000004000.  Starting simulation...
+info: Entering event queue @ 757000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 758000004000.  Starting simulation...
+info: Entering event queue @ 758000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 759000004000.  Starting simulation...
+info: Entering event queue @ 759000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 760000004000.  Starting simulation...
+info: Entering event queue @ 760000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 761000004000.  Starting simulation...
+info: Entering event queue @ 761000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 762000004000.  Starting simulation...
+info: Entering event queue @ 762000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 763000004000.  Starting simulation...
+info: Entering event queue @ 763000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 764000004000.  Starting simulation...
+info: Entering event queue @ 764000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 765000004000.  Starting simulation...
+info: Entering event queue @ 765000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 766000004000.  Starting simulation...
+info: Entering event queue @ 766000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 767000004000.  Starting simulation...
+info: Entering event queue @ 767000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 768000004000.  Starting simulation...
+info: Entering event queue @ 768000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 769000004000.  Starting simulation...
+info: Entering event queue @ 769000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 770000004000.  Starting simulation...
+info: Entering event queue @ 770000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 771000004000.  Starting simulation...
+info: Entering event queue @ 771000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 772000004000.  Starting simulation...
+info: Entering event queue @ 772000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 773000004000.  Starting simulation...
+info: Entering event queue @ 773000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 774000004000.  Starting simulation...
+info: Entering event queue @ 774000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 775000004000.  Starting simulation...
+info: Entering event queue @ 775000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 776000004000.  Starting simulation...
+info: Entering event queue @ 776000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 777000004000.  Starting simulation...
+info: Entering event queue @ 777000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 778000004000.  Starting simulation...
+info: Entering event queue @ 778000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 779000004000.  Starting simulation...
+info: Entering event queue @ 779000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 780000004000.  Starting simulation...
+info: Entering event queue @ 780000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 781000004000.  Starting simulation...
+info: Entering event queue @ 781000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 782000004000.  Starting simulation...
+info: Entering event queue @ 782000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 783000004000.  Starting simulation...
+info: Entering event queue @ 783000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 784000004000.  Starting simulation...
+info: Entering event queue @ 784000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 785000004000.  Starting simulation...
+info: Entering event queue @ 785000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 786000004000.  Starting simulation...
+info: Entering event queue @ 786000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 787000004000.  Starting simulation...
+info: Entering event queue @ 787000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 788000004000.  Starting simulation...
+info: Entering event queue @ 788000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 789000004000.  Starting simulation...
+info: Entering event queue @ 789000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 790000004000.  Starting simulation...
+info: Entering event queue @ 790000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 791000004000.  Starting simulation...
+info: Entering event queue @ 791000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 792000004000.  Starting simulation...
+info: Entering event queue @ 792000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 793000004000.  Starting simulation...
+info: Entering event queue @ 793000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 794000004000.  Starting simulation...
+info: Entering event queue @ 794000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 795000004000.  Starting simulation...
+info: Entering event queue @ 795000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 796000004000.  Starting simulation...
+info: Entering event queue @ 796000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 797000004000.  Starting simulation...
+info: Entering event queue @ 797000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 798000004000.  Starting simulation...
+info: Entering event queue @ 798000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 799000004000.  Starting simulation...
+info: Entering event queue @ 799000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 800000004000.  Starting simulation...
+info: Entering event queue @ 800000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 801000004000.  Starting simulation...
+info: Entering event queue @ 801000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 802000004000.  Starting simulation...
+info: Entering event queue @ 802000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 803000004000.  Starting simulation...
+info: Entering event queue @ 803000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 804000004000.  Starting simulation...
+info: Entering event queue @ 804000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 805000004000.  Starting simulation...
+info: Entering event queue @ 805000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 806000004000.  Starting simulation...
+info: Entering event queue @ 806000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 807000004000.  Starting simulation...
+info: Entering event queue @ 807000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 808000004000.  Starting simulation...
+info: Entering event queue @ 808000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 809000004000.  Starting simulation...
+info: Entering event queue @ 809000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 810000004000.  Starting simulation...
+info: Entering event queue @ 810000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 811000004000.  Starting simulation...
+info: Entering event queue @ 811000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 812000004000.  Starting simulation...
+info: Entering event queue @ 812000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 813000004000.  Starting simulation...
+info: Entering event queue @ 813000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 814000004000.  Starting simulation...
+info: Entering event queue @ 814000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 815000004000.  Starting simulation...
+info: Entering event queue @ 815000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 816000004000.  Starting simulation...
+info: Entering event queue @ 816000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 817000004000.  Starting simulation...
+info: Entering event queue @ 817000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 818000004000.  Starting simulation...
+info: Entering event queue @ 818000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 819000004000.  Starting simulation...
+info: Entering event queue @ 819000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 820000004000.  Starting simulation...
+info: Entering event queue @ 820000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 821000004000.  Starting simulation...
+info: Entering event queue @ 821000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 822000004000.  Starting simulation...
+info: Entering event queue @ 822000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 823000004000.  Starting simulation...
+info: Entering event queue @ 823000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 824000004000.  Starting simulation...
+info: Entering event queue @ 824000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 825000004000.  Starting simulation...
+info: Entering event queue @ 825000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 826000004000.  Starting simulation...
+info: Entering event queue @ 826000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 827000004000.  Starting simulation...
+info: Entering event queue @ 827000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 828000004000.  Starting simulation...
+info: Entering event queue @ 828000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 829000004000.  Starting simulation...
+info: Entering event queue @ 829000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 830000004000.  Starting simulation...
+info: Entering event queue @ 830000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 831000004000.  Starting simulation...
+info: Entering event queue @ 831000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 832000004000.  Starting simulation...
+info: Entering event queue @ 832000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 833000004000.  Starting simulation...
+info: Entering event queue @ 833000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 834000004000.  Starting simulation...
+info: Entering event queue @ 834000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 835000004000.  Starting simulation...
+info: Entering event queue @ 835000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 836000004000.  Starting simulation...
+info: Entering event queue @ 836000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 837000004000.  Starting simulation...
+info: Entering event queue @ 837000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 838000004000.  Starting simulation...
+info: Entering event queue @ 838000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 839000004000.  Starting simulation...
+info: Entering event queue @ 839000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 840000004000.  Starting simulation...
+info: Entering event queue @ 840000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 841000004000.  Starting simulation...
+info: Entering event queue @ 841000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 842000004000.  Starting simulation...
+info: Entering event queue @ 842000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 843000004000.  Starting simulation...
+info: Entering event queue @ 843000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 844000004000.  Starting simulation...
+info: Entering event queue @ 844000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 845000004000.  Starting simulation...
+info: Entering event queue @ 845000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 846000004000.  Starting simulation...
+info: Entering event queue @ 846000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 847000004000.  Starting simulation...
+info: Entering event queue @ 847000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 848000004000.  Starting simulation...
+info: Entering event queue @ 848000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 849000004000.  Starting simulation...
+info: Entering event queue @ 849000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 850000004000.  Starting simulation...
+info: Entering event queue @ 850000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 851000004000.  Starting simulation...
+info: Entering event queue @ 851000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 852000004000.  Starting simulation...
+info: Entering event queue @ 852000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 853000004000.  Starting simulation...
+info: Entering event queue @ 853000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 854000004000.  Starting simulation...
+info: Entering event queue @ 854000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 855000004000.  Starting simulation...
+info: Entering event queue @ 855000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 856000004000.  Starting simulation...
+info: Entering event queue @ 856000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 857000004000.  Starting simulation...
+info: Entering event queue @ 857000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 858000004000.  Starting simulation...
+info: Entering event queue @ 858000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 859000004000.  Starting simulation...
+info: Entering event queue @ 859000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 860000004000.  Starting simulation...
+info: Entering event queue @ 860000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 861000004000.  Starting simulation...
+info: Entering event queue @ 861000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 862000004000.  Starting simulation...
+info: Entering event queue @ 862000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 863000004000.  Starting simulation...
+info: Entering event queue @ 863000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 864000004000.  Starting simulation...
+info: Entering event queue @ 864000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 865000004000.  Starting simulation...
+info: Entering event queue @ 865000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 866000004000.  Starting simulation...
+info: Entering event queue @ 866000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 867000004000.  Starting simulation...
+info: Entering event queue @ 867000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 868000004000.  Starting simulation...
+info: Entering event queue @ 868000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 869000004000.  Starting simulation...
+info: Entering event queue @ 869000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 870000004000.  Starting simulation...
+info: Entering event queue @ 870000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 871000004000.  Starting simulation...
+info: Entering event queue @ 871000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 872000004000.  Starting simulation...
+info: Entering event queue @ 872000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 873000004000.  Starting simulation...
+info: Entering event queue @ 873000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 874000004000.  Starting simulation...
+info: Entering event queue @ 874000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 875000004000.  Starting simulation...
+info: Entering event queue @ 875000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 876000004000.  Starting simulation...
+info: Entering event queue @ 876000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 877000004000.  Starting simulation...
+info: Entering event queue @ 877000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 878000004000.  Starting simulation...
+info: Entering event queue @ 878000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 879000004000.  Starting simulation...
+info: Entering event queue @ 879000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 880000004000.  Starting simulation...
+info: Entering event queue @ 880000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 881000004000.  Starting simulation...
+info: Entering event queue @ 881000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 882000004000.  Starting simulation...
+info: Entering event queue @ 882000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 883000004000.  Starting simulation...
+info: Entering event queue @ 883000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 884000004000.  Starting simulation...
+info: Entering event queue @ 884000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 885000004000.  Starting simulation...
+info: Entering event queue @ 885000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 886000004000.  Starting simulation...
+info: Entering event queue @ 886000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 887000004000.  Starting simulation...
+info: Entering event queue @ 887000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 888000004000.  Starting simulation...
+info: Entering event queue @ 888000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 889000004000.  Starting simulation...
+info: Entering event queue @ 889000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 890000004000.  Starting simulation...
+info: Entering event queue @ 890000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 891000004000.  Starting simulation...
+info: Entering event queue @ 891000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 892000004000.  Starting simulation...
+info: Entering event queue @ 892000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 893000004000.  Starting simulation...
+info: Entering event queue @ 893000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 894000004000.  Starting simulation...
+info: Entering event queue @ 894000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 895000004000.  Starting simulation...
+info: Entering event queue @ 895000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 896000004000.  Starting simulation...
+info: Entering event queue @ 896000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 897000004000.  Starting simulation...
+info: Entering event queue @ 897000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 898000004000.  Starting simulation...
+info: Entering event queue @ 898000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 899000004000.  Starting simulation...
+info: Entering event queue @ 899000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 900000004000.  Starting simulation...
+info: Entering event queue @ 900000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 901000004000.  Starting simulation...
+info: Entering event queue @ 901000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 902000004000.  Starting simulation...
+info: Entering event queue @ 902000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 903000004000.  Starting simulation...
+info: Entering event queue @ 903000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 904000004000.  Starting simulation...
+info: Entering event queue @ 904000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 905000004000.  Starting simulation...
+info: Entering event queue @ 905000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 906000004000.  Starting simulation...
+info: Entering event queue @ 906000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 907000004000.  Starting simulation...
+info: Entering event queue @ 907000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 908000004000.  Starting simulation...
+info: Entering event queue @ 908000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 909000004000.  Starting simulation...
+info: Entering event queue @ 909000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 910000004000.  Starting simulation...
+info: Entering event queue @ 910000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 911000004000.  Starting simulation...
+info: Entering event queue @ 911000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 912000004000.  Starting simulation...
+info: Entering event queue @ 912000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 913000004000.  Starting simulation...
+info: Entering event queue @ 913000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 914000004000.  Starting simulation...
+info: Entering event queue @ 914000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 915000004000.  Starting simulation...
+info: Entering event queue @ 915000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 916000004000.  Starting simulation...
+info: Entering event queue @ 916000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 917000004000.  Starting simulation...
+info: Entering event queue @ 917000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 918000004000.  Starting simulation...
+info: Entering event queue @ 918000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 919000004000.  Starting simulation...
+info: Entering event queue @ 919000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 920000004000.  Starting simulation...
+info: Entering event queue @ 920000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 921000004000.  Starting simulation...
+info: Entering event queue @ 921000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 922000004000.  Starting simulation...
+info: Entering event queue @ 922000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 923000004000.  Starting simulation...
+info: Entering event queue @ 923000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 924000004000.  Starting simulation...
+info: Entering event queue @ 924000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 925000004000.  Starting simulation...
+info: Entering event queue @ 925000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 926000004000.  Starting simulation...
+info: Entering event queue @ 926000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 927000004000.  Starting simulation...
+info: Entering event queue @ 927000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 928000004000.  Starting simulation...
+info: Entering event queue @ 928000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 929000004000.  Starting simulation...
+info: Entering event queue @ 929000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 930000004000.  Starting simulation...
+info: Entering event queue @ 930000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 931000004000.  Starting simulation...
+info: Entering event queue @ 931000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 932000004000.  Starting simulation...
+info: Entering event queue @ 932000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 933000004000.  Starting simulation...
+info: Entering event queue @ 933000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 934000004000.  Starting simulation...
+info: Entering event queue @ 934000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 935000004000.  Starting simulation...
+info: Entering event queue @ 935000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 936000004000.  Starting simulation...
+info: Entering event queue @ 936000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 937000004000.  Starting simulation...
+info: Entering event queue @ 937000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 938000004000.  Starting simulation...
+info: Entering event queue @ 938000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 939000004000.  Starting simulation...
+info: Entering event queue @ 939000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 940000004000.  Starting simulation...
+info: Entering event queue @ 940000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 941000004000.  Starting simulation...
+info: Entering event queue @ 941000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 942000004000.  Starting simulation...
+info: Entering event queue @ 942000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 943000004000.  Starting simulation...
+info: Entering event queue @ 943000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 944000004000.  Starting simulation...
+info: Entering event queue @ 944000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 945000004000.  Starting simulation...
+info: Entering event queue @ 945000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 946000004000.  Starting simulation...
+info: Entering event queue @ 946000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 947000004000.  Starting simulation...
+info: Entering event queue @ 947000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 948000004000.  Starting simulation...
+info: Entering event queue @ 948000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 949000004000.  Starting simulation...
+info: Entering event queue @ 949000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 950000004000.  Starting simulation...
+info: Entering event queue @ 950000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 951000004000.  Starting simulation...
+info: Entering event queue @ 951000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 952000004000.  Starting simulation...
+info: Entering event queue @ 952000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 953000004000.  Starting simulation...
+info: Entering event queue @ 953000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 954000004000.  Starting simulation...
+info: Entering event queue @ 954000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 955000004000.  Starting simulation...
+info: Entering event queue @ 955000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 956000004000.  Starting simulation...
+info: Entering event queue @ 956000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 957000004000.  Starting simulation...
+info: Entering event queue @ 957000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 958000004000.  Starting simulation...
+info: Entering event queue @ 958000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 959000004000.  Starting simulation...
+info: Entering event queue @ 959000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 960000004000.  Starting simulation...
+info: Entering event queue @ 960000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 961000004000.  Starting simulation...
+info: Entering event queue @ 961000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 962000004000.  Starting simulation...
+info: Entering event queue @ 962000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 963000004000.  Starting simulation...
+info: Entering event queue @ 963000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 964000004000.  Starting simulation...
+info: Entering event queue @ 964000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 965000004000.  Starting simulation...
+info: Entering event queue @ 965000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 966000004000.  Starting simulation...
+info: Entering event queue @ 966000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 967000004000.  Starting simulation...
+info: Entering event queue @ 967000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 968000004000.  Starting simulation...
+info: Entering event queue @ 968000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 969000004000.  Starting simulation...
+info: Entering event queue @ 969000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 970000004000.  Starting simulation...
+info: Entering event queue @ 970000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 971000004000.  Starting simulation...
+info: Entering event queue @ 971000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 972000004000.  Starting simulation...
+info: Entering event queue @ 972000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 973000004000.  Starting simulation...
+info: Entering event queue @ 973000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 974000004000.  Starting simulation...
+info: Entering event queue @ 974000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 975000004000.  Starting simulation...
+info: Entering event queue @ 975000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 976000004000.  Starting simulation...
+info: Entering event queue @ 976000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 977000004000.  Starting simulation...
+info: Entering event queue @ 977000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 978000004000.  Starting simulation...
+info: Entering event queue @ 978000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 979000004000.  Starting simulation...
+info: Entering event queue @ 979000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 980000004000.  Starting simulation...
+info: Entering event queue @ 980000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 981000004000.  Starting simulation...
+info: Entering event queue @ 981000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 982000004000.  Starting simulation...
+info: Entering event queue @ 982000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 983000004000.  Starting simulation...
+info: Entering event queue @ 983000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 984000004000.  Starting simulation...
+info: Entering event queue @ 984000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 985000004000.  Starting simulation...
+info: Entering event queue @ 985000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 986000004000.  Starting simulation...
+info: Entering event queue @ 986000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 987000004000.  Starting simulation...
+info: Entering event queue @ 987000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 988000004000.  Starting simulation...
+info: Entering event queue @ 988000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 989000004000.  Starting simulation...
+info: Entering event queue @ 989000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 990000004000.  Starting simulation...
+info: Entering event queue @ 990000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 991000004000.  Starting simulation...
+info: Entering event queue @ 991000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 992000004000.  Starting simulation...
+info: Entering event queue @ 992000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 993000004000.  Starting simulation...
+info: Entering event queue @ 993000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 994000004000.  Starting simulation...
+info: Entering event queue @ 994000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 995000004000.  Starting simulation...
+info: Entering event queue @ 995000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 996000004000.  Starting simulation...
+info: Entering event queue @ 996000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 997000004000.  Starting simulation...
+info: Entering event queue @ 997000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 998000004000.  Starting simulation...
+info: Entering event queue @ 998000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 999000004000.  Starting simulation...
+info: Entering event queue @ 999000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1000000004000.  Starting simulation...
+info: Entering event queue @ 1000000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1001000004000.  Starting simulation...
+info: Entering event queue @ 1001000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1002000004000.  Starting simulation...
+info: Entering event queue @ 1002000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1003000004000.  Starting simulation...
+info: Entering event queue @ 1003000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1004000004000.  Starting simulation...
+info: Entering event queue @ 1004000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1005000004000.  Starting simulation...
+info: Entering event queue @ 1005000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1006000004000.  Starting simulation...
+info: Entering event queue @ 1006000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1007000004000.  Starting simulation...
+info: Entering event queue @ 1007000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1008000004000.  Starting simulation...
+info: Entering event queue @ 1008000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1009000004000.  Starting simulation...
+info: Entering event queue @ 1009000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1010000004000.  Starting simulation...
+info: Entering event queue @ 1010000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1011000004000.  Starting simulation...
+info: Entering event queue @ 1011000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1012000004000.  Starting simulation...
+info: Entering event queue @ 1012000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1013000004000.  Starting simulation...
+info: Entering event queue @ 1013000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1014000004000.  Starting simulation...
+info: Entering event queue @ 1014000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1015000004000.  Starting simulation...
+info: Entering event queue @ 1015000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1016000004000.  Starting simulation...
+info: Entering event queue @ 1016000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1017000004000.  Starting simulation...
+info: Entering event queue @ 1017000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1018000004000.  Starting simulation...
+info: Entering event queue @ 1018000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1019000004000.  Starting simulation...
+info: Entering event queue @ 1019000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1020000004000.  Starting simulation...
+info: Entering event queue @ 1020000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1021000004000.  Starting simulation...
+info: Entering event queue @ 1021000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1022000004000.  Starting simulation...
+info: Entering event queue @ 1022000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1023000004000.  Starting simulation...
+info: Entering event queue @ 1023000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1024000004000.  Starting simulation...
+info: Entering event queue @ 1024000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1025000004000.  Starting simulation...
+info: Entering event queue @ 1025000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1026000004000.  Starting simulation...
+info: Entering event queue @ 1026000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1027000004000.  Starting simulation...
+info: Entering event queue @ 1027000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1028000004000.  Starting simulation...
+info: Entering event queue @ 1028000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1029000004000.  Starting simulation...
+info: Entering event queue @ 1029000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1030000004000.  Starting simulation...
+info: Entering event queue @ 1030000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1031000004000.  Starting simulation...
+info: Entering event queue @ 1031000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1032000004000.  Starting simulation...
+info: Entering event queue @ 1032000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1033000004000.  Starting simulation...
+info: Entering event queue @ 1033000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1034000004000.  Starting simulation...
+info: Entering event queue @ 1034000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1035000004000.  Starting simulation...
+info: Entering event queue @ 1035000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1036000004000.  Starting simulation...
+info: Entering event queue @ 1036000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1037000004000.  Starting simulation...
+info: Entering event queue @ 1037000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1038000004000.  Starting simulation...
+info: Entering event queue @ 1038000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1039000004000.  Starting simulation...
+info: Entering event queue @ 1039000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1040000004000.  Starting simulation...
+info: Entering event queue @ 1040000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1041000004000.  Starting simulation...
+info: Entering event queue @ 1041000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1042000004000.  Starting simulation...
+info: Entering event queue @ 1042000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1043000004000.  Starting simulation...
+info: Entering event queue @ 1043000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1044000004000.  Starting simulation...
+info: Entering event queue @ 1044000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1045000004000.  Starting simulation...
+info: Entering event queue @ 1045000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1046000004000.  Starting simulation...
+info: Entering event queue @ 1046000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1047000004000.  Starting simulation...
+info: Entering event queue @ 1047000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1048000004000.  Starting simulation...
+info: Entering event queue @ 1048000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1049000004000.  Starting simulation...
+info: Entering event queue @ 1049000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1050000004000.  Starting simulation...
+info: Entering event queue @ 1050000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1051000004000.  Starting simulation...
+info: Entering event queue @ 1051000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1052000004000.  Starting simulation...
+info: Entering event queue @ 1052000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1053000004000.  Starting simulation...
+info: Entering event queue @ 1053000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1054000004000.  Starting simulation...
+info: Entering event queue @ 1054000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1055000004000.  Starting simulation...
+info: Entering event queue @ 1055000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1056000004000.  Starting simulation...
+info: Entering event queue @ 1056000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1057000004000.  Starting simulation...
+info: Entering event queue @ 1057000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1058000004000.  Starting simulation...
+info: Entering event queue @ 1058000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1059000004000.  Starting simulation...
+info: Entering event queue @ 1059000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1060000004000.  Starting simulation...
+info: Entering event queue @ 1060000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1061000004000.  Starting simulation...
+info: Entering event queue @ 1061000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1062000004000.  Starting simulation...
+info: Entering event queue @ 1062000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1063000004000.  Starting simulation...
+info: Entering event queue @ 1063000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1064000004000.  Starting simulation...
+info: Entering event queue @ 1064000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1065000004000.  Starting simulation...
+info: Entering event queue @ 1065000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1066000004000.  Starting simulation...
+info: Entering event queue @ 1066000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1067000004000.  Starting simulation...
+info: Entering event queue @ 1067000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1068000004000.  Starting simulation...
+info: Entering event queue @ 1068000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1069000004000.  Starting simulation...
+info: Entering event queue @ 1069000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1070000004000.  Starting simulation...
+info: Entering event queue @ 1070000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1071000004000.  Starting simulation...
+info: Entering event queue @ 1071000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1072000004000.  Starting simulation...
+info: Entering event queue @ 1072000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1073000004000.  Starting simulation...
+info: Entering event queue @ 1073000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1074000004000.  Starting simulation...
+info: Entering event queue @ 1074000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1075000004000.  Starting simulation...
+info: Entering event queue @ 1075000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1076000004000.  Starting simulation...
+info: Entering event queue @ 1076000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1077000004000.  Starting simulation...
+info: Entering event queue @ 1077000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1078000004000.  Starting simulation...
+info: Entering event queue @ 1078000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1079000004000.  Starting simulation...
+info: Entering event queue @ 1079000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1080000004000.  Starting simulation...
+info: Entering event queue @ 1080000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1081000004000.  Starting simulation...
+info: Entering event queue @ 1081000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1082000004000.  Starting simulation...
+info: Entering event queue @ 1082000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1083000004000.  Starting simulation...
+info: Entering event queue @ 1083000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1084000004000.  Starting simulation...
+info: Entering event queue @ 1084000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1085000004000.  Starting simulation...
+info: Entering event queue @ 1085000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1086000004000.  Starting simulation...
+info: Entering event queue @ 1086000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1087000004000.  Starting simulation...
+info: Entering event queue @ 1087000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1088000004000.  Starting simulation...
+info: Entering event queue @ 1088000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1089000004000.  Starting simulation...
+info: Entering event queue @ 1089000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1090000004000.  Starting simulation...
+info: Entering event queue @ 1090000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1091000004000.  Starting simulation...
+info: Entering event queue @ 1091000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1092000004000.  Starting simulation...
+info: Entering event queue @ 1092000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1093000004000.  Starting simulation...
+info: Entering event queue @ 1093000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1094000004000.  Starting simulation...
+info: Entering event queue @ 1094000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1095000004000.  Starting simulation...
+info: Entering event queue @ 1095000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1096000004000.  Starting simulation...
+info: Entering event queue @ 1096000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1097000004000.  Starting simulation...
+info: Entering event queue @ 1097000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1098000004000.  Starting simulation...
+info: Entering event queue @ 1098000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1099000004000.  Starting simulation...
+info: Entering event queue @ 1099000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1100000004000.  Starting simulation...
+info: Entering event queue @ 1100000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1101000004000.  Starting simulation...
+info: Entering event queue @ 1101000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1102000004000.  Starting simulation...
+info: Entering event queue @ 1102000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1103000004000.  Starting simulation...
+info: Entering event queue @ 1103000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1104000004000.  Starting simulation...
+info: Entering event queue @ 1104000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1105000004000.  Starting simulation...
+info: Entering event queue @ 1105000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1106000004000.  Starting simulation...
+info: Entering event queue @ 1106000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1107000004000.  Starting simulation...
+info: Entering event queue @ 1107000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1108000004000.  Starting simulation...
+info: Entering event queue @ 1108000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1109000004000.  Starting simulation...
+info: Entering event queue @ 1109000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1110000004000.  Starting simulation...
+info: Entering event queue @ 1110000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1111000004000.  Starting simulation...
+info: Entering event queue @ 1111000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1112000004000.  Starting simulation...
+info: Entering event queue @ 1112000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1113000004000.  Starting simulation...
+info: Entering event queue @ 1113000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1114000004000.  Starting simulation...
+info: Entering event queue @ 1114000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1115000004000.  Starting simulation...
+info: Entering event queue @ 1115000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1116000004000.  Starting simulation...
+info: Entering event queue @ 1116000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1117000004000.  Starting simulation...
+info: Entering event queue @ 1117000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1118000004000.  Starting simulation...
+info: Entering event queue @ 1118000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1119000004000.  Starting simulation...
+info: Entering event queue @ 1119000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1120000004000.  Starting simulation...
+info: Entering event queue @ 1120000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1121000004000.  Starting simulation...
+info: Entering event queue @ 1121000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1122000004000.  Starting simulation...
+info: Entering event queue @ 1122000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1123000004000.  Starting simulation...
+info: Entering event queue @ 1123000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1124000004000.  Starting simulation...
+info: Entering event queue @ 1124000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1125000004000.  Starting simulation...
+info: Entering event queue @ 1125000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1126000004000.  Starting simulation...
+info: Entering event queue @ 1126000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1127000004000.  Starting simulation...
+info: Entering event queue @ 1127000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1128000004000.  Starting simulation...
+info: Entering event queue @ 1128000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1129000004000.  Starting simulation...
+info: Entering event queue @ 1129000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1130000004000.  Starting simulation...
+info: Entering event queue @ 1130000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1131000004000.  Starting simulation...
+info: Entering event queue @ 1131000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1132000004000.  Starting simulation...
+info: Entering event queue @ 1132000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1133000004000.  Starting simulation...
+info: Entering event queue @ 1133000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1134000004000.  Starting simulation...
+info: Entering event queue @ 1134000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1135000004000.  Starting simulation...
+info: Entering event queue @ 1135000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1136000004000.  Starting simulation...
+info: Entering event queue @ 1136000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1137000004000.  Starting simulation...
+info: Entering event queue @ 1137000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1138000004000.  Starting simulation...
+info: Entering event queue @ 1138000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1139000004000.  Starting simulation...
+info: Entering event queue @ 1139000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1140000004000.  Starting simulation...
+info: Entering event queue @ 1140000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1141000004000.  Starting simulation...
+info: Entering event queue @ 1141000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1142000004000.  Starting simulation...
+info: Entering event queue @ 1142000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1143000004000.  Starting simulation...
+info: Entering event queue @ 1143000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1144000004000.  Starting simulation...
+info: Entering event queue @ 1144000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1145000004000.  Starting simulation...
+info: Entering event queue @ 1145000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1146000004000.  Starting simulation...
+info: Entering event queue @ 1146000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1147000004000.  Starting simulation...
+info: Entering event queue @ 1147000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1148000004000.  Starting simulation...
+info: Entering event queue @ 1148000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1149000004000.  Starting simulation...
+info: Entering event queue @ 1149000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1150000004000.  Starting simulation...
+info: Entering event queue @ 1150000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1151000004000.  Starting simulation...
+info: Entering event queue @ 1151000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1152000004000.  Starting simulation...
+info: Entering event queue @ 1152000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1153000004000.  Starting simulation...
+info: Entering event queue @ 1153000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1154000004000.  Starting simulation...
+info: Entering event queue @ 1154000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1155000004000.  Starting simulation...
+info: Entering event queue @ 1155000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1156000004000.  Starting simulation...
+info: Entering event queue @ 1156000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1157000004000.  Starting simulation...
+info: Entering event queue @ 1157000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1158000004000.  Starting simulation...
+info: Entering event queue @ 1158000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1159000004000.  Starting simulation...
+info: Entering event queue @ 1159000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1160000004000.  Starting simulation...
+info: Entering event queue @ 1160000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1161000004000.  Starting simulation...
+info: Entering event queue @ 1161000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1162000004000.  Starting simulation...
+info: Entering event queue @ 1162000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1163000004000.  Starting simulation...
+info: Entering event queue @ 1163000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1164000004000.  Starting simulation...
+info: Entering event queue @ 1164000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1165000004000.  Starting simulation...
+info: Entering event queue @ 1165000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1166000004000.  Starting simulation...
+info: Entering event queue @ 1166000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1167000004000.  Starting simulation...
+info: Entering event queue @ 1167000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1168000004000.  Starting simulation...
+info: Entering event queue @ 1168000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1169000004000.  Starting simulation...
+info: Entering event queue @ 1169000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1170000004000.  Starting simulation...
+info: Entering event queue @ 1170000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1171000004000.  Starting simulation...
+info: Entering event queue @ 1171000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1172000004000.  Starting simulation...
+info: Entering event queue @ 1172000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1173000004000.  Starting simulation...
+info: Entering event queue @ 1173000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1174000004000.  Starting simulation...
+info: Entering event queue @ 1174000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1175000004000.  Starting simulation...
+info: Entering event queue @ 1175000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1176000004000.  Starting simulation...
+info: Entering event queue @ 1176000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1177000004000.  Starting simulation...
+info: Entering event queue @ 1177000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1178000004000.  Starting simulation...
+info: Entering event queue @ 1178000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1179000004000.  Starting simulation...
+info: Entering event queue @ 1179000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1180000004000.  Starting simulation...
+info: Entering event queue @ 1180000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1181000004000.  Starting simulation...
+info: Entering event queue @ 1181000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1182000004000.  Starting simulation...
+info: Entering event queue @ 1182000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1183000004000.  Starting simulation...
+info: Entering event queue @ 1183000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1184000004000.  Starting simulation...
+info: Entering event queue @ 1184000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1185000004000.  Starting simulation...
+info: Entering event queue @ 1185000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1186000004000.  Starting simulation...
+info: Entering event queue @ 1186000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1187000004000.  Starting simulation...
+info: Entering event queue @ 1187000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1188000004000.  Starting simulation...
+info: Entering event queue @ 1188000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1189000004000.  Starting simulation...
+info: Entering event queue @ 1189000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1190000004000.  Starting simulation...
+info: Entering event queue @ 1190000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1191000004000.  Starting simulation...
+info: Entering event queue @ 1191000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1192000004000.  Starting simulation...
+info: Entering event queue @ 1192000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1193000004000.  Starting simulation...
+info: Entering event queue @ 1193000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1194000004000.  Starting simulation...
+info: Entering event queue @ 1194000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1195000004000.  Starting simulation...
+info: Entering event queue @ 1195000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1196000004000.  Starting simulation...
+info: Entering event queue @ 1196000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1197000004000.  Starting simulation...
+info: Entering event queue @ 1197000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1198000004000.  Starting simulation...
+info: Entering event queue @ 1198000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1199000004000.  Starting simulation...
+info: Entering event queue @ 1199000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1200000004000.  Starting simulation...
+info: Entering event queue @ 1200000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1201000004000.  Starting simulation...
+info: Entering event queue @ 1201000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1202000004000.  Starting simulation...
+info: Entering event queue @ 1202000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1203000004000.  Starting simulation...
+info: Entering event queue @ 1203000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1204000004000.  Starting simulation...
+info: Entering event queue @ 1204000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1205000004000.  Starting simulation...
+info: Entering event queue @ 1205000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1206000004000.  Starting simulation...
+info: Entering event queue @ 1206000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1207000004000.  Starting simulation...
+info: Entering event queue @ 1207000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1208000004000.  Starting simulation...
+info: Entering event queue @ 1208000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1209000004000.  Starting simulation...
+info: Entering event queue @ 1209000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1210000004000.  Starting simulation...
+info: Entering event queue @ 1210000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1211000004000.  Starting simulation...
+info: Entering event queue @ 1211000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1212000004000.  Starting simulation...
+info: Entering event queue @ 1212000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1213000004000.  Starting simulation...
+info: Entering event queue @ 1213000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1214000004000.  Starting simulation...
+info: Entering event queue @ 1214000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1215000004000.  Starting simulation...
+info: Entering event queue @ 1215000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1216000004000.  Starting simulation...
+info: Entering event queue @ 1216000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1217000004000.  Starting simulation...
+info: Entering event queue @ 1217000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1218000004000.  Starting simulation...
+info: Entering event queue @ 1218000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1219000004000.  Starting simulation...
+info: Entering event queue @ 1219000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1220000004000.  Starting simulation...
+info: Entering event queue @ 1220000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1221000004000.  Starting simulation...
+info: Entering event queue @ 1221000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1222000004000.  Starting simulation...
+info: Entering event queue @ 1222000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1223000004000.  Starting simulation...
+info: Entering event queue @ 1223000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1224000004000.  Starting simulation...
+info: Entering event queue @ 1224000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1225000004000.  Starting simulation...
+info: Entering event queue @ 1225000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1226000004000.  Starting simulation...
+info: Entering event queue @ 1226000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1227000004000.  Starting simulation...
+info: Entering event queue @ 1227000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1228000004000.  Starting simulation...
+info: Entering event queue @ 1228000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1229000004000.  Starting simulation...
+info: Entering event queue @ 1229000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1230000004000.  Starting simulation...
+info: Entering event queue @ 1230000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1231000004000.  Starting simulation...
+info: Entering event queue @ 1231000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1232000004000.  Starting simulation...
+info: Entering event queue @ 1232000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1233000004000.  Starting simulation...
+info: Entering event queue @ 1233000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1234000004000.  Starting simulation...
+info: Entering event queue @ 1234000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1235000004000.  Starting simulation...
+info: Entering event queue @ 1235000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1236000004000.  Starting simulation...
+info: Entering event queue @ 1236000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1237000004000.  Starting simulation...
+info: Entering event queue @ 1237000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1238000004000.  Starting simulation...
+info: Entering event queue @ 1238000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1239000004000.  Starting simulation...
+info: Entering event queue @ 1239000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1240000004000.  Starting simulation...
+info: Entering event queue @ 1240000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1241000004000.  Starting simulation...
+info: Entering event queue @ 1241000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1242000004000.  Starting simulation...
+info: Entering event queue @ 1242000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1243000004000.  Starting simulation...
+info: Entering event queue @ 1243000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1244000004000.  Starting simulation...
+info: Entering event queue @ 1244000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1245000004000.  Starting simulation...
+info: Entering event queue @ 1245000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1246000004000.  Starting simulation...
+info: Entering event queue @ 1246000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1247000004000.  Starting simulation...
+info: Entering event queue @ 1247000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1248000004000.  Starting simulation...
+info: Entering event queue @ 1248000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1249000004000.  Starting simulation...
+info: Entering event queue @ 1249000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1250000004000.  Starting simulation...
+info: Entering event queue @ 1250000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1251000004000.  Starting simulation...
+info: Entering event queue @ 1251000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1252000004000.  Starting simulation...
+info: Entering event queue @ 1252000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1253000004000.  Starting simulation...
+info: Entering event queue @ 1253000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1254000004000.  Starting simulation...
+info: Entering event queue @ 1254000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1255000004000.  Starting simulation...
+info: Entering event queue @ 1255000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1256000004000.  Starting simulation...
+info: Entering event queue @ 1256000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1257000004000.  Starting simulation...
+info: Entering event queue @ 1257000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1258000004000.  Starting simulation...
+info: Entering event queue @ 1258000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1259000004000.  Starting simulation...
+info: Entering event queue @ 1259000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1260000004000.  Starting simulation...
+info: Entering event queue @ 1260000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1261000004000.  Starting simulation...
+info: Entering event queue @ 1261000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1262000004000.  Starting simulation...
+info: Entering event queue @ 1262000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1263000004000.  Starting simulation...
+info: Entering event queue @ 1263000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1264000004000.  Starting simulation...
+info: Entering event queue @ 1264000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1265000004000.  Starting simulation...
+info: Entering event queue @ 1265000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1266000004000.  Starting simulation...
+info: Entering event queue @ 1266000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1267000004000.  Starting simulation...
+info: Entering event queue @ 1267000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1268000004000.  Starting simulation...
+info: Entering event queue @ 1268000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1269000004000.  Starting simulation...
+info: Entering event queue @ 1269000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1270000004000.  Starting simulation...
+info: Entering event queue @ 1270000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1271000004000.  Starting simulation...
+info: Entering event queue @ 1271000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1272000004000.  Starting simulation...
+info: Entering event queue @ 1272000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1273000004000.  Starting simulation...
+info: Entering event queue @ 1273000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1274000004000.  Starting simulation...
+info: Entering event queue @ 1274000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1275000004000.  Starting simulation...
+info: Entering event queue @ 1275000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1276000004000.  Starting simulation...
+info: Entering event queue @ 1276000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1277000004000.  Starting simulation...
+info: Entering event queue @ 1277000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1278000004000.  Starting simulation...
+info: Entering event queue @ 1278000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1279000004000.  Starting simulation...
+info: Entering event queue @ 1279000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1280000004000.  Starting simulation...
+info: Entering event queue @ 1280000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1281000004000.  Starting simulation...
+info: Entering event queue @ 1281000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1282000004000.  Starting simulation...
+info: Entering event queue @ 1282000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1283000004000.  Starting simulation...
+info: Entering event queue @ 1283000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1284000004000.  Starting simulation...
+info: Entering event queue @ 1284000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1285000004000.  Starting simulation...
+info: Entering event queue @ 1285000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1286000004000.  Starting simulation...
+info: Entering event queue @ 1286000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1287000004000.  Starting simulation...
+info: Entering event queue @ 1287000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1288000004000.  Starting simulation...
+info: Entering event queue @ 1288000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1289000004000.  Starting simulation...
+info: Entering event queue @ 1289000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1290000004000.  Starting simulation...
+info: Entering event queue @ 1290000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1291000004000.  Starting simulation...
+info: Entering event queue @ 1291000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1292000004000.  Starting simulation...
+info: Entering event queue @ 1292000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1293000004000.  Starting simulation...
+info: Entering event queue @ 1293000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1294000004000.  Starting simulation...
+info: Entering event queue @ 1294000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1295000004000.  Starting simulation...
+info: Entering event queue @ 1295000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1296000004000.  Starting simulation...
+info: Entering event queue @ 1296000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1297000004000.  Starting simulation...
+info: Entering event queue @ 1297000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1298000004000.  Starting simulation...
+info: Entering event queue @ 1298000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1299000004000.  Starting simulation...
+info: Entering event queue @ 1299000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1300000004000.  Starting simulation...
+info: Entering event queue @ 1300000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1301000004000.  Starting simulation...
+info: Entering event queue @ 1301000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1302000004000.  Starting simulation...
+info: Entering event queue @ 1302000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1303000004000.  Starting simulation...
+info: Entering event queue @ 1303000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1304000004000.  Starting simulation...
+info: Entering event queue @ 1304000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1305000004000.  Starting simulation...
+info: Entering event queue @ 1305000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1306000004000.  Starting simulation...
+info: Entering event queue @ 1306000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1307000004000.  Starting simulation...
+info: Entering event queue @ 1307000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1308000004000.  Starting simulation...
+info: Entering event queue @ 1308000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1309000004000.  Starting simulation...
+info: Entering event queue @ 1309000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1310000004000.  Starting simulation...
+info: Entering event queue @ 1310000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1311000004000.  Starting simulation...
+info: Entering event queue @ 1311000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1312000004000.  Starting simulation...
+info: Entering event queue @ 1312000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1313000004000.  Starting simulation...
+info: Entering event queue @ 1313000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1314000004000.  Starting simulation...
+info: Entering event queue @ 1314000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1315000004000.  Starting simulation...
+info: Entering event queue @ 1315000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1316000004000.  Starting simulation...
+info: Entering event queue @ 1316000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1317000004000.  Starting simulation...
+info: Entering event queue @ 1317000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1318000004000.  Starting simulation...
+info: Entering event queue @ 1318000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1319000004000.  Starting simulation...
+info: Entering event queue @ 1319000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1320000004000.  Starting simulation...
+info: Entering event queue @ 1320000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1321000004000.  Starting simulation...
+info: Entering event queue @ 1321000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1322000004000.  Starting simulation...
+info: Entering event queue @ 1322000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1323000004000.  Starting simulation...
+info: Entering event queue @ 1323000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1324000004000.  Starting simulation...
+info: Entering event queue @ 1324000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1325000004000.  Starting simulation...
+info: Entering event queue @ 1325000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1326000004000.  Starting simulation...
+info: Entering event queue @ 1326000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1327000004000.  Starting simulation...
+info: Entering event queue @ 1327000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1328000004000.  Starting simulation...
+info: Entering event queue @ 1328000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1329000004000.  Starting simulation...
+info: Entering event queue @ 1329000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1330000004000.  Starting simulation...
+info: Entering event queue @ 1330000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1331000004000.  Starting simulation...
+info: Entering event queue @ 1331000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1332000004000.  Starting simulation...
+info: Entering event queue @ 1332000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1333000004000.  Starting simulation...
+info: Entering event queue @ 1333000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1334000004000.  Starting simulation...
+info: Entering event queue @ 1334000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1335000004000.  Starting simulation...
+info: Entering event queue @ 1335000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1336000004000.  Starting simulation...
+info: Entering event queue @ 1336000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1337000004000.  Starting simulation...
+info: Entering event queue @ 1337000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1338000004000.  Starting simulation...
+info: Entering event queue @ 1338000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1339000004000.  Starting simulation...
+info: Entering event queue @ 1339000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1340000004000.  Starting simulation...
+info: Entering event queue @ 1340000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1341000004000.  Starting simulation...
+info: Entering event queue @ 1341000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1342000004000.  Starting simulation...
+info: Entering event queue @ 1342000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1343000004000.  Starting simulation...
+info: Entering event queue @ 1343000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1344000004000.  Starting simulation...
+info: Entering event queue @ 1344000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1345000004000.  Starting simulation...
+info: Entering event queue @ 1345000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1346000004000.  Starting simulation...
+info: Entering event queue @ 1346000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1347000004000.  Starting simulation...
+info: Entering event queue @ 1347000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1348000004000.  Starting simulation...
+info: Entering event queue @ 1348000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1349000004000.  Starting simulation...
+info: Entering event queue @ 1349000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1350000004000.  Starting simulation...
+info: Entering event queue @ 1350000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1351000004000.  Starting simulation...
+info: Entering event queue @ 1351000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1352000004000.  Starting simulation...
+info: Entering event queue @ 1352000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1353000004000.  Starting simulation...
+info: Entering event queue @ 1353000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1354000004000.  Starting simulation...
+info: Entering event queue @ 1354000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1355000004000.  Starting simulation...
+info: Entering event queue @ 1355000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1356000004000.  Starting simulation...
+info: Entering event queue @ 1356000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1357000004000.  Starting simulation...
+info: Entering event queue @ 1357000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1358000004000.  Starting simulation...
+info: Entering event queue @ 1358000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1359000004000.  Starting simulation...
+info: Entering event queue @ 1359000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1360000004000.  Starting simulation...
+info: Entering event queue @ 1360000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1361000004000.  Starting simulation...
+info: Entering event queue @ 1361000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1362000004000.  Starting simulation...
+info: Entering event queue @ 1362000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1363000004000.  Starting simulation...
+info: Entering event queue @ 1363000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1364000004000.  Starting simulation...
+info: Entering event queue @ 1364000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1365000004000.  Starting simulation...
+info: Entering event queue @ 1365000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1366000004000.  Starting simulation...
+info: Entering event queue @ 1366000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1367000004000.  Starting simulation...
+info: Entering event queue @ 1367000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1368000004000.  Starting simulation...
+info: Entering event queue @ 1368000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1369000004000.  Starting simulation...
+info: Entering event queue @ 1369000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1370000004000.  Starting simulation...
+info: Entering event queue @ 1370000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1371000004000.  Starting simulation...
+info: Entering event queue @ 1371000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1372000004000.  Starting simulation...
+info: Entering event queue @ 1372000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1373000004000.  Starting simulation...
+info: Entering event queue @ 1373000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1374000004000.  Starting simulation...
+info: Entering event queue @ 1374000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1375000004000.  Starting simulation...
+info: Entering event queue @ 1375000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1376000004000.  Starting simulation...
+info: Entering event queue @ 1376000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1377000004000.  Starting simulation...
+info: Entering event queue @ 1377000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1378000004000.  Starting simulation...
+info: Entering event queue @ 1378000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1379000004000.  Starting simulation...
+info: Entering event queue @ 1379000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1380000004000.  Starting simulation...
+info: Entering event queue @ 1380000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1381000004000.  Starting simulation...
+info: Entering event queue @ 1381000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1382000004000.  Starting simulation...
+info: Entering event queue @ 1382000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1383000004000.  Starting simulation...
+info: Entering event queue @ 1383000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1384000004000.  Starting simulation...
+info: Entering event queue @ 1384000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1385000004000.  Starting simulation...
+info: Entering event queue @ 1385000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1386000004000.  Starting simulation...
+info: Entering event queue @ 1386000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1387000004000.  Starting simulation...
+info: Entering event queue @ 1387000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1388000004000.  Starting simulation...
+info: Entering event queue @ 1388000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1389000004000.  Starting simulation...
+info: Entering event queue @ 1389000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1390000004000.  Starting simulation...
+info: Entering event queue @ 1390000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1391000004000.  Starting simulation...
+info: Entering event queue @ 1391000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1392000004000.  Starting simulation...
+info: Entering event queue @ 1392000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1393000004000.  Starting simulation...
+info: Entering event queue @ 1393000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1394000004000.  Starting simulation...
+info: Entering event queue @ 1394000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1395000004000.  Starting simulation...
+info: Entering event queue @ 1395000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1396000004000.  Starting simulation...
+info: Entering event queue @ 1396000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1397000004000.  Starting simulation...
+info: Entering event queue @ 1397000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1398000004000.  Starting simulation...
+info: Entering event queue @ 1398000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1399000004000.  Starting simulation...
+info: Entering event queue @ 1399000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1400000004000.  Starting simulation...
+info: Entering event queue @ 1400000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1401000004000.  Starting simulation...
+info: Entering event queue @ 1401000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1402000004000.  Starting simulation...
+info: Entering event queue @ 1402000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1403000004000.  Starting simulation...
+info: Entering event queue @ 1403000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1404000004000.  Starting simulation...
+info: Entering event queue @ 1404000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1405000004000.  Starting simulation...
+info: Entering event queue @ 1405000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1406000004000.  Starting simulation...
+info: Entering event queue @ 1406000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1407000004000.  Starting simulation...
+info: Entering event queue @ 1407000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1408000004000.  Starting simulation...
+info: Entering event queue @ 1408000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1409000004000.  Starting simulation...
+info: Entering event queue @ 1409000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1410000004000.  Starting simulation...
+info: Entering event queue @ 1410000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1411000004000.  Starting simulation...
+info: Entering event queue @ 1411000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1412000004000.  Starting simulation...
+info: Entering event queue @ 1412000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1413000004000.  Starting simulation...
+info: Entering event queue @ 1413000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1414000004000.  Starting simulation...
+info: Entering event queue @ 1414000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1415000004000.  Starting simulation...
+info: Entering event queue @ 1415000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1416000004000.  Starting simulation...
+info: Entering event queue @ 1416000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1417000004000.  Starting simulation...
+info: Entering event queue @ 1417000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1418000004000.  Starting simulation...
+info: Entering event queue @ 1418000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1419000004000.  Starting simulation...
+info: Entering event queue @ 1419000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1420000004000.  Starting simulation...
+info: Entering event queue @ 1420000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1421000004000.  Starting simulation...
+info: Entering event queue @ 1421000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1422000004000.  Starting simulation...
+info: Entering event queue @ 1422000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1423000004000.  Starting simulation...
+info: Entering event queue @ 1423000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1424000004000.  Starting simulation...
+info: Entering event queue @ 1424000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1425000004000.  Starting simulation...
+info: Entering event queue @ 1425000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1426000004000.  Starting simulation...
+info: Entering event queue @ 1426000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1427000004000.  Starting simulation...
+info: Entering event queue @ 1427000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1428000004000.  Starting simulation...
+info: Entering event queue @ 1428000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1429000004000.  Starting simulation...
+info: Entering event queue @ 1429000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1430000004000.  Starting simulation...
+info: Entering event queue @ 1430000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1431000004000.  Starting simulation...
+info: Entering event queue @ 1431000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1432000004000.  Starting simulation...
+info: Entering event queue @ 1432000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1433000004000.  Starting simulation...
+info: Entering event queue @ 1433000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1434000004000.  Starting simulation...
+info: Entering event queue @ 1434000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1435000004000.  Starting simulation...
+info: Entering event queue @ 1435000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1436000004000.  Starting simulation...
+info: Entering event queue @ 1436000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1437000004000.  Starting simulation...
+info: Entering event queue @ 1437000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1438000004000.  Starting simulation...
+info: Entering event queue @ 1438000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1439000004000.  Starting simulation...
+info: Entering event queue @ 1439000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1440000004000.  Starting simulation...
+info: Entering event queue @ 1440000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1441000004000.  Starting simulation...
+info: Entering event queue @ 1441000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1442000004000.  Starting simulation...
+info: Entering event queue @ 1442000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1443000004000.  Starting simulation...
+info: Entering event queue @ 1443000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1444000004000.  Starting simulation...
+info: Entering event queue @ 1444000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1445000004000.  Starting simulation...
+info: Entering event queue @ 1445000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1446000004000.  Starting simulation...
+info: Entering event queue @ 1446000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1447000004000.  Starting simulation...
+info: Entering event queue @ 1447000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1448000004000.  Starting simulation...
+info: Entering event queue @ 1448000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1449000004000.  Starting simulation...
+info: Entering event queue @ 1449000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1450000004000.  Starting simulation...
+info: Entering event queue @ 1450000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1451000004000.  Starting simulation...
+info: Entering event queue @ 1451000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1452000004000.  Starting simulation...
+info: Entering event queue @ 1452000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1453000004000.  Starting simulation...
+info: Entering event queue @ 1453000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1454000004000.  Starting simulation...
+info: Entering event queue @ 1454000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1455000004000.  Starting simulation...
+info: Entering event queue @ 1455000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1456000004000.  Starting simulation...
+info: Entering event queue @ 1456000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1457000004000.  Starting simulation...
+info: Entering event queue @ 1457000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1458000004000.  Starting simulation...
+info: Entering event queue @ 1458000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1459000004000.  Starting simulation...
+info: Entering event queue @ 1459000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1460000004000.  Starting simulation...
+info: Entering event queue @ 1460000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1461000004000.  Starting simulation...
+info: Entering event queue @ 1461000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1462000004000.  Starting simulation...
+info: Entering event queue @ 1462000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1463000004000.  Starting simulation...
+info: Entering event queue @ 1463000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1464000004000.  Starting simulation...
+info: Entering event queue @ 1464000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1465000004000.  Starting simulation...
+info: Entering event queue @ 1465000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1466000004000.  Starting simulation...
+info: Entering event queue @ 1466000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1467000004000.  Starting simulation...
+info: Entering event queue @ 1467000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1468000004000.  Starting simulation...
+info: Entering event queue @ 1468000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1469000004000.  Starting simulation...
+info: Entering event queue @ 1469000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1470000004000.  Starting simulation...
+info: Entering event queue @ 1470000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1471000004000.  Starting simulation...
+info: Entering event queue @ 1471000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1472000004000.  Starting simulation...
+info: Entering event queue @ 1472000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1473000004000.  Starting simulation...
+info: Entering event queue @ 1473000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1474000004000.  Starting simulation...
+info: Entering event queue @ 1474000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1475000004000.  Starting simulation...
+info: Entering event queue @ 1475000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1476000004000.  Starting simulation...
+info: Entering event queue @ 1476000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1477000004000.  Starting simulation...
+info: Entering event queue @ 1477000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1478000004000.  Starting simulation...
+info: Entering event queue @ 1478000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1479000004000.  Starting simulation...
+info: Entering event queue @ 1479000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1480000004000.  Starting simulation...
+info: Entering event queue @ 1480000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1481000004000.  Starting simulation...
+info: Entering event queue @ 1481000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1482000004000.  Starting simulation...
+info: Entering event queue @ 1482000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1483000004000.  Starting simulation...
+info: Entering event queue @ 1483000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1484000004000.  Starting simulation...
+info: Entering event queue @ 1484000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1485000004000.  Starting simulation...
+info: Entering event queue @ 1485000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1486000004000.  Starting simulation...
+info: Entering event queue @ 1486000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1487000004000.  Starting simulation...
+info: Entering event queue @ 1487000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1488000004000.  Starting simulation...
+info: Entering event queue @ 1488000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1489000004000.  Starting simulation...
+info: Entering event queue @ 1489000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1490000004000.  Starting simulation...
+info: Entering event queue @ 1490000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1491000004000.  Starting simulation...
+info: Entering event queue @ 1491000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1492000004000.  Starting simulation...
+info: Entering event queue @ 1492000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1493000004000.  Starting simulation...
+info: Entering event queue @ 1493000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1494000004000.  Starting simulation...
+info: Entering event queue @ 1494000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1495000004000.  Starting simulation...
+info: Entering event queue @ 1495000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1496000004000.  Starting simulation...
+info: Entering event queue @ 1496000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1497000004000.  Starting simulation...
+info: Entering event queue @ 1497000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1498000004000.  Starting simulation...
+info: Entering event queue @ 1498000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1499000004000.  Starting simulation...
+info: Entering event queue @ 1499000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1500000004000.  Starting simulation...
+info: Entering event queue @ 1500000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1501000004000.  Starting simulation...
+info: Entering event queue @ 1501000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1502000004000.  Starting simulation...
+info: Entering event queue @ 1502000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1503000004000.  Starting simulation...
+info: Entering event queue @ 1503000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1504000004000.  Starting simulation...
+info: Entering event queue @ 1504000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1505000004000.  Starting simulation...
+info: Entering event queue @ 1505000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1506000004000.  Starting simulation...
+info: Entering event queue @ 1506000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1507000004000.  Starting simulation...
+info: Entering event queue @ 1507000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1508000004000.  Starting simulation...
+info: Entering event queue @ 1508000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1509000004000.  Starting simulation...
+info: Entering event queue @ 1509000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1510000004000.  Starting simulation...
+info: Entering event queue @ 1510000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1511000004000.  Starting simulation...
+info: Entering event queue @ 1511000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1512000004000.  Starting simulation...
+info: Entering event queue @ 1512000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1513000004000.  Starting simulation...
+info: Entering event queue @ 1513000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1514000004000.  Starting simulation...
+info: Entering event queue @ 1514000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1515000004000.  Starting simulation...
+info: Entering event queue @ 1515000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1516000004000.  Starting simulation...
+info: Entering event queue @ 1516000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1517000004000.  Starting simulation...
+info: Entering event queue @ 1517000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1518000004000.  Starting simulation...
+info: Entering event queue @ 1518000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1519000004000.  Starting simulation...
+info: Entering event queue @ 1519000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1520000004000.  Starting simulation...
+info: Entering event queue @ 1520000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1521000004000.  Starting simulation...
+info: Entering event queue @ 1521000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1522000004000.  Starting simulation...
+info: Entering event queue @ 1522000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1523000004000.  Starting simulation...
+info: Entering event queue @ 1523000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1524000004000.  Starting simulation...
+info: Entering event queue @ 1524000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1525000004000.  Starting simulation...
+info: Entering event queue @ 1525000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1526000004000.  Starting simulation...
+info: Entering event queue @ 1526000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1527000004000.  Starting simulation...
+info: Entering event queue @ 1527000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1528000004000.  Starting simulation...
+info: Entering event queue @ 1528000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1529000004000.  Starting simulation...
+info: Entering event queue @ 1529000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1530000004000.  Starting simulation...
+info: Entering event queue @ 1530000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1531000004000.  Starting simulation...
+info: Entering event queue @ 1531000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1532000004000.  Starting simulation...
+info: Entering event queue @ 1532000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1533000004000.  Starting simulation...
+info: Entering event queue @ 1533000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1534000004000.  Starting simulation...
+info: Entering event queue @ 1534000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1535000004000.  Starting simulation...
+info: Entering event queue @ 1535000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1536000004000.  Starting simulation...
+info: Entering event queue @ 1536000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1537000004000.  Starting simulation...
+info: Entering event queue @ 1537000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1538000004000.  Starting simulation...
+info: Entering event queue @ 1538000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1539000004000.  Starting simulation...
+info: Entering event queue @ 1539000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1540000004000.  Starting simulation...
+info: Entering event queue @ 1540000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1541000004000.  Starting simulation...
+info: Entering event queue @ 1541000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1542000004000.  Starting simulation...
+info: Entering event queue @ 1542000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1543000004000.  Starting simulation...
+info: Entering event queue @ 1543000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1544000004000.  Starting simulation...
+info: Entering event queue @ 1544000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1545000004000.  Starting simulation...
+info: Entering event queue @ 1545000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1546000004000.  Starting simulation...
+info: Entering event queue @ 1546000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1547000004000.  Starting simulation...
+info: Entering event queue @ 1547000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1548000004000.  Starting simulation...
+info: Entering event queue @ 1548000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1549000004000.  Starting simulation...
+info: Entering event queue @ 1549000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1550000004000.  Starting simulation...
+info: Entering event queue @ 1550000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1551000004000.  Starting simulation...
+info: Entering event queue @ 1551000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1552000004000.  Starting simulation...
+info: Entering event queue @ 1552000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1553000004000.  Starting simulation...
+info: Entering event queue @ 1553000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1554000004000.  Starting simulation...
+info: Entering event queue @ 1554000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1555000004000.  Starting simulation...
+info: Entering event queue @ 1555000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1556000004000.  Starting simulation...
+info: Entering event queue @ 1556000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1557000004000.  Starting simulation...
+info: Entering event queue @ 1557000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1558000004000.  Starting simulation...
+info: Entering event queue @ 1558000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1559000004000.  Starting simulation...
+info: Entering event queue @ 1559000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1560000004000.  Starting simulation...
+info: Entering event queue @ 1560000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1561000004000.  Starting simulation...
+info: Entering event queue @ 1561000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1562000004000.  Starting simulation...
+info: Entering event queue @ 1562000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1563000004000.  Starting simulation...
+info: Entering event queue @ 1563000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1564000004000.  Starting simulation...
+info: Entering event queue @ 1564000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1565000004000.  Starting simulation...
+info: Entering event queue @ 1565000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1566000004000.  Starting simulation...
+info: Entering event queue @ 1566000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1567000004000.  Starting simulation...
+info: Entering event queue @ 1567000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1568000004000.  Starting simulation...
+info: Entering event queue @ 1568000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1569000004000.  Starting simulation...
+info: Entering event queue @ 1569000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1570000004000.  Starting simulation...
+info: Entering event queue @ 1570000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1571000004000.  Starting simulation...
+info: Entering event queue @ 1571000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1572000004000.  Starting simulation...
+info: Entering event queue @ 1572000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1573000004000.  Starting simulation...
+info: Entering event queue @ 1573000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1574000004000.  Starting simulation...
+info: Entering event queue @ 1574000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1575000004000.  Starting simulation...
+info: Entering event queue @ 1575000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1576000004000.  Starting simulation...
+info: Entering event queue @ 1576000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1577000004000.  Starting simulation...
+info: Entering event queue @ 1577000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1578000004000.  Starting simulation...
+info: Entering event queue @ 1578000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1579000004000.  Starting simulation...
+info: Entering event queue @ 1579000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1580000004000.  Starting simulation...
+info: Entering event queue @ 1580000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1581000004000.  Starting simulation...
+info: Entering event queue @ 1581000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1582000004000.  Starting simulation...
+info: Entering event queue @ 1582000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1583000004000.  Starting simulation...
+info: Entering event queue @ 1583000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1584000004000.  Starting simulation...
+info: Entering event queue @ 1584000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1585000004000.  Starting simulation...
+info: Entering event queue @ 1585000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1586000004000.  Starting simulation...
+info: Entering event queue @ 1586000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1587000004000.  Starting simulation...
+info: Entering event queue @ 1587000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1588000004000.  Starting simulation...
+info: Entering event queue @ 1588000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1589000004000.  Starting simulation...
+info: Entering event queue @ 1589000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1590000004000.  Starting simulation...
+info: Entering event queue @ 1590000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1591000004000.  Starting simulation...
+info: Entering event queue @ 1591000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1592000004000.  Starting simulation...
+info: Entering event queue @ 1592000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1593000004000.  Starting simulation...
+info: Entering event queue @ 1593000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1594000004000.  Starting simulation...
+info: Entering event queue @ 1594000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1595000004000.  Starting simulation...
+info: Entering event queue @ 1595000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1596000004000.  Starting simulation...
+info: Entering event queue @ 1596000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1597000004000.  Starting simulation...
+info: Entering event queue @ 1597000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1598000004000.  Starting simulation...
+info: Entering event queue @ 1598000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1599000004000.  Starting simulation...
+info: Entering event queue @ 1599000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1600000004000.  Starting simulation...
+info: Entering event queue @ 1600000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1601000004000.  Starting simulation...
+info: Entering event queue @ 1601000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1602000004000.  Starting simulation...
+info: Entering event queue @ 1602000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1603000004000.  Starting simulation...
+info: Entering event queue @ 1603000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1604000004000.  Starting simulation...
+info: Entering event queue @ 1604000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1605000004000.  Starting simulation...
+info: Entering event queue @ 1605000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1606000004000.  Starting simulation...
+info: Entering event queue @ 1606000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1607000004000.  Starting simulation...
+info: Entering event queue @ 1607000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1608000004000.  Starting simulation...
+info: Entering event queue @ 1608000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1609000004000.  Starting simulation...
+info: Entering event queue @ 1609000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1610000004000.  Starting simulation...
+info: Entering event queue @ 1610000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1611000004000.  Starting simulation...
+info: Entering event queue @ 1611000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1612000004000.  Starting simulation...
+info: Entering event queue @ 1612000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1613000004000.  Starting simulation...
+info: Entering event queue @ 1613000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1614000004000.  Starting simulation...
+info: Entering event queue @ 1614000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1615000004000.  Starting simulation...
+info: Entering event queue @ 1615000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1616000004000.  Starting simulation...
+info: Entering event queue @ 1616000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1617000004000.  Starting simulation...
+info: Entering event queue @ 1617000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1618000004000.  Starting simulation...
+info: Entering event queue @ 1618000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1619000004000.  Starting simulation...
+info: Entering event queue @ 1619000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1620000004000.  Starting simulation...
+info: Entering event queue @ 1620000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1621000004000.  Starting simulation...
+info: Entering event queue @ 1621000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1622000004000.  Starting simulation...
+info: Entering event queue @ 1622000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1623000004000.  Starting simulation...
+info: Entering event queue @ 1623000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1624000004000.  Starting simulation...
+info: Entering event queue @ 1624000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1625000004000.  Starting simulation...
+info: Entering event queue @ 1625000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1626000004000.  Starting simulation...
+info: Entering event queue @ 1626000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1627000004000.  Starting simulation...
+info: Entering event queue @ 1627000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1628000004000.  Starting simulation...
+info: Entering event queue @ 1628000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1629000004000.  Starting simulation...
+info: Entering event queue @ 1629000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1630000004000.  Starting simulation...
+info: Entering event queue @ 1630000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1631000004000.  Starting simulation...
+info: Entering event queue @ 1631000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1632000004000.  Starting simulation...
+info: Entering event queue @ 1632000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1633000004000.  Starting simulation...
+info: Entering event queue @ 1633000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1634000004000.  Starting simulation...
+info: Entering event queue @ 1634000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1635000004000.  Starting simulation...
+info: Entering event queue @ 1635000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1636000004000.  Starting simulation...
+info: Entering event queue @ 1636000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1637000004000.  Starting simulation...
+info: Entering event queue @ 1637000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1638000004000.  Starting simulation...
+info: Entering event queue @ 1638000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1639000004000.  Starting simulation...
+info: Entering event queue @ 1639000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1640000004000.  Starting simulation...
+info: Entering event queue @ 1640000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1641000004000.  Starting simulation...
+info: Entering event queue @ 1641000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1642000004000.  Starting simulation...
+info: Entering event queue @ 1642000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1643000004000.  Starting simulation...
+info: Entering event queue @ 1643000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1644000004000.  Starting simulation...
+info: Entering event queue @ 1644000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1645000004000.  Starting simulation...
+info: Entering event queue @ 1645000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1646000004000.  Starting simulation...
+info: Entering event queue @ 1646000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1647000004000.  Starting simulation...
+info: Entering event queue @ 1647000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1648000004000.  Starting simulation...
+info: Entering event queue @ 1648000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1649000004000.  Starting simulation...
+info: Entering event queue @ 1649000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1650000004000.  Starting simulation...
+info: Entering event queue @ 1650000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1651000004000.  Starting simulation...
+info: Entering event queue @ 1651000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1652000004000.  Starting simulation...
+info: Entering event queue @ 1652000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1653000004000.  Starting simulation...
+info: Entering event queue @ 1653000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1654000004000.  Starting simulation...
+info: Entering event queue @ 1654000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1655000004000.  Starting simulation...
+info: Entering event queue @ 1655000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1656000004000.  Starting simulation...
+info: Entering event queue @ 1656000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1657000004000.  Starting simulation...
+info: Entering event queue @ 1657000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1658000004000.  Starting simulation...
+info: Entering event queue @ 1658000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1659000004000.  Starting simulation...
+info: Entering event queue @ 1659000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1660000004000.  Starting simulation...
+info: Entering event queue @ 1660000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1661000004000.  Starting simulation...
+info: Entering event queue @ 1661000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1662000004000.  Starting simulation...
+info: Entering event queue @ 1662000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1663000004000.  Starting simulation...
+info: Entering event queue @ 1663000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1664000004000.  Starting simulation...
+info: Entering event queue @ 1664000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1665000004000.  Starting simulation...
+info: Entering event queue @ 1665000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1666000004000.  Starting simulation...
+info: Entering event queue @ 1666000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1667000004000.  Starting simulation...
+info: Entering event queue @ 1667000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1668000004000.  Starting simulation...
+info: Entering event queue @ 1668000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1669000004000.  Starting simulation...
+info: Entering event queue @ 1669000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1670000004000.  Starting simulation...
+info: Entering event queue @ 1670000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1671000004000.  Starting simulation...
+info: Entering event queue @ 1671000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1672000004000.  Starting simulation...
+info: Entering event queue @ 1672000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1673000004000.  Starting simulation...
+info: Entering event queue @ 1673000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1674000004000.  Starting simulation...
+info: Entering event queue @ 1674000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1675000004000.  Starting simulation...
+info: Entering event queue @ 1675000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1676000004000.  Starting simulation...
+info: Entering event queue @ 1676000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1677000004000.  Starting simulation...
+info: Entering event queue @ 1677000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1678000004000.  Starting simulation...
+info: Entering event queue @ 1678000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1679000004000.  Starting simulation...
+info: Entering event queue @ 1679000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1680000004000.  Starting simulation...
+info: Entering event queue @ 1680000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1681000004000.  Starting simulation...
+info: Entering event queue @ 1681000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1682000004000.  Starting simulation...
+info: Entering event queue @ 1682000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1683000004000.  Starting simulation...
+info: Entering event queue @ 1683000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1684000004000.  Starting simulation...
+info: Entering event queue @ 1684000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1685000004000.  Starting simulation...
+info: Entering event queue @ 1685000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1686000004000.  Starting simulation...
+info: Entering event queue @ 1686000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1687000004000.  Starting simulation...
+info: Entering event queue @ 1687000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1688000004000.  Starting simulation...
+info: Entering event queue @ 1688000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1689000004000.  Starting simulation...
+info: Entering event queue @ 1689000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1690000004000.  Starting simulation...
+info: Entering event queue @ 1690000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1691000004000.  Starting simulation...
+info: Entering event queue @ 1691000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1692000004000.  Starting simulation...
+info: Entering event queue @ 1692000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1693000004000.  Starting simulation...
+info: Entering event queue @ 1693000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1694000004000.  Starting simulation...
+info: Entering event queue @ 1694000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1695000004000.  Starting simulation...
+info: Entering event queue @ 1695000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1696000004000.  Starting simulation...
+info: Entering event queue @ 1696000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1697000004000.  Starting simulation...
+info: Entering event queue @ 1697000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1698000004000.  Starting simulation...
+info: Entering event queue @ 1698000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1699000004000.  Starting simulation...
+info: Entering event queue @ 1699000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1700000004000.  Starting simulation...
+info: Entering event queue @ 1700000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1701000004000.  Starting simulation...
+info: Entering event queue @ 1701000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1702000004000.  Starting simulation...
+info: Entering event queue @ 1702000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1703000004000.  Starting simulation...
+info: Entering event queue @ 1703000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1704000004000.  Starting simulation...
+info: Entering event queue @ 1704000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1705000004000.  Starting simulation...
+info: Entering event queue @ 1705000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1706000004000.  Starting simulation...
+info: Entering event queue @ 1706000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1707000004000.  Starting simulation...
+info: Entering event queue @ 1707000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1708000004000.  Starting simulation...
+info: Entering event queue @ 1708000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1709000004000.  Starting simulation...
+info: Entering event queue @ 1709000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1710000004000.  Starting simulation...
+info: Entering event queue @ 1710000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1711000004000.  Starting simulation...
+info: Entering event queue @ 1711000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1712000004000.  Starting simulation...
+info: Entering event queue @ 1712000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1713000004000.  Starting simulation...
+info: Entering event queue @ 1713000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1714000004000.  Starting simulation...
+info: Entering event queue @ 1714000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1715000004000.  Starting simulation...
+info: Entering event queue @ 1715000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1716000004000.  Starting simulation...
+info: Entering event queue @ 1716000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1717000004000.  Starting simulation...
+info: Entering event queue @ 1717000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1718000004000.  Starting simulation...
+info: Entering event queue @ 1718000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1719000004000.  Starting simulation...
+info: Entering event queue @ 1719000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1720000004000.  Starting simulation...
+info: Entering event queue @ 1720000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1721000004000.  Starting simulation...
+info: Entering event queue @ 1721000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1722000004000.  Starting simulation...
+info: Entering event queue @ 1722000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1723000004000.  Starting simulation...
+info: Entering event queue @ 1723000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1724000004000.  Starting simulation...
+info: Entering event queue @ 1724000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1725000004000.  Starting simulation...
+info: Entering event queue @ 1725000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1726000004000.  Starting simulation...
+info: Entering event queue @ 1726000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1727000004000.  Starting simulation...
+info: Entering event queue @ 1727000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1728000004000.  Starting simulation...
+info: Entering event queue @ 1728000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1729000004000.  Starting simulation...
+info: Entering event queue @ 1729000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1730000004000.  Starting simulation...
+info: Entering event queue @ 1730000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1731000004000.  Starting simulation...
+info: Entering event queue @ 1731000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1732000004000.  Starting simulation...
+info: Entering event queue @ 1732000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1733000004000.  Starting simulation...
+info: Entering event queue @ 1733000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1734000004000.  Starting simulation...
+info: Entering event queue @ 1734000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1735000004000.  Starting simulation...
+info: Entering event queue @ 1735000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1736000004000.  Starting simulation...
+info: Entering event queue @ 1736000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1737000004000.  Starting simulation...
+info: Entering event queue @ 1737000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1738000004000.  Starting simulation...
+info: Entering event queue @ 1738000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1739000004000.  Starting simulation...
+info: Entering event queue @ 1739000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1740000004000.  Starting simulation...
+info: Entering event queue @ 1740000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1741000004000.  Starting simulation...
+info: Entering event queue @ 1741000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1742000004000.  Starting simulation...
+info: Entering event queue @ 1742000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1743000004000.  Starting simulation...
+info: Entering event queue @ 1743000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1744000004000.  Starting simulation...
+info: Entering event queue @ 1744000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1745000004000.  Starting simulation...
+info: Entering event queue @ 1745000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1746000004000.  Starting simulation...
+info: Entering event queue @ 1746000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1747000004000.  Starting simulation...
+info: Entering event queue @ 1747000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1748000004000.  Starting simulation...
+info: Entering event queue @ 1748000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1749000004000.  Starting simulation...
+info: Entering event queue @ 1749000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1750000004000.  Starting simulation...
+info: Entering event queue @ 1750000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1751000004000.  Starting simulation...
+info: Entering event queue @ 1751000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1752000004000.  Starting simulation...
+info: Entering event queue @ 1752000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1753000004000.  Starting simulation...
+info: Entering event queue @ 1753000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1754000004000.  Starting simulation...
+info: Entering event queue @ 1754000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1755000004000.  Starting simulation...
+info: Entering event queue @ 1755000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1756000004000.  Starting simulation...
+info: Entering event queue @ 1756000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1757000004000.  Starting simulation...
+info: Entering event queue @ 1757000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1758000004000.  Starting simulation...
+info: Entering event queue @ 1758000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1759000004000.  Starting simulation...
+info: Entering event queue @ 1759000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1760000004000.  Starting simulation...
+info: Entering event queue @ 1760000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1761000004000.  Starting simulation...
+info: Entering event queue @ 1761000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1762000004000.  Starting simulation...
+info: Entering event queue @ 1762000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1763000004000.  Starting simulation...
+info: Entering event queue @ 1763000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1764000004000.  Starting simulation...
+info: Entering event queue @ 1764000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1765000004000.  Starting simulation...
+info: Entering event queue @ 1765000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1766000004000.  Starting simulation...
+info: Entering event queue @ 1766000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1767000004000.  Starting simulation...
+info: Entering event queue @ 1767000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1768000004000.  Starting simulation...
+info: Entering event queue @ 1768000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1769000004000.  Starting simulation...
+info: Entering event queue @ 1769000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1770000004000.  Starting simulation...
+info: Entering event queue @ 1770000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1771000004000.  Starting simulation...
+info: Entering event queue @ 1771000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1772000004000.  Starting simulation...
+info: Entering event queue @ 1772000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1773000004000.  Starting simulation...
+info: Entering event queue @ 1773000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1774000004000.  Starting simulation...
+info: Entering event queue @ 1774000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1775000004000.  Starting simulation...
+info: Entering event queue @ 1775000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1776000004000.  Starting simulation...
+info: Entering event queue @ 1776000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1777000004000.  Starting simulation...
+info: Entering event queue @ 1777000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1778000004000.  Starting simulation...
+info: Entering event queue @ 1778000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1779000004000.  Starting simulation...
+info: Entering event queue @ 1779000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1780000004000.  Starting simulation...
+info: Entering event queue @ 1780000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1781000004000.  Starting simulation...
+info: Entering event queue @ 1781000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1782000004000.  Starting simulation...
+info: Entering event queue @ 1782000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1783000004000.  Starting simulation...
+info: Entering event queue @ 1783000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1784000004000.  Starting simulation...
+info: Entering event queue @ 1784000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1785000004000.  Starting simulation...
+info: Entering event queue @ 1785000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1786000004000.  Starting simulation...
+info: Entering event queue @ 1786000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1787000004000.  Starting simulation...
+info: Entering event queue @ 1787000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1788000004000.  Starting simulation...
+info: Entering event queue @ 1788000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1789000004000.  Starting simulation...
+info: Entering event queue @ 1789000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1790000004000.  Starting simulation...
+info: Entering event queue @ 1790000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1791000004000.  Starting simulation...
+info: Entering event queue @ 1791000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1792000004000.  Starting simulation...
+info: Entering event queue @ 1792000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1793000004000.  Starting simulation...
+info: Entering event queue @ 1793000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1794000004000.  Starting simulation...
+info: Entering event queue @ 1794000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1795000004000.  Starting simulation...
+info: Entering event queue @ 1795000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1796000004000.  Starting simulation...
+info: Entering event queue @ 1796000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1797000004000.  Starting simulation...
+info: Entering event queue @ 1797000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1798000004000.  Starting simulation...
+info: Entering event queue @ 1798000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1799000004000.  Starting simulation...
+info: Entering event queue @ 1799000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1800000004000.  Starting simulation...
+info: Entering event queue @ 1800000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1801000004000.  Starting simulation...
+info: Entering event queue @ 1801000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1802000004000.  Starting simulation...
+info: Entering event queue @ 1802000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1803000004000.  Starting simulation...
+info: Entering event queue @ 1803000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1804000004000.  Starting simulation...
+info: Entering event queue @ 1804000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1805000004000.  Starting simulation...
+info: Entering event queue @ 1805000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1806000004000.  Starting simulation...
+info: Entering event queue @ 1806000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1807000004000.  Starting simulation...
+info: Entering event queue @ 1807000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1808000004000.  Starting simulation...
+info: Entering event queue @ 1808000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1809000004000.  Starting simulation...
+info: Entering event queue @ 1809000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1810000004000.  Starting simulation...
+info: Entering event queue @ 1810000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1811000004000.  Starting simulation...
+info: Entering event queue @ 1811000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1812000004000.  Starting simulation...
+info: Entering event queue @ 1812000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1813000004000.  Starting simulation...
+info: Entering event queue @ 1813000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1814000004000.  Starting simulation...
+info: Entering event queue @ 1814000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1815000004000.  Starting simulation...
+info: Entering event queue @ 1815000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1816000004000.  Starting simulation...
+info: Entering event queue @ 1816000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1817000004000.  Starting simulation...
+info: Entering event queue @ 1817000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1818000004000.  Starting simulation...
+info: Entering event queue @ 1818000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1819000004000.  Starting simulation...
+info: Entering event queue @ 1819000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1820000004000.  Starting simulation...
+info: Entering event queue @ 1820000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1821000004000.  Starting simulation...
+info: Entering event queue @ 1821000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1822000004000.  Starting simulation...
+info: Entering event queue @ 1822000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1823000004000.  Starting simulation...
+info: Entering event queue @ 1823000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1824000004000.  Starting simulation...
+info: Entering event queue @ 1824000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1825000004000.  Starting simulation...
+info: Entering event queue @ 1825000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1826000004000.  Starting simulation...
+info: Entering event queue @ 1826000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1827000004000.  Starting simulation...
+info: Entering event queue @ 1827000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1828000004000.  Starting simulation...
+info: Entering event queue @ 1828000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1829000004000.  Starting simulation...
+info: Entering event queue @ 1829000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1830000004000.  Starting simulation...
+info: Entering event queue @ 1830000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1831000004000.  Starting simulation...
+info: Entering event queue @ 1831000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1832000004000.  Starting simulation...
+info: Entering event queue @ 1832000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1833000004000.  Starting simulation...
+info: Entering event queue @ 1833000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1834000004000.  Starting simulation...
+info: Entering event queue @ 1834000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1835000004000.  Starting simulation...
+info: Entering event queue @ 1835000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1836000004000.  Starting simulation...
+info: Entering event queue @ 1836000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1837000004000.  Starting simulation...
+info: Entering event queue @ 1837000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1838000004000.  Starting simulation...
+info: Entering event queue @ 1838000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1839000004000.  Starting simulation...
+info: Entering event queue @ 1839000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1840000004000.  Starting simulation...
+info: Entering event queue @ 1840000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1841000004000.  Starting simulation...
+info: Entering event queue @ 1841000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1842000004000.  Starting simulation...
+info: Entering event queue @ 1842000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1843000004000.  Starting simulation...
+info: Entering event queue @ 1843000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1844000004000.  Starting simulation...
+info: Entering event queue @ 1844000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1845000004000.  Starting simulation...
+info: Entering event queue @ 1845000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1846000004000.  Starting simulation...
+info: Entering event queue @ 1846000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1847000004000.  Starting simulation...
+info: Entering event queue @ 1847000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1848000004000.  Starting simulation...
+info: Entering event queue @ 1848000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1849000004000.  Starting simulation...
+info: Entering event queue @ 1849000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1850000004000.  Starting simulation...
+info: Entering event queue @ 1850000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1851000004000.  Starting simulation...
+info: Entering event queue @ 1851000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1852000004000.  Starting simulation...
+info: Entering event queue @ 1852000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1853000004000.  Starting simulation...
+info: Entering event queue @ 1853000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1854000004000.  Starting simulation...
+info: Entering event queue @ 1854000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1855000004000.  Starting simulation...
+info: Entering event queue @ 1855000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1856000004000.  Starting simulation...
+info: Entering event queue @ 1856000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1857000004000.  Starting simulation...
+info: Entering event queue @ 1857000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1858000004000.  Starting simulation...
+info: Entering event queue @ 1858000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1859000004000.  Starting simulation...
+info: Entering event queue @ 1859000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1860000004000.  Starting simulation...
+info: Entering event queue @ 1860000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1861000004000.  Starting simulation...
+info: Entering event queue @ 1861000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1862000004000.  Starting simulation...
+info: Entering event queue @ 1862000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1863000004000.  Starting simulation...
+info: Entering event queue @ 1863000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1864000004000.  Starting simulation...
+info: Entering event queue @ 1864000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1865000004000.  Starting simulation...
+info: Entering event queue @ 1865000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1866000004000.  Starting simulation...
+info: Entering event queue @ 1866000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1867000004000.  Starting simulation...
+info: Entering event queue @ 1867000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1868000004000.  Starting simulation...
+info: Entering event queue @ 1868000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1869000004000.  Starting simulation...
+info: Entering event queue @ 1869000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1870000004000.  Starting simulation...
+info: Entering event queue @ 1870000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1871000004000.  Starting simulation...
+info: Entering event queue @ 1871000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1872000004000.  Starting simulation...
+info: Entering event queue @ 1872000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1873000004000.  Starting simulation...
+info: Entering event queue @ 1873000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1874000004000.  Starting simulation...
+info: Entering event queue @ 1874000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1875000004000.  Starting simulation...
+info: Entering event queue @ 1875000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1876000004000.  Starting simulation...
+info: Entering event queue @ 1876000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1877000004000.  Starting simulation...
+info: Entering event queue @ 1877000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1878000004000.  Starting simulation...
+info: Entering event queue @ 1878000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1879000004000.  Starting simulation...
+info: Entering event queue @ 1879000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1880000004000.  Starting simulation...
+info: Entering event queue @ 1880000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1881000004000.  Starting simulation...
+info: Entering event queue @ 1881000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1882000004000.  Starting simulation...
+info: Entering event queue @ 1882000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1883000004000.  Starting simulation...
+info: Entering event queue @ 1883000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1884000004000.  Starting simulation...
+info: Entering event queue @ 1884000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1885000004000.  Starting simulation...
+info: Entering event queue @ 1885000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1886000004000.  Starting simulation...
+info: Entering event queue @ 1886000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1887000004000.  Starting simulation...
+info: Entering event queue @ 1887000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1888000004000.  Starting simulation...
+info: Entering event queue @ 1888000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1889000004000.  Starting simulation...
+info: Entering event queue @ 1889000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1890000004000.  Starting simulation...
+info: Entering event queue @ 1890000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1891000004000.  Starting simulation...
+info: Entering event queue @ 1891000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1892000004000.  Starting simulation...
+info: Entering event queue @ 1892000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1893000004000.  Starting simulation...
+info: Entering event queue @ 1893000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1894000004000.  Starting simulation...
+info: Entering event queue @ 1894000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1895000004000.  Starting simulation...
+info: Entering event queue @ 1895000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1896000004000.  Starting simulation...
+info: Entering event queue @ 1896000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1897000004000.  Starting simulation...
+info: Entering event queue @ 1897000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1898000004000.  Starting simulation...
+info: Entering event queue @ 1898000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1899000004000.  Starting simulation...
+info: Entering event queue @ 1899000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1900000004000.  Starting simulation...
+info: Entering event queue @ 1900000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1901000004000.  Starting simulation...
+info: Entering event queue @ 1901000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1902000004000.  Starting simulation...
+info: Entering event queue @ 1902000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1903000004000.  Starting simulation...
+info: Entering event queue @ 1903000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1904000004000.  Starting simulation...
+info: Entering event queue @ 1904000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1905000004000.  Starting simulation...
+info: Entering event queue @ 1905000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1906000004000.  Starting simulation...
+info: Entering event queue @ 1906000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1907000004000.  Starting simulation...
+info: Entering event queue @ 1907000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1908000004000.  Starting simulation...
+info: Entering event queue @ 1908000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1909000004000.  Starting simulation...
+info: Entering event queue @ 1909000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1910000004000.  Starting simulation...
+info: Entering event queue @ 1910000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1911000004000.  Starting simulation...
+info: Entering event queue @ 1911000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1912000004000.  Starting simulation...
+info: Entering event queue @ 1912000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1913000004000.  Starting simulation...
+info: Entering event queue @ 1913000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1914000004000.  Starting simulation...
+info: Entering event queue @ 1914000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1915000004000.  Starting simulation...
+info: Entering event queue @ 1915000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1916000004000.  Starting simulation...
+info: Entering event queue @ 1916000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1917000004000.  Starting simulation...
+info: Entering event queue @ 1917000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1918000004000.  Starting simulation...
+info: Entering event queue @ 1918000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1919000004000.  Starting simulation...
+info: Entering event queue @ 1919000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1920000004000.  Starting simulation...
+info: Entering event queue @ 1920000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1921000004000.  Starting simulation...
+info: Entering event queue @ 1921000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1922000004000.  Starting simulation...
+info: Entering event queue @ 1922000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1923000004000.  Starting simulation...
+info: Entering event queue @ 1923000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1924000004000.  Starting simulation...
+info: Entering event queue @ 1924000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1925000004000.  Starting simulation...
+info: Entering event queue @ 1925000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1926000004000.  Starting simulation...
+info: Entering event queue @ 1926000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1927000004000.  Starting simulation...
+info: Entering event queue @ 1927000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1928000004000.  Starting simulation...
+info: Entering event queue @ 1928000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1929000004000.  Starting simulation...
+info: Entering event queue @ 1929000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1930000004000.  Starting simulation...
+info: Entering event queue @ 1930000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1931000004000.  Starting simulation...
+info: Entering event queue @ 1931000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1932000004000.  Starting simulation...
+info: Entering event queue @ 1932000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1933000004000.  Starting simulation...
+info: Entering event queue @ 1933000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1934000004000.  Starting simulation...
+info: Entering event queue @ 1934000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1935000004000.  Starting simulation...
+info: Entering event queue @ 1935000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1936000004000.  Starting simulation...
+info: Entering event queue @ 1936000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1937000004000.  Starting simulation...
+info: Entering event queue @ 1937000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1938000004000.  Starting simulation...
+info: Entering event queue @ 1938000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1939000004000.  Starting simulation...
+info: Entering event queue @ 1939000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1940000004000.  Starting simulation...
+info: Entering event queue @ 1940000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1941000004000.  Starting simulation...
+info: Entering event queue @ 1941000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1942000004000.  Starting simulation...
+info: Entering event queue @ 1942000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1943000004000.  Starting simulation...
+info: Entering event queue @ 1943000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1944000004000.  Starting simulation...
+info: Entering event queue @ 1944000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1945000004000.  Starting simulation...
+info: Entering event queue @ 1945000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1946000004000.  Starting simulation...
+info: Entering event queue @ 1946000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1947000004000.  Starting simulation...
+info: Entering event queue @ 1947000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1948000004000.  Starting simulation...
+info: Entering event queue @ 1948000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1949000004000.  Starting simulation...
+info: Entering event queue @ 1949000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1950000004000.  Starting simulation...
+info: Entering event queue @ 1950000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1951000004000.  Starting simulation...
+info: Entering event queue @ 1951000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1952000004000.  Starting simulation...
+info: Entering event queue @ 1952000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1953000004000.  Starting simulation...
+info: Entering event queue @ 1953000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1954000004000.  Starting simulation...
+info: Entering event queue @ 1954000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1955000004000.  Starting simulation...
+info: Entering event queue @ 1955000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1956000004000.  Starting simulation...
+info: Entering event queue @ 1956000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1957000004000.  Starting simulation...
+info: Entering event queue @ 1957000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1958000004000.  Starting simulation...
+info: Entering event queue @ 1958000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1959000004000.  Starting simulation...
+info: Entering event queue @ 1959000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1960000004000.  Starting simulation...
+info: Entering event queue @ 1960000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1961000004000.  Starting simulation...
+info: Entering event queue @ 1961000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1962000004000.  Starting simulation...
+info: Entering event queue @ 1962000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1963000004000.  Starting simulation...
+info: Entering event queue @ 1963000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1964000004000.  Starting simulation...
+info: Entering event queue @ 1964000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1965000004000.  Starting simulation...
+info: Entering event queue @ 1965000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1966000004000.  Starting simulation...
+info: Entering event queue @ 1966000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1967000004000.  Starting simulation...
+info: Entering event queue @ 1967000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1968000004000.  Starting simulation...
+info: Entering event queue @ 1968000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1969000004000.  Starting simulation...
+info: Entering event queue @ 1969000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1970000004000.  Starting simulation...
+info: Entering event queue @ 1970000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1971000004000.  Starting simulation...
+info: Entering event queue @ 1971000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1972000004000.  Starting simulation...
+info: Entering event queue @ 1972000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1973000004000.  Starting simulation...
+info: Entering event queue @ 1973000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1974000004000.  Starting simulation...
+info: Entering event queue @ 1974000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1975000004000.  Starting simulation...
+info: Entering event queue @ 1975000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1976000004000.  Starting simulation...
+info: Entering event queue @ 1976000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1977000004000.  Starting simulation...
+info: Entering event queue @ 1977000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1978000004000.  Starting simulation...
+info: Entering event queue @ 1978000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1979000004000.  Starting simulation...
+info: Entering event queue @ 1979000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1980000004000.  Starting simulation...
+info: Entering event queue @ 1980000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1981000004000.  Starting simulation...
+info: Entering event queue @ 1981000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1982000004000.  Starting simulation...
+info: Entering event queue @ 1982000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1983000004000.  Starting simulation...
+info: Entering event queue @ 1983000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1984000004000.  Starting simulation...
+info: Entering event queue @ 1984000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1985000004000.  Starting simulation...
+info: Entering event queue @ 1985000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1986000004000.  Starting simulation...
+info: Entering event queue @ 1986000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1987000004000.  Starting simulation...
+info: Entering event queue @ 1987000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1988000004000.  Starting simulation...
+info: Entering event queue @ 1988000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1989000004000.  Starting simulation...
+info: Entering event queue @ 1989000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1990000004000.  Starting simulation...
+info: Entering event queue @ 1990000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1991000004000.  Starting simulation...
+info: Entering event queue @ 1991000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1992000004000.  Starting simulation...
+info: Entering event queue @ 1992000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1993000004000.  Starting simulation...
+info: Entering event queue @ 1993000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1994000004000.  Starting simulation...
+info: Entering event queue @ 1994000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1995000004000.  Starting simulation...
+info: Entering event queue @ 1995000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1996000004000.  Starting simulation...
+info: Entering event queue @ 1996000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1997000004000.  Starting simulation...
+info: Entering event queue @ 1997000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1998000004000.  Starting simulation...
+info: Entering event queue @ 1998000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 1999000004000.  Starting simulation...
+info: Entering event queue @ 1999000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2000000004000.  Starting simulation...
+info: Entering event queue @ 2000000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2001000004000.  Starting simulation...
+info: Entering event queue @ 2001000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2002000004000.  Starting simulation...
+info: Entering event queue @ 2002000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2003000004000.  Starting simulation...
+info: Entering event queue @ 2003000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2004000004000.  Starting simulation...
+info: Entering event queue @ 2004000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2005000004000.  Starting simulation...
+info: Entering event queue @ 2005000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2006000004000.  Starting simulation...
+info: Entering event queue @ 2006000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2007000004000.  Starting simulation...
+info: Entering event queue @ 2007000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2008000004000.  Starting simulation...
+info: Entering event queue @ 2008000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2009000004000.  Starting simulation...
+info: Entering event queue @ 2009000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2010000004000.  Starting simulation...
+info: Entering event queue @ 2010000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2011000004000.  Starting simulation...
+info: Entering event queue @ 2011000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2012000004000.  Starting simulation...
+info: Entering event queue @ 2012000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2013000004000.  Starting simulation...
+info: Entering event queue @ 2013000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2014000004000.  Starting simulation...
+info: Entering event queue @ 2014000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2015000004000.  Starting simulation...
+info: Entering event queue @ 2015000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2016000004000.  Starting simulation...
+info: Entering event queue @ 2016000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2017000004000.  Starting simulation...
+info: Entering event queue @ 2017000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2018000004000.  Starting simulation...
+info: Entering event queue @ 2018000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2019000004000.  Starting simulation...
+info: Entering event queue @ 2019000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2020000004000.  Starting simulation...
+info: Entering event queue @ 2020000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2021000004000.  Starting simulation...
+info: Entering event queue @ 2021000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2022000004000.  Starting simulation...
+info: Entering event queue @ 2022000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2023000004000.  Starting simulation...
+info: Entering event queue @ 2023000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2024000004000.  Starting simulation...
+info: Entering event queue @ 2024000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2025000004000.  Starting simulation...
+info: Entering event queue @ 2025000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2026000004000.  Starting simulation...
+info: Entering event queue @ 2026000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2027000004000.  Starting simulation...
+info: Entering event queue @ 2027000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2028000004000.  Starting simulation...
+info: Entering event queue @ 2028000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2029000004000.  Starting simulation...
+info: Entering event queue @ 2029000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2030000004000.  Starting simulation...
+info: Entering event queue @ 2030000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2031000004000.  Starting simulation...
+info: Entering event queue @ 2031000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2032000004000.  Starting simulation...
+info: Entering event queue @ 2032000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2033000004000.  Starting simulation...
+info: Entering event queue @ 2033000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2034000004000.  Starting simulation...
+info: Entering event queue @ 2034000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2035000004000.  Starting simulation...
+info: Entering event queue @ 2035000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2036000004000.  Starting simulation...
+info: Entering event queue @ 2036000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2037000004000.  Starting simulation...
+info: Entering event queue @ 2037000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2038000004000.  Starting simulation...
+info: Entering event queue @ 2038000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2039000004000.  Starting simulation...
+info: Entering event queue @ 2039000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2040000004000.  Starting simulation...
+info: Entering event queue @ 2040000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2041000004000.  Starting simulation...
+info: Entering event queue @ 2041000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2042000004000.  Starting simulation...
+info: Entering event queue @ 2042000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2043000004000.  Starting simulation...
+info: Entering event queue @ 2043000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2044000004000.  Starting simulation...
+info: Entering event queue @ 2044000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2045000004000.  Starting simulation...
+info: Entering event queue @ 2045000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2046000004000.  Starting simulation...
+info: Entering event queue @ 2046000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2047000004000.  Starting simulation...
+info: Entering event queue @ 2047000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2048000004000.  Starting simulation...
+info: Entering event queue @ 2048000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2049000004000.  Starting simulation...
+info: Entering event queue @ 2049000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2050000004000.  Starting simulation...
+info: Entering event queue @ 2050000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2051000004000.  Starting simulation...
+info: Entering event queue @ 2051000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2052000004000.  Starting simulation...
+info: Entering event queue @ 2052000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2053000004000.  Starting simulation...
+info: Entering event queue @ 2053000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2054000004000.  Starting simulation...
+info: Entering event queue @ 2054000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2055000004000.  Starting simulation...
+info: Entering event queue @ 2055000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2056000004000.  Starting simulation...
+info: Entering event queue @ 2056000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2057000004000.  Starting simulation...
+info: Entering event queue @ 2057000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2058000004000.  Starting simulation...
+info: Entering event queue @ 2058000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2059000004000.  Starting simulation...
+info: Entering event queue @ 2059000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2060000004000.  Starting simulation...
+info: Entering event queue @ 2060000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2061000004000.  Starting simulation...
+info: Entering event queue @ 2061000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2062000004000.  Starting simulation...
+info: Entering event queue @ 2062000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2063000004000.  Starting simulation...
+info: Entering event queue @ 2063000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2064000004000.  Starting simulation...
+info: Entering event queue @ 2064000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2065000004000.  Starting simulation...
+info: Entering event queue @ 2065000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2066000004000.  Starting simulation...
+info: Entering event queue @ 2066000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2067000004000.  Starting simulation...
+info: Entering event queue @ 2067000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2068000004000.  Starting simulation...
+info: Entering event queue @ 2068000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2069000004000.  Starting simulation...
+info: Entering event queue @ 2069000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2070000004000.  Starting simulation...
+info: Entering event queue @ 2070000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2071000004000.  Starting simulation...
+info: Entering event queue @ 2071000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2072000004000.  Starting simulation...
+info: Entering event queue @ 2072000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2073000004000.  Starting simulation...
+info: Entering event queue @ 2073000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2074000004000.  Starting simulation...
+info: Entering event queue @ 2074000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2075000004000.  Starting simulation...
+info: Entering event queue @ 2075000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2076000004000.  Starting simulation...
+info: Entering event queue @ 2076000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2077000004000.  Starting simulation...
+info: Entering event queue @ 2077000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2078000004000.  Starting simulation...
+info: Entering event queue @ 2078000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2079000004000.  Starting simulation...
+info: Entering event queue @ 2079000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2080000004000.  Starting simulation...
+info: Entering event queue @ 2080000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2081000004000.  Starting simulation...
+info: Entering event queue @ 2081000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2082000004000.  Starting simulation...
+info: Entering event queue @ 2082000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2083000004000.  Starting simulation...
+info: Entering event queue @ 2083000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2084000004000.  Starting simulation...
+info: Entering event queue @ 2084000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2085000004000.  Starting simulation...
+info: Entering event queue @ 2085000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2086000004000.  Starting simulation...
+info: Entering event queue @ 2086000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2087000004000.  Starting simulation...
+info: Entering event queue @ 2087000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2088000004000.  Starting simulation...
+info: Entering event queue @ 2088000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2089000004000.  Starting simulation...
+info: Entering event queue @ 2089000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2090000004000.  Starting simulation...
+info: Entering event queue @ 2090000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2091000004000.  Starting simulation...
+info: Entering event queue @ 2091000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2092000004000.  Starting simulation...
+info: Entering event queue @ 2092000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2093000004000.  Starting simulation...
+info: Entering event queue @ 2093000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2094000004000.  Starting simulation...
+info: Entering event queue @ 2094000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2095000004000.  Starting simulation...
+info: Entering event queue @ 2095000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2096000004000.  Starting simulation...
+info: Entering event queue @ 2096000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2097000004000.  Starting simulation...
+info: Entering event queue @ 2097000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2098000004000.  Starting simulation...
+info: Entering event queue @ 2098000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2099000004000.  Starting simulation...
+info: Entering event queue @ 2099000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2100000004000.  Starting simulation...
+info: Entering event queue @ 2100000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2101000004000.  Starting simulation...
+info: Entering event queue @ 2101000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2102000004000.  Starting simulation...
+info: Entering event queue @ 2102000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2103000004000.  Starting simulation...
+info: Entering event queue @ 2103000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2104000004000.  Starting simulation...
+info: Entering event queue @ 2104000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2105000004000.  Starting simulation...
+info: Entering event queue @ 2105000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2106000004000.  Starting simulation...
+info: Entering event queue @ 2106000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2107000004000.  Starting simulation...
+info: Entering event queue @ 2107000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2108000004000.  Starting simulation...
+info: Entering event queue @ 2108000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2109000004000.  Starting simulation...
+info: Entering event queue @ 2109000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2110000004000.  Starting simulation...
+info: Entering event queue @ 2110000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2111000004000.  Starting simulation...
+info: Entering event queue @ 2111000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2112000004000.  Starting simulation...
+info: Entering event queue @ 2112000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2113000004000.  Starting simulation...
+info: Entering event queue @ 2113000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2114000004000.  Starting simulation...
+info: Entering event queue @ 2114000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2115000004000.  Starting simulation...
+info: Entering event queue @ 2115000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2116000004000.  Starting simulation...
+info: Entering event queue @ 2116000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2117000004000.  Starting simulation...
+info: Entering event queue @ 2117000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2118000004000.  Starting simulation...
+info: Entering event queue @ 2118000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2119000004000.  Starting simulation...
+info: Entering event queue @ 2119000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2120000004000.  Starting simulation...
+info: Entering event queue @ 2120000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2121000004000.  Starting simulation...
+info: Entering event queue @ 2121000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2122000004000.  Starting simulation...
+info: Entering event queue @ 2122000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2123000004000.  Starting simulation...
+info: Entering event queue @ 2123000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2124000004000.  Starting simulation...
+info: Entering event queue @ 2124000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2125000004000.  Starting simulation...
+info: Entering event queue @ 2125000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2126000004000.  Starting simulation...
+info: Entering event queue @ 2126000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2127000004000.  Starting simulation...
+info: Entering event queue @ 2127000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2128000004000.  Starting simulation...
+info: Entering event queue @ 2128000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2129000004000.  Starting simulation...
+info: Entering event queue @ 2129000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2130000004000.  Starting simulation...
+info: Entering event queue @ 2130000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2131000004000.  Starting simulation...
+info: Entering event queue @ 2131000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2132000004000.  Starting simulation...
+info: Entering event queue @ 2132000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2133000004000.  Starting simulation...
+info: Entering event queue @ 2133000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2134000004000.  Starting simulation...
+info: Entering event queue @ 2134000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2135000004000.  Starting simulation...
+info: Entering event queue @ 2135000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2136000004000.  Starting simulation...
+info: Entering event queue @ 2136000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2137000004000.  Starting simulation...
+info: Entering event queue @ 2137000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2138000004000.  Starting simulation...
+info: Entering event queue @ 2138000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2139000004000.  Starting simulation...
+info: Entering event queue @ 2139000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2140000004000.  Starting simulation...
+info: Entering event queue @ 2140000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2141000004000.  Starting simulation...
+info: Entering event queue @ 2141000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2142000004000.  Starting simulation...
+info: Entering event queue @ 2142000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2143000004000.  Starting simulation...
+info: Entering event queue @ 2143000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2144000004000.  Starting simulation...
+info: Entering event queue @ 2144000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2145000004000.  Starting simulation...
+info: Entering event queue @ 2145000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2146000004000.  Starting simulation...
+info: Entering event queue @ 2146000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2147000004000.  Starting simulation...
+info: Entering event queue @ 2147000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2148000004000.  Starting simulation...
+info: Entering event queue @ 2148000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2149000004000.  Starting simulation...
+info: Entering event queue @ 2149000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2150000004000.  Starting simulation...
+info: Entering event queue @ 2150000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2151000004000.  Starting simulation...
+info: Entering event queue @ 2151000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2152000004000.  Starting simulation...
+info: Entering event queue @ 2152000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2153000004000.  Starting simulation...
+info: Entering event queue @ 2153000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2154000004000.  Starting simulation...
+info: Entering event queue @ 2154000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2155000004000.  Starting simulation...
+info: Entering event queue @ 2155000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2156000004000.  Starting simulation...
+info: Entering event queue @ 2156000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2157000004000.  Starting simulation...
+info: Entering event queue @ 2157000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2158000004000.  Starting simulation...
+info: Entering event queue @ 2158000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2159000004000.  Starting simulation...
+info: Entering event queue @ 2159000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2160000004000.  Starting simulation...
+info: Entering event queue @ 2160000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2161000004000.  Starting simulation...
+info: Entering event queue @ 2161000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2162000004000.  Starting simulation...
+info: Entering event queue @ 2162000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2163000004000.  Starting simulation...
+info: Entering event queue @ 2163000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2164000004000.  Starting simulation...
+info: Entering event queue @ 2164000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2165000004000.  Starting simulation...
+info: Entering event queue @ 2165000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2166000004000.  Starting simulation...
+info: Entering event queue @ 2166000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2167000004000.  Starting simulation...
+info: Entering event queue @ 2167000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2168000004000.  Starting simulation...
+info: Entering event queue @ 2168000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2169000004000.  Starting simulation...
+info: Entering event queue @ 2169000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2170000004000.  Starting simulation...
+info: Entering event queue @ 2170000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2171000004000.  Starting simulation...
+info: Entering event queue @ 2171000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2172000004000.  Starting simulation...
+info: Entering event queue @ 2172000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2173000004000.  Starting simulation...
+info: Entering event queue @ 2173000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2174000004000.  Starting simulation...
+info: Entering event queue @ 2174000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2175000004000.  Starting simulation...
+info: Entering event queue @ 2175000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2176000004000.  Starting simulation...
+info: Entering event queue @ 2176000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2177000004000.  Starting simulation...
+info: Entering event queue @ 2177000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2178000004000.  Starting simulation...
+info: Entering event queue @ 2178000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2179000004000.  Starting simulation...
+info: Entering event queue @ 2179000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2180000004000.  Starting simulation...
+info: Entering event queue @ 2180000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2181000004000.  Starting simulation...
+info: Entering event queue @ 2181000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2182000004000.  Starting simulation...
+info: Entering event queue @ 2182000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2183000004000.  Starting simulation...
+info: Entering event queue @ 2183000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2184000004000.  Starting simulation...
+info: Entering event queue @ 2184000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2185000004000.  Starting simulation...
+info: Entering event queue @ 2185000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2186000004000.  Starting simulation...
+info: Entering event queue @ 2186000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2187000004000.  Starting simulation...
+info: Entering event queue @ 2187000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2188000004000.  Starting simulation...
+info: Entering event queue @ 2188000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2189000004000.  Starting simulation...
+info: Entering event queue @ 2189000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2190000004000.  Starting simulation...
+info: Entering event queue @ 2190000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2191000004000.  Starting simulation...
+info: Entering event queue @ 2191000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2192000004000.  Starting simulation...
+info: Entering event queue @ 2192000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2193000004000.  Starting simulation...
+info: Entering event queue @ 2193000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2194000004000.  Starting simulation...
+info: Entering event queue @ 2194000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2195000004000.  Starting simulation...
+info: Entering event queue @ 2195000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2196000004000.  Starting simulation...
+info: Entering event queue @ 2196000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2197000004000.  Starting simulation...
+info: Entering event queue @ 2197000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2198000004000.  Starting simulation...
+info: Entering event queue @ 2198000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2199000004000.  Starting simulation...
+info: Entering event queue @ 2199000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2200000004000.  Starting simulation...
+info: Entering event queue @ 2200000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2201000004000.  Starting simulation...
+info: Entering event queue @ 2201000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2202000004000.  Starting simulation...
+info: Entering event queue @ 2202000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2203000004000.  Starting simulation...
+info: Entering event queue @ 2203000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2204000004000.  Starting simulation...
+info: Entering event queue @ 2204000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2205000004000.  Starting simulation...
+info: Entering event queue @ 2205000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2206000004000.  Starting simulation...
+info: Entering event queue @ 2206000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2207000004000.  Starting simulation...
+info: Entering event queue @ 2207000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2208000004000.  Starting simulation...
+info: Entering event queue @ 2208000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2209000004000.  Starting simulation...
+info: Entering event queue @ 2209000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2210000004000.  Starting simulation...
+info: Entering event queue @ 2210000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2211000004000.  Starting simulation...
+info: Entering event queue @ 2211000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2212000004000.  Starting simulation...
+info: Entering event queue @ 2212000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2213000004000.  Starting simulation...
+info: Entering event queue @ 2213000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2214000004000.  Starting simulation...
+info: Entering event queue @ 2214000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2215000004000.  Starting simulation...
+info: Entering event queue @ 2215000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2216000004000.  Starting simulation...
+info: Entering event queue @ 2216000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2217000004000.  Starting simulation...
+info: Entering event queue @ 2217000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2218000004000.  Starting simulation...
+info: Entering event queue @ 2218000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2219000004000.  Starting simulation...
+info: Entering event queue @ 2219000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2220000004000.  Starting simulation...
+info: Entering event queue @ 2220000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2221000004000.  Starting simulation...
+info: Entering event queue @ 2221000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2222000004000.  Starting simulation...
+info: Entering event queue @ 2222000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2223000004000.  Starting simulation...
+info: Entering event queue @ 2223000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2224000004000.  Starting simulation...
+info: Entering event queue @ 2224000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2225000004000.  Starting simulation...
+info: Entering event queue @ 2225000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2226000004000.  Starting simulation...
+info: Entering event queue @ 2226000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2227000004000.  Starting simulation...
+info: Entering event queue @ 2227000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2228000004000.  Starting simulation...
+info: Entering event queue @ 2228000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2229000004000.  Starting simulation...
+info: Entering event queue @ 2229000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2230000004000.  Starting simulation...
+info: Entering event queue @ 2230000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2231000004000.  Starting simulation...
+info: Entering event queue @ 2231000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2232000004000.  Starting simulation...
+info: Entering event queue @ 2232000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2233000004000.  Starting simulation...
+info: Entering event queue @ 2233000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2234000004000.  Starting simulation...
+info: Entering event queue @ 2234000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2235000004000.  Starting simulation...
+info: Entering event queue @ 2235000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2236000004000.  Starting simulation...
+info: Entering event queue @ 2236000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2237000004000.  Starting simulation...
+info: Entering event queue @ 2237000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2238000004000.  Starting simulation...
+info: Entering event queue @ 2238000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2239000004000.  Starting simulation...
+info: Entering event queue @ 2239000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2240000004000.  Starting simulation...
+info: Entering event queue @ 2240000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2241000004000.  Starting simulation...
+info: Entering event queue @ 2241000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2242000004000.  Starting simulation...
+info: Entering event queue @ 2242000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2243000004000.  Starting simulation...
+info: Entering event queue @ 2243000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2244000004000.  Starting simulation...
+info: Entering event queue @ 2244000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2245000004000.  Starting simulation...
+info: Entering event queue @ 2245000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2246000004000.  Starting simulation...
+info: Entering event queue @ 2246000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2247000004000.  Starting simulation...
+info: Entering event queue @ 2247000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2248000004000.  Starting simulation...
+info: Entering event queue @ 2248000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2249000004000.  Starting simulation...
+info: Entering event queue @ 2249000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2250000004000.  Starting simulation...
+info: Entering event queue @ 2250000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2251000004000.  Starting simulation...
+info: Entering event queue @ 2251000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2252000004000.  Starting simulation...
+info: Entering event queue @ 2252000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2253000004000.  Starting simulation...
+info: Entering event queue @ 2253000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2254000004000.  Starting simulation...
+info: Entering event queue @ 2254000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2255000004000.  Starting simulation...
+info: Entering event queue @ 2255000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2256000004000.  Starting simulation...
+info: Entering event queue @ 2256000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2257000004000.  Starting simulation...
+info: Entering event queue @ 2257000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2258000004000.  Starting simulation...
+info: Entering event queue @ 2258000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2259000004000.  Starting simulation...
+info: Entering event queue @ 2259000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2260000004000.  Starting simulation...
+info: Entering event queue @ 2260000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2261000004000.  Starting simulation...
+info: Entering event queue @ 2261000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2262000004000.  Starting simulation...
+info: Entering event queue @ 2262000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2263000004000.  Starting simulation...
+info: Entering event queue @ 2263000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2264000004000.  Starting simulation...
+info: Entering event queue @ 2264000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2265000004000.  Starting simulation...
+info: Entering event queue @ 2265000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2266000004000.  Starting simulation...
+info: Entering event queue @ 2266000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2267000004000.  Starting simulation...
+info: Entering event queue @ 2267000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2268000004000.  Starting simulation...
+info: Entering event queue @ 2268000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2269000004000.  Starting simulation...
+info: Entering event queue @ 2269000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2270000004000.  Starting simulation...
+info: Entering event queue @ 2270000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2271000004000.  Starting simulation...
+info: Entering event queue @ 2271000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2272000004000.  Starting simulation...
+info: Entering event queue @ 2272000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2273000004000.  Starting simulation...
+info: Entering event queue @ 2273000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2274000004000.  Starting simulation...
+info: Entering event queue @ 2274000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2275000004000.  Starting simulation...
+info: Entering event queue @ 2275000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2276000004000.  Starting simulation...
+info: Entering event queue @ 2276000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2277000004000.  Starting simulation...
+info: Entering event queue @ 2277000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2278000004000.  Starting simulation...
+info: Entering event queue @ 2278000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2279000004000.  Starting simulation...
+info: Entering event queue @ 2279000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2280000004000.  Starting simulation...
+info: Entering event queue @ 2280000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2281000004000.  Starting simulation...
+info: Entering event queue @ 2281000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2282000004000.  Starting simulation...
+info: Entering event queue @ 2282000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2283000004000.  Starting simulation...
+info: Entering event queue @ 2283000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2284000004000.  Starting simulation...
+info: Entering event queue @ 2284000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2285000004000.  Starting simulation...
+info: Entering event queue @ 2285000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2286000004000.  Starting simulation...
+info: Entering event queue @ 2286000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2287000004000.  Starting simulation...
+info: Entering event queue @ 2287000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2288000004000.  Starting simulation...
+info: Entering event queue @ 2288000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2289000004000.  Starting simulation...
+info: Entering event queue @ 2289000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2290000004000.  Starting simulation...
+info: Entering event queue @ 2290000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2291000004000.  Starting simulation...
+info: Entering event queue @ 2291000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2292000004000.  Starting simulation...
+info: Entering event queue @ 2292000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2293000004000.  Starting simulation...
+info: Entering event queue @ 2293000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2294000004000.  Starting simulation...
+info: Entering event queue @ 2294000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2295000004000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2295000006000.  Starting simulation...
+info: Entering event queue @ 2295000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2296000006000.  Starting simulation...
+info: Entering event queue @ 2296000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2297000006000.  Starting simulation...
+info: Entering event queue @ 2297000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2298000006000.  Starting simulation...
+info: Entering event queue @ 2298000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2299000006000.  Starting simulation...
+info: Entering event queue @ 2299000013500.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2300000013500.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2300000006000.  Starting simulation...
+info: Entering event queue @ 2300000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2301000006000.  Starting simulation...
+info: Entering event queue @ 2301000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2302000006000.  Starting simulation...
+info: Entering event queue @ 2302000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2303000006000.  Starting simulation...
+info: Entering event queue @ 2303000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2304000006000.  Starting simulation...
+info: Entering event queue @ 2304000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2305000006000.  Starting simulation...
+info: Entering event queue @ 2305000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2306000006000.  Starting simulation...
+info: Entering event queue @ 2306000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2307000006000.  Starting simulation...
+info: Entering event queue @ 2307000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2308000006000.  Starting simulation...
+info: Entering event queue @ 2308000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2309000006000.  Starting simulation...
+info: Entering event queue @ 2309000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2310000006000.  Starting simulation...
+info: Entering event queue @ 2310000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2311000006000.  Starting simulation...
+info: Entering event queue @ 2311000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2312000006000.  Starting simulation...
+info: Entering event queue @ 2312000016000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
-info: Entering event queue @ 2313000006000.  Starting simulation...
+info: Entering event queue @ 2313000016000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2313000010500.  Starting simulation...
+info: Entering event queue @ 2313000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2314000010500.  Starting simulation...
+info: Entering event queue @ 2314000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2315000010500.  Starting simulation...
+info: Entering event queue @ 2315000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2316000010500.  Starting simulation...
+info: Entering event queue @ 2316000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2317000010500.  Starting simulation...
+info: Entering event queue @ 2317000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2318000010500.  Starting simulation...
+info: Entering event queue @ 2318000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2319000010500.  Starting simulation...
+info: Entering event queue @ 2319000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2320000010500.  Starting simulation...
+info: Entering event queue @ 2320000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2321000010500.  Starting simulation...
+info: Entering event queue @ 2321000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2322000010500.  Starting simulation...
+info: Entering event queue @ 2322000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2323000010500.  Starting simulation...
+info: Entering event queue @ 2323000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2324000010500.  Starting simulation...
+info: Entering event queue @ 2324000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2325000010500.  Starting simulation...
+info: Entering event queue @ 2325000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2326000010500.  Starting simulation...
+info: Entering event queue @ 2326000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2327000010500.  Starting simulation...
+info: Entering event queue @ 2327000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2328000010500.  Starting simulation...
+info: Entering event queue @ 2328000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2329000010500.  Starting simulation...
+info: Entering event queue @ 2329000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2330000010500.  Starting simulation...
+info: Entering event queue @ 2330000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
 switching cpus
-info: Entering event queue @ 2331000010500.  Starting simulation...
+info: Entering event queue @ 2331000020000.  Starting simulation...
 Switching CPUs...
 Next CPU: AtomicSimpleCPU
+info: Entering event queue @ 2332000020000.  Starting simulation...
 switching cpus
-info: Entering event queue @ 2332000010500.  Starting simulation...
+info: Entering event queue @ 2332000020500.  Starting simulation...
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
index 33d5e9d03..e70b188fa 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/config.ini
@@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table
+children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain
 acpi_description_table_pointer=system.acpi_description_table_pointer
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=atomic
 mem_ranges=0:134217727
@@ -53,7 +54,7 @@ oem_table_id=
 
 [system.apicbridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=11529215046068469760:11529215046068473855
 req_size=16
@@ -63,20 +64,24 @@ slave=system.iobus.master[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
-slave=system.membus.master[1]
+slave=system.membus.master[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
 
 [system.cpu]
 type=AtomicSimpleCPU
-children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
-branchPred=Null
+children=apic_clk_domain dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -95,6 +100,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -105,12 +114,17 @@ workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -121,12 +135,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -135,16 +158,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.dtb_walker_cache.cpu_side
 
 [system.cpu.dtb_walker_cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -155,18 +179,27 @@ prefetcher=Null
 response_latency=2
 size=1024
 system=system
+tags=system.cpu.dtb_walker_cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dtb.walker.port
 mem_side=system.cpu.toL2Bus.slave[3]
 
+[system.cpu.dtb_walker_cache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=1024
+
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -177,22 +210,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
 system=system
 int_master=system.membus.slave[3]
-int_slave=system.membus.master[3]
-pio=system.membus.master[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
@@ -205,16 +247,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.itb_walker_cache.cpu_side
 
 [system.cpu.itb_walker_cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -225,18 +268,27 @@ prefetcher=Null
 response_latency=2
 size=1024
 system=system
+tags=system.cpu.itb_walker_cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.itb.walker.port
 mem_side=system.cpu.toL2Bus.slave[2]
 
+[system.cpu.itb_walker_cache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=1024
+
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -247,16 +299,24 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -267,6 +327,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.e820_table]
 type=X86E820Table
 children=entries0 entries1 entries2
@@ -638,8 +703,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -649,10 +713,10 @@ slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -663,28 +727,36 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[18]
 mem_side=system.membus.slave[4]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
 slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -707,7 +779,7 @@ system=system
 
 [system.pc.behind_pci]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854779128
 pio_latency=100000
@@ -725,7 +797,7 @@ pio=system.iobus.master[12]
 [system.pc.com_1]
 type=Uart8250
 children=terminal
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=9223372036854776824
 pio_latency=100000
 platform=system.pc
@@ -749,7 +821,7 @@ port=3456
 
 [system.pc.fake_com_2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776568
 pio_latency=100000
@@ -766,7 +838,7 @@ pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776808
 pio_latency=100000
@@ -783,7 +855,7 @@ pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776552
 pio_latency=100000
@@ -800,7 +872,7 @@ pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776818
 pio_latency=100000
@@ -817,7 +889,7 @@ pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854775936
 pio_latency=100000
@@ -835,7 +907,8 @@ pio=system.iobus.master[11]
 [system.pc.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.pc
 size=16777216
@@ -858,7 +931,7 @@ speaker=system.pc.south_bridge.speaker
 [system.pc.south_bridge.cmos]
 type=Cmos
 children=int_pin
-clock=1000
+clk_domain=system.clk_domain
 int_pin=system.pc.south_bridge.cmos.int_pin
 pio_addr=9223372036854775920
 pio_latency=100000
@@ -871,7 +944,7 @@ type=X86IntSourcePin
 
 [system.pc.south_bridge.dma1]
 type=I8237
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=9223372036854775808
 pio_latency=100000
 system=system
@@ -918,7 +991,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
@@ -950,7 +1023,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -970,7 +1043,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1053,7 +1126,7 @@ number=12
 [system.pc.south_bridge.io_apic]
 type=I82094AA
 apic_id=1
-clock=1000
+clk_domain=system.clk_domain
 external_int_pic=system.pc.south_bridge.pic1
 int_latency=1000
 pio_addr=4273995776
@@ -1065,7 +1138,7 @@ pio=system.iobus.master[10]
 [system.pc.south_bridge.keyboard]
 type=I8042
 children=keyboard_int_pin mouse_int_pin
-clock=1000
+clk_domain=system.clk_domain
 command_port=9223372036854775908
 data_port=9223372036854775904
 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
@@ -1084,7 +1157,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pic1]
 type=I8259
 children=output
-clock=1000
+clk_domain=system.clk_domain
 mode=I8259Master
 output=system.pc.south_bridge.pic1.output
 pio_addr=9223372036854775840
@@ -1099,7 +1172,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pic2]
 type=I8259
 children=output
-clock=1000
+clk_domain=system.clk_domain
 mode=I8259Slave
 output=system.pc.south_bridge.pic2.output
 pio_addr=9223372036854775968
@@ -1114,7 +1187,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pit]
 type=I8254
 children=int_pin
-clock=1000
+clk_domain=system.clk_domain
 int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=100000
@@ -1126,7 +1199,7 @@ type=X86IntSourcePin
 
 [system.pc.south_bridge.speaker]
 type=PcSpeaker
-clock=1000
+clk_domain=system.clk_domain
 i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=100000
@@ -1136,19 +1209,24 @@ pio=system.iobus.master[9]
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -1159,8 +1237,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[0]
+port=system.membus.master[3]
 
 [system.smbios_table]
 type=X86SMBiosSMBiosTable
@@ -1183,3 +1260,7 @@ starting_addr_segment=0
 vendor=
 version=
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
index 451dd9824..2013fc7c1 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-atomic/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 18 2013 13:37:41
-gem5 started Apr 18 2013 14:20:21
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 07:08:04
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5112099861500 because m5_exit instruction encountered
+Exiting @ tick 5112102211000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
index 640918742..032606990 100644
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/config.ini
@@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=LinuxX86System
-children=acpi_description_table_pointer apicbridge bridge cpu e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table
+children=acpi_description_table_pointer apicbridge bridge clk_domain cpu cpu_clk_domain e820_table intel_mp_pointer intel_mp_table intrctrl iobus iocache membus pc physmem smbios_table voltage_domain
 acpi_description_table_pointer=system.acpi_description_table_pointer
 boot_osflags=earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 e820_table=system.e820_table
 init_param=0
 intel_mp_pointer=system.intel_mp_pointer
 intel_mp_table=system.intel_mp_table
-kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+kernel=/dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
 load_addr_mask=18446744073709551615
 mem_mode=timing
 mem_ranges=0:134217727
@@ -53,7 +54,7 @@ oem_table_id=
 
 [system.apicbridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=11529215046068469760:11529215046068473855
 req_size=16
@@ -63,20 +64,24 @@ slave=system.iobus.master[0]
 
 [system.bridge]
 type=Bridge
-clock=1000
+clk_domain=system.clk_domain
 delay=50000
 ranges=4273995776:4273999871 9223372036854775808:11529215046068469759 13835058055282163712:18446744073709551615
 req_size=16
 resp_size=16
 master=system.iobus.slave[0]
-slave=system.membus.master[1]
+slave=system.membus.master[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
 
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
-branchPred=Null
+children=apic_clk_domain dcache dtb dtb_walker_cache icache interrupts isa itb itb_walker_cache l2cache toL2Bus tracer
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -94,6 +99,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -101,12 +107,17 @@ workload=
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -117,12 +128,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -131,16 +151,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.dtb_walker_cache.cpu_side
 
 [system.cpu.dtb_walker_cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -151,18 +172,27 @@ prefetcher=Null
 response_latency=2
 size=1024
 system=system
+tags=system.cpu.dtb_walker_cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dtb.walker.port
 mem_side=system.cpu.toL2Bus.slave[3]
 
+[system.cpu.dtb_walker_cache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=1024
+
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -173,22 +203,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
 system=system
 int_master=system.membus.slave[3]
-int_slave=system.membus.master[3]
-pio=system.membus.master[2]
+int_slave=system.membus.master[2]
+pio=system.membus.master[1]
 
 [system.cpu.isa]
 type=X86ISA
@@ -201,16 +240,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.itb_walker_cache.cpu_side
 
 [system.cpu.itb_walker_cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -221,18 +261,27 @@ prefetcher=Null
 response_latency=2
 size=1024
 system=system
+tags=system.cpu.itb_walker_cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.itb.walker.port
 mem_side=system.cpu.toL2Bus.slave[2]
 
+[system.cpu.itb_walker_cache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=1024
+
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -243,16 +292,24 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[2]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -263,6 +320,11 @@ slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb_walke
 [system.cpu.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.e820_table]
 type=X86E820Table
 children=entries0 entries1 entries2
@@ -634,8 +696,7 @@ sys=system
 
 [system.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -645,10 +706,10 @@ slave=system.bridge.master system.pc.south_bridge.ide.dma system.pc.south_bridge
 
 [system.iocache]
 type=BaseCache
+children=tags
 addr_ranges=0:134217727
 assoc=8
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 forward_snoops=false
 hit_latency=50
 is_top_level=true
@@ -659,28 +720,36 @@ prefetcher=Null
 response_latency=50
 size=1024
 system=system
+tags=system.iocache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.iobus.master[18]
 mem_side=system.membus.slave[4]
 
+[system.iocache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.clk_domain
+hit_latency=50
+size=1024
+
 [system.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 default=system.membus.badaddr_responder.pio
-master=system.physmem.port system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave
+master=system.bridge.slave system.cpu.interrupts.pio system.cpu.interrupts.int_slave system.physmem.port
 slave=system.apicbridge.master system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_master system.iocache.mem_side
 
 [system.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -703,7 +772,7 @@ system=system
 
 [system.pc.behind_pci]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854779128
 pio_latency=100000
@@ -721,7 +790,7 @@ pio=system.iobus.master[12]
 [system.pc.com_1]
 type=Uart8250
 children=terminal
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=9223372036854776824
 pio_latency=100000
 platform=system.pc
@@ -745,7 +814,7 @@ port=3456
 
 [system.pc.fake_com_2]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776568
 pio_latency=100000
@@ -762,7 +831,7 @@ pio=system.iobus.master[14]
 
 [system.pc.fake_com_3]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776808
 pio_latency=100000
@@ -779,7 +848,7 @@ pio=system.iobus.master[15]
 
 [system.pc.fake_com_4]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776552
 pio_latency=100000
@@ -796,7 +865,7 @@ pio=system.iobus.master[16]
 
 [system.pc.fake_floppy]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854776818
 pio_latency=100000
@@ -813,7 +882,7 @@ pio=system.iobus.master[17]
 
 [system.pc.i_dont_exist]
 type=IsaFake
-clock=1000
+clk_domain=system.clk_domain
 fake_mem=false
 pio_addr=9223372036854775936
 pio_latency=100000
@@ -831,7 +900,8 @@ pio=system.iobus.master[11]
 [system.pc.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=system.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=system.pc
 size=16777216
@@ -854,7 +924,7 @@ speaker=system.pc.south_bridge.speaker
 [system.pc.south_bridge.cmos]
 type=Cmos
 children=int_pin
-clock=1000
+clk_domain=system.clk_domain
 int_pin=system.pc.south_bridge.cmos.int_pin
 pio_addr=9223372036854775920
 pio_latency=100000
@@ -867,7 +937,7 @@ type=X86IntSourcePin
 
 [system.pc.south_bridge.dma1]
 type=I8237
-clock=1000
+clk_domain=system.clk_domain
 pio_addr=9223372036854775808
 pio_latency=100000
 system=system
@@ -914,7 +984,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=system.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=system.pc.south_bridge.ide.disks0 system.pc.south_bridge.ide.disks1
@@ -946,7 +1016,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/dist/m5/system/disks/linux-x86.img
 read_only=true
 
 [system.pc.south_bridge.ide.disks1]
@@ -966,7 +1036,7 @@ table_size=65536
 
 [system.pc.south_bridge.ide.disks1.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [system.pc.south_bridge.int_lines0]
@@ -1049,7 +1119,7 @@ number=12
 [system.pc.south_bridge.io_apic]
 type=I82094AA
 apic_id=1
-clock=1000
+clk_domain=system.clk_domain
 external_int_pic=system.pc.south_bridge.pic1
 int_latency=1000
 pio_addr=4273995776
@@ -1061,7 +1131,7 @@ pio=system.iobus.master[10]
 [system.pc.south_bridge.keyboard]
 type=I8042
 children=keyboard_int_pin mouse_int_pin
-clock=1000
+clk_domain=system.clk_domain
 command_port=9223372036854775908
 data_port=9223372036854775904
 keyboard_int_pin=system.pc.south_bridge.keyboard.keyboard_int_pin
@@ -1080,7 +1150,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pic1]
 type=I8259
 children=output
-clock=1000
+clk_domain=system.clk_domain
 mode=I8259Master
 output=system.pc.south_bridge.pic1.output
 pio_addr=9223372036854775840
@@ -1095,7 +1165,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pic2]
 type=I8259
 children=output
-clock=1000
+clk_domain=system.clk_domain
 mode=I8259Slave
 output=system.pc.south_bridge.pic2.output
 pio_addr=9223372036854775968
@@ -1110,7 +1180,7 @@ type=X86IntSourcePin
 [system.pc.south_bridge.pit]
 type=I8254
 children=int_pin
-clock=1000
+clk_domain=system.clk_domain
 int_pin=system.pc.south_bridge.pit.int_pin
 pio_addr=9223372036854775872
 pio_latency=100000
@@ -1122,7 +1192,7 @@ type=X86IntSourcePin
 
 [system.pc.south_bridge.speaker]
 type=PcSpeaker
-clock=1000
+clk_domain=system.clk_domain
 i8254=system.pc.south_bridge.pit
 pio_addr=9223372036854775905
 pio_latency=100000
@@ -1132,19 +1202,24 @@ pio=system.iobus.master[9]
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -1155,8 +1230,7 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
-port=system.membus.master[0]
+port=system.membus.master[3]
 
 [system.smbios_table]
 type=X86SMBiosSMBiosTable
@@ -1179,3 +1253,7 @@ starting_addr_segment=0
 vendor=
 version=
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
index c33799826..00f397a8d 100755
--- a/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
+++ b/tests/quick/fs/10.linux-boot/ref/x86/linux/pc-simple-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-si
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr 18 2013 13:37:41
-gem5 started Apr 18 2013 13:43:22
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:25:04
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
+info: kernel located at: /dist/m5/system/binaries/x86_64-vmlinux-2.6.22.9
       0: rtc: Real-time clock set to Sun Jan  1 00:00:00 2012
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 5187335906000 because m5_exit instruction encountered
+Exiting @ tick 5196173457000 because m5_exit instruction encountered
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
index 56a5a7d83..0062dcbb2 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini
@@ -1,19 +1,20 @@
 [drivesys]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami
+children=bridge clk_domain cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami voltage_domain
 boot_cpu_frequency=250
 boot_osflags=root=/dev/hda1 console=ttyS0
-clock=1000
-console=/scratch/nilay/GEM5/system/binaries/console
+cache_line_size=64
+clk_domain=drivesys.clk_domain
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=drivesys.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-server.rcS
+pal=/dist/m5/system/binaries/ts_osfpal
+readfile=/z/m5/regression/zizzer/gem5/configs/boot/netperf-server.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -28,7 +29,7 @@ system_port=drivesys.membus.slave[0]
 
 [drivesys.bridge]
 type=Bridge
-clock=1000
+clk_domain=drivesys.clk_domain
 delay=50000
 ranges=8796093022208:18446744073709551615
 req_size=16
@@ -36,12 +37,16 @@ resp_size=16
 master=drivesys.iobus.slave[0]
 slave=drivesys.membus.master[0]
 
+[drivesys.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=drivesys.voltage_domain
+
 [drivesys.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer
-branchPred=Null
+children=clk_domain dtb interrupts isa itb tracer
 checker=Null
-clock=250
+clk_domain=drivesys.cpu.clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -60,6 +65,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -70,6 +79,11 @@ workload=
 dcache_port=drivesys.membus.slave[2]
 icache_port=drivesys.membus.slave[1]
 
+[drivesys.cpu.clk_domain]
+type=SrcClockDomain
+clock=250
+voltage_domain=drivesys.voltage_domain
+
 [drivesys.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -104,7 +118,7 @@ table_size=65536
 
 [drivesys.disk0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [drivesys.disk2]
@@ -124,7 +138,7 @@ table_size=65536
 
 [drivesys.disk2.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [drivesys.intrctrl]
@@ -133,7 +147,7 @@ sys=drivesys
 
 [drivesys.iobridge]
 type=Bridge
-clock=1000
+clk_domain=drivesys.clk_domain
 delay=50000
 ranges=0:134217727
 req_size=16
@@ -143,8 +157,7 @@ slave=drivesys.iobus.master[29]
 
 [drivesys.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=drivesys.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -155,9 +168,9 @@ slave=drivesys.bridge.master drivesys.tsunami.ide.dma drivesys.tsunami.ethernet.
 [drivesys.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=drivesys.clk_domain
 header_cycles=1
+system=drivesys
 use_default_range=false
 width=8
 default=drivesys.membus.badaddr_responder.pio
@@ -166,7 +179,7 @@ slave=drivesys.system_port drivesys.cpu.icache_port drivesys.cpu.dcache_port dri
 
 [drivesys.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -182,29 +195,15 @@ warn_access=
 pio=drivesys.membus.default
 
 [drivesys.physmem]
-type=SimpleDRAM
-addr_mapping=openmap
-banks_per_rank=8
-clock=1000
-conf_table_reported=false
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=drivesys.clk_domain
+conf_table_reported=true
 in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+latency=30000
+latency_var=0
 null=false
-page_policy=open
 range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
-tREFI=7800000
-tRFC=300000
-tRP=14000
-tWTR=1000
-write_buffer_size=32
-write_thresh_perc=70
-zero=false
 port=drivesys.membus.master[1]
 
 [drivesys.simple_disk]
@@ -215,7 +214,7 @@ system=drivesys
 
 [drivesys.simple_disk.disk]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [drivesys.terminal]
@@ -233,7 +232,7 @@ system=drivesys
 
 [drivesys.tsunami.backdoor]
 type=AlphaBackdoor
-clock=1000
+clk_domain=drivesys.clk_domain
 cpu=drivesys.cpu
 disk=drivesys.simple_disk
 pio_addr=8804682956800
@@ -245,7 +244,7 @@ pio=drivesys.iobus.master[24]
 
 [drivesys.tsunami.cchip]
 type=TsunamiCChip
-clock=1000
+clk_domain=drivesys.clk_domain
 pio_addr=8803072344064
 pio_latency=100000
 system=drivesys
@@ -254,6 +253,7 @@ pio=drivesys.iobus.master[0]
 
 [drivesys.tsunami.ethernet]
 type=NSGigE
+children=clk_domain
 BAR0=1
 BAR0LegacyIO=false
 BAR0Size=256
@@ -292,7 +292,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=2000
+clk_domain=drivesys.tsunami.ethernet.clk_domain
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -322,9 +322,14 @@ dma=drivesys.iobus.slave[2]
 interface=etherlink.int1
 pio=drivesys.iobus.master[27]
 
+[drivesys.tsunami.ethernet.clk_domain]
+type=SrcClockDomain
+clock=2000
+voltage_domain=drivesys.voltage_domain
+
 [drivesys.tsunami.fake_OROM]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -341,7 +346,7 @@ pio=drivesys.iobus.master[8]
 
 [drivesys.tsunami.fake_ata0]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -358,7 +363,7 @@ pio=drivesys.iobus.master[19]
 
 [drivesys.tsunami.fake_ata1]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -375,7 +380,7 @@ pio=drivesys.iobus.master[20]
 
 [drivesys.tsunami.fake_pnp_addr]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -392,7 +397,7 @@ pio=drivesys.iobus.master[9]
 
 [drivesys.tsunami.fake_pnp_read0]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -409,7 +414,7 @@ pio=drivesys.iobus.master[11]
 
 [drivesys.tsunami.fake_pnp_read1]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -426,7 +431,7 @@ pio=drivesys.iobus.master[12]
 
 [drivesys.tsunami.fake_pnp_read2]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -443,7 +448,7 @@ pio=drivesys.iobus.master[13]
 
 [drivesys.tsunami.fake_pnp_read3]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -460,7 +465,7 @@ pio=drivesys.iobus.master[14]
 
 [drivesys.tsunami.fake_pnp_read4]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -477,7 +482,7 @@ pio=drivesys.iobus.master[15]
 
 [drivesys.tsunami.fake_pnp_read5]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -494,7 +499,7 @@ pio=drivesys.iobus.master[16]
 
 [drivesys.tsunami.fake_pnp_read6]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -511,7 +516,7 @@ pio=drivesys.iobus.master[17]
 
 [drivesys.tsunami.fake_pnp_read7]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -528,7 +533,7 @@ pio=drivesys.iobus.master[18]
 
 [drivesys.tsunami.fake_pnp_write]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -545,7 +550,7 @@ pio=drivesys.iobus.master[10]
 
 [drivesys.tsunami.fake_ppc]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -562,7 +567,7 @@ pio=drivesys.iobus.master[7]
 
 [drivesys.tsunami.fake_sm_chip]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -579,7 +584,7 @@ pio=drivesys.iobus.master[2]
 
 [drivesys.tsunami.fake_uart1]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -596,7 +601,7 @@ pio=drivesys.iobus.master[3]
 
 [drivesys.tsunami.fake_uart2]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -613,7 +618,7 @@ pio=drivesys.iobus.master[4]
 
 [drivesys.tsunami.fake_uart3]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -630,7 +635,7 @@ pio=drivesys.iobus.master[5]
 
 [drivesys.tsunami.fake_uart4]
 type=IsaFake
-clock=1000
+clk_domain=drivesys.clk_domain
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -647,7 +652,7 @@ pio=drivesys.iobus.master[6]
 
 [drivesys.tsunami.fb]
 type=BadDevice
-clock=1000
+clk_domain=drivesys.clk_domain
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=100000
@@ -694,7 +699,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=drivesys.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=drivesys.disk0 drivesys.disk2
@@ -711,7 +716,7 @@ pio=drivesys.iobus.master[25]
 
 [drivesys.tsunami.io]
 type=TsunamiIO
-clock=1000
+clk_domain=drivesys.clk_domain
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -723,7 +728,7 @@ pio=drivesys.iobus.master[22]
 
 [drivesys.tsunami.pchip]
 type=TsunamiPChip
-clock=1000
+clk_domain=drivesys.clk_domain
 pio_addr=8802535473152
 pio_latency=100000
 system=drivesys
@@ -733,7 +738,8 @@ pio=drivesys.iobus.master[1]
 [drivesys.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=drivesys.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=drivesys.tsunami
 size=16777216
@@ -742,7 +748,7 @@ pio=drivesys.iobus.default
 
 [drivesys.tsunami.uart]
 type=Uart8250
-clock=1000
+clk_domain=drivesys.clk_domain
 pio_addr=8804615848952
 pio_latency=100000
 platform=drivesys.tsunami
@@ -750,6 +756,10 @@ system=drivesys
 terminal=drivesys.terminal
 pio=drivesys.iobus.master[23]
 
+[drivesys.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
 [etherdump]
 type=EtherDump
 file=ethertrace
@@ -774,20 +784,21 @@ time_sync_spin_threshold=100000000
 
 [testsys]
 type=LinuxAlphaSystem
-children=bridge cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami
+children=bridge clk_domain cpu disk0 disk2 intrctrl iobridge iobus membus physmem simple_disk terminal tsunami voltage_domain
 boot_cpu_frequency=500
 boot_osflags=root=/dev/hda1 console=ttyS0
-clock=1000
-console=/scratch/nilay/GEM5/system/binaries/console
+cache_line_size=64
+clk_domain=testsys.clk_domain
+console=/dist/m5/system/binaries/console
 init_param=0
-kernel=/scratch/nilay/GEM5/system/binaries/vmlinux
+kernel=/dist/m5/system/binaries/vmlinux
 load_addr_mask=1099511627775
 mem_mode=atomic
 mem_ranges=0:134217727
 memories=testsys.physmem
 num_work_ids=16
-pal=/scratch/nilay/GEM5/system/binaries/ts_osfpal
-readfile=/scratch/nilay/GEM5/gem5/configs/boot/netperf-stream-client.rcS
+pal=/dist/m5/system/binaries/ts_osfpal
+readfile=/z/m5/regression/zizzer/gem5/configs/boot/netperf-stream-client.rcS
 symbolfile=
 system_rev=1024
 system_type=34
@@ -802,7 +813,7 @@ system_port=testsys.membus.slave[0]
 
 [testsys.bridge]
 type=Bridge
-clock=1000
+clk_domain=testsys.clk_domain
 delay=50000
 ranges=8796093022208:18446744073709551615
 req_size=16
@@ -810,12 +821,16 @@ resp_size=16
 master=testsys.iobus.slave[0]
 slave=testsys.membus.master[0]
 
+[testsys.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=testsys.voltage_domain
+
 [testsys.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer
-branchPred=Null
+children=clk_domain dtb interrupts isa itb tracer
 checker=Null
-clock=500
+clk_domain=testsys.cpu.clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -834,6 +849,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -844,6 +863,11 @@ workload=
 dcache_port=testsys.membus.slave[2]
 icache_port=testsys.membus.slave[1]
 
+[testsys.cpu.clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=testsys.voltage_domain
+
 [testsys.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -878,7 +902,7 @@ table_size=65536
 
 [testsys.disk0.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [testsys.disk2]
@@ -898,7 +922,7 @@ table_size=65536
 
 [testsys.disk2.image.child]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/dist/m5/system/disks/linux-bigswap2.img
 read_only=true
 
 [testsys.intrctrl]
@@ -907,7 +931,7 @@ sys=testsys
 
 [testsys.iobridge]
 type=Bridge
-clock=1000
+clk_domain=testsys.clk_domain
 delay=50000
 ranges=0:134217727
 req_size=16
@@ -917,8 +941,7 @@ slave=testsys.iobus.master[29]
 
 [testsys.iobus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=testsys.clk_domain
 header_cycles=1
 use_default_range=true
 width=8
@@ -929,9 +952,9 @@ slave=testsys.bridge.master testsys.tsunami.ide.dma testsys.tsunami.ethernet.dma
 [testsys.membus]
 type=CoherentBus
 children=badaddr_responder
-block_size=64
-clock=1000
+clk_domain=testsys.clk_domain
 header_cycles=1
+system=testsys
 use_default_range=false
 width=8
 default=testsys.membus.badaddr_responder.pio
@@ -940,7 +963,7 @@ slave=testsys.system_port testsys.cpu.icache_port testsys.cpu.dcache_port testsy
 
 [testsys.membus.badaddr_responder]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=0
 pio_latency=100000
@@ -956,29 +979,15 @@ warn_access=
 pio=testsys.membus.default
 
 [testsys.physmem]
-type=SimpleDRAM
-addr_mapping=openmap
-banks_per_rank=8
-clock=1000
-conf_table_reported=false
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=testsys.clk_domain
+conf_table_reported=true
 in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+latency=30000
+latency_var=0
 null=false
-page_policy=open
 range=0:134217727
-ranks_per_channel=2
-read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
-tREFI=7800000
-tRFC=300000
-tRP=14000
-tWTR=1000
-write_buffer_size=32
-write_thresh_perc=70
-zero=false
 port=testsys.membus.master[1]
 
 [testsys.simple_disk]
@@ -989,7 +998,7 @@ system=testsys
 
 [testsys.simple_disk.disk]
 type=RawDiskImage
-image_file=/scratch/nilay/GEM5/system/disks/linux-latest.img
+image_file=/dist/m5/system/disks/linux-latest.img
 read_only=true
 
 [testsys.terminal]
@@ -1007,7 +1016,7 @@ system=testsys
 
 [testsys.tsunami.backdoor]
 type=AlphaBackdoor
-clock=1000
+clk_domain=testsys.clk_domain
 cpu=testsys.cpu
 disk=testsys.simple_disk
 pio_addr=8804682956800
@@ -1019,7 +1028,7 @@ pio=testsys.iobus.master[24]
 
 [testsys.tsunami.cchip]
 type=TsunamiCChip
-clock=1000
+clk_domain=testsys.clk_domain
 pio_addr=8803072344064
 pio_latency=100000
 system=testsys
@@ -1028,6 +1037,7 @@ pio=testsys.iobus.master[0]
 
 [testsys.tsunami.ethernet]
 type=NSGigE
+children=clk_domain
 BAR0=1
 BAR0LegacyIO=false
 BAR0Size=256
@@ -1066,7 +1076,7 @@ SubClassCode=0
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=4107
-clock=2000
+clk_domain=testsys.tsunami.ethernet.clk_domain
 config_latency=20000
 dma_data_free=false
 dma_desc_free=false
@@ -1096,9 +1106,14 @@ dma=testsys.iobus.slave[2]
 interface=etherlink.int0
 pio=testsys.iobus.master[27]
 
+[testsys.tsunami.ethernet.clk_domain]
+type=SrcClockDomain
+clock=2000
+voltage_domain=testsys.voltage_domain
+
 [testsys.tsunami.fake_OROM]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8796093677568
 pio_latency=100000
@@ -1115,7 +1130,7 @@ pio=testsys.iobus.master[8]
 
 [testsys.tsunami.fake_ata0]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848432
 pio_latency=100000
@@ -1132,7 +1147,7 @@ pio=testsys.iobus.master[19]
 
 [testsys.tsunami.fake_ata1]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848304
 pio_latency=100000
@@ -1149,7 +1164,7 @@ pio=testsys.iobus.master[20]
 
 [testsys.tsunami.fake_pnp_addr]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848569
 pio_latency=100000
@@ -1166,7 +1181,7 @@ pio=testsys.iobus.master[9]
 
 [testsys.tsunami.fake_pnp_read0]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848451
 pio_latency=100000
@@ -1183,7 +1198,7 @@ pio=testsys.iobus.master[11]
 
 [testsys.tsunami.fake_pnp_read1]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848515
 pio_latency=100000
@@ -1200,7 +1215,7 @@ pio=testsys.iobus.master[12]
 
 [testsys.tsunami.fake_pnp_read2]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848579
 pio_latency=100000
@@ -1217,7 +1232,7 @@ pio=testsys.iobus.master[13]
 
 [testsys.tsunami.fake_pnp_read3]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848643
 pio_latency=100000
@@ -1234,7 +1249,7 @@ pio=testsys.iobus.master[14]
 
 [testsys.tsunami.fake_pnp_read4]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848707
 pio_latency=100000
@@ -1251,7 +1266,7 @@ pio=testsys.iobus.master[15]
 
 [testsys.tsunami.fake_pnp_read5]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848771
 pio_latency=100000
@@ -1268,7 +1283,7 @@ pio=testsys.iobus.master[16]
 
 [testsys.tsunami.fake_pnp_read6]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848835
 pio_latency=100000
@@ -1285,7 +1300,7 @@ pio=testsys.iobus.master[17]
 
 [testsys.tsunami.fake_pnp_read7]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848899
 pio_latency=100000
@@ -1302,7 +1317,7 @@ pio=testsys.iobus.master[18]
 
 [testsys.tsunami.fake_pnp_write]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615850617
 pio_latency=100000
@@ -1319,7 +1334,7 @@ pio=testsys.iobus.master[10]
 
 [testsys.tsunami.fake_ppc]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848891
 pio_latency=100000
@@ -1336,7 +1351,7 @@ pio=testsys.iobus.master[7]
 
 [testsys.tsunami.fake_sm_chip]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848816
 pio_latency=100000
@@ -1353,7 +1368,7 @@ pio=testsys.iobus.master[2]
 
 [testsys.tsunami.fake_uart1]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848696
 pio_latency=100000
@@ -1370,7 +1385,7 @@ pio=testsys.iobus.master[3]
 
 [testsys.tsunami.fake_uart2]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848936
 pio_latency=100000
@@ -1387,7 +1402,7 @@ pio=testsys.iobus.master[4]
 
 [testsys.tsunami.fake_uart3]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848680
 pio_latency=100000
@@ -1404,7 +1419,7 @@ pio=testsys.iobus.master[5]
 
 [testsys.tsunami.fake_uart4]
 type=IsaFake
-clock=1000
+clk_domain=testsys.clk_domain
 fake_mem=false
 pio_addr=8804615848944
 pio_latency=100000
@@ -1421,7 +1436,7 @@ pio=testsys.iobus.master[6]
 
 [testsys.tsunami.fb]
 type=BadDevice
-clock=1000
+clk_domain=testsys.clk_domain
 devicename=FrameBuffer
 pio_addr=8804615848912
 pio_latency=100000
@@ -1468,7 +1483,7 @@ SubClassCode=1
 SubsystemID=0
 SubsystemVendorID=0
 VendorID=32902
-clock=1000
+clk_domain=testsys.clk_domain
 config_latency=20000
 ctrl_offset=0
 disks=testsys.disk0 testsys.disk2
@@ -1485,7 +1500,7 @@ pio=testsys.iobus.master[25]
 
 [testsys.tsunami.io]
 type=TsunamiIO
-clock=1000
+clk_domain=testsys.clk_domain
 frequency=976562500
 pio_addr=8804615847936
 pio_latency=100000
@@ -1497,7 +1512,7 @@ pio=testsys.iobus.master[22]
 
 [testsys.tsunami.pchip]
 type=TsunamiPChip
-clock=1000
+clk_domain=testsys.clk_domain
 pio_addr=8802535473152
 pio_latency=100000
 system=testsys
@@ -1507,7 +1522,8 @@ pio=testsys.iobus.master[1]
 [testsys.tsunami.pciconfig]
 type=PciConfigAll
 bus=0
-clock=1000
+clk_domain=testsys.clk_domain
+pio_addr=0
 pio_latency=30000
 platform=testsys.tsunami
 size=16777216
@@ -1516,7 +1532,7 @@ pio=testsys.iobus.default
 
 [testsys.tsunami.uart]
 type=Uart8250
-clock=1000
+clk_domain=testsys.clk_domain
 pio_addr=8804615848952
 pio_latency=100000
 platform=testsys.tsunami
@@ -1524,3 +1540,7 @@ system=testsys
 terminal=testsys.terminal
 pio=testsys.iobus.master[23]
 
+[testsys.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
index d501adb38..8798f32cd 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/drivesys.terminal
@@ -4,7 +4,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
 
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
-
CPU Clock at 1000000 MHz IntrClockFrequency=1024 
+
CPU Clock at 4000 MHz IntrClockFrequency=1024 
 
Booting with 1 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
 
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
@@ -36,7 +36,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Mount-cache hash table entries: 512
 
SMP mode deactivated.
 
Brought up 1 CPUs
-
SMP: Total of 1 processors activated (1998756.81 BogoMIPS).
+
SMP: Total of 1 processors activated (8000.15 BogoMIPS).
 
NET: Registered protocol family 16
 
EISA bus registered
 
pci: enabling save/restore of SRM state
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
index 4fa3d404b..af627b8fa 100755
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
@@ -3,14 +3,14 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/lin
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:07:46
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:52
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/fs/80.netperf-stream/alpha/linux/twosys-tsunami-simple-atomic
 Global frequency set at 1000000000000 ticks per second
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: testsys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
-info: kernel located at: /scratch/nilay/GEM5/system/binaries/vmlinux
+info: kernel located at: /dist/m5/system/binaries/vmlinux
       0: drivesys.tsunami.io.rtc: Real-time clock set to Thu Jan  1 00:00:00 2009
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 4321612280500 because checkpoint
+Exiting @ tick 4321621592000 because checkpoint
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
index cf36dbc01..4ccc9d7bc 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.200409                       # Nu
 sim_ticks                                200409284500                       # Number of ticks simulated
 final_tick                               4321214250500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                               10833540                       # Simulator instruction rate (inst/s)
-host_op_rate                                 10833535                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4145057481                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 475668                       # Number of bytes of host memory used
-host_seconds                                    48.35                       # Real time elapsed on the host
+host_inst_rate                               21337245                       # Simulator instruction rate (inst/s)
+host_op_rate                                 21337231                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8163912733                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 473328                       # Number of bytes of host memory used
+host_seconds                                    24.55                       # Real time elapsed on the host
 sim_insts                                   523790075                       # Number of instructions simulated
 sim_ops                                     523790075                       # Number of ops (including micro ops) simulated
 testsys.physmem.bytes_read::cpu.inst         81046720                       # Number of bytes read from this memory
@@ -445,11 +445,11 @@ sim_seconds                                  0.000407                       # Nu
 sim_ticks                                   407341500                       # Number of ticks simulated
 final_tick                               4321621592000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                             5619093232                       # Simulator instruction rate (inst/s)
-host_op_rate                               5617709608                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                             4367114686                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 475668                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                            10977168844                       # Simulator instruction rate (inst/s)
+host_op_rate                              10973505866                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                             8529941400                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 473328                       # Number of bytes of host memory used
+host_seconds                                     0.05                       # Real time elapsed on the host
 sim_insts                                   523862353                       # Number of instructions simulated
 sim_ops                                     523862353                       # Number of ops (including micro ops) simulated
 testsys.physmem.bytes_read::cpu.inst           144504                       # Number of bytes read from this memory
diff --git a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
index 9468ea620..371f1a3fb 100644
--- a/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
+++ b/tests/quick/fs/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/testsys.terminal
@@ -4,7 +4,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
First free page after ROM 0xFFFFFC0000018000
 
HWRPB 0xFFFFFC0000018000 l1pt 0xFFFFFC0000040000 l2pt 0xFFFFFC0000042000 l3pt_rpb 0xFFFFFC0000044000 l3pt_kernel 0xFFFFFC0000048000 l2reserv 0xFFFFFC0000046000
 
kstart = 0xFFFFFC0000310000, kend = 0xFFFFFC0000855898, kentry = 0xFFFFFC0000310000, numCPUs = 0x1
-
CPU Clock at 1000000 MHz IntrClockFrequency=1024 
+
CPU Clock at 2000 MHz IntrClockFrequency=1024 
 
Booting with 1 processor(s) 
 
KSP: 0x20043FE8 PTBR 0x20
 
Console Callback at 0x0, fixup at 0x0, crb offset: 0x510
@@ -36,7 +36,7 @@ M5 console: m5AlphaAccess @ 0xFFFFFD0200000000
 
Mount-cache hash table entries: 512
 
SMP mode deactivated.
 
Brought up 1 CPUs
-
SMP: Total of 1 processors activated (1998756.81 BogoMIPS).
+
SMP: Total of 1 processors activated (4002.20 BogoMIPS).
 
NET: Registered protocol family 16
 
EISA bus registered
 
pci: enabling save/restore of SRM state
@@ -117,7 +117,7 @@ Socket Socket  Message  Elapsed
 Size   Size    Size     Time     Throughput  

 bytes  bytes   bytes    secs.    10^6bits/sec  

 

-5000000 5000000 5000000    1.29       30.91   

+5000000 5000000 5000000    1.30       30.82   

 netperf benchmark

 /benchmarks/netperf-bin/netperf -H 10.0.0.1 -t TCP_STREAM -k16384,0 -K16384,0 -- -m 65536 -M 65536 -s 262144 -S 262144

 TCP STREAM TEST to 10.0.0.1 : dirty data

diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
index c1097366b..8be59c81c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +42,7 @@ activity=0
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +72,7 @@ multRepeatRate=1
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +91,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +101,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +115,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -154,10 +177,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,16 +191,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -196,7 +227,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,10 +238,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -221,19 +256,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -244,6 +284,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
index fa2cf12dd..b50e34b75 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorde
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:17:23
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:26
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 18737000 because target called exit()
+Exiting @ tick 25046000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
index 765a5ac14..dce50f688 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -454,10 +477,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +491,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -496,7 +527,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -507,10 +538,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +584,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
index 800d8e238..ab8450b87 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:12
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:26
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 16032500 because target called exit()
+Exiting @ tick 20671000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
index 38823b11f..3d9687a29 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
index dc9014a9b..1fb01db1e 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:33:24
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:26
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
index 4a9baa29b..90c3ec168 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 49b667e6c..11de6c024 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:03:49
+Real time: Sep/22/2013 05:27:18
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 8
-Elapsed_time_in_minutes: 0.133333
-Elapsed_time_in_hours: 0.00222222
-Elapsed_time_in_days: 9.25926e-05
+Elapsed_time_in_seconds: 6
+Elapsed_time_in_minutes: 0.1
+Elapsed_time_in_hours: 0.00166667
+Elapsed_time_in_days: 6.94444e-05
 
-Virtual_time_in_seconds: 0.65
-Virtual_time_in_minutes: 0.0108333
-Virtual_time_in_hours:   0.000180556
-Virtual_time_in_days:    7.52315e-06
+Virtual_time_in_seconds: 0.5
+Virtual_time_in_minutes: 0.00833333
+Virtual_time_in_hours:   0.000138889
+Virtual_time_in_days:    5.78704e-06
 
 Ruby_current_time: 138616
 Ruby_start_time: 0
 Ruby_cycles: 138616
 
-mbytes_resident: 76.7812
-mbytes_total: 170.938
-resident_ratio: 0.4492
+mbytes_resident: 70.7109
+mbytes_total: 125.152
+resident_ratio: 0.564999
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
index e45cd058f..bbc0c797e 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simerr
@@ -1,2 +1,6 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
index 226bed9cc..5fac9bcf7 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  1 2012 14:01:54
-gem5 started Sep  1 2012 14:02:52
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:27:02
+gem5 started Sep 22 2013 05:27:12
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 966ab8ba5..5c3b6f3c7 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000139                       # Nu
 sim_ticks                                      138616                       # Number of ticks simulated
 final_tick                                     138616                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                    871                       # Simulator instruction rate (inst/s)
-host_op_rate                                      871                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                  18892                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 175044                       # Number of bytes of host memory used
-host_seconds                                     7.34                       # Real time elapsed on the host
+host_inst_rate                                   1056                       # Simulator instruction rate (inst/s)
+host_op_rate                                     1056                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                  22900                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 128160                       # Number of bytes of host memory used
+host_seconds                                     6.05                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1249                       # Number of cache demand hits
@@ -101,6 +101,18 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2         6392
 system.ruby.network.routers3.msg_bytes.Writeback_Data::0        10584                      
 system.ruby.network.routers3.msg_bytes.Writeback_Data::1        10152                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::0         2312                      
+system.ruby.network.msg_count.Control            8850                      
+system.ruby.network.msg_count.Request_Control         3123                      
+system.ruby.network.msg_count.Response_Data         9681                      
+system.ruby.network.msg_count.Response_Control        14286                      
+system.ruby.network.msg_count.Writeback_Data          864                      
+system.ruby.network.msg_count.Writeback_Control          867                      
+system.ruby.network.msg_byte.Control            70800                      
+system.ruby.network.msg_byte.Request_Control        24984                      
+system.ruby.network.msg_byte.Response_Data       697032                      
+system.ruby.network.msg_byte.Response_Control       114288                      
+system.ruby.network.msg_byte.Writeback_Data        62208                      
+system.ruby.network.msg_byte.Writeback_Control         6936                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -272,18 +284,6 @@ system.ruby.l1_cntrl0.IS.Data_Exclusive           583      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data_all_Acks            691      0.00%      0.00%
 system.ruby.l1_cntrl0.IM.Data_all_Acks            216      0.00%      0.00%
 system.ruby.l1_cntrl0.M_I.WB_Ack                  436      0.00%      0.00%
-system.ruby.network.msg_count.Control            8850                      
-system.ruby.network.msg_count.Request_Control         3123                      
-system.ruby.network.msg_count.Response_Data         9681                      
-system.ruby.network.msg_count.Response_Control        14286                      
-system.ruby.network.msg_count.Writeback_Data          864                      
-system.ruby.network.msg_count.Writeback_Control          867                      
-system.ruby.network.msg_byte.Control            70800                      
-system.ruby.network.msg_byte.Request_Control        24984                      
-system.ruby.network.msg_byte.Response_Data       697032                      
-system.ruby.network.msg_byte.Response_Control       114288                      
-system.ruby.network.msg_byte.Writeback_Data        62208                      
-system.ruby.network.msg_byte.Writeback_Control         6936                      
 system.ruby.l2_cntrl0.L1_GET_INSTR                691      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETS                     583      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETX                     216      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
index e1b2b2ccf..454f386da 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index 94f281262..f796e6d64 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Aug/29/2013 10:04:57
+Real time: Sep/22/2013 05:36:35
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0.0166667
 Elapsed_time_in_hours: 0.000277778
 Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.74
-Virtual_time_in_minutes: 0.0123333
-Virtual_time_in_hours:   0.000205556
-Virtual_time_in_days:    8.56481e-06
+Virtual_time_in_seconds: 0.52
+Virtual_time_in_minutes: 0.00866667
+Virtual_time_in_hours:   0.000144444
+Virtual_time_in_days:    6.01852e-06
 
 Ruby_current_time: 117611
 Ruby_start_time: 0
 Ruby_cycles: 117611
 
-mbytes_resident: 78.3398
-mbytes_total: 172.082
-resident_ratio: 0.45527
+mbytes_resident: 72.1758
+mbytes_total: 126.289
+resident_ratio: 0.571513
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
index e45cd058f..bbc0c797e 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -1,2 +1,6 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
index 0b27bcc43..7aebf91e4 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hell
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  1 2012 14:10:16
-gem5 started Sep  1 2012 14:11:17
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:36:12
+gem5 started Sep 22 2013 05:36:34
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 3af3398f7..a243c0ad3 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000118                       # Nu
 sim_ticks                                      117611                       # Number of ticks simulated
 final_tick                                     117611                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  19051                       # Simulator instruction rate (inst/s)
-host_op_rate                                    19050                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 350596                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 176216                       # Number of bytes of host memory used
-host_seconds                                     0.34                       # Real time elapsed on the host
+host_inst_rate                                  22489                       # Simulator instruction rate (inst/s)
+host_op_rate                                    22487                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 413867                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 129324                       # Number of bytes of host memory used
+host_seconds                                     0.28                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1332                       # Number of cache demand hits
@@ -98,6 +98,18 @@ system.ruby.network.routers3.msg_bytes.Writeback_Control::0        21664
 system.ruby.network.routers3.msg_bytes.Writeback_Control::1        17488                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::2         7192                      
 system.ruby.network.routers3.msg_bytes.Unblock_Control::2        19768                      
+system.ruby.network.msg_count.Request_Control         7413                      
+system.ruby.network.msg_count.Response_Data         6654                      
+system.ruby.network.msg_count.ResponseL2hit_Data          759                      
+system.ruby.network.msg_count.Writeback_Data         4644                      
+system.ruby.network.msg_count.Writeback_Control        17379                      
+system.ruby.network.msg_count.Unblock_Control         7413                      
+system.ruby.network.msg_byte.Request_Control        59304                      
+system.ruby.network.msg_byte.Response_Data       479088                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        54648                      
+system.ruby.network.msg_byte.Writeback_Data       334368                      
+system.ruby.network.msg_byte.Writeback_Control       139032                      
+system.ruby.network.msg_byte.Unblock_Control        59304                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -277,18 +289,6 @@ system.ruby.l1_cntrl0.IM.Exclusive_Data           191      0.00%      0.00%
 system.ruby.l1_cntrl0.OM.All_acks                 191      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Exclusive_Data          1171      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack_Data         1354      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control         7413                      
-system.ruby.network.msg_count.Response_Data         6654                      
-system.ruby.network.msg_count.ResponseL2hit_Data          759                      
-system.ruby.network.msg_count.Writeback_Data         4644                      
-system.ruby.network.msg_count.Writeback_Control        17379                      
-system.ruby.network.msg_count.Unblock_Control         7413                      
-system.ruby.network.msg_byte.Request_Control        59304                      
-system.ruby.network.msg_byte.Response_Data       479088                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        54648                      
-system.ruby.network.msg_byte.Writeback_Data       334368                      
-system.ruby.network.msg_byte.Writeback_Control       139032                      
-system.ruby.network.msg_byte.Unblock_Control        59304                      
 system.ruby.l2_cntrl0.L1_GETS                    1171      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETX                     191      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_PUTX                    1354      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
index 5bdc495d8..98cbeddd9 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 442dd3499..878f29081 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:04:43
+Real time: Sep/22/2013 05:45:04
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 4
+Elapsed_time_in_minutes: 0.0666667
+Elapsed_time_in_hours: 0.00111111
+Elapsed_time_in_days: 4.62963e-05
 
-Virtual_time_in_seconds: 0.6
-Virtual_time_in_minutes: 0.01
-Virtual_time_in_hours:   0.000166667
-Virtual_time_in_days:    6.94444e-06
+Virtual_time_in_seconds: 0.44
+Virtual_time_in_minutes: 0.00733333
+Virtual_time_in_hours:   0.000122222
+Virtual_time_in_days:    5.09259e-06
 
 Ruby_current_time: 113627
 Ruby_start_time: 0
 Ruby_cycles: 113627
 
-mbytes_resident: 75.7461
-mbytes_total: 170.031
-resident_ratio: 0.445506
+mbytes_resident: 69.5977
+mbytes_total: 124.223
+resident_ratio: 0.560265
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
index e45cd058f..bbc0c797e 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -1,2 +1,6 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
index c5809ae71..972ce6ed2 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/al
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  9 2012 13:38:07
-gem5 started Sep  9 2012 13:38:15
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:44:48
+gem5 started Sep 22 2013 05:44:59
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
index be82f1052..da21a8b1c 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000114                       # Nu
 sim_ticks                                      113627                       # Number of ticks simulated
 final_tick                                     113627                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  27885                       # Simulator instruction rate (inst/s)
-host_op_rate                                    27883                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 495765                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 174116                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
+host_inst_rate                                   1471                       # Simulator instruction rate (inst/s)
+host_op_rate                                     1471                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                  26154                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 127208                       # Number of bytes of host memory used
+host_seconds                                     4.34                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1312                       # Number of cache demand hits
@@ -82,6 +82,18 @@ system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4        14688
 system.ruby.network.routers3.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers3.msg_bytes.Writeback_Data::4       113976                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::4         7736                      
+system.ruby.network.msg_count.Request_Control         7731                      
+system.ruby.network.msg_count.Response_Data         3534                      
+system.ruby.network.msg_count.ResponseL2hit_Data          612                      
+system.ruby.network.msg_count.Response_Control            3                      
+system.ruby.network.msg_count.Writeback_Data         4749                      
+system.ruby.network.msg_count.Writeback_Control         2901                      
+system.ruby.network.msg_byte.Request_Control        61848                      
+system.ruby.network.msg_byte.Response_Data       254448                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        44064                      
+system.ruby.network.msg_byte.Response_Control           24                      
+system.ruby.network.msg_byte.Writeback_Data       341928                      
+system.ruby.network.msg_byte.Writeback_Control        23208                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -230,18 +242,6 @@ system.ruby.l1_cntrl0.IM.Ack                        1      0.00%      0.00%
 system.ruby.l1_cntrl0.SM.Data_All_Tokens           20      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data_Shared              161      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data_All_Tokens         1010      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control         7731                      
-system.ruby.network.msg_count.Response_Data         3534                      
-system.ruby.network.msg_count.ResponseL2hit_Data          612                      
-system.ruby.network.msg_count.Response_Control            3                      
-system.ruby.network.msg_count.Writeback_Data         4749                      
-system.ruby.network.msg_count.Writeback_Control         2901                      
-system.ruby.network.msg_byte.Request_Control        61848                      
-system.ruby.network.msg_byte.Response_Data       254448                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        44064                      
-system.ruby.network.msg_byte.Response_Control           24                      
-system.ruby.network.msg_byte.Writeback_Data       341928                      
-system.ruby.network.msg_byte.Writeback_Control        23208                      
 system.ruby.l2_cntrl0.L1_GETS                    1122      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETS_Last_Token           49      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETX                     211      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
index 0bd814b7d..5efa528b0 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
index 167b82c92..23062d8c8 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:02:57
+Real time: Sep/22/2013 05:18:00
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.8
-Virtual_time_in_minutes: 0.0133333
-Virtual_time_in_hours:   0.000222222
-Virtual_time_in_days:    9.25926e-06
+Virtual_time_in_seconds: 0.41
+Virtual_time_in_minutes: 0.00683333
+Virtual_time_in_hours:   0.000113889
+Virtual_time_in_days:    4.74537e-06
 
 Ruby_current_time: 93341
 Ruby_start_time: 0
 Ruby_cycles: 93341
 
-mbytes_resident: 75.5039
-mbytes_total: 169.965
-resident_ratio: 0.444255
+mbytes_resident: 69.2852
+mbytes_total: 124.195
+resident_ratio: 0.557873
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
index e45cd058f..bbc0c797e 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr
@@ -1,2 +1,6 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
index d752652fe..2f946fb64 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  1 2012 13:53:26
-gem5 started Sep  1 2012 13:54:22
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:17:28
+gem5 started Sep 22 2013 05:18:00
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
index 0558d3744..2decdb14a 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000093                       # Nu
 sim_ticks                                       93341                       # Number of ticks simulated
 final_tick                                      93341                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  19138                       # Simulator instruction rate (inst/s)
-host_op_rate                                    19136                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 279518                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 174048                       # Number of bytes of host memory used
-host_seconds                                     0.33                       # Real time elapsed on the host
+host_inst_rate                                  35131                       # Simulator instruction rate (inst/s)
+host_op_rate                                    35128                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 513083                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 127180                       # Number of bytes of host memory used
+host_seconds                                     0.18                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.L1Dcache.demand_hits         1332                       # Number of cache demand hits
@@ -83,6 +83,16 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2         9144
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3         9144                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::5         7384                      
 system.ruby.network.routers2.msg_bytes.Unblock_Control::5         9272                      
+system.ruby.network.msg_count.Request_Control         3477                      
+system.ruby.network.msg_count.Response_Data         3477                      
+system.ruby.network.msg_count.Writeback_Data          660                      
+system.ruby.network.msg_count.Writeback_Control         9627                      
+system.ruby.network.msg_count.Unblock_Control         3477                      
+system.ruby.network.msg_byte.Request_Control        27816                      
+system.ruby.network.msg_byte.Response_Data       250344                      
+system.ruby.network.msg_byte.Writeback_Data        47520                      
+system.ruby.network.msg_byte.Writeback_Control        77016                      
+system.ruby.network.msg_byte.Unblock_Control        27816                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -227,16 +237,6 @@ system.ruby.l1_cntrl0.MI.Store                     27      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack           1143      0.00%      0.00%
 system.ruby.l1_cntrl0.MT.Complete_L2_to_L1          133      0.00%      0.00%
 system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1           70      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control         3477                      
-system.ruby.network.msg_count.Response_Data         3477                      
-system.ruby.network.msg_count.Writeback_Data          660                      
-system.ruby.network.msg_count.Writeback_Control         9627                      
-system.ruby.network.msg_count.Unblock_Control         3477                      
-system.ruby.network.msg_byte.Request_Control        27816                      
-system.ruby.network.msg_byte.Response_Data       250344                      
-system.ruby.network.msg_byte.Writeback_Data        47520                      
-system.ruby.network.msg_byte.Writeback_Control        77016                      
-system.ruby.network.msg_byte.Unblock_Control        27816                      
 system.ruby.dir_cntrl0.GETX                       186      0.00%      0.00%
 system.ruby.dir_cntrl0.GETS                      1022      0.00%      0.00%
 system.ruby.dir_cntrl0.PUT                       1143      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
index 3473bb901..5c6bf177e 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
index 92d7e563b..07bf20a9b 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:03:31
+Real time: Sep/28/2013 03:05:29
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.61
-Virtual_time_in_minutes: 0.0101667
-Virtual_time_in_hours:   0.000169444
-Virtual_time_in_days:    7.06019e-06
+Virtual_time_in_seconds: 0.43
+Virtual_time_in_minutes: 0.00716667
+Virtual_time_in_hours:   0.000119444
+Virtual_time_in_days:    4.97685e-06
 
 Ruby_current_time: 143853
 Ruby_start_time: 0
 Ruby_cycles: 143853
 
-mbytes_resident: 75.2305
-mbytes_total: 169.531
-resident_ratio: 0.443779
+mbytes_resident: 69.0312
+mbytes_total: 123.75
+resident_ratio: 0.557828
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
index 5da3f0737..bbc0c797e 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simerr
@@ -1,6 +1,6 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
index 070ea92d3..cedef1822 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:45:23
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:27
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
index 8d6d3a37f..c8df30ebb 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000144                       # Nu
 sim_ticks                                      143853                       # Number of ticks simulated
 final_tick                                     143853                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  32139                       # Simulator instruction rate (inst/s)
-host_op_rate                                    32136                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 723384                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 173604                       # Number of bytes of host memory used
-host_seconds                                     0.20                       # Real time elapsed on the host
+host_inst_rate                                  29196                       # Simulator instruction rate (inst/s)
+host_op_rate                                    29194                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 657174                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 126724                       # Number of bytes of host memory used
+host_seconds                                     0.22                       # Real time elapsed on the host
 sim_insts                                        6390                       # Number of instructions simulated
 sim_ops                                          6390                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         6718                       # Number of cache demand hits
@@ -56,6 +56,14 @@ system.ruby.network.routers2.msg_bytes.Control::2        13840
 system.ruby.network.routers2.msg_bytes.Data::2       124272                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4       124560                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3        13808                      
+system.ruby.network.msg_count.Control            5190                      
+system.ruby.network.msg_count.Data               5178                      
+system.ruby.network.msg_count.Response_Data         5190                      
+system.ruby.network.msg_count.Writeback_Control         5178                      
+system.ruby.network.msg_byte.Control            41520                      
+system.ruby.network.msg_byte.Data              372816                      
+system.ruby.network.msg_byte.Response_Data       373680                      
+system.ruby.network.msg_byte.Writeback_Control        41424                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -157,14 +165,6 @@ system.ruby.l1_cntrl0.M.Replacement              1726      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack           1726      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data                    1457      0.00%      0.00%
 system.ruby.l1_cntrl0.IM.Data                     273      0.00%      0.00%
-system.ruby.network.msg_count.Control            5190                      
-system.ruby.network.msg_count.Data               5178                      
-system.ruby.network.msg_count.Response_Data         5190                      
-system.ruby.network.msg_count.Writeback_Control         5178                      
-system.ruby.network.msg_byte.Control            41520                      
-system.ruby.network.msg_byte.Data              372816                      
-system.ruby.network.msg_byte.Response_Data       373680                      
-system.ruby.network.msg_byte.Writeback_Control        41424                      
 system.ruby.dir_cntrl0.GETX                      1730      0.00%      0.00%
 system.ruby.dir_cntrl0.PUTX                      1726      0.00%      0.00%
 system.ruby.dir_cntrl0.Memory_Data               1730      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
index c41a1c22b..595a8159f 100644
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -119,10 +143,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
index fc43aac0c..b5f87b785 100755
--- a/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:45:47
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:26
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
index 5c71a7c03..c5e8a16e6 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -454,10 +477,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +491,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -496,7 +527,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -507,10 +538,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +584,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
index 4ea05c228..c47a79c1f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/o3-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:13
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:27
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello world!
-Exiting @ tick 9350000 because target called exit()
+Exiting @ tick 11933500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
index 81a4de4d4..b66459c3a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
index d9d6fa90d..034bc5823 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:45:35
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:27
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
index 759014fd3..362eaad12 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
index 110acb8ec..1ce96a614 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:03:38
+Real time: Sep/22/2013 05:27:18
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 5
+Elapsed_time_in_minutes: 0.0833333
+Elapsed_time_in_hours: 0.00138889
+Elapsed_time_in_days: 5.78704e-05
 
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours:   0.000141667
-Virtual_time_in_days:    5.90278e-06
+Virtual_time_in_seconds: 0.38
+Virtual_time_in_minutes: 0.00633333
+Virtual_time_in_hours:   0.000105556
+Virtual_time_in_days:    4.39815e-06
 
 Ruby_current_time: 52575
 Ruby_start_time: 0
 Ruby_cycles: 52575
 
-mbytes_resident: 74.6133
-mbytes_total: 168.652
-resident_ratio: 0.442432
+mbytes_resident: 68.4688
+mbytes_total: 122.754
+resident_ratio: 0.557772
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
index 31ae36f2e..492f3e68f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simerr
@@ -1,3 +1,7 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
index b08e9f127..5722711d2 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  1 2012 14:01:54
-gem5 started Sep  1 2012 14:03:04
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:27:02
+gem5 started Sep 22 2013 05:27:13
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
index 784ed2300..5b945b27d 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000053                       # Nu
 sim_ticks                                       52575                       # Number of ticks simulated
 final_tick                                      52575                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   7067                       # Simulator instruction rate (inst/s)
-host_op_rate                                     7067                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 144167                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 172704                       # Number of bytes of host memory used
-host_seconds                                     0.36                       # Real time elapsed on the host
+host_inst_rate                                    459                       # Simulator instruction rate (inst/s)
+host_op_rate                                      459                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                   9361                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 125832                       # Number of bytes of host memory used
+host_seconds                                     5.62                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.L1Dcache.demand_hits          437                       # Number of cache demand hits
@@ -100,6 +100,18 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2         2176
 system.ruby.network.routers3.msg_bytes.Writeback_Data::0         3384                      
 system.ruby.network.routers3.msg_bytes.Writeback_Data::1         4464                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::0          616                      
+system.ruby.network.msg_count.Control            3357                      
+system.ruby.network.msg_count.Request_Control         1293                      
+system.ruby.network.msg_count.Response_Data         3666                      
+system.ruby.network.msg_count.Response_Control         5220                      
+system.ruby.network.msg_count.Writeback_Data          327                      
+system.ruby.network.msg_count.Writeback_Control          231                      
+system.ruby.network.msg_byte.Control            26856                      
+system.ruby.network.msg_byte.Request_Control        10344                      
+system.ruby.network.msg_byte.Response_Data       263952                      
+system.ruby.network.msg_byte.Response_Control        41760                      
+system.ruby.network.msg_byte.Writeback_Data        23544                      
+system.ruby.network.msg_byte.Writeback_Control         1848                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -271,18 +283,6 @@ system.ruby.l1_cntrl0.IS.Data_Exclusive           204      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data_all_Acks            300      0.00%      0.00%
 system.ruby.l1_cntrl0.IM.Data_all_Acks             68      0.00%      0.00%
 system.ruby.l1_cntrl0.M_I.WB_Ack                  124      0.00%      0.00%
-system.ruby.network.msg_count.Control            3357                      
-system.ruby.network.msg_count.Request_Control         1293                      
-system.ruby.network.msg_count.Response_Data         3666                      
-system.ruby.network.msg_count.Response_Control         5220                      
-system.ruby.network.msg_count.Writeback_Data          327                      
-system.ruby.network.msg_count.Writeback_Control          231                      
-system.ruby.network.msg_byte.Control            26856                      
-system.ruby.network.msg_byte.Request_Control        10344                      
-system.ruby.network.msg_byte.Response_Data       263952                      
-system.ruby.network.msg_byte.Response_Control        41760                      
-system.ruby.network.msg_byte.Writeback_Data        23544                      
-system.ruby.network.msg_byte.Writeback_Control         1848                      
 system.ruby.l2_cntrl0.L1_GET_INSTR                300      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETS                     204      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETX                      68      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
index 3660a930a..1cc47929f 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
index ccd8b498a..fb852a546 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:04:53
+Real time: Sep/22/2013 05:36:30
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 1
-Elapsed_time_in_minutes: 0.0166667
-Elapsed_time_in_hours: 0.000277778
-Elapsed_time_in_days: 1.15741e-05
+Elapsed_time_in_seconds: 7
+Elapsed_time_in_minutes: 0.116667
+Elapsed_time_in_hours: 0.00194444
+Elapsed_time_in_days: 8.10185e-05
 
-Virtual_time_in_seconds: 0.55
-Virtual_time_in_minutes: 0.00916667
-Virtual_time_in_hours:   0.000152778
-Virtual_time_in_days:    6.36574e-06
+Virtual_time_in_seconds: 0.39
+Virtual_time_in_minutes: 0.0065
+Virtual_time_in_hours:   0.000108333
+Virtual_time_in_days:    4.51389e-06
 
 Ruby_current_time: 44968
 Ruby_start_time: 0
 Ruby_cycles: 44968
 
-mbytes_resident: 75.9648
-mbytes_total: 169.809
-resident_ratio: 0.447379
+mbytes_resident: 69.9375
+mbytes_total: 124.047
+resident_ratio: 0.563799
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
index 31ae36f2e..492f3e68f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simerr
@@ -1,3 +1,7 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
index 0eff99821..e2683dd74 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hell
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  1 2012 14:10:16
-gem5 started Sep  1 2012 14:11:29
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:36:12
+gem5 started Sep 22 2013 05:36:23
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
index 88933afb4..811c48f82 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000045                       # Nu
 sim_ticks                                       44968                       # Number of ticks simulated
 final_tick                                      44968                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  10546                       # Simulator instruction rate (inst/s)
-host_op_rate                                    10545                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 183989                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 174912                       # Number of bytes of host memory used
-host_seconds                                     0.24                       # Real time elapsed on the host
+host_inst_rate                                    423                       # Simulator instruction rate (inst/s)
+host_op_rate                                      423                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                   7389                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 127028                       # Number of bytes of host memory used
+host_seconds                                     6.09                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.L1Dcache.demand_hits          469                       # Number of cache demand hits
@@ -98,6 +98,18 @@ system.ruby.network.routers3.msg_bytes.Writeback_Control::0         8032
 system.ruby.network.routers3.msg_bytes.Writeback_Control::1         6512                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::2         2648                      
 system.ruby.network.routers3.msg_bytes.Unblock_Control::2         7464                      
+system.ruby.network.msg_count.Request_Control         2799                      
+system.ruby.network.msg_count.Response_Data         2538                      
+system.ruby.network.msg_count.ResponseL2hit_Data          261                      
+system.ruby.network.msg_count.Writeback_Data         1734                      
+system.ruby.network.msg_count.Writeback_Control         6447                      
+system.ruby.network.msg_count.Unblock_Control         2798                      
+system.ruby.network.msg_byte.Request_Control        22392                      
+system.ruby.network.msg_byte.Response_Data       182736                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        18792                      
+system.ruby.network.msg_byte.Writeback_Data       124848                      
+system.ruby.network.msg_byte.Writeback_Control        51576                      
+system.ruby.network.msg_byte.Unblock_Control        22384                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -276,18 +288,6 @@ system.ruby.l1_cntrl0.IM.Exclusive_Data            58      0.00%      0.00%
 system.ruby.l1_cntrl0.OM.All_acks                  58      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Exclusive_Data           452      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack_Data          502      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control         2799                      
-system.ruby.network.msg_count.Response_Data         2538                      
-system.ruby.network.msg_count.ResponseL2hit_Data          261                      
-system.ruby.network.msg_count.Writeback_Data         1734                      
-system.ruby.network.msg_count.Writeback_Control         6447                      
-system.ruby.network.msg_count.Unblock_Control         2798                      
-system.ruby.network.msg_byte.Request_Control        22392                      
-system.ruby.network.msg_byte.Response_Data       182736                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        18792                      
-system.ruby.network.msg_byte.Writeback_Data       124848                      
-system.ruby.network.msg_byte.Writeback_Control        51576                      
-system.ruby.network.msg_byte.Unblock_Control        22384                      
 system.ruby.l2_cntrl0.L1_GETS                     454      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETX                      58      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_PUTX                     502      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
index 963916828..57448e3a7 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
index 07281999c..95ae6441f 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:04:45
+Real time: Sep/22/2013 05:45:04
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 4
+Elapsed_time_in_minutes: 0.0666667
+Elapsed_time_in_hours: 0.00111111
+Elapsed_time_in_days: 4.62963e-05
 
-Virtual_time_in_seconds: 0.5
-Virtual_time_in_minutes: 0.00833333
-Virtual_time_in_hours:   0.000138889
-Virtual_time_in_days:    5.78704e-06
+Virtual_time_in_seconds: 0.35
+Virtual_time_in_minutes: 0.00583333
+Virtual_time_in_hours:   9.72222e-05
+Virtual_time_in_days:    4.05093e-06
 
 Ruby_current_time: 43073
 Ruby_start_time: 0
 Ruby_cycles: 43073
 
-mbytes_resident: 74.1172
-mbytes_total: 168.629
-resident_ratio: 0.439552
+mbytes_resident: 67.8711
+mbytes_total: 121.816
+resident_ratio: 0.557159
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
index 31ae36f2e..492f3e68f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simerr
@@ -1,3 +1,7 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
index f8e247e3b..76c77f4a5 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/al
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  9 2012 13:38:07
-gem5 started Sep  9 2012 13:38:15
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:44:48
+gem5 started Sep 22 2013 05:45:00
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
index 18f891852..c2d79012b 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000043                       # Nu
 sim_ticks                                       43073                       # Number of ticks simulated
 final_tick                                      43073                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  28702                       # Simulator instruction rate (inst/s)
-host_op_rate                                    28696                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 479543                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 172680                       # Number of bytes of host memory used
-host_seconds                                     0.09                       # Real time elapsed on the host
+host_inst_rate                                    753                       # Simulator instruction rate (inst/s)
+host_op_rate                                      753                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                  12587                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 125800                       # Number of bytes of host memory used
+host_seconds                                     3.42                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.L1Dcache.demand_hits          461                       # Number of cache demand hits
@@ -82,6 +82,18 @@ system.ruby.network.routers3.msg_bytes.ResponseL2hit_Data::4         5040
 system.ruby.network.routers3.msg_bytes.Response_Control::4            8                      
 system.ruby.network.routers3.msg_bytes.Writeback_Data::4        42192                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::4         2920                      
+system.ruby.network.msg_count.Request_Control         2916                      
+system.ruby.network.msg_count.Response_Data         1344                      
+system.ruby.network.msg_count.ResponseL2hit_Data          210                      
+system.ruby.network.msg_count.Response_Control            3                      
+system.ruby.network.msg_count.Writeback_Data         1758                      
+system.ruby.network.msg_count.Writeback_Control         1095                      
+system.ruby.network.msg_byte.Request_Control        23328                      
+system.ruby.network.msg_byte.Response_Data        96768                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        15120                      
+system.ruby.network.msg_byte.Response_Control           24                      
+system.ruby.network.msg_byte.Writeback_Data       126576                      
+system.ruby.network.msg_byte.Writeback_Control         8760                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -230,18 +242,6 @@ system.ruby.l1_cntrl0.IM.Ack                        1      0.00%      0.00%
 system.ruby.l1_cntrl0.SM.Data_All_Tokens            8      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data_Shared               56      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data_All_Tokens          396      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control         2916                      
-system.ruby.network.msg_count.Response_Data         1344                      
-system.ruby.network.msg_count.ResponseL2hit_Data          210                      
-system.ruby.network.msg_count.Response_Control            3                      
-system.ruby.network.msg_count.Writeback_Data         1758                      
-system.ruby.network.msg_count.Writeback_Control         1095                      
-system.ruby.network.msg_byte.Request_Control        23328                      
-system.ruby.network.msg_byte.Response_Data        96768                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        15120                      
-system.ruby.network.msg_byte.Response_Control           24                      
-system.ruby.network.msg_byte.Writeback_Data       126576                      
-system.ruby.network.msg_byte.Writeback_Control         8760                      
 system.ruby.l2_cntrl0.L1_GETS                     448      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETS_Last_Token            4      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETX                      66      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
index 88d0e9108..fed15fed0 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
index 11219bf48..fa2e0f324 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Aug/29/2013 10:02:56
+Real time: Sep/22/2013 05:17:49
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.71
-Virtual_time_in_minutes: 0.0118333
-Virtual_time_in_hours:   0.000197222
-Virtual_time_in_days:    8.21759e-06
+Virtual_time_in_seconds: 0.34
+Virtual_time_in_minutes: 0.00566667
+Virtual_time_in_hours:   9.44444e-05
+Virtual_time_in_days:    3.93519e-06
 
 Ruby_current_time: 35432
 Ruby_start_time: 0
 Ruby_cycles: 35432
 
-mbytes_resident: 74.0898
-mbytes_total: 168.559
-resident_ratio: 0.439573
+mbytes_resident: 67.9453
+mbytes_total: 122.797
+resident_ratio: 0.553315
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
index 31ae36f2e..492f3e68f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simerr
@@ -1,3 +1,7 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
index 8fae8fc4c..fa7b05ab3 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  1 2012 13:53:26
-gem5 started Sep  1 2012 13:54:34
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:17:28
+gem5 started Sep 22 2013 05:17:49
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
index f2e316805..f43282687 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000035                       # Nu
 sim_ticks                                       35432                       # Number of ticks simulated
 final_tick                                      35432                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   6072                       # Simulator instruction rate (inst/s)
-host_op_rate                                     6072                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                  83479                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 172608                       # Number of bytes of host memory used
-host_seconds                                     0.42                       # Real time elapsed on the host
+host_inst_rate                                  19167                       # Simulator instruction rate (inst/s)
+host_op_rate                                    19165                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 263474                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 125748                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.L1Dcache.demand_hits          469                       # Number of cache demand hits
@@ -82,6 +82,16 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2         3400
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3         3400                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::5         2752                      
 system.ruby.network.routers2.msg_bytes.Unblock_Control::5         3520                      
+system.ruby.network.msg_count.Request_Control         1323                      
+system.ruby.network.msg_count.Response_Data         1323                      
+system.ruby.network.msg_count.Writeback_Data          243                      
+system.ruby.network.msg_count.Writeback_Control         3582                      
+system.ruby.network.msg_count.Unblock_Control         1320                      
+system.ruby.network.msg_byte.Request_Control        10584                      
+system.ruby.network.msg_byte.Response_Data        95256                      
+system.ruby.network.msg_byte.Writeback_Data        17496                      
+system.ruby.network.msg_byte.Writeback_Control        28656                      
+system.ruby.network.msg_byte.Unblock_Control        10560                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -226,16 +236,6 @@ system.ruby.l1_cntrl0.MI.Store                      4      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack            425      0.00%      0.00%
 system.ruby.l1_cntrl0.MT.Complete_L2_to_L1           45      0.00%      0.00%
 system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1           24      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control         1323                      
-system.ruby.network.msg_count.Response_Data         1323                      
-system.ruby.network.msg_count.Writeback_Data          243                      
-system.ruby.network.msg_count.Writeback_Control         3582                      
-system.ruby.network.msg_count.Unblock_Control         1320                      
-system.ruby.network.msg_byte.Request_Control        10584                      
-system.ruby.network.msg_byte.Response_Data        95256                      
-system.ruby.network.msg_byte.Writeback_Data        17496                      
-system.ruby.network.msg_byte.Writeback_Control        28656                      
-system.ruby.network.msg_byte.Unblock_Control        10560                      
 system.ruby.dir_cntrl0.GETX                        51      0.00%      0.00%
 system.ruby.dir_cntrl0.GETS                       410      0.00%      0.00%
 system.ruby.dir_cntrl0.PUT                        425      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
index 222831dad..56f1e35ca 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
index 4a527e28b..dcfc1172a 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:03:45
+Real time: Sep/28/2013 03:05:38
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 19
-Elapsed_time_in_minutes: 0.316667
-Elapsed_time_in_hours: 0.00527778
-Elapsed_time_in_days: 0.000219907
+Elapsed_time_in_seconds: 0
+Elapsed_time_in_minutes: 0
+Elapsed_time_in_hours: 0
+Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours:   0.000141667
-Virtual_time_in_days:    5.90278e-06
+Virtual_time_in_seconds: 0.33
+Virtual_time_in_minutes: 0.0055
+Virtual_time_in_hours:   9.16667e-05
+Virtual_time_in_days:    3.81944e-06
 
 Ruby_current_time: 52498
 Ruby_start_time: 0
 Ruby_cycles: 52498
 
-mbytes_resident: 73.0898
-mbytes_total: 167.129
-resident_ratio: 0.43735
+mbytes_resident: 66.7812
+mbytes_total: 121.352
+resident_ratio: 0.550312
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
index 3bd6641db..492f3e68f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simerr
@@ -1,6 +1,6 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
index 8e744dee3..980ebae91 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:29:25
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:38
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
index 892e92009..2e221d41c 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000052                       # Nu
 sim_ticks                                       52498                       # Number of ticks simulated
 final_tick                                      52498                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                    139                       # Simulator instruction rate (inst/s)
-host_op_rate                                      139                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                   2832                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 171144                       # Number of bytes of host memory used
-host_seconds                                    18.54                       # Real time elapsed on the host
+host_inst_rate                                  20624                       # Simulator instruction rate (inst/s)
+host_op_rate                                    20621                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 420021                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 124268                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 sim_insts                                        2577                       # Number of instructions simulated
 sim_ops                                          2577                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         2668                       # Number of cache demand hits
@@ -55,6 +55,14 @@ system.ruby.network.routers2.msg_bytes.Control::2         5008
 system.ruby.network.routers2.msg_bytes.Data::2        44784                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4        45072                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3         4976                      
+system.ruby.network.msg_count.Control            1878                      
+system.ruby.network.msg_count.Data               1866                      
+system.ruby.network.msg_count.Response_Data         1878                      
+system.ruby.network.msg_count.Writeback_Control         1866                      
+system.ruby.network.msg_byte.Control            15024                      
+system.ruby.network.msg_byte.Data              134352                      
+system.ruby.network.msg_byte.Response_Data       135216                      
+system.ruby.network.msg_byte.Writeback_Control        14928                      
 system.cpu.dtb.fetch_hits                           0                       # ITB hits
 system.cpu.dtb.fetch_misses                         0                       # ITB misses
 system.cpu.dtb.fetch_acv                            0                       # ITB acv
@@ -156,14 +164,6 @@ system.ruby.l1_cntrl0.M.Replacement               622      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack            622      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data                     542      0.00%      0.00%
 system.ruby.l1_cntrl0.IM.Data                      84      0.00%      0.00%
-system.ruby.network.msg_count.Control            1878                      
-system.ruby.network.msg_count.Data               1866                      
-system.ruby.network.msg_count.Response_Data         1878                      
-system.ruby.network.msg_count.Writeback_Control         1866                      
-system.ruby.network.msg_byte.Control            15024                      
-system.ruby.network.msg_byte.Data              134352                      
-system.ruby.network.msg_byte.Response_Data       135216                      
-system.ruby.network.msg_byte.Writeback_Control        14928                      
 system.ruby.dir_cntrl0.GETX                       626      0.00%      0.00%
 system.ruby.dir_cntrl0.PUTX                       622      0.00%      0.00%
 system.ruby.dir_cntrl0.Memory_Data                626      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
index adb7f583e..81f228137 100644
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -119,10 +143,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/tru64/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/tru64/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
index d3b147605..f5b60c70f 100755
--- a/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/alpha/tru64/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 13:46:30
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:38
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/tru64/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
index 99487a7ba..a65f6cef4 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred checker dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=system.cpu.checker
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -134,9 +139,8 @@ predType=tournament
 [system.cpu.checker]
 type=O3Checker
 children=dtb isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -155,6 +159,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.checker.tracer
@@ -170,7 +175,7 @@ walker=system.cpu.checker.dtb.walker
 
 [system.cpu.checker.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[5]
@@ -200,7 +205,7 @@ walker=system.cpu.checker.itb.walker
 
 [system.cpu.checker.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[4]
@@ -210,10 +215,10 @@ type=ExeTracer
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -224,12 +229,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -238,7 +252,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -508,10 +522,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -522,12 +536,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -556,17 +579,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -577,16 +600,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -605,7 +636,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -616,10 +647,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -630,19 +665,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -653,6 +693,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
index d6f213d3f..ceaa08d85 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing-checker/simout
@@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 26 2013 15:15:53
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 07:58:36
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing-checker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 13706000 because target called exit()
+Exiting @ tick 16494000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
index a72da393a..c7dae4bd5 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -161,7 +175,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
@@ -431,10 +445,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -445,12 +459,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -479,17 +502,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -500,16 +523,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -528,7 +559,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -539,10 +570,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -553,19 +588,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -576,6 +616,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
index ed98a8f73..91a377601 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/o3-timing/simout
@@ -3,11 +3,11 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 26 2013 15:15:53
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:14:18
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 13706000 because target called exit()
+Exiting @ tick 16494000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
index 8b4c27750..05132e433 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=checker dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=system.cpu.checker
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -66,14 +75,14 @@ icache_port=system.membus.slave[1]
 [system.cpu.checker]
 type=DummyChecker
 children=dtb isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=-1
 do_checkpoint_insts=true
 do_quiesce=true
 do_statistics_insts=true
 dtb=system.cpu.checker.dtb
+exitOnError=false
 function_trace=false
 function_trace_start=0
 interrupts=Null
@@ -86,9 +95,12 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.checker.tracer
+updateOnError=false
+warnOnlyOnLoadError=true
 workload=system.cpu.workload
 
 [system.cpu.checker.dtb]
@@ -99,7 +111,7 @@ walker=system.cpu.checker.dtb.walker
 
 [system.cpu.checker.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
@@ -128,7 +140,7 @@ walker=system.cpu.checker.itb.walker
 
 [system.cpu.checker.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 
@@ -143,7 +155,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -176,7 +188,7 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -192,7 +204,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -203,11 +215,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +233,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
index 891f01e6f..3a9ca0eef 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic-dummychecker/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:44:07
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:10:56
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic-dummychecker
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
index b76b7c5a6..ea8fd73bf 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -71,7 +80,7 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[4]
@@ -104,7 +113,7 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.membus.slave[3]
@@ -120,7 +129,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -131,11 +140,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -144,13 +158,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
index 38a423124..7cee6c9ed 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-ato
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:43:56
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 08:14:08
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
index 276d0c57a..aa887d8df 100644
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +81,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=ArmTLB
 children=walker
@@ -89,17 +104,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,12 +125,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=ArmInterrupts
 
@@ -144,17 +168,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=ArmTableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
 num_squash_per_cycle=2
 sys=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -165,17 +189,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -192,7 +225,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/arm/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/arm/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -203,11 +236,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -216,13 +254,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
index 58b706eaf..db0e6caaf 100755
--- a/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/arm/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 19:43:25
-gem5 started Jan 23 2013 19:44:20
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 07:58:15
+gem5 started Sep 22 2013 09:24:32
+gem5 executing on zizzer
 command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing -re tests/run.py build/ARM/tests/opt/quick/se/00.hello/arm/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
index 5f7d725ac..2a0a5918d 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +42,7 @@ activity=0
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +72,7 @@ multRepeatRate=1
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +91,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +101,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +115,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=MipsTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=MipsInterrupts
 
@@ -156,10 +179,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -170,16 +193,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -198,7 +229,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -209,10 +240,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -223,19 +258,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -246,6 +286,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
index 146a5ec3a..0184d25db 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/inorder-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:56:08
-gem5 started Mar 26 2013 14:56:29
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:51:54
+gem5 started Sep 22 2013 05:52:06
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 19339000 because target called exit()
+Exiting @ tick 24587000 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
index 97699de37..daf8c58a2 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=MipsTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=MipsInterrupts
 
@@ -456,10 +479,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -470,16 +493,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -498,7 +529,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -509,10 +540,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -523,19 +558,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -546,6 +586,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
index 33a7977e7..64f5582df 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/o3-timing/simout
@@ -3,12 +3,12 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timin
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:56:08
-gem5 started Mar 26 2013 14:56:29
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:51:54
+gem5 started Sep 22 2013 05:52:09
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 info: Increasing stack size by one page.
 Hello World!
-Exiting @ tick 17026500 because target called exit()
+Exiting @ tick 21805500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
index 781c5e460..917891d7e 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -90,7 +99,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -101,11 +110,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -114,13 +128,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
index 2d983a191..b1c55ad09 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-a
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:16:48
-gem5 started Jan 23 2013 15:17:17
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:51:54
+gem5 started Sep 22 2013 05:52:07
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
index 62d44e3cc..793123a59 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -98,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
index 5da3f0737..bbc0c797e 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simerr
@@ -1,6 +1,6 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
index bc8425f96..5beaf8240 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:16:48
-gem5 started Jan 23 2013 15:17:40
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:51:54
+gem5 started Sep 22 2013 05:52:07
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
index 481b5bfc9..f05a7d5c9 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000125                       # Nu
 sim_ticks                                      125334                       # Number of ticks simulated
 final_tick                                     125334                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  33064                       # Simulator instruction rate (inst/s)
-host_op_rate                                    33061                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 712624                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 174400                       # Number of bytes of host memory used
-host_seconds                                     0.18                       # Real time elapsed on the host
+host_inst_rate                                   6951                       # Simulator instruction rate (inst/s)
+host_op_rate                                     6951                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 149835                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 127304                       # Number of bytes of host memory used
+host_seconds                                     0.84                       # Real time elapsed on the host
 sim_insts                                        5814                       # Number of instructions simulated
 sim_ops                                          5814                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         6410                       # Number of cache demand hits
@@ -56,6 +56,14 @@ system.ruby.network.routers2.msg_bytes.Control::2        11944
 system.ruby.network.routers2.msg_bytes.Data::2       107208                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4       107496                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3        11912                      
+system.ruby.network.msg_count.Control            4479                      
+system.ruby.network.msg_count.Data               4467                      
+system.ruby.network.msg_count.Response_Data         4479                      
+system.ruby.network.msg_count.Writeback_Control         4467                      
+system.ruby.network.msg_byte.Control            35832                      
+system.ruby.network.msg_byte.Data              321624                      
+system.ruby.network.msg_byte.Response_Data       322488                      
+system.ruby.network.msg_byte.Writeback_Control        35736                      
 system.cpu.dtb.read_hits                            0                       # DTB read hits
 system.cpu.dtb.read_misses                          0                       # DTB read misses
 system.cpu.dtb.read_accesses                        0                       # DTB read accesses
@@ -143,14 +151,6 @@ system.ruby.l1_cntrl0.M.Replacement              1489      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack           1489      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data                    1273      0.00%      0.00%
 system.ruby.l1_cntrl0.IM.Data                     220      0.00%      0.00%
-system.ruby.network.msg_count.Control            4479                      
-system.ruby.network.msg_count.Data               4467                      
-system.ruby.network.msg_count.Response_Data         4479                      
-system.ruby.network.msg_count.Writeback_Control         4467                      
-system.ruby.network.msg_byte.Control            35832                      
-system.ruby.network.msg_byte.Data              321624                      
-system.ruby.network.msg_byte.Response_Data       322488                      
-system.ruby.network.msg_byte.Writeback_Control        35736                      
 system.ruby.dir_cntrl0.GETX                      1493      0.00%      0.00%
 system.ruby.dir_cntrl0.PUTX                      1489      0.00%      0.00%
 system.ruby.dir_cntrl0.Memory_Data               1493      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
index 050099df0..aa6f1a156 100644
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=MipsTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=MipsInterrupts
 
@@ -121,10 +145,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -135,17 +159,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -162,7 +195,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/mips/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -173,11 +206,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -186,13 +224,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
index 3cdc50c15..f65ffe2d1 100755
--- a/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/mips/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-t
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:16:48
-gem5 started Jan 23 2013 15:17:28
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:51:54
+gem5 started Sep 22 2013 05:52:20
+gem5 executing on zizzer
 command line: build/MIPS/gem5.opt -d build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS/tests/opt/quick/se/00.hello/mips/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
index 1aa882d35..92f5ec07b 100644
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -44,7 +50,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -93,6 +99,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -122,11 +129,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -134,10 +139,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -148,12 +153,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=PowerTLB
 size=64
@@ -423,10 +437,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -437,12 +451,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=PowerInterrupts
 
@@ -455,10 +478,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -469,16 +492,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -497,7 +528,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/power/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -508,10 +539,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -522,19 +557,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -545,6 +585,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
index b6781a5c9..14f2d2615 100755
--- a/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/o3-timing/simout
@@ -3,11 +3,11 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:59:37
-gem5 started Mar 26 2013 14:59:57
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:59:47
+gem5 started Sep 22 2013 05:59:59
+gem5 executing on zizzer
 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 14724500 because target called exit()
+Exiting @ tick 18469500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
index de2e34e4d..0bfe98e66 100644
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,13 +30,17 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
 UnifiedTLB=true
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -54,6 +59,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -89,7 +98,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/power/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/power/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -100,11 +109,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -113,13 +127,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
index 82ad348ff..df127b542 100755
--- a/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/power/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/POWER/tests/opt/quick/se/00.hello/power/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:33:02
-gem5 started Jan 23 2013 15:33:19
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:59:47
+gem5 started Sep 22 2013 05:59:59
+gem5 executing on zizzer
 command line: build/POWER/gem5.opt -d build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic -re tests/run.py build/POWER/tests/opt/quick/se/00.hello/power/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
index 08313d557..803d2e67f 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +42,7 @@ activity=0
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +72,7 @@ multRepeatRate=1
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +91,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +101,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +115,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -154,10 +177,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,16 +191,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -196,7 +227,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,10 +238,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -221,19 +256,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -244,6 +284,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
index 06a0491cb..5555171c3 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/inorder-timing/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorde
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:04:14
-gem5 started Mar 26 2013 15:04:37
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:10:26
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Hello World!Exiting @ tick 16783500 because target called exit()
+Hello World!Exiting @ tick 20802500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
index d5e3e4b20..5f0f231f3 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
index 805340a73..3faafe3e1 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:12:14
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:09:49
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
index b14794472..0e46b888b 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -96,7 +95,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
index ec0034585..417331876 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:04:06
+Real time: Sep/22/2013 06:10:01
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.51
-Virtual_time_in_minutes: 0.0085
-Virtual_time_in_hours:   0.000141667
-Virtual_time_in_days:    5.90278e-06
+Virtual_time_in_seconds: 0.38
+Virtual_time_in_minutes: 0.00633333
+Virtual_time_in_hours:   0.000105556
+Virtual_time_in_days:    4.39815e-06
 
 Ruby_current_time: 107952
 Ruby_start_time: 0
 Ruby_cycles: 107952
 
-mbytes_resident: 76.2656
-mbytes_total: 176.473
-resident_ratio: 0.432189
+mbytes_resident: 69.6172
+mbytes_total: 130.562
+resident_ratio: 0.53321
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
index 5da3f0737..bbc0c797e 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simerr
@@ -1,6 +1,6 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 warn: Sockets disabled, not accepting gdb connections
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
index 34599be55..fe6ceebff 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:01:36
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:10:00
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
index 924fe00af..550fedd36 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000108                       # Nu
 sim_ticks                                      107952                       # Number of ticks simulated
 final_tick                                     107952                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                  23456                       # Simulator instruction rate (inst/s)
-host_op_rate                                    23454                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 475251                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 180712                       # Number of bytes of host memory used
-host_seconds                                     0.23                       # Real time elapsed on the host
+host_inst_rate                                  25358                       # Simulator instruction rate (inst/s)
+host_op_rate                                    25356                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 513807                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 133700                       # Number of bytes of host memory used
+host_seconds                                     0.21                       # Real time elapsed on the host
 sim_insts                                        5327                       # Number of instructions simulated
 sim_ops                                          5327                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         5469                       # Number of cache demand hits
@@ -56,6 +56,14 @@ system.ruby.network.routers2.msg_bytes.Control::2        10312
 system.ruby.network.routers2.msg_bytes.Data::2        92520                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4        92808                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3        10280                      
+system.ruby.network.msg_count.Control            3867                      
+system.ruby.network.msg_count.Data               3855                      
+system.ruby.network.msg_count.Response_Data         3867                      
+system.ruby.network.msg_count.Writeback_Control         3855                      
+system.ruby.network.msg_byte.Control            30936                      
+system.ruby.network.msg_byte.Data              277560                      
+system.ruby.network.msg_byte.Response_Data       278424                      
+system.ruby.network.msg_byte.Writeback_Control        30840                      
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                           107952                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -125,14 +133,6 @@ system.ruby.l1_cntrl0.M.Replacement              1285      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack           1285      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data                    1110      0.00%      0.00%
 system.ruby.l1_cntrl0.IM.Data                     179      0.00%      0.00%
-system.ruby.network.msg_count.Control            3867                      
-system.ruby.network.msg_count.Data               3855                      
-system.ruby.network.msg_count.Response_Data         3867                      
-system.ruby.network.msg_count.Writeback_Control         3855                      
-system.ruby.network.msg_byte.Control            30936                      
-system.ruby.network.msg_byte.Data              277560                      
-system.ruby.network.msg_byte.Response_Data       278424                      
-system.ruby.network.msg_byte.Writeback_Control        30840                      
 system.ruby.dir_cntrl0.GETX                      1289      0.00%      0.00%
 system.ruby.dir_cntrl0.PUTX                      1285      0.00%      0.00%
 system.ruby.dir_cntrl0.Memory_Data               1289      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
index 3ba498627..794c187b4 100644
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -119,10 +143,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/sparc/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/sparc/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
index 411439c6e..c2df02496 100755
--- a/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/sparc/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:12:36
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:07:31
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/00.hello/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
index aae98d141..3ff31f398 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,9 +30,14 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
-children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
+children=apic_clk_domain branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
 LFSTSize=1024
 LQEntries=32
 LSQCheckLoads=true
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -113,6 +120,11 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.branchPred]
 type=BranchPredictor
 BTBEntries=4096
@@ -121,11 +133,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +143,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +157,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -161,7 +180,8 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
@@ -430,10 +450,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -444,15 +464,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -472,16 +501,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -492,16 +522,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -520,7 +558,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -531,10 +569,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -545,19 +587,24 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -568,6 +615,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
index 6136a5e78..2fb7489b2 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/o3-timing/simout
@@ -3,11 +3,11 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:13:59
-gem5 started Mar 26 2013 15:14:41
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:21:36
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Hello world!
-Exiting @ tick 15474000 because target called exit()
+Exiting @ tick 19639500 because target called exit()
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
index 7de6f390d..6906721ce 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
-children=dtb interrupts isa itb tracer workload
-branchPred=Null
+children=apic_clk_domain dtb interrupts isa itb tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -63,6 +72,11 @@ workload=system.cpu.workload
 dcache_port=system.membus.slave[2]
 icache_port=system.membus.slave[1]
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -71,13 +85,14 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[4]
 
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -97,7 +112,8 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.membus.slave[3]
 
@@ -112,7 +128,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -123,10 +139,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -137,13 +157,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port system.cp
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
index 41b657a83..5c187d2d2 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-ato
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:21:58
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:21:50
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
index 585043740..3bbe64bb8 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=apic_clk_domain clk_domain dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu.clk_domain
 cpu_id=0
@@ -127,7 +126,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
index 09ae639bb..b58867c62 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Aug/29/2013 09:58:16
+Real time: Sep/22/2013 07:07:53
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0.0166667
 Elapsed_time_in_hours: 0.000277778
 Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.63
-Virtual_time_in_minutes: 0.0105
-Virtual_time_in_hours:   0.000175
-Virtual_time_in_days:    7.29167e-06
+Virtual_time_in_seconds: 0.43
+Virtual_time_in_minutes: 0.00716667
+Virtual_time_in_hours:   0.000119444
+Virtual_time_in_days:    4.97685e-06
 
 Ruby_current_time: 121759
 Ruby_start_time: 0
 Ruby_cycles: 121759
 
-mbytes_resident: 87.7695
-mbytes_total: 186.375
-resident_ratio: 0.470951
+mbytes_resident: 80.4375
+mbytes_total: 139.961
+resident_ratio: 0.574714
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
index 8c2cd3936..cb677e65b 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:21:58
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 07:07:52
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
index 06a39e4b5..8372264a3 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000122                       # Nu
 sim_ticks                                      121759                       # Number of ticks simulated
 final_tick                                     121759                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_inst_rate                                   9985                       # Simulator instruction rate (inst/s)
-host_op_rate                                    18087                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                                 225916                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 190852                       # Number of bytes of host memory used
-host_seconds                                     0.54                       # Real time elapsed on the host
+host_inst_rate                                  28174                       # Simulator instruction rate (inst/s)
+host_op_rate                                    51034                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                                 637400                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 143324                       # Number of bytes of host memory used
+host_seconds                                     0.19                       # Real time elapsed on the host
 sim_insts                                        5381                       # Number of instructions simulated
 sim_ops                                          9748                       # Number of ops (including micro ops) simulated
 system.ruby.l1_cntrl0.cacheMemory.demand_hits         7475                       # Number of cache demand hits
@@ -56,6 +56,14 @@ system.ruby.network.routers2.msg_bytes.Control::2        11016
 system.ruby.network.routers2.msg_bytes.Data::2        98856                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4        99144                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3        10984                      
+system.ruby.network.msg_count.Control            4131                      
+system.ruby.network.msg_count.Data               4119                      
+system.ruby.network.msg_count.Response_Data         4131                      
+system.ruby.network.msg_count.Writeback_Control         4119                      
+system.ruby.network.msg_byte.Control            33048                      
+system.ruby.network.msg_byte.Data              296568                      
+system.ruby.network.msg_byte.Response_Data       297432                      
+system.ruby.network.msg_byte.Writeback_Control        32952                      
 system.cpu.workload.num_syscalls                   11                       # Number of system calls
 system.cpu.numCycles                           121759                       # number of cpu cycles simulated
 system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
@@ -125,14 +133,6 @@ system.ruby.l1_cntrl0.M.Replacement              1373      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack           1373      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data                    1122      0.00%      0.00%
 system.ruby.l1_cntrl0.IM.Data                     255      0.00%      0.00%
-system.ruby.network.msg_count.Control            4131                      
-system.ruby.network.msg_count.Data               4119                      
-system.ruby.network.msg_count.Response_Data         4131                      
-system.ruby.network.msg_count.Writeback_Control         4119                      
-system.ruby.network.msg_byte.Control            33048                      
-system.ruby.network.msg_byte.Data              296568                      
-system.ruby.network.msg_byte.Response_Data       297432                      
-system.ruby.network.msg_byte.Writeback_Control        32952                      
 system.ruby.dir_cntrl0.GETX                      1377      0.00%      0.00%
 system.ruby.dir_cntrl0.PUTX                      1373      0.00%      0.00%
 system.ruby.dir_cntrl0.Memory_Data               1377      0.00%      0.00%
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
index 4f3f120ab..2a7188a36 100644
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
-children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
+children=apic_clk_domain dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -59,12 +65,17 @@ workload=system.cpu.workload
 dcache_port=system.cpu.dcache.cpu_side
 icache_port=system.cpu.icache.cpu_side
 
+[system.cpu.apic_clk_domain]
+type=DerivedClockDomain
+clk_divider=16
+clk_domain=system.cpu_clk_domain
+
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,12 +86,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=X86TLB
 children=walker
@@ -89,16 +109,17 @@ walker=system.cpu.dtb.walker
 
 [system.cpu.dtb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[3]
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -109,15 +130,24 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=X86LocalApic
-clock=8000
+clk_domain=system.cpu.apic_clk_domain
 int_latency=1000
 pio_addr=2305843009213693952
 pio_latency=100000
@@ -137,16 +167,17 @@ walker=system.cpu.itb.walker
 
 [system.cpu.itb.walker]
 type=X86PagetableWalker
-clock=500
+clk_domain=system.cpu_clk_domain
+num_squash_per_cycle=4
 system=system
 port=system.cpu.toL2Bus.slave[2]
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -157,16 +188,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -185,7 +224,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/x86/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/x86/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -196,10 +235,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -210,13 +253,16 @@ slave=system.system_port system.cpu.l2cache.mem_side system.cpu.interrupts.int_m
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
index e6d8615da..628ef5965 100755
--- a/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
+++ b/tests/quick/se/00.hello/ref/x86/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-tim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 11 2013 13:21:48
-gem5 started Mar 11 2013 13:21:58
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:21:20
+gem5 started Sep 22 2013 06:48:05
+gem5 executing on zizzer
 command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing -re tests/run.py build/X86/tests/opt/quick/se/00.hello/x86/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
index 934dbc782..5d2204eb4 100644
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa0 isa1 itb l2cache toL2Bus tracer workload0 workload1
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=2
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=AlphaTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=AlphaInterrupts
 
@@ -457,10 +480,10 @@ size=48
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -471,16 +494,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -499,7 +530,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -518,7 +549,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/hello/bin/alpha/linux/hello
+executable=/dist/m5/regression/test-progs/hello/bin/alpha/linux/hello
 gid=100
 input=cin
 max_stack_size=67108864
@@ -529,10 +560,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -543,19 +578,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -566,6 +606,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
index 6461709eb..32cdff876 100755
--- a/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
+++ b/tests/quick/se/01.hello-2T-smt/ref/alpha/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:13
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:38
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/01.hello-2T-smt/alpha/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -13,4 +13,4 @@ info: Increasing stack size by one page.
 info: Increasing stack size by one page.
 Hello world!
 Hello world!
-Exiting @ tick 24422500 because target called exit()
+Exiting @ tick 24404000 because target called exit()
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
index 4bb52cb94..86810fed8 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=InOrderCPU
 children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -36,7 +42,7 @@ activity=0
 branchPred=system.cpu.branchPred
 cachePorts=2
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 div16Latency=1
 div16RepeatRate=1
@@ -66,6 +72,7 @@ multRepeatRate=1
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 stageTracing=false
 stageWidth=4
 switched_out=false
@@ -84,11 +91,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -96,10 +101,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -110,22 +115,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -136,12 +150,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -154,10 +177,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -168,16 +191,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -196,7 +227,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
@@ -207,10 +238,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -221,19 +256,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -244,6 +284,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
index 637eeae2b..947073917 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/inorder-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/ino
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:09:42
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:11:33
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/inorder-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -20,4 +20,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 22838500 because target called exit()
+Exiting @ tick 27282000 because target called exit()
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
index 1c51ba20c..d46e2cc0c 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,6 +30,11 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=DerivO3CPU
 children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -454,10 +477,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -468,16 +491,24 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -496,7 +527,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
@@ -507,10 +538,14 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,19 +556,24 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -544,6 +584,9 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
index eeaf23c5e..f835cd945 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:04:14
-gem5 started Mar 26 2013 15:04:37
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:07:44
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/o3-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
@@ -20,4 +20,4 @@ LDTX:		Passed
 LDTW:		Passed
 STTW:		Passed
 Done
-Exiting @ tick 23775500 because target called exit()
+Exiting @ tick 26524500 because target called exit()
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
index a6e90c248..72cf29eda 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -88,7 +97,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
@@ -99,11 +108,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -112,13 +126,16 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
index b525c9dd9..24f0721ea 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-atomic/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 15:49:34
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:11:45
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-atomic
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
index fd5e57b82..77bbda99d 100644
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu.icache.cpu_side
 
 [system.cpu.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=262144
 system=system
+tags=system.cpu.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.dcache_port
 mem_side=system.cpu.toL2Bus.slave[1]
 
+[system.cpu.dcache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=262144
+
 [system.cpu.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=2
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=131072
 system=system
+tags=system.cpu.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.icache_port
 mem_side=system.cpu.toL2Bus.slave[0]
 
+[system.cpu.icache.tags]
+type=LRU
+assoc=2
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=131072
+
 [system.cpu.interrupts]
 type=SparcInterrupts
 
@@ -119,10 +143,10 @@ size=64
 
 [system.cpu.l2cache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -133,17 +157,26 @@ prefetcher=Null
 response_latency=20
 size=2097152
 system=system
+tags=system.cpu.l2cache.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu.toL2Bus.master[0]
 mem_side=system.membus.slave[1]
 
+[system.cpu.l2cache.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=2097152
+
 [system.cpu.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=32
 master=system.cpu.l2cache.cpu_side
@@ -160,7 +193,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/insttest/bin/sparc/linux/insttest
+executable=/dist/m5/regression/test-progs/insttest/bin/sparc/linux/insttest
 gid=100
 input=cin
 max_stack_size=67108864
@@ -171,11 +204,16 @@ simpoint=0
 system=system
 uid=100
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
@@ -184,13 +222,16 @@ slave=system.system_port system.cpu.l2cache.mem_side
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
index 2651935f3..de66adf5c 100755
--- a/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
+++ b/tests/quick/se/02.insttest/ref/sparc/linux/simple-timing/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/sim
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 15:49:45
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:07:35
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing -re tests/run.py build/SPARC/tests/opt/quick/se/02.insttest/sparc/linux/simple-timing
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
index 1686f16ad..b2863a63a 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu membus physmem
+children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -29,12 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[0]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu]
 type=AtomicSimpleCPU
 children=dtb interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -94,10 +99,14 @@ max_stack_size=67108864
 output=cout
 system=system
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -108,8 +117,8 @@ slave=system.system_port system.cpu.icache_port system.cpu.dcache_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
@@ -117,3 +126,7 @@ null=false
 range=0:134217727
 port=system.membus.master[0]
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
index e5b133727..a5ca10935 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-atomic/simout
@@ -1,8 +1,10 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  8 2013 10:00:13
-gem5 started Jun  8 2013 10:00:28
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:39
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-atomic
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
index c06c84e34..d9ac6433c 100644
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
diff --git a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
index fa0029313..f1715e087 100755
--- a/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
+++ b/tests/quick/se/20.eio-short/ref/alpha/eio/simple-timing/simout
@@ -1,8 +1,10 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 24 2013 11:53:30
-gem5 started Aug 24 2013 12:01:38
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:39
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/20.eio-short/alpha/eio/simple-timing
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
index 85ac3f7de..dbb4c3a8f 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -27,14 +28,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[1]
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -69,10 +74,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -83,22 +88,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -109,12 +123,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=AlphaInterrupts
 
@@ -141,9 +164,8 @@ system=system
 [system.cpu1]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=1
 do_checkpoint_insts=true
 do_quiesce=true
@@ -178,10 +200,10 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -192,22 +214,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -218,12 +249,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=AlphaInterrupts
 
@@ -250,9 +290,8 @@ system=system
 [system.cpu2]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=2
 do_checkpoint_insts=true
 do_quiesce=true
@@ -287,10 +326,10 @@ icache_port=system.cpu2.icache.cpu_side
 
 [system.cpu2.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -301,22 +340,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu2.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu2.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -327,12 +375,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu2.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.interrupts]
 type=AlphaInterrupts
 
@@ -359,9 +416,8 @@ system=system
 [system.cpu3]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=3
 do_checkpoint_insts=true
 do_quiesce=true
@@ -396,10 +452,10 @@ icache_port=system.cpu3.icache.cpu_side
 
 [system.cpu3.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -410,22 +466,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
 
+[system.cpu3.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.dtb]
 type=AlphaTLB
 size=64
 
 [system.cpu3.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +501,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
 
+[system.cpu3.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.interrupts]
 type=AlphaInterrupts
 
@@ -465,12 +539,17 @@ max_stack_size=67108864
 output=cout
 system=system
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -481,39 +560,46 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
+mem_side=system.membus.slave[1]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
 
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
+slave=system.system_port system.l2c.mem_side
 
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=0:1073741823
+range=0:134217727
 port=system.membus.master[0]
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -521,3 +607,7 @@ width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
index b26c03cc4..700bb6659 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simerr
@@ -6,3 +6,4 @@ hack: be nice to actually delete the event here
 gzip: stdout: Broken pipe
 
 gzip: stdout: Broken pipe
+stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
index 6f7f12863..44418ccaa 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/simout
@@ -1,8 +1,10 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jun  8 2013 10:00:13
-gem5 started Jun  8 2013 10:00:28
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:39
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
index 2e9aa5100..9ec6d0e6d 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000250                       # Nu
 sim_ticks                                   250015500                       # Number of ticks simulated
 final_tick                                  250015500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                3032804                       # Simulator instruction rate (inst/s)
-host_op_rate                                  3032728                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              379104441                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1154504                       # Number of bytes of host memory used
-host_seconds                                     0.66                       # Real time elapsed on the host
+host_inst_rate                                2981071                       # Simulator instruction rate (inst/s)
+host_op_rate                                  2980990                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                              372637325                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 238220                       # Number of bytes of host memory used
+host_seconds                                     0.67                       # Real time elapsed on the host
 sim_insts                                     2000004                       # Number of instructions simulated
 sim_ops                                       2000004                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu0.inst            25792                       # Number of bytes read from this memory
@@ -60,6 +60,167 @@ system.physmem.bw_total::total              877513594                       # To
 system.membus.throughput                    877513594                       # Throughput (bytes/s)
 system.membus.data_through_bus                 219392                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.l2c.tags.replacements                        0                       # number of replacements
+system.l2c.tags.tagsinuse                 1962.780232                       # Cycle average of tags in use
+system.l2c.tags.total_refs                        332                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                     2932                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     0.113233                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks      17.466765                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      267.152061                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data      219.176305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst      267.152061                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data      219.176305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst      267.152061                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data      219.176305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst      267.152061                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data      219.176305                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.000267                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.004076                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.003344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.004076                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.003344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.004076                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.003344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.004076                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.003344                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.029950                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst                 60                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data                  9                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst                 60                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst                 60                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst                 60                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks             116                       # number of Writeback hits
+system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
+system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
+system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
+system.l2c.overall_hits::total                    276                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst              403                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data              315                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst              403                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data              315                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst              403                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data              315                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst              403                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.data              315                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
+system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
+system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
+system.l2c.overall_misses::total                 3428                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.inst            463                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data            324                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst            463                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data            324                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst            463                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data            324                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst            463                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.data            324                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks          116                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data             463                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.870410                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.972222                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.870410                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.972222                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.870410                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.972222                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst      0.870410                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data      0.972222                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.912325                       # miss rate for ReadReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.870410                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.980562                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.925486                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.925486                       # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.toL2Bus.throughput                   977859373                       # Throughput (bytes/s)
 system.toL2Bus.data_through_bus                244480                       # Total data (bytes)
 system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
@@ -118,15 +279,15 @@ system.cpu0.num_idle_cycles                         0                       # Nu
 system.cpu0.num_busy_cycles                    500032                       # Number of busy cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.icache.tags.replacements                   152                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.replacements              152                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   218.086151                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.425950                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
 system.cpu0.icache.ReadReq_hits::cpu0.inst       499556                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst       499556                       # number of demand (read+write) hits
@@ -160,15 +321,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                    61                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.replacements               61                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   276.872320                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.540766                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.540766                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
 system.cpu0.dcache.ReadReq_hits::cpu0.data       124111                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data        56201                       # number of WriteReq hits
@@ -267,15 +428,15 @@ system.cpu1.num_idle_cycles                         0                       # Nu
 system.cpu1.num_busy_cycles                    500032                       # Number of busy cycles
 system.cpu1.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu1.icache.tags.replacements                   152                       # number of replacements
-system.cpu1.icache.tags.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.replacements              152                       # number of replacements
+system.cpu1.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.tags.occ_blocks::cpu1.inst   218.086151                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.425950                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
 system.cpu1.icache.ReadReq_hits::cpu1.inst       499556                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst       499556                       # number of demand (read+write) hits
@@ -309,15 +470,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets          nan
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                    61                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.replacements               61                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.tags.occ_blocks::cpu1.data   276.872320                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.540766                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.540766                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
 system.cpu1.dcache.ReadReq_hits::cpu1.data       124111                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data        56201                       # number of WriteReq hits
@@ -416,15 +577,15 @@ system.cpu2.num_idle_cycles                         0                       # Nu
 system.cpu2.num_busy_cycles                    500032                       # Number of busy cycles
 system.cpu2.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu2.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu2.icache.tags.replacements                   152                       # number of replacements
-system.cpu2.icache.tags.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.tags.replacements              152                       # number of replacements
+system.cpu2.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu2.icache.tags.occ_blocks::cpu2.inst   218.086151                       # Average occupied blocks per requestor
 system.cpu2.icache.tags.occ_percent::cpu2.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total        0.425950                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
 system.cpu2.icache.ReadReq_hits::cpu2.inst       499556                       # number of ReadReq hits
 system.cpu2.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
 system.cpu2.icache.demand_hits::cpu2.inst       499556                       # number of demand (read+write) hits
@@ -458,15 +619,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets          nan
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements                    61                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.tags.replacements               61                       # number of replacements
+system.cpu2.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu2.dcache.tags.occ_blocks::cpu2.data   276.872320                       # Average occupied blocks per requestor
 system.cpu2.dcache.tags.occ_percent::cpu2.data     0.540766                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total        0.540766                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
 system.cpu2.dcache.ReadReq_hits::cpu2.data       124111                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
 system.cpu2.dcache.WriteReq_hits::cpu2.data        56201                       # number of WriteReq hits
@@ -565,15 +726,15 @@ system.cpu3.num_idle_cycles                         0                       # Nu
 system.cpu3.num_busy_cycles                    500032                       # Number of busy cycles
 system.cpu3.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu3.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu3.icache.tags.replacements                   152                       # number of replacements
-system.cpu3.icache.tags.tagsinuse               218.086151                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs                  499556                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs               1078.954644                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.tags.replacements              152                       # number of replacements
+system.cpu3.icache.tags.tagsinuse          218.086151                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs             499556                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs          1078.954644                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu3.icache.tags.occ_blocks::cpu3.inst   218.086151                       # Average occupied blocks per requestor
 system.cpu3.icache.tags.occ_percent::cpu3.inst     0.425950                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total        0.425950                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.425950                       # Average percentage of cache occupancy
 system.cpu3.icache.ReadReq_hits::cpu3.inst       499556                       # number of ReadReq hits
 system.cpu3.icache.ReadReq_hits::total         499556                       # number of ReadReq hits
 system.cpu3.icache.demand_hits::cpu3.inst       499556                       # number of demand (read+write) hits
@@ -607,15 +768,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets          nan
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements                    61                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse               276.872320                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs                  180312                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs                   463                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs                389.442765                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.tags.replacements               61                       # number of replacements
+system.cpu3.dcache.tags.tagsinuse          276.872320                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs             180312                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs              463                       # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs           389.442765                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu3.dcache.tags.occ_blocks::cpu3.data   276.872320                       # Average occupied blocks per requestor
 system.cpu3.dcache.tags.occ_percent::cpu3.data     0.540766                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total        0.540766                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.540766                       # Average percentage of cache occupancy
 system.cpu3.dcache.ReadReq_hits::cpu3.data       124111                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_hits::total         124111                       # number of ReadReq hits
 system.cpu3.dcache.WriteReq_hits::cpu3.data        56201                       # number of WriteReq hits
@@ -659,166 +820,5 @@ system.cpu3.dcache.cache_copies                     0                       # nu
 system.cpu3.dcache.writebacks::writebacks           29                       # number of writebacks
 system.cpu3.dcache.writebacks::total               29                       # number of writebacks
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                             0                       # number of replacements
-system.l2c.tags.tagsinuse                      1962.780232                       # Cycle average of tags in use
-system.l2c.tags.total_refs                             332                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                          2932                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          0.113233                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks           17.466765                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst           267.152061                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data           219.176305                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.000267                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst            0.004076                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data            0.003344                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.029950                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                 60                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                    276                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks             116                       # number of Writeback hits
-system.l2c.Writeback_hits::total                  116                       # number of Writeback hits
-system.l2c.demand_hits::cpu0.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                  60                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                     276                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                 60                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                    276                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst              403                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data              315                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                 2872                       # number of ReadReq misses
-system.l2c.ReadExReq_misses::cpu0.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data            139                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                556                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst               403                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data               454                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                  3428                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu1.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu2.data              454                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst              403                       # number of overall misses
-system.l2c.overall_misses::cpu3.data              454                       # number of overall misses
-system.l2c.overall_misses::total                 3428                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            463                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data            324                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               3148                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks          116                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total              116                       # number of Writeback accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data          139                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              556                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data             463                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                3704                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data            463                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               3704                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.870410                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.972222                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.912325                       # miss rate for ReadReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.870410                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.980562                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.925486                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.870410                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.980562                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.925486                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
index 1b0504991..03af5b9e4 100644
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/config.ini
@@ -38,7 +38,6 @@ voltage_domain=system.voltage_domain
 [system.cpu0]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=0
@@ -158,7 +157,6 @@ system=system
 [system.cpu1]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=1
@@ -278,7 +276,6 @@ system=system
 [system.cpu2]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=2
@@ -398,7 +395,6 @@ system=system
 [system.cpu3]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
 clk_domain=system.cpu_clk_domain
 cpu_id=3
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
index 8b296506e..0997e3f27 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simerr
@@ -4,7 +4,6 @@ warn: Prefetch instructions in Alpha do not do anything
 hack: be nice to actually delete the event here
 
 gzip: stdout: Broken pipe
-
-gzip: stdout: Broken pipe
+stdout: Broken pipe
 
 gzip: stdout: Broken pipe
diff --git a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
index 8dc0648e9..0e186045b 100755
--- a/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
+++ b/tests/quick/se/30.eio-mp/ref/alpha/eio/simple-timing-mp/simout
@@ -1,8 +1,10 @@
+Redirecting stdout to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simout
+Redirecting stderr to build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 24 2013 11:53:30
-gem5 started Aug 24 2013 12:01:38
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:40
 gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp -re tests/run.py build/ALPHA/tests/opt/quick/se/30.eio-mp/alpha/eio/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
index 49d73401e..717f44afc 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -27,7 +28,12 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[1]
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=DerivO3CPU
@@ -43,7 +49,7 @@ backComSize=5
 branchPred=system.cpu0.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -92,6 +98,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -121,11 +128,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -133,10 +138,10 @@ predType=tournament
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -147,12 +152,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=SparcTLB
 size=64
@@ -422,10 +436,10 @@ opLat=3
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -436,12 +450,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=SparcInterrupts
 
@@ -463,7 +486,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
@@ -488,7 +511,7 @@ backComSize=5
 branchPred=system.cpu1.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -537,6 +560,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -566,11 +590,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -578,10 +600,10 @@ predType=tournament
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -592,12 +614,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=SparcTLB
 size=64
@@ -867,10 +898,10 @@ opLat=3
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -881,12 +912,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=SparcInterrupts
 
@@ -914,7 +954,7 @@ backComSize=5
 branchPred=system.cpu2.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -963,6 +1003,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -992,11 +1033,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -1004,10 +1043,10 @@ predType=tournament
 
 [system.cpu2.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -1018,12 +1057,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu2.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.dtb]
 type=SparcTLB
 size=64
@@ -1293,10 +1341,10 @@ opLat=3
 
 [system.cpu2.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -1307,12 +1355,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu2.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.interrupts]
 type=SparcInterrupts
 
@@ -1340,7 +1397,7 @@ backComSize=5
 branchPred=system.cpu3.branchPred
 cachePorts=200
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 commitToDecodeDelay=1
 commitToFetchDelay=1
 commitToIEWDelay=1
@@ -1389,6 +1446,7 @@ renameToFetchDelay=1
 renameToIEWDelay=2
 renameToROBDelay=1
 renameWidth=8
+simpoint_start_insts=
 smtCommitPolicy=RoundRobin
 smtFetchPolicy=SingleThread
 smtIQPolicy=Partitioned
@@ -1418,11 +1476,9 @@ RASSize=16
 choiceCtrBits=2
 choicePredictorSize=8192
 globalCtrBits=2
-globalHistoryBits=13
 globalPredictorSize=8192
 instShiftAmt=2
 localCtrBits=2
-localHistoryBits=11
 localHistoryTableSize=2048
 localPredictorSize=2048
 numThreads=1
@@ -1430,10 +1486,10 @@ predType=tournament
 
 [system.cpu3.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -1444,12 +1500,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
 
+[system.cpu3.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.dtb]
 type=SparcTLB
 size=64
@@ -1719,10 +1784,10 @@ opLat=3
 
 [system.cpu3.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -1733,12 +1798,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
 
+[system.cpu3.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.interrupts]
 type=SparcInterrupts
 
@@ -1752,12 +1826,17 @@ size=64
 [system.cpu3.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -1768,39 +1847,52 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
+mem_side=system.membus.slave[1]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
 
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
+slave=system.system_port system.l2c.mem_side
 
 [system.physmem]
 type=SimpleDRAM
 activation_limit=4
-addr_mapping=openmap
+addr_mapping=RaBaChCo
 banks_per_rank=8
+burst_length=8
 channels=1
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
 in_addr_map=true
-lines_per_rowbuffer=32
 mem_sched_policy=frfcfs
 null=false
 page_policy=open
 range=0:134217727
 ranks_per_channel=2
 read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
 tBURST=5000
 tCL=13750
 tRCD=13750
@@ -1811,13 +1903,11 @@ tWTR=7500
 tXAW=40000
 write_buffer_size=32
 write_thresh_perc=70
-zero=false
 port=system.membus.master[0]
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -1825,3 +1915,7 @@ width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
index 3c88e0e72..f522c13b1 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/simout
@@ -3,47 +3,47 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:04:14
-gem5 started Mar 26 2013 15:04:37
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:07:31
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/o3-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
-[Iteration 1, Thread 1] Got lock
-[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 1, Thread 1] Got lock
+[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1
 [Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 1 completed
-[Iteration 2, Thread 1] Got lock
-[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 2, Thread 2] Got lock
 [Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 1] Got lock
+[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 2 completed
-[Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 3, Thread 1] Got lock
 [Iteration 3, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 3, Thread 2] Got lock
+[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
 Iteration 3 completed
-[Iteration 4, Thread 2] Got lock
-[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1
 [Iteration 4, Thread 3] Got lock
 [Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
+[Iteration 4, Thread 2] Got lock
+[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2
 Iteration 4 completed
 [Iteration 5, Thread 3] Got lock
 [Iteration 5, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 5, Thread 1] Got lock
-[Iteration 5, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 1] Got lock
+[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 5 completed
 [Iteration 6, Thread 1] Got lock
 [Iteration 6, Thread 1] Critical section done, previously next=0, now next=1
@@ -52,33 +52,33 @@ Iteration 5 completed
 [Iteration 6, Thread 3] Got lock
 [Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 6 completed
-[Iteration 7, Thread 1] Got lock
-[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
 [Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 7, Thread 2] Got lock
+[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 1] Got lock
+[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 7 completed
-[Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 8, Thread 2] Got lock
-[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 8, Thread 1] Got lock
+[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 8 completed
 [Iteration 9, Thread 3] Got lock
 [Iteration 9, Thread 3] Critical section done, previously next=0, now next=3
-[Iteration 9, Thread 1] Got lock
-[Iteration 9, Thread 1] Critical section done, previously next=3, now next=1
 [Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 1] Got lock
+[Iteration 9, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 9 completed
-[Iteration 10, Thread 2] Got lock
-[Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 10, Thread 3] Got lock
-[Iteration 10, Thread 3] Critical section done, previously next=2, now next=3
+[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3
+[Iteration 10, Thread 2] Got lock
+[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2
 [Iteration 10, Thread 1] Got lock
-[Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 105945500 because target called exit()
+Exiting @ tick 110804500 because target called exit()
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
index 606c05841..aa7fc3405 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -27,14 +28,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[1]
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -53,6 +58,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -65,10 +74,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -79,22 +88,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -105,12 +123,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=SparcInterrupts
 
@@ -132,7 +159,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
@@ -146,9 +173,8 @@ uid=100
 [system.cpu1]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=1
 do_checkpoint_insts=true
 do_quiesce=true
@@ -167,6 +193,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -179,10 +209,10 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -193,22 +223,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -219,12 +258,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=SparcInterrupts
 
@@ -241,9 +289,8 @@ type=ExeTracer
 [system.cpu2]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=2
 do_checkpoint_insts=true
 do_quiesce=true
@@ -262,6 +309,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -274,10 +325,10 @@ icache_port=system.cpu2.icache.cpu_side
 
 [system.cpu2.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -288,22 +339,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu2.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu2.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -314,12 +374,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu2.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.interrupts]
 type=SparcInterrupts
 
@@ -336,9 +405,8 @@ type=ExeTracer
 [system.cpu3]
 type=AtomicSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=3
 do_checkpoint_insts=true
 do_quiesce=true
@@ -357,6 +425,10 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_interval=100000000
+simpoint_profile=false
+simpoint_profile_file=simpoint.bb.gz
+simpoint_start_insts=
 simulate_data_stalls=false
 simulate_inst_stalls=false
 switched_out=false
@@ -369,10 +441,10 @@ icache_port=system.cpu3.icache.cpu_side
 
 [system.cpu3.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -383,22 +455,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
 
+[system.cpu3.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu3.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -409,12 +490,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
 
+[system.cpu3.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.interrupts]
 type=SparcInterrupts
 
@@ -428,12 +518,17 @@ size=64
 [system.cpu3.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -444,42 +539,54 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
+mem_side=system.membus.slave[1]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
 
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
+slave=system.system_port system.l2c.mem_side
 
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
-range=0:1073741823
-zero=false
+range=0:134217727
 port=system.membus.master[0]
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
+system=system
 use_default_range=false
 width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
index e013c98f2..a3bbfbbb8 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 15:49:24
-gem5 started Jan 23 2013 16:09:53
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:09:34
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-atomic-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
index 42fbfc6a4..8179c99d9 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-atomic-mp/stats.txt
@@ -4,11 +4,11 @@ sim_seconds                                  0.000088                       # Nu
 sim_ticks                                    87707000                       # Number of ticks simulated
 final_tick                                   87707000                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                 1000000000000                       # Frequency of simulated ticks
-host_inst_rate                                1256528                       # Simulator instruction rate (inst/s)
-host_op_rate                                  1256465                       # Simulator op (including micro ops) rate (op/s)
-host_tick_rate                              162691956                       # Simulator tick rate (ticks/s)
-host_mem_usage                                1160656                       # Number of bytes of host memory used
-host_seconds                                     0.54                       # Real time elapsed on the host
+host_inst_rate                                 170274                       # Simulator instruction rate (inst/s)
+host_op_rate                                   170274                       # Simulator op (including micro ops) rate (op/s)
+host_tick_rate                               22048637                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 246052                       # Number of bytes of host memory used
+host_seconds                                     3.98                       # Real time elapsed on the host
 sim_insts                                      677327                       # Number of instructions simulated
 sim_ops                                        677327                       # Number of ops (including micro ops) simulated
 system.physmem.bytes_read::cpu0.inst            18048                       # Number of bytes read from this memory
@@ -60,6 +60,184 @@ system.physmem.bw_total::total              407903588                       # To
 system.membus.throughput                    407903588                       # Throughput (bytes/s)
 system.membus.data_through_bus                  35776                       # Total data (bytes)
 system.membus.snoop_data_through_bus                0                       # Total snoop data (bytes)
+system.l2c.tags.replacements                        0                       # number of replacements
+system.l2c.tags.tagsinuse                  366.582542                       # Cycle average of tags in use
+system.l2c.tags.total_refs                       1220                       # Total number of references to valid blocks.
+system.l2c.tags.sampled_refs                      421                       # Sample count of references to valid blocks.
+system.l2c.tags.avg_refs                     2.897862                       # Average number of references to valid blocks.
+system.l2c.tags.warmup_cycle                        0                       # Cycle when the warmup percentage was hit.
+system.l2c.tags.occ_blocks::writebacks       0.966439                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.inst      239.426226                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu0.data       55.207595                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.inst       59.511852                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu1.data        6.721145                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.inst        1.930661                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu2.data        0.935410                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.inst        0.977573                       # Average occupied blocks per requestor
+system.l2c.tags.occ_blocks::cpu3.data        0.905640                       # Average occupied blocks per requestor
+system.l2c.tags.occ_percent::writebacks      0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.inst       0.003653                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu0.data       0.000842                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.inst       0.000908                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu1.data       0.000103                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.inst       0.000029                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu2.data       0.000014                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.inst       0.000015                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::cpu3.data       0.000014                       # Average percentage of cache occupancy
+system.l2c.tags.occ_percent::total           0.005594                       # Average percentage of cache occupancy
+system.l2c.ReadReq_hits::cpu0.inst                185                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.inst                296                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu1.data                  3                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.inst                356                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.inst                357                       # number of ReadReq hits
+system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
+system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
+system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
+system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
+system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
+system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
+system.l2c.demand_hits::cpu0.inst                 185                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.inst                 296                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.inst                 356                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.inst                 357                       # number of demand (read+write) hits
+system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
+system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
+system.l2c.overall_hits::cpu0.inst                185                       # number of overall hits
+system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
+system.l2c.overall_hits::cpu1.inst                296                       # number of overall hits
+system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
+system.l2c.overall_hits::cpu2.inst                356                       # number of overall hits
+system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
+system.l2c.overall_hits::cpu3.inst                357                       # number of overall hits
+system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
+system.l2c.overall_hits::total                   1220                       # number of overall hits
+system.l2c.ReadReq_misses::cpu0.inst              282                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.inst               62                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.inst                2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.inst                2                       # number of ReadReq misses
+system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
+system.l2c.ReadReq_misses::total                  423                       # number of ReadReq misses
+system.l2c.UpgradeReq_misses::cpu0.data            29                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu1.data            18                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu2.data            19                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::cpu3.data            18                       # number of UpgradeReq misses
+system.l2c.UpgradeReq_misses::total                84                       # number of UpgradeReq misses
+system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
+system.l2c.ReadExReq_misses::total                136                       # number of ReadExReq misses
+system.l2c.demand_misses::cpu0.inst               282                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.inst                62                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.inst                 2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.inst                 2                       # number of demand (read+write) misses
+system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
+system.l2c.demand_misses::total                   559                       # number of demand (read+write) misses
+system.l2c.overall_misses::cpu0.inst              282                       # number of overall misses
+system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
+system.l2c.overall_misses::cpu1.inst               62                       # number of overall misses
+system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
+system.l2c.overall_misses::cpu2.inst                2                       # number of overall misses
+system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
+system.l2c.overall_misses::cpu3.inst                2                       # number of overall misses
+system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
+system.l2c.overall_misses::total                  559                       # number of overall misses
+system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.inst            358                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu1.data             10                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.inst            358                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu2.data             10                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.inst            359                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::cpu3.data             10                       # number of ReadReq accesses(hits+misses)
+system.l2c.ReadReq_accesses::total               1643                       # number of ReadReq accesses(hits+misses)
+system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
+system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu0.data           31                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu1.data           18                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu2.data           19                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::cpu3.data           18                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.UpgradeReq_accesses::total              86                       # number of UpgradeReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
+system.l2c.ReadExReq_accesses::total              136                       # number of ReadExReq accesses(hits+misses)
+system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.inst             358                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu1.data              23                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.inst             358                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu2.data              22                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.inst             359                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::cpu3.data              22                       # number of demand (read+write) accesses
+system.l2c.demand_accesses::total                1779                       # number of demand (read+write) accesses
+system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.inst            358                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu1.data             23                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.inst            358                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu2.data             22                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.inst            359                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::cpu3.data             22                       # number of overall (read+write) accesses
+system.l2c.overall_accesses::total               1779                       # number of overall (read+write) accesses
+system.l2c.ReadReq_miss_rate::cpu0.inst      0.603854                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.inst      0.173184                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu1.data      0.700000                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.inst      0.005587                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu2.data      0.100000                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.inst      0.005571                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::cpu3.data      0.100000                       # miss rate for ReadReq accesses
+system.l2c.ReadReq_miss_rate::total          0.257456                       # miss rate for ReadReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu0.data     0.935484                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
+system.l2c.UpgradeReq_miss_rate::total       0.976744                       # miss rate for UpgradeReq accesses
+system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
+system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
+system.l2c.demand_miss_rate::cpu0.inst       0.603854                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.inst       0.173184                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu1.data       0.869565                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.inst       0.005587                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu2.data       0.590909                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.inst       0.005571                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::cpu3.data       0.590909                       # miss rate for demand accesses
+system.l2c.demand_miss_rate::total           0.314221                       # miss rate for demand accesses
+system.l2c.overall_miss_rate::cpu0.inst      0.603854                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.inst      0.173184                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu1.data      0.869565                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.inst      0.005587                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu2.data      0.590909                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.inst      0.005571                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::cpu3.data      0.590909                       # miss rate for overall accesses
+system.l2c.overall_miss_rate::total          0.314221                       # miss rate for overall accesses
+system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
+system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
+system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
+system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
+system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
+system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
+system.l2c.fast_writes                              0                       # number of fast writes performed
+system.l2c.cache_copies                             0                       # number of cache copies performed
+system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 system.toL2Bus.throughput                  1893577480                       # Throughput (bytes/s)
 system.toL2Bus.data_through_bus                166080                       # Total data (bytes)
 system.toL2Bus.snoop_data_through_bus               0                       # Total snoop data (bytes)
@@ -86,15 +264,15 @@ system.cpu0.num_idle_cycles                         0                       # Nu
 system.cpu0.num_busy_cycles                    175415                       # Number of busy cycles
 system.cpu0.not_idle_fraction                       1                       # Percentage of non-idle cycles
 system.cpu0.idle_fraction                           0                       # Percentage of idle cycles
-system.cpu0.icache.tags.replacements                   215                       # number of replacements
-system.cpu0.icache.tags.tagsinuse               222.772698                       # Cycle average of tags in use
-system.cpu0.icache.tags.total_refs                  174921                       # Total number of references to valid blocks.
-system.cpu0.icache.tags.sampled_refs                   467                       # Sample count of references to valid blocks.
-system.cpu0.icache.tags.avg_refs                374.563169                       # Average number of references to valid blocks.
-system.cpu0.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.icache.tags.replacements              215                       # number of replacements
+system.cpu0.icache.tags.tagsinuse          222.772698                       # Cycle average of tags in use
+system.cpu0.icache.tags.total_refs             174921                       # Total number of references to valid blocks.
+system.cpu0.icache.tags.sampled_refs              467                       # Sample count of references to valid blocks.
+system.cpu0.icache.tags.avg_refs           374.563169                       # Average number of references to valid blocks.
+system.cpu0.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu0.icache.tags.occ_blocks::cpu0.inst   222.772698                       # Average occupied blocks per requestor
 system.cpu0.icache.tags.occ_percent::cpu0.inst     0.435103                       # Average percentage of cache occupancy
-system.cpu0.icache.tags.occ_percent::total        0.435103                       # Average percentage of cache occupancy
+system.cpu0.icache.tags.occ_percent::total     0.435103                       # Average percentage of cache occupancy
 system.cpu0.icache.ReadReq_hits::cpu0.inst       174921                       # number of ReadReq hits
 system.cpu0.icache.ReadReq_hits::total         174921                       # number of ReadReq hits
 system.cpu0.icache.demand_hits::cpu0.inst       174921                       # number of demand (read+write) hits
@@ -128,15 +306,15 @@ system.cpu0.icache.avg_blocked_cycles::no_targets          nan
 system.cpu0.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu0.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu0.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu0.dcache.tags.replacements                     2                       # number of replacements
-system.cpu0.dcache.tags.tagsinuse               150.745494                       # Cycle average of tags in use
-system.cpu0.dcache.tags.total_refs                   81883                       # Total number of references to valid blocks.
-system.cpu0.dcache.tags.sampled_refs                   167                       # Sample count of references to valid blocks.
-system.cpu0.dcache.tags.avg_refs                490.317365                       # Average number of references to valid blocks.
-system.cpu0.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu0.dcache.tags.replacements                2                       # number of replacements
+system.cpu0.dcache.tags.tagsinuse          150.745494                       # Cycle average of tags in use
+system.cpu0.dcache.tags.total_refs              81883                       # Total number of references to valid blocks.
+system.cpu0.dcache.tags.sampled_refs              167                       # Sample count of references to valid blocks.
+system.cpu0.dcache.tags.avg_refs           490.317365                       # Average number of references to valid blocks.
+system.cpu0.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu0.dcache.tags.occ_blocks::cpu0.data   150.745494                       # Average occupied blocks per requestor
 system.cpu0.dcache.tags.occ_percent::cpu0.data     0.294425                       # Average percentage of cache occupancy
-system.cpu0.dcache.tags.occ_percent::total        0.294425                       # Average percentage of cache occupancy
+system.cpu0.dcache.tags.occ_percent::total     0.294425                       # Average percentage of cache occupancy
 system.cpu0.dcache.ReadReq_hits::cpu0.data        54430                       # number of ReadReq hits
 system.cpu0.dcache.ReadReq_hits::total          54430                       # number of ReadReq hits
 system.cpu0.dcache.WriteReq_hits::cpu0.data        27578                       # number of WriteReq hits
@@ -210,15 +388,15 @@ system.cpu1.num_idle_cycles               7873.724337                       # Nu
 system.cpu1.num_busy_cycles              165421.275663                       # Number of busy cycles
 system.cpu1.not_idle_fraction                0.954565                       # Percentage of non-idle cycles
 system.cpu1.idle_fraction                    0.045435                       # Percentage of idle cycles
-system.cpu1.icache.tags.replacements                   278                       # number of replacements
-system.cpu1.icache.tags.tagsinuse                76.751702                       # Cycle average of tags in use
-system.cpu1.icache.tags.total_refs                  167072                       # Total number of references to valid blocks.
-system.cpu1.icache.tags.sampled_refs                   358                       # Sample count of references to valid blocks.
-system.cpu1.icache.tags.avg_refs                466.681564                       # Average number of references to valid blocks.
-system.cpu1.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.icache.tags.replacements              278                       # number of replacements
+system.cpu1.icache.tags.tagsinuse           76.751702                       # Cycle average of tags in use
+system.cpu1.icache.tags.total_refs             167072                       # Total number of references to valid blocks.
+system.cpu1.icache.tags.sampled_refs              358                       # Sample count of references to valid blocks.
+system.cpu1.icache.tags.avg_refs           466.681564                       # Average number of references to valid blocks.
+system.cpu1.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu1.icache.tags.occ_blocks::cpu1.inst    76.751702                       # Average occupied blocks per requestor
 system.cpu1.icache.tags.occ_percent::cpu1.inst     0.149906                       # Average percentage of cache occupancy
-system.cpu1.icache.tags.occ_percent::total        0.149906                       # Average percentage of cache occupancy
+system.cpu1.icache.tags.occ_percent::total     0.149906                       # Average percentage of cache occupancy
 system.cpu1.icache.ReadReq_hits::cpu1.inst       167072                       # number of ReadReq hits
 system.cpu1.icache.ReadReq_hits::total         167072                       # number of ReadReq hits
 system.cpu1.icache.demand_hits::cpu1.inst       167072                       # number of demand (read+write) hits
@@ -252,15 +430,15 @@ system.cpu1.icache.avg_blocked_cycles::no_targets          nan
 system.cpu1.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu1.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu1.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu1.dcache.tags.replacements                     0                       # number of replacements
-system.cpu1.dcache.tags.tagsinuse                30.316999                       # Cycle average of tags in use
-system.cpu1.dcache.tags.total_refs                   26731                       # Total number of references to valid blocks.
-system.cpu1.dcache.tags.sampled_refs                    26                       # Sample count of references to valid blocks.
-system.cpu1.dcache.tags.avg_refs               1028.115385                       # Average number of references to valid blocks.
-system.cpu1.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu1.dcache.tags.replacements                0                       # number of replacements
+system.cpu1.dcache.tags.tagsinuse           30.316999                       # Cycle average of tags in use
+system.cpu1.dcache.tags.total_refs              26731                       # Total number of references to valid blocks.
+system.cpu1.dcache.tags.sampled_refs               26                       # Sample count of references to valid blocks.
+system.cpu1.dcache.tags.avg_refs          1028.115385                       # Average number of references to valid blocks.
+system.cpu1.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu1.dcache.tags.occ_blocks::cpu1.data    30.316999                       # Average occupied blocks per requestor
 system.cpu1.dcache.tags.occ_percent::cpu1.data     0.059213                       # Average percentage of cache occupancy
-system.cpu1.dcache.tags.occ_percent::total        0.059213                       # Average percentage of cache occupancy
+system.cpu1.dcache.tags.occ_percent::total     0.059213                       # Average percentage of cache occupancy
 system.cpu1.dcache.ReadReq_hits::cpu1.data        40470                       # number of ReadReq hits
 system.cpu1.dcache.ReadReq_hits::total          40470                       # number of ReadReq hits
 system.cpu1.dcache.WriteReq_hits::cpu1.data        12563                       # number of WriteReq hits
@@ -332,15 +510,15 @@ system.cpu2.num_idle_cycles               7936.951217                       # Nu
 system.cpu2.num_busy_cycles              165358.048783                       # Number of busy cycles
 system.cpu2.not_idle_fraction                0.954200                       # Percentage of non-idle cycles
 system.cpu2.idle_fraction                    0.045800                       # Percentage of idle cycles
-system.cpu2.icache.tags.replacements                   278                       # number of replacements
-system.cpu2.icache.tags.tagsinuse                74.781015                       # Cycle average of tags in use
-system.cpu2.icache.tags.total_refs                  167008                       # Total number of references to valid blocks.
-system.cpu2.icache.tags.sampled_refs                   358                       # Sample count of references to valid blocks.
-system.cpu2.icache.tags.avg_refs                466.502793                       # Average number of references to valid blocks.
-system.cpu2.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.icache.tags.replacements              278                       # number of replacements
+system.cpu2.icache.tags.tagsinuse           74.781015                       # Cycle average of tags in use
+system.cpu2.icache.tags.total_refs             167008                       # Total number of references to valid blocks.
+system.cpu2.icache.tags.sampled_refs              358                       # Sample count of references to valid blocks.
+system.cpu2.icache.tags.avg_refs           466.502793                       # Average number of references to valid blocks.
+system.cpu2.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu2.icache.tags.occ_blocks::cpu2.inst    74.781015                       # Average occupied blocks per requestor
 system.cpu2.icache.tags.occ_percent::cpu2.inst     0.146057                       # Average percentage of cache occupancy
-system.cpu2.icache.tags.occ_percent::total        0.146057                       # Average percentage of cache occupancy
+system.cpu2.icache.tags.occ_percent::total     0.146057                       # Average percentage of cache occupancy
 system.cpu2.icache.ReadReq_hits::cpu2.inst       167008                       # number of ReadReq hits
 system.cpu2.icache.ReadReq_hits::total         167008                       # number of ReadReq hits
 system.cpu2.icache.demand_hits::cpu2.inst       167008                       # number of demand (read+write) hits
@@ -374,15 +552,15 @@ system.cpu2.icache.avg_blocked_cycles::no_targets          nan
 system.cpu2.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu2.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu2.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu2.dcache.tags.replacements                     0                       # number of replacements
-system.cpu2.dcache.tags.tagsinuse                29.605505                       # Cycle average of tags in use
-system.cpu2.dcache.tags.total_refs                   33613                       # Total number of references to valid blocks.
-system.cpu2.dcache.tags.sampled_refs                    26                       # Sample count of references to valid blocks.
-system.cpu2.dcache.tags.avg_refs               1292.807692                       # Average number of references to valid blocks.
-system.cpu2.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu2.dcache.tags.replacements                0                       # number of replacements
+system.cpu2.dcache.tags.tagsinuse           29.605505                       # Cycle average of tags in use
+system.cpu2.dcache.tags.total_refs              33613                       # Total number of references to valid blocks.
+system.cpu2.dcache.tags.sampled_refs               26                       # Sample count of references to valid blocks.
+system.cpu2.dcache.tags.avg_refs          1292.807692                       # Average number of references to valid blocks.
+system.cpu2.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu2.dcache.tags.occ_blocks::cpu2.data    29.605505                       # Average occupied blocks per requestor
 system.cpu2.dcache.tags.occ_percent::cpu2.data     0.057823                       # Average percentage of cache occupancy
-system.cpu2.dcache.tags.occ_percent::total        0.057823                       # Average percentage of cache occupancy
+system.cpu2.dcache.tags.occ_percent::total     0.057823                       # Average percentage of cache occupancy
 system.cpu2.dcache.ReadReq_hits::cpu2.data        42194                       # number of ReadReq hits
 system.cpu2.dcache.ReadReq_hits::total          42194                       # number of ReadReq hits
 system.cpu2.dcache.WriteReq_hits::cpu2.data        15998                       # number of WriteReq hits
@@ -454,15 +632,15 @@ system.cpu3.num_idle_cycles               8001.119846                       # Nu
 system.cpu3.num_busy_cycles              165292.880154                       # Number of busy cycles
 system.cpu3.not_idle_fraction                0.953829                       # Percentage of non-idle cycles
 system.cpu3.idle_fraction                    0.046171                       # Percentage of idle cycles
-system.cpu3.icache.tags.replacements                   279                       # number of replacements
-system.cpu3.icache.tags.tagsinuse                72.874497                       # Cycle average of tags in use
-system.cpu3.icache.tags.total_refs                  166942                       # Total number of references to valid blocks.
-system.cpu3.icache.tags.sampled_refs                   359                       # Sample count of references to valid blocks.
-system.cpu3.icache.tags.avg_refs                465.019499                       # Average number of references to valid blocks.
-system.cpu3.icache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.icache.tags.replacements              279                       # number of replacements
+system.cpu3.icache.tags.tagsinuse           72.874497                       # Cycle average of tags in use
+system.cpu3.icache.tags.total_refs             166942                       # Total number of references to valid blocks.
+system.cpu3.icache.tags.sampled_refs              359                       # Sample count of references to valid blocks.
+system.cpu3.icache.tags.avg_refs           465.019499                       # Average number of references to valid blocks.
+system.cpu3.icache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu3.icache.tags.occ_blocks::cpu3.inst    72.874497                       # Average occupied blocks per requestor
 system.cpu3.icache.tags.occ_percent::cpu3.inst     0.142333                       # Average percentage of cache occupancy
-system.cpu3.icache.tags.occ_percent::total        0.142333                       # Average percentage of cache occupancy
+system.cpu3.icache.tags.occ_percent::total     0.142333                       # Average percentage of cache occupancy
 system.cpu3.icache.ReadReq_hits::cpu3.inst       166942                       # number of ReadReq hits
 system.cpu3.icache.ReadReq_hits::total         166942                       # number of ReadReq hits
 system.cpu3.icache.demand_hits::cpu3.inst       166942                       # number of demand (read+write) hits
@@ -496,15 +674,15 @@ system.cpu3.icache.avg_blocked_cycles::no_targets          nan
 system.cpu3.icache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.icache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.icache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu3.dcache.tags.replacements                     0                       # number of replacements
-system.cpu3.dcache.tags.tagsinuse                28.795404                       # Cycle average of tags in use
-system.cpu3.dcache.tags.total_refs                   30236                       # Total number of references to valid blocks.
-system.cpu3.dcache.tags.sampled_refs                    27                       # Sample count of references to valid blocks.
-system.cpu3.dcache.tags.avg_refs               1119.851852                       # Average number of references to valid blocks.
-system.cpu3.dcache.tags.warmup_cycle                     0                       # Cycle when the warmup percentage was hit.
+system.cpu3.dcache.tags.replacements                0                       # number of replacements
+system.cpu3.dcache.tags.tagsinuse           28.795404                       # Cycle average of tags in use
+system.cpu3.dcache.tags.total_refs              30236                       # Total number of references to valid blocks.
+system.cpu3.dcache.tags.sampled_refs               27                       # Sample count of references to valid blocks.
+system.cpu3.dcache.tags.avg_refs          1119.851852                       # Average number of references to valid blocks.
+system.cpu3.dcache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
 system.cpu3.dcache.tags.occ_blocks::cpu3.data    28.795404                       # Average occupied blocks per requestor
 system.cpu3.dcache.tags.occ_percent::cpu3.data     0.056241                       # Average percentage of cache occupancy
-system.cpu3.dcache.tags.occ_percent::total        0.056241                       # Average percentage of cache occupancy
+system.cpu3.dcache.tags.occ_percent::total     0.056241                       # Average percentage of cache occupancy
 system.cpu3.dcache.ReadReq_hits::cpu3.data        41301                       # number of ReadReq hits
 system.cpu3.dcache.ReadReq_hits::total          41301                       # number of ReadReq hits
 system.cpu3.dcache.WriteReq_hits::cpu3.data        14260                       # number of WriteReq hits
@@ -554,183 +732,5 @@ system.cpu3.dcache.avg_blocked_cycles::no_targets          nan
 system.cpu3.dcache.fast_writes                      0                       # number of fast writes performed
 system.cpu3.dcache.cache_copies                     0                       # number of cache copies performed
 system.cpu3.dcache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.l2c.tags.replacements                             0                       # number of replacements
-system.l2c.tags.tagsinuse                       366.582542                       # Cycle average of tags in use
-system.l2c.tags.total_refs                            1220                       # Total number of references to valid blocks.
-system.l2c.tags.sampled_refs                           421                       # Sample count of references to valid blocks.
-system.l2c.tags.avg_refs                          2.897862                       # Average number of references to valid blocks.
-system.l2c.tags.warmup_cycle                             0                       # Cycle when the warmup percentage was hit.
-system.l2c.tags.occ_blocks::writebacks            0.966439                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.inst           239.426226                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu0.data            55.207595                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.inst            59.511852                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu1.data             6.721145                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.inst             1.930661                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu2.data             0.935410                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.inst             0.977573                       # Average occupied blocks per requestor
-system.l2c.tags.occ_blocks::cpu3.data             0.905640                       # Average occupied blocks per requestor
-system.l2c.tags.occ_percent::writebacks           0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.inst            0.003653                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu0.data            0.000842                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.inst            0.000908                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu1.data            0.000103                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.inst            0.000029                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu2.data            0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.inst            0.000015                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::cpu3.data            0.000014                       # Average percentage of cache occupancy
-system.l2c.tags.occ_percent::total                0.005594                       # Average percentage of cache occupancy
-system.l2c.ReadReq_hits::cpu0.inst                185                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu0.data                  5                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.inst                296                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu1.data                  3                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.inst                356                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu2.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.inst                357                       # number of ReadReq hits
-system.l2c.ReadReq_hits::cpu3.data                  9                       # number of ReadReq hits
-system.l2c.ReadReq_hits::total                   1220                       # number of ReadReq hits
-system.l2c.Writeback_hits::writebacks               1                       # number of Writeback hits
-system.l2c.Writeback_hits::total                    1                       # number of Writeback hits
-system.l2c.UpgradeReq_hits::cpu0.data               2                       # number of UpgradeReq hits
-system.l2c.UpgradeReq_hits::total                   2                       # number of UpgradeReq hits
-system.l2c.demand_hits::cpu0.inst                 185                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu0.data                   5                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.inst                 296                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu1.data                   3                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.inst                 356                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu2.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.inst                 357                       # number of demand (read+write) hits
-system.l2c.demand_hits::cpu3.data                   9                       # number of demand (read+write) hits
-system.l2c.demand_hits::total                    1220                       # number of demand (read+write) hits
-system.l2c.overall_hits::cpu0.inst                185                       # number of overall hits
-system.l2c.overall_hits::cpu0.data                  5                       # number of overall hits
-system.l2c.overall_hits::cpu1.inst                296                       # number of overall hits
-system.l2c.overall_hits::cpu1.data                  3                       # number of overall hits
-system.l2c.overall_hits::cpu2.inst                356                       # number of overall hits
-system.l2c.overall_hits::cpu2.data                  9                       # number of overall hits
-system.l2c.overall_hits::cpu3.inst                357                       # number of overall hits
-system.l2c.overall_hits::cpu3.data                  9                       # number of overall hits
-system.l2c.overall_hits::total                   1220                       # number of overall hits
-system.l2c.ReadReq_misses::cpu0.inst              282                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu0.data               66                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.inst               62                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu1.data                7                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.inst                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu2.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.inst                2                       # number of ReadReq misses
-system.l2c.ReadReq_misses::cpu3.data                1                       # number of ReadReq misses
-system.l2c.ReadReq_misses::total                  423                       # number of ReadReq misses
-system.l2c.UpgradeReq_misses::cpu0.data            29                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu1.data            18                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu2.data            19                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::cpu3.data            18                       # number of UpgradeReq misses
-system.l2c.UpgradeReq_misses::total                84                       # number of UpgradeReq misses
-system.l2c.ReadExReq_misses::cpu0.data             99                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu1.data             13                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu2.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::cpu3.data             12                       # number of ReadExReq misses
-system.l2c.ReadExReq_misses::total                136                       # number of ReadExReq misses
-system.l2c.demand_misses::cpu0.inst               282                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu0.data               165                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.inst                62                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu1.data                20                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.inst                 2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu2.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.inst                 2                       # number of demand (read+write) misses
-system.l2c.demand_misses::cpu3.data                13                       # number of demand (read+write) misses
-system.l2c.demand_misses::total                   559                       # number of demand (read+write) misses
-system.l2c.overall_misses::cpu0.inst              282                       # number of overall misses
-system.l2c.overall_misses::cpu0.data              165                       # number of overall misses
-system.l2c.overall_misses::cpu1.inst               62                       # number of overall misses
-system.l2c.overall_misses::cpu1.data               20                       # number of overall misses
-system.l2c.overall_misses::cpu2.inst                2                       # number of overall misses
-system.l2c.overall_misses::cpu2.data               13                       # number of overall misses
-system.l2c.overall_misses::cpu3.inst                2                       # number of overall misses
-system.l2c.overall_misses::cpu3.data               13                       # number of overall misses
-system.l2c.overall_misses::total                  559                       # number of overall misses
-system.l2c.ReadReq_accesses::cpu0.inst            467                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu0.data             71                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.inst            358                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu1.data             10                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.inst            358                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu2.data             10                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.inst            359                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::cpu3.data             10                       # number of ReadReq accesses(hits+misses)
-system.l2c.ReadReq_accesses::total               1643                       # number of ReadReq accesses(hits+misses)
-system.l2c.Writeback_accesses::writebacks            1                       # number of Writeback accesses(hits+misses)
-system.l2c.Writeback_accesses::total                1                       # number of Writeback accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu0.data           31                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu1.data           18                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu2.data           19                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::cpu3.data           18                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.UpgradeReq_accesses::total              86                       # number of UpgradeReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu0.data           99                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu1.data           13                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu2.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::cpu3.data           12                       # number of ReadExReq accesses(hits+misses)
-system.l2c.ReadExReq_accesses::total              136                       # number of ReadExReq accesses(hits+misses)
-system.l2c.demand_accesses::cpu0.inst             467                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu0.data             170                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.inst             358                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu1.data              23                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.inst             358                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu2.data              22                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.inst             359                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::cpu3.data              22                       # number of demand (read+write) accesses
-system.l2c.demand_accesses::total                1779                       # number of demand (read+write) accesses
-system.l2c.overall_accesses::cpu0.inst            467                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu0.data            170                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.inst            358                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu1.data             23                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.inst            358                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu2.data             22                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.inst            359                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::cpu3.data             22                       # number of overall (read+write) accesses
-system.l2c.overall_accesses::total               1779                       # number of overall (read+write) accesses
-system.l2c.ReadReq_miss_rate::cpu0.inst      0.603854                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu0.data      0.929577                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.inst      0.173184                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu1.data      0.700000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.inst      0.005587                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu2.data      0.100000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.inst      0.005571                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::cpu3.data      0.100000                       # miss rate for ReadReq accesses
-system.l2c.ReadReq_miss_rate::total          0.257456                       # miss rate for ReadReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu0.data     0.935484                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu1.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu2.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::cpu3.data            1                       # miss rate for UpgradeReq accesses
-system.l2c.UpgradeReq_miss_rate::total       0.976744                       # miss rate for UpgradeReq accesses
-system.l2c.ReadExReq_miss_rate::cpu0.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu1.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu2.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::cpu3.data            1                       # miss rate for ReadExReq accesses
-system.l2c.ReadExReq_miss_rate::total               1                       # miss rate for ReadExReq accesses
-system.l2c.demand_miss_rate::cpu0.inst       0.603854                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu0.data       0.970588                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.inst       0.173184                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu1.data       0.869565                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.inst       0.005587                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu2.data       0.590909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.inst       0.005571                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::cpu3.data       0.590909                       # miss rate for demand accesses
-system.l2c.demand_miss_rate::total           0.314221                       # miss rate for demand accesses
-system.l2c.overall_miss_rate::cpu0.inst      0.603854                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu0.data      0.970588                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.inst      0.173184                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu1.data      0.869565                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.inst      0.005587                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu2.data      0.590909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.inst      0.005571                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::cpu3.data      0.590909                       # miss rate for overall accesses
-system.l2c.overall_miss_rate::total          0.314221                       # miss rate for overall accesses
-system.l2c.blocked_cycles::no_mshrs                 0                       # number of cycles access was blocked
-system.l2c.blocked_cycles::no_targets               0                       # number of cycles access was blocked
-system.l2c.blocked::no_mshrs                        0                       # number of cycles access was blocked
-system.l2c.blocked::no_targets                      0                       # number of cycles access was blocked
-system.l2c.avg_blocked_cycles::no_mshrs           nan                       # average number of cycles each access was blocked
-system.l2c.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
-system.l2c.fast_writes                              0                       # number of fast writes performed
-system.l2c.cache_copies                             0                       # number of cache copies performed
-system.l2c.no_allocate_misses                       0                       # Number of misses that were no-allocate
 
 ---------- End Simulation Statistics   ----------
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
index b4eef5d4b..51f67db18 100644
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/config.ini
@@ -8,9 +8,10 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu_clk_domain l2c membus physmem toL2Bus voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
@@ -27,14 +28,18 @@ work_cpus_ckpt_count=0
 work_end_ckpt_count=0
 work_end_exit_count=0
 work_item_id=-1
-system_port=system.membus.slave[1]
+system_port=system.membus.slave[0]
+
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
 
 [system.cpu0]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer workload
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=0
 do_checkpoint_insts=true
 do_quiesce=true
@@ -52,6 +57,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu0.tracer
@@ -61,10 +67,10 @@ icache_port=system.cpu0.icache.cpu_side
 
 [system.cpu0.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -75,22 +81,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.dcache_port
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu0.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu0.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -101,12 +116,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.icache_port
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu0.interrupts]
 type=SparcInterrupts
 
@@ -128,7 +152,7 @@ egid=100
 env=
 errout=cerr
 euid=100
-executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic
+executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic
 gid=100
 input=cin
 max_stack_size=67108864
@@ -142,9 +166,8 @@ uid=100
 [system.cpu1]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=1
 do_checkpoint_insts=true
 do_quiesce=true
@@ -162,6 +185,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu1.tracer
@@ -171,10 +195,10 @@ icache_port=system.cpu1.icache.cpu_side
 
 [system.cpu1.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -185,22 +209,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.dcache_port
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu1.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu1.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -211,12 +244,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.icache_port
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu1.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1.interrupts]
 type=SparcInterrupts
 
@@ -233,9 +275,8 @@ type=ExeTracer
 [system.cpu2]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=2
 do_checkpoint_insts=true
 do_quiesce=true
@@ -253,6 +294,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu2.tracer
@@ -262,10 +304,10 @@ icache_port=system.cpu2.icache.cpu_side
 
 [system.cpu2.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -276,22 +318,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.dcache_port
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu2.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu2.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -302,12 +353,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.icache_port
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu2.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2.interrupts]
 type=SparcInterrupts
 
@@ -324,9 +384,8 @@ type=ExeTracer
 [system.cpu3]
 type=TimingSimpleCPU
 children=dcache dtb icache interrupts isa itb tracer
-branchPred=Null
 checker=Null
-clock=500
+clk_domain=system.cpu_clk_domain
 cpu_id=3
 do_checkpoint_insts=true
 do_quiesce=true
@@ -344,6 +403,7 @@ max_loads_any_thread=0
 numThreads=1
 profile=0
 progress_interval=0
+simpoint_start_insts=
 switched_out=false
 system=system
 tracer=system.cpu3.tracer
@@ -353,10 +413,10 @@ icache_port=system.cpu3.icache.cpu_side
 
 [system.cpu3.dcache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -367,22 +427,31 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.dcache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.dcache_port
 mem_side=system.toL2Bus.slave[7]
 
+[system.cpu3.dcache.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.dtb]
 type=SparcTLB
 size=64
 
 [system.cpu3.icache]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=1
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -393,12 +462,21 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.icache.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.icache_port
 mem_side=system.toL2Bus.slave[6]
 
+[system.cpu3.icache.tags]
+type=LRU
+assoc=1
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3.interrupts]
 type=SparcInterrupts
 
@@ -412,12 +490,17 @@ size=64
 [system.cpu3.tracer]
 type=ExeTracer
 
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -428,40 +511,46 @@ prefetcher=Null
 response_latency=20
 size=4194304
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
-mem_side=system.membus.slave[0]
+mem_side=system.membus.slave[1]
+
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=4194304
 
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
 width=8
 master=system.physmem.port
-slave=system.l2c.mem_side system.system_port
+slave=system.system_port system.l2c.mem_side
 
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -469,3 +558,7 @@ width=8
 master=system.l2c.cpu_side
 slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
index adbb7069b..7a29b18d1 100755
--- a/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
+++ b/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/simple-timing-mp/simout
@@ -3,75 +3,75 @@ Redirecting stderr to build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sp
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 15:04:14
-gem5 started Mar 26 2013 15:04:37
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 06:07:13
+gem5 started Sep 22 2013 06:10:12
+gem5 executing on zizzer
 command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test-atomic/sparc/linux/simple-timing-mp
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Init done
 [Iteration 1, Thread 1] Got lock
 [Iteration 1, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 1, Thread 3] Got lock
-[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 1, Thread 2] Got lock
-[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 1, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 1, Thread 3] Got lock
+[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 1 completed
-[Iteration 2, Thread 3] Got lock
-[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3
 [Iteration 2, Thread 2] Got lock
-[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2
 [Iteration 2, Thread 1] Got lock
 [Iteration 2, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 2, Thread 3] Got lock
+[Iteration 2, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 2 completed
 [Iteration 3, Thread 1] Got lock
 [Iteration 3, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 3, Thread 3] Got lock
-[Iteration 3, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 3, Thread 2] Got lock
-[Iteration 3, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 3, Thread 3] Got lock
+[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 3 completed
 [Iteration 4, Thread 2] Got lock
 [Iteration 4, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 4, Thread 3] Got lock
-[Iteration 4, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 4, Thread 1] Got lock
-[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 4, Thread 3] Got lock
+[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 4 completed
 [Iteration 5, Thread 1] Got lock
 [Iteration 5, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 5, Thread 3] Got lock
-[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 5, Thread 2] Got lock
-[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 5, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 5, Thread 3] Got lock
+[Iteration 5, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 5 completed
 [Iteration 6, Thread 2] Got lock
 [Iteration 6, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 6, Thread 3] Got lock
-[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 6, Thread 1] Got lock
-[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 6, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 6, Thread 3] Got lock
+[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 6 completed
 [Iteration 7, Thread 1] Got lock
 [Iteration 7, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 7, Thread 3] Got lock
-[Iteration 7, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 7, Thread 2] Got lock
-[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 7, Thread 3] Got lock
+[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 7 completed
 [Iteration 8, Thread 2] Got lock
 [Iteration 8, Thread 2] Critical section done, previously next=0, now next=2
-[Iteration 8, Thread 3] Got lock
-[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3
 [Iteration 8, Thread 1] Got lock
-[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1
+[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1
+[Iteration 8, Thread 3] Got lock
+[Iteration 8, Thread 3] Critical section done, previously next=1, now next=3
 Iteration 8 completed
 [Iteration 9, Thread 1] Got lock
 [Iteration 9, Thread 1] Critical section done, previously next=0, now next=1
-[Iteration 9, Thread 3] Got lock
-[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3
 [Iteration 9, Thread 2] Got lock
-[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2
+[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2
+[Iteration 9, Thread 3] Got lock
+[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3
 Iteration 9 completed
 [Iteration 10, Thread 2] Got lock
 [Iteration 10, Thread 2] Critical section done, previously next=0, now next=2
@@ -81,4 +81,4 @@ Iteration 9 completed
 [Iteration 10, Thread 1] Critical section done, previously next=3, now next=1
 Iteration 10 completed
 PASSED :-)
-Exiting @ tick 262970500 because target called exit()
+Exiting @ tick 262794500 because target called exit()
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
index 5908a1a40..051ef25fb 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:05:26
+Real time: Sep/22/2013 05:28:42
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 101
-Elapsed_time_in_minutes: 1.68333
-Elapsed_time_in_hours: 0.0280556
-Elapsed_time_in_days: 0.00116898
+Elapsed_time_in_seconds: 79
+Elapsed_time_in_minutes: 1.31667
+Elapsed_time_in_hours: 0.0219444
+Elapsed_time_in_days: 0.000914352
 
-Virtual_time_in_seconds: 100.98
-Virtual_time_in_minutes: 1.683
-Virtual_time_in_hours:   0.02805
-Virtual_time_in_days:    0.00116875
+Virtual_time_in_seconds: 79.09
+Virtual_time_in_minutes: 1.31817
+Virtual_time_in_hours:   0.0219694
+Virtual_time_in_days:    0.000915394
 
 Ruby_current_time: 7257449
 Ruby_start_time: 0
 Ruby_cycles: 7257449
 
-mbytes_resident: 79.3281
-mbytes_total: 297.352
-resident_ratio: 0.266795
+mbytes_resident: 69.1055
+mbytes_total: 251.578
+resident_ratio: 0.275713
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
index 82781df07..53312cb70 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memte
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  9 2013 02:02:21
-gem5 started Apr  9 2013 02:03:11
-gem5 executing on vein
+gem5 compiled Sep 22 2013 05:27:02
+gem5 started Sep 22 2013 05:27:23
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
index d27642359..e71048b46 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.007257                       # Nu
 sim_ticks                                     7257449                       # Number of ticks simulated
 final_tick                                    7257449                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  71632                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305516                       # Number of bytes of host memory used
-host_seconds                                   101.32                       # Real time elapsed on the host
+host_tick_rate                                  91873                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257620                       # Number of bytes of host memory used
+host_seconds                                    78.99                       # Real time elapsed on the host
 system.ruby.l1_cntrl4.L1Dcache.demand_hits            2                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Dcache.demand_misses        76641                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Dcache.demand_accesses        76643                       # Number of cache demand accesses
@@ -325,6 +325,18 @@ system.ruby.network.routers10.msg_bytes.Response_Control::2      4842768
 system.ruby.network.routers10.msg_bytes.Writeback_Data::0      8120304                      
 system.ruby.network.routers10.msg_bytes.Writeback_Data::1     28664064                      
 system.ruby.network.routers10.msg_bytes.Writeback_Control::0      1656240                      
+system.ruby.network.msg_count.Control         3646183                      
+system.ruby.network.msg_count.Request_Control      1770458                      
+system.ruby.network.msg_count.Response_Data      4285974                      
+system.ruby.network.msg_count.Response_Control      6337828                      
+system.ruby.network.msg_count.Writeback_Data      1532683                      
+system.ruby.network.msg_count.Writeback_Control       621092                      
+system.ruby.network.msg_byte.Control         29169464                      
+system.ruby.network.msg_byte.Request_Control     14163664                      
+system.ruby.network.msg_byte.Response_Data    308590128                      
+system.ruby.network.msg_byte.Response_Control     50702624                      
+system.ruby.network.msg_byte.Writeback_Data    110353176                      
+system.ruby.network.msg_byte.Writeback_Control      4968736                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu0.num_reads                           99060                       # number of read accesses completed
@@ -883,18 +895,6 @@ system.ruby.l2_cntrl0.MT_IB.WB_Data_clean           29      0.00%      0.00%
 system.ruby.l2_cntrl0.MT_SB.L1_PUTX                 2      0.00%      0.00%
 system.ruby.l2_cntrl0.MT_SB.L2_Replacement          199      0.00%      0.00%
 system.ruby.l2_cntrl0.MT_SB.Unblock               780      0.00%      0.00%
-system.ruby.network.msg_count.Control         3646183                      
-system.ruby.network.msg_count.Request_Control      1770458                      
-system.ruby.network.msg_count.Response_Data      4285974                      
-system.ruby.network.msg_count.Response_Control      6337828                      
-system.ruby.network.msg_count.Writeback_Data      1532683                      
-system.ruby.network.msg_count.Writeback_Control       621092                      
-system.ruby.network.msg_byte.Control         29169464                      
-system.ruby.network.msg_byte.Request_Control     14163664                      
-system.ruby.network.msg_byte.Response_Data    308590128                      
-system.ruby.network.msg_byte.Response_Control     50702624                      
-system.ruby.network.msg_byte.Writeback_Data    110353176                      
-system.ruby.network.msg_byte.Writeback_Control      4968736                      
 system.ruby.dir_cntrl0.Fetch                   604998      0.00%      0.00%
 system.ruby.dir_cntrl0.Data                    212955      0.00%      0.00%
 system.ruby.dir_cntrl0.Memory_Data             604995      0.00%      0.00%
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
index cb8083e15..d118d8b60 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:07:55
+Real time: Sep/22/2013 05:38:45
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 182
-Elapsed_time_in_minutes: 3.03333
-Elapsed_time_in_hours: 0.0505556
-Elapsed_time_in_days: 0.00210648
+Elapsed_time_in_seconds: 142
+Elapsed_time_in_minutes: 2.36667
+Elapsed_time_in_hours: 0.0394444
+Elapsed_time_in_days: 0.00164352
 
-Virtual_time_in_seconds: 181.59
-Virtual_time_in_minutes: 3.0265
-Virtual_time_in_hours:   0.0504417
-Virtual_time_in_days:    0.00210174
+Virtual_time_in_seconds: 142.1
+Virtual_time_in_minutes: 2.36833
+Virtual_time_in_hours:   0.0394722
+Virtual_time_in_days:    0.00164468
 
 Ruby_current_time: 7481441
 Ruby_start_time: 0
 Ruby_cycles: 7481441
 
-mbytes_resident: 80.625
-mbytes_total: 299.508
-resident_ratio: 0.269205
+mbytes_resident: 70.6289
+mbytes_total: 253.738
+resident_ratio: 0.278353
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
index 30ecc5910..802dd1a62 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memt
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  9 2013 02:05:20
-gem5 started Apr  9 2013 02:06:11
-gem5 executing on vein
+gem5 compiled Sep 22 2013 05:36:12
+gem5 started Sep 22 2013 05:36:22
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
index 7344fcbda..95538d9b6 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.007481                       # Nu
 sim_ticks                                     7481441                       # Number of ticks simulated
 final_tick                                    7481441                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  41233                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 306700                       # Number of bytes of host memory used
-host_seconds                                   181.44                       # Real time elapsed on the host
+host_tick_rate                                  52727                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 259832                       # Number of bytes of host memory used
+host_seconds                                   141.89                       # Real time elapsed on the host
 system.ruby.l1_cntrl4.L1Dcache.demand_hits           21                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Dcache.demand_misses        77428                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Dcache.demand_accesses        77449                       # Number of cache demand accesses
@@ -307,6 +307,26 @@ system.ruby.network.routers10.msg_bytes.Writeback_Control::2      3115216
 system.ruby.network.routers10.msg_bytes.Forwarded_Control::0        67368                      
 system.ruby.network.routers10.msg_bytes.Invalidate_Control::0          152                      
 system.ruby.network.routers10.msg_bytes.Unblock_Control::2      9858144                      
+system.ruby.network.msg_count.Request_Control      3673936                      
+system.ruby.network.msg_count.Response_Data      3630768                      
+system.ruby.network.msg_count.ResponseL2hit_Data        17766                      
+system.ruby.network.msg_count.ResponseLocal_Data        25260                      
+system.ruby.network.msg_count.Response_Control         9012                      
+system.ruby.network.msg_count.Writeback_Data      2479504                      
+system.ruby.network.msg_count.Writeback_Control      8511972                      
+system.ruby.network.msg_count.Forwarded_Control        25263                      
+system.ruby.network.msg_count.Invalidate_Control           57                      
+system.ruby.network.msg_count.Unblock_Control      3696804                      
+system.ruby.network.msg_byte.Request_Control     29391488                      
+system.ruby.network.msg_byte.Response_Data    261415296                      
+system.ruby.network.msg_byte.ResponseL2hit_Data      1279152                      
+system.ruby.network.msg_byte.ResponseLocal_Data      1818720                      
+system.ruby.network.msg_byte.Response_Control        72096                      
+system.ruby.network.msg_byte.Writeback_Data    178524288                      
+system.ruby.network.msg_byte.Writeback_Control     68095776                      
+system.ruby.network.msg_byte.Forwarded_Control       202104                      
+system.ruby.network.msg_byte.Invalidate_Control          456                      
+system.ruby.network.msg_byte.Unblock_Control     29574432                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu0.num_reads                           99553                       # number of read accesses completed
@@ -1105,26 +1125,6 @@ system.ruby.l2_cntrl0.MI.Writeback_Ack         604406      0.00%      0.00%
 system.ruby.l2_cntrl0.OLSI.L1_PUTS_only          1011      0.00%      0.00%
 system.ruby.l2_cntrl0.OLSI.L1_PUTS                108      0.00%      0.00%
 system.ruby.l2_cntrl0.OLSI.Writeback_Ack          239      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control      3673936                      
-system.ruby.network.msg_count.Response_Data      3630768                      
-system.ruby.network.msg_count.ResponseL2hit_Data        17766                      
-system.ruby.network.msg_count.ResponseLocal_Data        25260                      
-system.ruby.network.msg_count.Response_Control         9012                      
-system.ruby.network.msg_count.Writeback_Data      2479504                      
-system.ruby.network.msg_count.Writeback_Control      8511972                      
-system.ruby.network.msg_count.Forwarded_Control        25263                      
-system.ruby.network.msg_count.Invalidate_Control           57                      
-system.ruby.network.msg_count.Unblock_Control      3696804                      
-system.ruby.network.msg_byte.Request_Control     29391488                      
-system.ruby.network.msg_byte.Response_Data    261415296                      
-system.ruby.network.msg_byte.ResponseL2hit_Data      1279152                      
-system.ruby.network.msg_byte.ResponseLocal_Data      1818720                      
-system.ruby.network.msg_byte.Response_Control        72096                      
-system.ruby.network.msg_byte.Writeback_Data    178524288                      
-system.ruby.network.msg_byte.Writeback_Control     68095776                      
-system.ruby.network.msg_byte.Forwarded_Control       202104                      
-system.ruby.network.msg_byte.Invalidate_Control          456                      
-system.ruby.network.msg_byte.Unblock_Control     29574432                      
 system.ruby.dir_cntrl0.GETX                    211949      0.00%      0.00%
 system.ruby.dir_cntrl0.GETS                    393220      0.00%      0.00%
 system.ruby.dir_cntrl0.PUTX                    604433      0.00%      0.00%
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
index 11200a202..a202baa14 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini
@@ -17,7 +17,7 @@ kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
 num_work_ids=16
 readfile=
 symbolfile=
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
index 87304c1a3..e0121fbf8 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:06:47
+Real time: Sep/22/2013 05:46:37
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 124
-Elapsed_time_in_minutes: 2.06667
-Elapsed_time_in_hours: 0.0344444
-Elapsed_time_in_days: 0.00143519
+Elapsed_time_in_seconds: 97
+Elapsed_time_in_minutes: 1.61667
+Elapsed_time_in_hours: 0.0269444
+Elapsed_time_in_days: 0.00112269
 
-Virtual_time_in_seconds: 123.4
-Virtual_time_in_minutes: 2.05667
-Virtual_time_in_hours:   0.0342778
-Virtual_time_in_days:    0.00142824
+Virtual_time_in_seconds: 97.69
+Virtual_time_in_minutes: 1.62817
+Virtual_time_in_hours:   0.0271361
+Virtual_time_in_days:    0.00113067
 
 Ruby_current_time: 6151475
 Ruby_start_time: 0
 Ruby_cycles: 6151475
 
-mbytes_resident: 79.2969
-mbytes_total: 297.457
-resident_ratio: 0.266596
+mbytes_resident: 68.8125
+mbytes_total: 251.641
+resident_ratio: 0.273455
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
index e78fa46c2..9d06307c2 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  9 2013 02:08:32
-gem5 started Apr  9 2013 02:09:19
-gem5 executing on vein
+gem5 compiled Sep 22 2013 05:44:48
+gem5 started Sep 22 2013 05:44:59
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
index 17d7f958c..30f4ed177 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.006151                       # Nu
 sim_ticks                                     6151475                       # Number of ticks simulated
 final_tick                                    6151475                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  49950                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 304600                       # Number of bytes of host memory used
-host_seconds                                   123.15                       # Real time elapsed on the host
+host_tick_rate                                  63154                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 257684                       # Number of bytes of host memory used
+host_seconds                                    97.40                       # Real time elapsed on the host
 system.ruby.l1_cntrl4.L1Dcache.demand_hits           20                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Dcache.demand_misses        76947                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Dcache.demand_accesses        76967                       # Number of cache demand accesses
@@ -265,6 +265,24 @@ system.ruby.network.routers10.msg_bytes.Writeback_Data::4     63441936
 system.ruby.network.routers10.msg_bytes.Writeback_Control::4      3020648                      
 system.ruby.network.routers10.msg_bytes.Broadcast_Control::1     34542088                      
 system.ruby.network.routers10.msg_bytes.Persistent_Control::3     18697824                      
+system.ruby.network.msg_count.Request_Control      3695895                      
+system.ruby.network.msg_count.Response_Data      1838719                      
+system.ruby.network.msg_count.ResponseL2hit_Data         5073                      
+system.ruby.network.msg_count.ResponseLocal_Data         4698                      
+system.ruby.network.msg_count.Response_Control         4248                      
+system.ruby.network.msg_count.Writeback_Data      2643414                      
+system.ruby.network.msg_count.Writeback_Control      1132743                      
+system.ruby.network.msg_count.Broadcast_Control      9252345                      
+system.ruby.network.msg_count.Persistent_Control      5193840                      
+system.ruby.network.msg_byte.Request_Control     29567160                      
+system.ruby.network.msg_byte.Response_Data    132387768                      
+system.ruby.network.msg_byte.ResponseL2hit_Data       365256                      
+system.ruby.network.msg_byte.ResponseLocal_Data       338256                      
+system.ruby.network.msg_byte.Response_Control        33984                      
+system.ruby.network.msg_byte.Writeback_Data    190325808                      
+system.ruby.network.msg_byte.Writeback_Control      9061944                      
+system.ruby.network.msg_byte.Broadcast_Control     74018760                      
+system.ruby.network.msg_byte.Persistent_Control     41550720                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu0.num_reads                          100000                       # number of read accesses completed
@@ -1217,24 +1235,6 @@ system.ruby.l2_cntrl0.I_L.Persistent_GETS        83699      0.00%      0.00%
 system.ruby.l2_cntrl0.I_L.Own_Lock_or_Unlock          330      0.00%      0.00%
 system.ruby.l2_cntrl0.S_L.L2_Replacement            1      0.00%      0.00%
 system.ruby.l2_cntrl0.S_L.Own_Lock_or_Unlock            5      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control      3695895                      
-system.ruby.network.msg_count.Response_Data      1838719                      
-system.ruby.network.msg_count.ResponseL2hit_Data         5073                      
-system.ruby.network.msg_count.ResponseLocal_Data         4698                      
-system.ruby.network.msg_count.Response_Control         4248                      
-system.ruby.network.msg_count.Writeback_Data      2643414                      
-system.ruby.network.msg_count.Writeback_Control      1132743                      
-system.ruby.network.msg_count.Broadcast_Control      9252345                      
-system.ruby.network.msg_count.Persistent_Control      5193840                      
-system.ruby.network.msg_byte.Request_Control     29567160                      
-system.ruby.network.msg_byte.Response_Data    132387768                      
-system.ruby.network.msg_byte.ResponseL2hit_Data       365256                      
-system.ruby.network.msg_byte.ResponseLocal_Data       338256                      
-system.ruby.network.msg_byte.Response_Control        33984                      
-system.ruby.network.msg_byte.Writeback_Data    190325808                      
-system.ruby.network.msg_byte.Writeback_Control      9061944                      
-system.ruby.network.msg_byte.Broadcast_Control     74018760                      
-system.ruby.network.msg_byte.Persistent_Control     41550720                      
 system.ruby.dir_cntrl0.GETX                    255487      0.00%      0.00%
 system.ruby.dir_cntrl0.GETS                    476933      0.00%      0.00%
 system.ruby.dir_cntrl0.Lockdown                130603      0.00%      0.00%
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
index 50647016f..3e6cf4aa4 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:05:07
+Real time: Sep/22/2013 05:19:16
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 131
-Elapsed_time_in_minutes: 2.18333
-Elapsed_time_in_hours: 0.0363889
-Elapsed_time_in_days: 0.0015162
+Elapsed_time_in_seconds: 98
+Elapsed_time_in_minutes: 1.63333
+Elapsed_time_in_hours: 0.0272222
+Elapsed_time_in_days: 0.00113426
 
-Virtual_time_in_seconds: 131.88
-Virtual_time_in_minutes: 2.198
-Virtual_time_in_hours:   0.0366333
-Virtual_time_in_days:    0.00152639
+Virtual_time_in_seconds: 98.86
+Virtual_time_in_minutes: 1.64767
+Virtual_time_in_hours:   0.0274611
+Virtual_time_in_days:    0.00114421
 
 Ruby_current_time: 5795833
 Ruby_start_time: 0
 Ruby_cycles: 5795833
 
-mbytes_resident: 75.793
-mbytes_total: 298.383
-resident_ratio: 0.254026
+mbytes_resident: 69.3711
+mbytes_total: 252.59
+resident_ratio: 0.274639
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
index 899bc58f8..5f6410683 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alp
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  9 2013 01:58:20
-gem5 started Apr  9 2013 01:59:05
-gem5 executing on vein
+gem5 compiled Sep 22 2013 05:17:28
+gem5 started Sep 22 2013 05:17:37
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
index 98f43c561..2c76706ec 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.005796                       # Nu
 sim_ticks                                     5795833                       # Number of ticks simulated
 final_tick                                    5795833                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                  44085                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 305548                       # Number of bytes of host memory used
-host_seconds                                   131.47                       # Real time elapsed on the host
+host_tick_rate                                  58777                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 258656                       # Number of bytes of host memory used
+host_seconds                                    98.61                       # Real time elapsed on the host
 system.ruby.l1_cntrl4.L1Dcache.demand_hits           14                       # Number of cache demand hits
 system.ruby.l1_cntrl4.L1Dcache.demand_misses        77212                       # Number of cache demand misses
 system.ruby.l1_cntrl4.L1Dcache.demand_accesses        77226                       # Number of cache demand accesses
@@ -308,6 +308,20 @@ system.ruby.network.routers9.msg_bytes.Writeback_Control::3      4658336
 system.ruby.network.routers9.msg_bytes.Writeback_Control::5      2944376                      
 system.ruby.network.routers9.msg_bytes.Broadcast_Control::3     34549816                      
 system.ruby.network.routers9.msg_bytes.Unblock_Control::5      4940768                      
+system.ruby.network.msg_count.Request_Control      1853520                      
+system.ruby.network.msg_count.Response_Data      1852131                      
+system.ruby.network.msg_count.Response_Control     12897795                      
+system.ruby.network.msg_count.Writeback_Data       642069                      
+system.ruby.network.msg_count.Writeback_Control      4597894                      
+system.ruby.network.msg_count.Broadcast_Control      9254415                      
+system.ruby.network.msg_count.Unblock_Control      1852789                      
+system.ruby.network.msg_byte.Request_Control     14828160                      
+system.ruby.network.msg_byte.Response_Data    133353432                      
+system.ruby.network.msg_byte.Response_Control    103182360                      
+system.ruby.network.msg_byte.Writeback_Data     46228968                      
+system.ruby.network.msg_byte.Writeback_Control     36783152                      
+system.ruby.network.msg_byte.Broadcast_Control     74035320                      
+system.ruby.network.msg_byte.Unblock_Control     14822312                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu0.num_reads                           99395                       # number of read accesses completed
@@ -1054,20 +1068,6 @@ system.ruby.l1_cntrl0.MMT.L1_to_L2::total          758
 system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1 |          21     10.29%     10.29% |          25     12.25%     22.55% |          34     16.67%     39.22% |          24     11.76%     50.98% |          25     12.25%     63.24% |          27     13.24%     76.47% |          27     13.24%     89.71% |          21     10.29%    100.00%
 system.ruby.l1_cntrl0.MMT.Complete_L2_to_L1::total          204                      
 
-system.ruby.network.msg_count.Request_Control      1853520                      
-system.ruby.network.msg_count.Response_Data      1852131                      
-system.ruby.network.msg_count.Response_Control     12897795                      
-system.ruby.network.msg_count.Writeback_Data       642069                      
-system.ruby.network.msg_count.Writeback_Control      4597894                      
-system.ruby.network.msg_count.Broadcast_Control      9254415                      
-system.ruby.network.msg_count.Unblock_Control      1852789                      
-system.ruby.network.msg_byte.Request_Control     14828160                      
-system.ruby.network.msg_byte.Response_Data    133353432                      
-system.ruby.network.msg_byte.Response_Control    103182360                      
-system.ruby.network.msg_byte.Writeback_Data     46228968                      
-system.ruby.network.msg_byte.Writeback_Control     36783152                      
-system.ruby.network.msg_byte.Broadcast_Control     74035320                      
-system.ruby.network.msg_byte.Unblock_Control     14822312                      
 system.ruby.dir_cntrl0.GETX                    220023      0.00%      0.00%
 system.ruby.dir_cntrl0.GETS                    406995      0.00%      0.00%
 system.ruby.dir_cntrl0.PUT                     585083      0.00%      0.00%
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
index f52cdf318..cd6eb6e26 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/config.ini
@@ -17,7 +17,7 @@ kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=0:268435455
-memories=system.physmem system.funcmem
+memories=system.funcmem system.physmem
 num_work_ids=16
 readfile=
 symbolfile=
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
index 9ecd89c86..5e18bea6c 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:05:30
+Real time: Sep/28/2013 03:06:25
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 48
-Elapsed_time_in_minutes: 0.8
-Elapsed_time_in_hours: 0.0133333
-Elapsed_time_in_days: 0.000555556
+Elapsed_time_in_seconds: 36
+Elapsed_time_in_minutes: 0.6
+Elapsed_time_in_hours: 0.01
+Elapsed_time_in_days: 0.000416667
 
-Virtual_time_in_seconds: 47.63
-Virtual_time_in_minutes: 0.793833
-Virtual_time_in_hours:   0.0132306
-Virtual_time_in_days:    0.000551273
+Virtual_time_in_seconds: 36.54
+Virtual_time_in_minutes: 0.609
+Virtual_time_in_hours:   0.01015
+Virtual_time_in_days:    0.000422917
 
 Ruby_current_time: 8664886
 Ruby_start_time: 0
 Ruby_cycles: 8664886
 
-mbytes_resident: 75.6094
-mbytes_total: 295.949
-resident_ratio: 0.255494
+mbytes_resident: 67.1875
+mbytes_total: 250.145
+resident_ratio: 0.269579
 
 Busy Controller Counts:
 L1Cache-0:0  L1Cache-1:0  L1Cache-2:0  L1Cache-3:0  L1Cache-4:0  L1Cache-5:0  L1Cache-6:0  L1Cache-7:0  
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
index 3495746a7..1c746b09a 100755
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memt
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Apr  9 2013 01:51:40
-gem5 started Apr  9 2013 01:54:58
-gem5 executing on vein
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:49
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
index 10a35fe3c..74bfa5d0c 100644
--- a/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
+++ b/tests/quick/se/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.008665                       # Nu
 sim_ticks                                     8664886                       # Number of ticks simulated
 final_tick                                    8664886                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 183404                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 303056                       # Number of bytes of host memory used
-host_seconds                                    47.25                       # Real time elapsed on the host
+host_tick_rate                                 239244                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 256152                       # Number of bytes of host memory used
+host_seconds                                    36.22                       # Real time elapsed on the host
 system.ruby.l1_cntrl4.cacheMemory.demand_hits            0                       # Number of cache demand hits
 system.ruby.l1_cntrl4.cacheMemory.demand_misses        77331                       # Number of cache demand misses
 system.ruby.l1_cntrl4.cacheMemory.demand_accesses        77331                       # Number of cache demand accesses
@@ -139,6 +139,14 @@ system.ruby.network.routers9.msg_bytes.Control::2      4940496
 system.ruby.network.routers9.msg_bytes.Data::2     44060256                      
 system.ruby.network.routers9.msg_bytes.Response_Data::4     44463816                      
 system.ruby.network.routers9.msg_bytes.Writeback_Control::3      4961080                      
+system.ruby.network.msg_count.Control         1852692                      
+system.ruby.network.msg_count.Data            1835849                      
+system.ruby.network.msg_count.Response_Data      1852658                      
+system.ruby.network.msg_count.Writeback_Control      1860405                      
+system.ruby.network.msg_byte.Control         14821536                      
+system.ruby.network.msg_byte.Data           132181128                      
+system.ruby.network.msg_byte.Response_Data    133391376                      
+system.ruby.network.msg_byte.Writeback_Control     14883240                      
 system.funcbus.throughput                           0                       # Throughput (bytes/s)
 system.funcbus.data_through_bus                     0                       # Total data (bytes)
 system.cpu0.num_reads                           99885                       # number of read accesses completed
@@ -367,14 +375,6 @@ system.ruby.l1_cntrl0.IS.Data::total           401489
 system.ruby.l1_cntrl0.IM.Data            |       27005     12.50%     12.50% |       26934     12.47%     24.96% |       26786     12.40%     37.36% |       27152     12.57%     49.93% |       27327     12.65%     62.58% |       27084     12.54%     75.11% |       27074     12.53%     87.64% |       26701     12.36%    100.00%
 system.ruby.l1_cntrl0.IM.Data::total           216063                      
 
-system.ruby.network.msg_count.Control         1852692                      
-system.ruby.network.msg_count.Data            1835849                      
-system.ruby.network.msg_count.Response_Data      1852658                      
-system.ruby.network.msg_count.Writeback_Control      1860405                      
-system.ruby.network.msg_byte.Control         14821536                      
-system.ruby.network.msg_byte.Data           132181128                      
-system.ruby.network.msg_byte.Response_Data    133391376                      
-system.ruby.network.msg_byte.Writeback_Control     14883240                      
 system.ruby.dir_cntrl0.GETX                    791175      0.00%      0.00%
 system.ruby.dir_cntrl0.PUTX                    609324      0.00%      0.00%
 system.ruby.dir_cntrl0.PUTX_NotOwner             2623      0.00%      0.00%
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
index 1f567a1b9..0b50bed4c 100644
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/config.ini
@@ -8,15 +8,16 @@ time_sync_spin_threshold=100000000
 
 [system]
 type=System
-children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcbus funcmem l2c membus physmem toL2Bus
+children=clk_domain cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 cpu_clk_domain funcbus funcmem l2c membus physmem toL2Bus voltage_domain
 boot_osflags=a
-clock=1000
+cache_line_size=64
+clk_domain=system.clk_domain
 init_param=0
 kernel=
 load_addr_mask=1099511627775
 mem_mode=timing
 mem_ranges=
-memories=system.funcmem system.physmem
+memories=system.physmem system.funcmem
 num_work_ids=16
 readfile=
 symbolfile=
@@ -29,11 +30,16 @@ work_end_exit_count=0
 work_item_id=-1
 system_port=system.membus.slave[1]
 
+[system.clk_domain]
+type=SrcClockDomain
+clock=1000
+voltage_domain=system.voltage_domain
+
 [system.cpu0]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -51,10 +57,10 @@ test=system.cpu0.l1c.cpu_side
 
 [system.cpu0.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -65,17 +71,26 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu0.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu0.test
 mem_side=system.toL2Bus.slave[0]
 
+[system.cpu0.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu1]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -93,10 +108,10 @@ test=system.cpu1.l1c.cpu_side
 
 [system.cpu1.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -107,17 +122,26 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu1.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu1.test
 mem_side=system.toL2Bus.slave[1]
 
+[system.cpu1.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu2]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -135,10 +159,10 @@ test=system.cpu2.l1c.cpu_side
 
 [system.cpu2.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -149,17 +173,26 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu2.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu2.test
 mem_side=system.toL2Bus.slave[2]
 
+[system.cpu2.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu3]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -177,10 +210,10 @@ test=system.cpu3.l1c.cpu_side
 
 [system.cpu3.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -191,17 +224,26 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu3.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu3.test
 mem_side=system.toL2Bus.slave[3]
 
+[system.cpu3.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu4]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -219,10 +261,10 @@ test=system.cpu4.l1c.cpu_side
 
 [system.cpu4.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -233,17 +275,26 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu4.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu4.test
 mem_side=system.toL2Bus.slave[4]
 
+[system.cpu4.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu5]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -261,10 +312,10 @@ test=system.cpu5.l1c.cpu_side
 
 [system.cpu5.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -275,17 +326,26 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu5.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu5.test
 mem_side=system.toL2Bus.slave[5]
 
+[system.cpu5.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu6]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -303,10 +363,10 @@ test=system.cpu6.l1c.cpu_side
 
 [system.cpu6.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -317,17 +377,26 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu6.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu6.test
 mem_side=system.toL2Bus.slave[6]
 
+[system.cpu6.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
 [system.cpu7]
 type=MemTest
 children=l1c
 atomic=false
-clock=500
+clk_domain=system.cpu_clk_domain
 issue_dmas=false
 max_loads=100000
 memory_size=65536
@@ -345,10 +414,10 @@ test=system.cpu7.l1c.cpu_side
 
 [system.cpu7.l1c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=4
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=2
 is_top_level=true
@@ -359,16 +428,29 @@ prefetcher=Null
 response_latency=2
 size=32768
 system=system
+tags=system.cpu7.l1c.tags
 tgts_per_mshr=20
 two_queue=false
 write_buffers=8
 cpu_side=system.cpu7.test
 mem_side=system.toL2Bus.slave[7]
 
+[system.cpu7.l1c.tags]
+type=LRU
+assoc=4
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=2
+size=32768
+
+[system.cpu_clk_domain]
+type=SrcClockDomain
+clock=500
+voltage_domain=system.voltage_domain
+
 [system.funcbus]
 type=NoncoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 use_default_range=false
 width=8
@@ -378,22 +460,21 @@ slave=system.cpu0.functional system.cpu1.functional system.cpu2.functional syste
 [system.funcmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=false
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.funcbus.master[0]
 
 [system.l2c]
 type=BaseCache
+children=tags
 addr_ranges=0:18446744073709551615
 assoc=8
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 forward_snoops=true
 hit_latency=20
 is_top_level=false
@@ -404,16 +485,24 @@ prefetcher=Null
 response_latency=20
 size=65536
 system=system
+tags=system.l2c.tags
 tgts_per_mshr=12
 two_queue=false
 write_buffers=8
 cpu_side=system.toL2Bus.master[0]
 mem_side=system.membus.slave[0]
 
+[system.l2c.tags]
+type=LRU
+assoc=8
+block_size=64
+clk_domain=system.cpu_clk_domain
+hit_latency=20
+size=65536
+
 [system.membus]
 type=CoherentBus
-block_size=64
-clock=1000
+clk_domain=system.clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -424,20 +513,18 @@ slave=system.l2c.mem_side system.system_port
 [system.physmem]
 type=SimpleMemory
 bandwidth=73.000000
-clock=1000
-conf_table_reported=false
+clk_domain=system.clk_domain
+conf_table_reported=true
 in_addr_map=true
 latency=30000
 latency_var=0
 null=false
 range=0:134217727
-zero=false
 port=system.membus.master[0]
 
 [system.toL2Bus]
 type=CoherentBus
-block_size=64
-clock=500
+clk_domain=system.cpu_clk_domain
 header_cycles=1
 system=system
 use_default_range=false
@@ -445,3 +532,7 @@ width=16
 master=system.l2c.cpu_side
 slave=system.cpu0.l1c.mem_side system.cpu1.l1c.mem_side system.cpu2.l1c.mem_side system.cpu3.l1c.mem_side system.cpu4.l1c.mem_side system.cpu5.l1c.mem_side system.cpu6.l1c.mem_side system.cpu7.l1c.mem_side
 
+[system.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
index 014cde607..ad8539d90 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simerr
@@ -1,74 +1,74 @@
-system.cpu6: completed 10000 read, 5435 write accesses @79021500
-system.cpu0: completed 10000 read, 5363 write accesses @79194500
-system.cpu7: completed 10000 read, 5392 write accesses @79770500
-system.cpu2: completed 10000 read, 5375 write accesses @80689500
-system.cpu1: completed 10000 read, 5373 write accesses @81623500
-system.cpu4: completed 10000 read, 5458 write accesses @81916000
-system.cpu5: completed 10000 read, 5507 write accesses @81975000
-system.cpu3: completed 10000 read, 5421 write accesses @82381000
-system.cpu2: completed 20000 read, 10678 write accesses @153864500
-system.cpu0: completed 20000 read, 10854 write accesses @154789000
-system.cpu7: completed 20000 read, 10817 write accesses @154953500
-system.cpu1: completed 20000 read, 10781 write accesses @155855500
-system.cpu3: completed 20000 read, 10799 write accesses @157033000
-system.cpu4: completed 20000 read, 10854 write accesses @157158000
-system.cpu6: completed 20000 read, 10878 write accesses @157795000
-system.cpu5: completed 20000 read, 10963 write accesses @159866500
-system.cpu0: completed 30000 read, 16180 write accesses @228385000
-system.cpu2: completed 30000 read, 15995 write accesses @229109500
-system.cpu7: completed 30000 read, 16232 write accesses @231170000
-system.cpu1: completed 30000 read, 16165 write accesses @231658500
-system.cpu4: completed 30000 read, 16252 write accesses @232783000
-system.cpu6: completed 30000 read, 16228 write accesses @233712000
-system.cpu3: completed 30000 read, 16226 write accesses @236523000
-system.cpu5: completed 30000 read, 16456 write accesses @239602000
-system.cpu0: completed 40000 read, 21598 write accesses @305262000
-system.cpu2: completed 40000 read, 21332 write accesses @306571000
-system.cpu1: completed 40000 read, 21599 write accesses @307778500
-system.cpu4: completed 40000 read, 21599 write accesses @307971000
-system.cpu7: completed 40000 read, 21551 write accesses @308441000
-system.cpu6: completed 40000 read, 21597 write accesses @310397000
-system.cpu3: completed 40000 read, 21704 write accesses @312891000
-system.cpu5: completed 40000 read, 21914 write accesses @315565000
-system.cpu4: completed 50000 read, 26891 write accesses @381925000
-system.cpu0: completed 50000 read, 26990 write accesses @382095500
-system.cpu2: completed 50000 read, 26686 write accesses @382917500
-system.cpu1: completed 50000 read, 26983 write accesses @384289000
-system.cpu6: completed 50000 read, 27066 write accesses @384539000
-system.cpu7: completed 50000 read, 26943 write accesses @385136500
-system.cpu3: completed 50000 read, 27037 write accesses @389922000
-system.cpu5: completed 50000 read, 27423 write accesses @393691500
-system.cpu6: completed 60000 read, 32353 write accesses @457634500
-system.cpu4: completed 60000 read, 32228 write accesses @457992000
-system.cpu1: completed 60000 read, 32457 write accesses @460714000
-system.cpu2: completed 60000 read, 32178 write accesses @461196500
-system.cpu0: completed 60000 read, 32542 write accesses @461690000
-system.cpu7: completed 60000 read, 32302 write accesses @462388500
-system.cpu3: completed 60000 read, 32488 write accesses @466103000
-system.cpu5: completed 60000 read, 32744 write accesses @469778000
-system.cpu6: completed 70000 read, 37747 write accesses @533745000
-system.cpu2: completed 70000 read, 37532 write accesses @535320500
-system.cpu4: completed 70000 read, 37773 write accesses @535591500
-system.cpu7: completed 70000 read, 37639 write accesses @538124500
-system.cpu0: completed 70000 read, 37909 write accesses @538334500
-system.cpu1: completed 70000 read, 37921 write accesses @541231500
-system.cpu3: completed 70000 read, 37871 write accesses @542226500
-system.cpu5: completed 70000 read, 38229 write accesses @548322500
-system.cpu4: completed 80000 read, 42983 write accesses @610769500
-system.cpu6: completed 80000 read, 43020 write accesses @610776000
-system.cpu2: completed 80000 read, 42982 write accesses @611661000
-system.cpu0: completed 80000 read, 43374 write accesses @615085500
-system.cpu1: completed 80000 read, 43250 write accesses @615627500
-system.cpu7: completed 80000 read, 43033 write accesses @615746000
-system.cpu3: completed 80000 read, 43154 write accesses @619760000
-system.cpu5: completed 80000 read, 43738 write accesses @625688001
-system.cpu6: completed 90000 read, 48339 write accesses @685422000
-system.cpu2: completed 90000 read, 48272 write accesses @687608500
-system.cpu4: completed 90000 read, 48507 write accesses @688615500
-system.cpu7: completed 90000 read, 48310 write accesses @688789000
-system.cpu0: completed 90000 read, 48650 write accesses @689991000
-system.cpu1: completed 90000 read, 48621 write accesses @693117500
-system.cpu3: completed 90000 read, 48493 write accesses @697608000
-system.cpu5: completed 90000 read, 49008 write accesses @701381500
-system.cpu6: completed 100000 read, 53851 write accesses @761435500
+system.cpu6: completed 10000 read, 5217 write accesses @68085999
+system.cpu4: completed 10000 read, 5435 write accesses @69661000
+system.cpu2: completed 10000 read, 5368 write accesses @70121500
+system.cpu3: completed 10000 read, 5457 write accesses @70317500
+system.cpu1: completed 10000 read, 5387 write accesses @70875500
+system.cpu7: completed 10000 read, 5470 write accesses @70949000
+system.cpu0: completed 10000 read, 5435 write accesses @71227500
+system.cpu5: completed 10000 read, 5514 write accesses @71894000
+system.cpu6: completed 20000 read, 10518 write accesses @132327500
+system.cpu4: completed 20000 read, 10839 write accesses @133525000
+system.cpu1: completed 20000 read, 10784 write accesses @134714500
+system.cpu7: completed 20000 read, 10701 write accesses @135318500
+system.cpu0: completed 20000 read, 10821 write accesses @135563500
+system.cpu2: completed 20000 read, 10843 write accesses @135684500
+system.cpu3: completed 20000 read, 10685 write accesses @135938500
+system.cpu5: completed 20000 read, 11031 write accesses @136425000
+system.cpu6: completed 30000 read, 16001 write accesses @197849500
+system.cpu4: completed 30000 read, 16254 write accesses @198725500
+system.cpu0: completed 30000 read, 16109 write accesses @199579499
+system.cpu1: completed 30000 read, 16209 write accesses @200016500
+system.cpu5: completed 30000 read, 16414 write accesses @200525000
+system.cpu3: completed 30000 read, 15978 write accesses @200724000
+system.cpu7: completed 30000 read, 16153 write accesses @201563500
+system.cpu2: completed 30000 read, 16316 write accesses @202401999
+system.cpu4: completed 40000 read, 21506 write accesses @263053500
+system.cpu6: completed 40000 read, 21338 write accesses @263431500
+system.cpu5: completed 40000 read, 21670 write accesses @263987000
+system.cpu3: completed 40000 read, 21219 write accesses @264608000
+system.cpu1: completed 40000 read, 21536 write accesses @265348500
+system.cpu0: completed 40000 read, 21604 write accesses @265426500
+system.cpu7: completed 40000 read, 21465 write accesses @265674000
+system.cpu2: completed 40000 read, 21690 write accesses @268754000
+system.cpu6: completed 50000 read, 26563 write accesses @327819000
+system.cpu4: completed 50000 read, 27066 write accesses @328101000
+system.cpu5: completed 50000 read, 26900 write accesses @328372000
+system.cpu3: completed 50000 read, 26596 write accesses @328811500
+system.cpu1: completed 50000 read, 26845 write accesses @328908500
+system.cpu7: completed 50000 read, 26873 write accesses @331316999
+system.cpu0: completed 50000 read, 26988 write accesses @331358000
+system.cpu2: completed 50000 read, 27102 write accesses @333876000
+system.cpu1: completed 60000 read, 32156 write accesses @392077000
+system.cpu6: completed 60000 read, 31998 write accesses @392784000
+system.cpu5: completed 60000 read, 32223 write accesses @393227500
+system.cpu4: completed 60000 read, 32446 write accesses @394175000
+system.cpu3: completed 60000 read, 32090 write accesses @394842000
+system.cpu0: completed 60000 read, 32282 write accesses @395716500
+system.cpu7: completed 60000 read, 32292 write accesses @397180000
+system.cpu2: completed 60000 read, 32266 write accesses @397288500
+system.cpu6: completed 70000 read, 37440 write accesses @457780500
+system.cpu1: completed 70000 read, 37577 write accesses @458242500
+system.cpu5: completed 70000 read, 37616 write accesses @458643500
+system.cpu4: completed 70000 read, 37952 write accesses @459569500
+system.cpu3: completed 70000 read, 37486 write accesses @460007500
+system.cpu0: completed 70000 read, 37804 write accesses @461418499
+system.cpu2: completed 70000 read, 37588 write accesses @461790000
+system.cpu7: completed 70000 read, 37743 write accesses @462130500
+system.cpu1: completed 80000 read, 42976 write accesses @523192500
+system.cpu5: completed 80000 read, 43028 write accesses @523895500
+system.cpu6: completed 80000 read, 42870 write accesses @524155000
+system.cpu4: completed 80000 read, 43341 write accesses @524226000
+system.cpu3: completed 80000 read, 42885 write accesses @524383000
+system.cpu2: completed 80000 read, 43005 write accesses @527239000
+system.cpu7: completed 80000 read, 43156 write accesses @528371000
+system.cpu0: completed 80000 read, 43239 write accesses @528519000
+system.cpu3: completed 90000 read, 48037 write accesses @586595000
+system.cpu1: completed 90000 read, 48299 write accesses @588010000
+system.cpu4: completed 90000 read, 48806 write accesses @589147500
+system.cpu6: completed 90000 read, 48454 write accesses @589844000
+system.cpu5: completed 90000 read, 48341 write accesses @590185000
+system.cpu2: completed 90000 read, 48395 write accesses @591584000
+system.cpu7: completed 90000 read, 48496 write accesses @592485000
+system.cpu0: completed 90000 read, 48680 write accesses @594831500
+system.cpu3: completed 100000 read, 53536 write accesses @652606500
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/50.memtest/ref/null/none/memtest/simout b/tests/quick/se/50.memtest/ref/null/none/memtest/simout
index 077a1416b..de32ac2d8 100755
--- a/tests/quick/se/50.memtest/ref/null/none/memtest/simout
+++ b/tests/quick/se/50.memtest/ref/null/none/memtest/simout
@@ -1,12 +1,12 @@
-Redirecting stdout to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simout
-Redirecting stderr to build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest/simerr
+Redirecting stdout to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simout
+Redirecting stderr to build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 14:39:12
-gem5 executing on ribera.cs.wisc.edu
-command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA/tests/opt/quick/se/50.memtest/alpha/linux/memtest
+gem5 compiled Sep 22 2013 05:53:51
+gem5 started Sep 22 2013 05:53:54
+gem5 executing on zizzer
+command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest -re tests/run.py build/NULL/tests/opt/quick/se/50.memtest/null/none/memtest
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 761435500 because maximum number of loads reached
+Exiting @ tick 652606500 because maximum number of loads reached
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
index 8578074a3..68f83a492 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Aug/29/2013 10:03:41
+Real time: Sep/22/2013 05:27:12
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.62
-Virtual_time_in_minutes: 0.0103333
-Virtual_time_in_hours:   0.000172222
-Virtual_time_in_days:    7.17593e-06
+Virtual_time_in_seconds: 0.46
+Virtual_time_in_minutes: 0.00766667
+Virtual_time_in_hours:   0.000127778
+Virtual_time_in_days:    5.32407e-06
 
 Ruby_current_time: 318321
 Ruby_start_time: 0
 Ruby_cycles: 318321
 
-mbytes_resident: 71.5117
-mbytes_total: 166.234
-resident_ratio: 0.43021
+mbytes_resident: 65.1133
+mbytes_total: 120.422
+resident_ratio: 0.54071
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
index cfdf73ce9..f5d2abbce 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simerr
@@ -1 +1,5 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
index fddb193cf..95d13e969 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubyt
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  1 2012 14:01:54
-gem5 started Sep  1 2012 14:05:06
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:27:02
+gem5 started Sep 22 2013 05:27:12
+gem5 executing on zizzer
 command line: build/ALPHA_MESI_CMP_directory/gem5.opt -d build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_MESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
index 8785bdf38..6ce8e4111 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000318                       # Nu
 sim_ticks                                      318321                       # Number of ticks simulated
 final_tick                                     318321                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1543352                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 170228                       # Number of bytes of host memory used
-host_seconds                                     0.21                       # Real time elapsed on the host
+host_tick_rate                                1986485                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 123316                       # Number of bytes of host memory used
+host_seconds                                     0.16                       # Real time elapsed on the host
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           81                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          861                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          942                       # Number of cache demand accesses
@@ -100,6 +100,18 @@ system.ruby.network.routers3.msg_bytes.Response_Control::2         6864
 system.ruby.network.routers3.msg_bytes.Writeback_Data::0        51984                      
 system.ruby.network.routers3.msg_bytes.Writeback_Data::1        36936                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::0          272                      
+system.ruby.network.msg_count.Control            5373                      
+system.ruby.network.msg_count.Request_Control         1689                      
+system.ruby.network.msg_count.Response_Data         7724                      
+system.ruby.network.msg_count.Response_Control         7854                      
+system.ruby.network.msg_count.Writeback_Data         3705                      
+system.ruby.network.msg_count.Writeback_Control          102                      
+system.ruby.network.msg_byte.Control            42984                      
+system.ruby.network.msg_byte.Request_Control        13512                      
+system.ruby.network.msg_byte.Response_Data       556128                      
+system.ruby.network.msg_byte.Response_Control        62832                      
+system.ruby.network.msg_byte.Writeback_Data       266760                      
+system.ruby.network.msg_byte.Writeback_Control          816                      
 system.ruby.network.routers0.throttle0.link_utilization     1.500686                      
 system.ruby.network.routers0.throttle0.msg_count.Request_Control::0          563                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::1          915                      
@@ -222,18 +234,6 @@ system.ruby.l1_cntrl0.M_I.Inv                     416      0.00%      0.00%
 system.ruby.l1_cntrl0.M_I.WB_Ack                  340      0.00%      0.00%
 system.ruby.l1_cntrl0.SINK_WB_ACK.Ifetch            1      0.00%      0.00%
 system.ruby.l1_cntrl0.SINK_WB_ACK.WB_Ack          415      0.00%      0.00%
-system.ruby.network.msg_count.Control            5373                      
-system.ruby.network.msg_count.Request_Control         1689                      
-system.ruby.network.msg_count.Response_Data         7724                      
-system.ruby.network.msg_count.Response_Control         7854                      
-system.ruby.network.msg_count.Writeback_Data         3705                      
-system.ruby.network.msg_count.Writeback_Control          102                      
-system.ruby.network.msg_byte.Control            42984                      
-system.ruby.network.msg_byte.Request_Control        13512                      
-system.ruby.network.msg_byte.Response_Data       556128                      
-system.ruby.network.msg_byte.Response_Control        62832                      
-system.ruby.network.msg_byte.Writeback_Data       266760                      
-system.ruby.network.msg_byte.Writeback_Control          816                      
 system.ruby.l2_cntrl0.L1_GET_INSTR                 56      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETS                      42      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETX                     818      0.00%      0.00%
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
index 85c7a39c3..f29b9c43a 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Aug/29/2013 10:04:54
+Real time: Sep/22/2013 05:36:23
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 1.04
-Virtual_time_in_minutes: 0.0173333
-Virtual_time_in_hours:   0.000288889
-Virtual_time_in_days:    1.2037e-05
+Virtual_time_in_seconds: 0.76
+Virtual_time_in_minutes: 0.0126667
+Virtual_time_in_hours:   0.000211111
+Virtual_time_in_days:    8.7963e-06
 
 Ruby_current_time: 327361
 Ruby_start_time: 0
 Ruby_cycles: 327361
 
-mbytes_resident: 72.9453
-mbytes_total: 167.379
-resident_ratio: 0.435833
+mbytes_resident: 66.6211
+mbytes_total: 121.586
+resident_ratio: 0.547934
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
index cfdf73ce9..f5d2abbce 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simerr
@@ -1 +1,5 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
index c5a30e355..2167c1256 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout
@@ -3,10 +3,10 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.ruby
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  1 2012 14:10:16
-gem5 started Sep  1 2012 14:14:49
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:36:12
+gem5 started Sep 22 2013 05:36:22
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_directory/gem5.opt -d build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_MOESI_CMP_directory/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 316521 because Ruby Tester completed
+Exiting @ tick 327361 because Ruby Tester completed
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
index 0d32f30e3..95db32b76 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000327                       # Nu
 sim_ticks                                      327361                       # Number of ticks simulated
 final_tick                                     327361                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 545722                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 171400                       # Number of bytes of host memory used
-host_seconds                                     0.60                       # Real time elapsed on the host
+host_tick_rate                                 746920                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 124508                       # Number of bytes of host memory used
+host_seconds                                     0.44                       # Real time elapsed on the host
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           78                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          852                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          930                       # Number of cache demand accesses
@@ -96,6 +96,18 @@ system.ruby.network.routers3.msg_bytes.Writeback_Control::0        14448
 system.ruby.network.routers3.msg_bytes.Writeback_Control::1        13520                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::2          640                      
 system.ruby.network.routers3.msg_bytes.Unblock_Control::2        14064                      
+system.ruby.network.msg_count.Request_Control         5287                      
+system.ruby.network.msg_count.Response_Data         5124                      
+system.ruby.network.msg_count.ResponseL2hit_Data          159                      
+system.ruby.network.msg_count.Writeback_Data         5004                      
+system.ruby.network.msg_count.Writeback_Control        10730                      
+system.ruby.network.msg_count.Unblock_Control         5275                      
+system.ruby.network.msg_byte.Request_Control        42296                      
+system.ruby.network.msg_byte.Response_Data       368928                      
+system.ruby.network.msg_byte.ResponseL2hit_Data        11448                      
+system.ruby.network.msg_byte.Writeback_Data       360288                      
+system.ruby.network.msg_byte.Writeback_Control        85840                      
+system.ruby.network.msg_byte.Unblock_Control        42200                      
 system.ruby.network.routers0.throttle0.link_utilization     1.384710                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::2          854                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::2           53                      
@@ -218,18 +230,6 @@ system.ruby.l1_cntrl0.IS.Exclusive_Data            94      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Ifetch                   136      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Store                    115      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack_Data          903      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control         5287                      
-system.ruby.network.msg_count.Response_Data         5124                      
-system.ruby.network.msg_count.ResponseL2hit_Data          159                      
-system.ruby.network.msg_count.Writeback_Data         5004                      
-system.ruby.network.msg_count.Writeback_Control        10730                      
-system.ruby.network.msg_count.Unblock_Control         5275                      
-system.ruby.network.msg_byte.Request_Control        42296                      
-system.ruby.network.msg_byte.Response_Data       368928                      
-system.ruby.network.msg_byte.ResponseL2hit_Data        11448                      
-system.ruby.network.msg_byte.Writeback_Data       360288                      
-system.ruby.network.msg_byte.Writeback_Control        85840                      
-system.ruby.network.msg_byte.Unblock_Control        42200                      
 system.ruby.l2_cntrl0.L1_GETS                     127      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETX                     895      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_PUTX                    2308      0.00%      0.00%
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
index d0fd81067..930f19cc4 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats
@@ -1,24 +1,24 @@
-Real time: Aug/29/2013 10:04:46
+Real time: Sep/22/2013 05:45:00
 
 Profiler Stats
 --------------
-Elapsed_time_in_seconds: 0
-Elapsed_time_in_minutes: 0
-Elapsed_time_in_hours: 0
-Elapsed_time_in_days: 0
+Elapsed_time_in_seconds: 1
+Elapsed_time_in_minutes: 0.0166667
+Elapsed_time_in_hours: 0.000277778
+Elapsed_time_in_days: 1.15741e-05
 
-Virtual_time_in_seconds: 0.6
-Virtual_time_in_minutes: 0.01
-Virtual_time_in_hours:   0.000166667
-Virtual_time_in_days:    6.94444e-06
+Virtual_time_in_seconds: 0.43
+Virtual_time_in_minutes: 0.00716667
+Virtual_time_in_hours:   0.000119444
+Virtual_time_in_days:    4.97685e-06
 
 Ruby_current_time: 225141
 Ruby_start_time: 0
 Ruby_cycles: 225141
 
-mbytes_resident: 71.8008
-mbytes_total: 166.332
-resident_ratio: 0.431695
+mbytes_resident: 65.2617
+mbytes_total: 120.52
+resident_ratio: 0.543642
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
index cfdf73ce9..f5d2abbce 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simerr
@@ -1 +1,5 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
index 6439642a6..733c0eefd 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  9 2012 13:38:07
-gem5 started Sep  9 2012 13:38:15
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:44:48
+gem5 started Sep 22 2013 05:44:59
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_CMP_token/gem5.opt -d build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_MOESI_CMP_token/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
index 637fd9943..c64681350 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000225                       # Nu
 sim_ticks                                      225141                       # Number of ticks simulated
 final_tick                                     225141                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                1294442                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 170328                       # Number of bytes of host memory used
-host_seconds                                     0.17                       # Real time elapsed on the host
+host_tick_rate                                1688456                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 123416                       # Number of bytes of host memory used
+host_seconds                                     0.13                       # Real time elapsed on the host
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           82                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          864                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          946                       # Number of cache demand accesses
@@ -90,6 +90,20 @@ system.ruby.network.routers3.msg_bytes.Response_Control::4            8
 system.ruby.network.routers3.msg_bytes.Writeback_Data::4       125136                      
 system.ruby.network.routers3.msg_bytes.Writeback_Control::4          576                      
 system.ruby.network.routers3.msg_bytes.Persistent_Control::3         5968                      
+system.ruby.network.msg_count.Request_Control         5349                      
+system.ruby.network.msg_count.Response_Data         2775                      
+system.ruby.network.msg_count.ResponseL2hit_Data          120                      
+system.ruby.network.msg_count.Response_Control            3                      
+system.ruby.network.msg_count.Writeback_Data         5214                      
+system.ruby.network.msg_count.Writeback_Control          216                      
+system.ruby.network.msg_count.Persistent_Control         2238                      
+system.ruby.network.msg_byte.Request_Control        42792                      
+system.ruby.network.msg_byte.Response_Data       199800                      
+system.ruby.network.msg_byte.ResponseL2hit_Data         8640                      
+system.ruby.network.msg_byte.Response_Control           24                      
+system.ruby.network.msg_byte.Writeback_Data       375408                      
+system.ruby.network.msg_byte.Writeback_Control         1728                      
+system.ruby.network.msg_byte.Persistent_Control        17904                      
 system.ruby.network.routers0.throttle0.link_utilization     2.077809                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          898                      
 system.ruby.network.routers0.throttle0.msg_count.ResponseL2hit_Data::4           40                      
@@ -216,20 +230,6 @@ system.ruby.l1_cntrl0.IS.Data_Shared                3      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data_All_Tokens           92      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Own_Lock_or_Unlock           19      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Request_Timeout           60      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control         5349                      
-system.ruby.network.msg_count.Response_Data         2775                      
-system.ruby.network.msg_count.ResponseL2hit_Data          120                      
-system.ruby.network.msg_count.Response_Control            3                      
-system.ruby.network.msg_count.Writeback_Data         5214                      
-system.ruby.network.msg_count.Writeback_Control          216                      
-system.ruby.network.msg_count.Persistent_Control         2238                      
-system.ruby.network.msg_byte.Request_Control        42792                      
-system.ruby.network.msg_byte.Response_Data       199800                      
-system.ruby.network.msg_byte.ResponseL2hit_Data         8640                      
-system.ruby.network.msg_byte.Response_Control           24                      
-system.ruby.network.msg_byte.Writeback_Data       375408                      
-system.ruby.network.msg_byte.Writeback_Control         1728                      
-system.ruby.network.msg_byte.Persistent_Control        17904                      
 system.ruby.l2_cntrl0.L1_GETS                      95      0.00%      0.00%
 system.ruby.l2_cntrl0.L1_GETX                     816      0.00%      0.00%
 system.ruby.l2_cntrl0.L2_Replacement              817      0.00%      0.00%
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
index 4a6d034a2..2be80bfa3 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Aug/29/2013 10:02:56
+Real time: Sep/22/2013 05:17:38
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.78
-Virtual_time_in_minutes: 0.013
-Virtual_time_in_hours:   0.000216667
-Virtual_time_in_days:    9.02778e-06
+Virtual_time_in_seconds: 0.38
+Virtual_time_in_minutes: 0.00633333
+Virtual_time_in_hours:   0.000105556
+Virtual_time_in_days:    4.39815e-06
 
 Ruby_current_time: 172201
 Ruby_start_time: 0
 Ruby_cycles: 172201
 
-mbytes_resident: 72.0898
-mbytes_total: 166.262
-resident_ratio: 0.433616
+mbytes_resident: 65.8359
+mbytes_total: 120.496
+resident_ratio: 0.546374
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
index cfdf73ce9..f5d2abbce 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simerr
@@ -1 +1,5 @@
+warn: rounding error > tolerance
+    0.072760 rounded to 0
+warn: rounding error > tolerance
+    0.072760 rounded to 0
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
index 4f22200bf..980451a66 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/al
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Sep  1 2012 13:53:26
-gem5 started Sep  1 2012 13:57:00
-gem5 executing on doudou.cs.wisc.edu
+gem5 compiled Sep 22 2013 05:17:28
+gem5 started Sep 22 2013 05:17:38
+gem5 executing on zizzer
 command line: build/ALPHA_MOESI_hammer/gem5.opt -d build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_MOESI_hammer/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
index e3dfac986..6281a101a 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000172                       # Nu
 sim_ticks                                      172201                       # Number of ticks simulated
 final_tick                                     172201                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                 356372                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 171280                       # Number of bytes of host memory used
-host_seconds                                     0.48                       # Real time elapsed on the host
+host_tick_rate                                1698559                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 123392                       # Number of bytes of host memory used
+host_seconds                                     0.10                       # Real time elapsed on the host
 system.ruby.l1_cntrl0.L1Dcache.demand_hits           70                       # Number of cache demand hits
 system.ruby.l1_cntrl0.L1Dcache.demand_misses          848                       # Number of cache demand misses
 system.ruby.l1_cntrl0.L1Dcache.demand_accesses          918                       # Number of cache demand accesses
@@ -81,6 +81,16 @@ system.ruby.network.routers2.msg_bytes.Writeback_Control::2         6744
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3         6752                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::5          600                      
 system.ruby.network.routers2.msg_bytes.Unblock_Control::5         6760                      
+system.ruby.network.msg_count.Request_Control         2554                      
+system.ruby.network.msg_count.Response_Data         2550                      
+system.ruby.network.msg_count.Writeback_Data         2303                      
+system.ruby.network.msg_count.Writeback_Control         5288                      
+system.ruby.network.msg_count.Unblock_Control         2535                      
+system.ruby.network.msg_byte.Request_Control        20432                      
+system.ruby.network.msg_byte.Response_Data       183600                      
+system.ruby.network.msg_byte.Writeback_Data       165816                      
+system.ruby.network.msg_byte.Writeback_Control        42304                      
+system.ruby.network.msg_byte.Unblock_Control        20280                      
 system.ruby.network.routers0.throttle0.link_utilization     2.466304                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          850                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          844                      
@@ -185,16 +195,6 @@ system.ruby.l1_cntrl0.MI_F.Writeback_Ack            5      0.00%      0.00%
 system.ruby.l1_cntrl0.MM_F.Block_Ack                1      0.00%      0.00%
 system.ruby.l1_cntrl0.IM_F.Exclusive_Data            4      0.00%      0.00%
 system.ruby.l1_cntrl0.MM_WF.All_acks_no_sharers            4      0.00%      0.00%
-system.ruby.network.msg_count.Request_Control         2554                      
-system.ruby.network.msg_count.Response_Data         2550                      
-system.ruby.network.msg_count.Writeback_Data         2303                      
-system.ruby.network.msg_count.Writeback_Control         5288                      
-system.ruby.network.msg_count.Unblock_Control         2535                      
-system.ruby.network.msg_byte.Request_Control        20432                      
-system.ruby.network.msg_byte.Response_Data       183600                      
-system.ruby.network.msg_byte.Writeback_Data       165816                      
-system.ruby.network.msg_byte.Writeback_Control        42304                      
-system.ruby.network.msg_byte.Unblock_Control        20280                      
 system.ruby.dir_cntrl0.GETX                       761      0.00%      0.00%
 system.ruby.dir_cntrl0.GETS                        87      0.00%      0.00%
 system.ruby.dir_cntrl0.PUT                        913      0.00%      0.00%
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
index cd80434d6..0797fe00b 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats
@@ -1,4 +1,4 @@
-Real time: Aug/29/2013 10:04:34
+Real time: Sep/28/2013 03:05:49
 
 Profiler Stats
 --------------
@@ -7,18 +7,18 @@ Elapsed_time_in_minutes: 0
 Elapsed_time_in_hours: 0
 Elapsed_time_in_days: 0
 
-Virtual_time_in_seconds: 0.48
-Virtual_time_in_minutes: 0.008
-Virtual_time_in_hours:   0.000133333
-Virtual_time_in_days:    5.55556e-06
+Virtual_time_in_seconds: 0.34
+Virtual_time_in_minutes: 0.00566667
+Virtual_time_in_hours:   9.44444e-05
+Virtual_time_in_days:    3.93519e-06
 
 Ruby_current_time: 221941
 Ruby_start_time: 0
 Ruby_cycles: 221941
 
-mbytes_resident: 70.1602
-mbytes_total: 164.824
-resident_ratio: 0.42569
+mbytes_resident: 63.7617
+mbytes_total: 118.02
+resident_ratio: 0.540264
 
 Busy Controller Counts:
 L1Cache-0:0  
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
index 8308e8186..f5d2abbce 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simerr
@@ -1,5 +1,5 @@
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
-Warning: rounding error > tolerance
+warn: rounding error > tolerance
     0.072760 rounded to 0
 hack: be nice to actually delete the event here
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
index 5f78b5f64..6606669ac 100755
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/simout
@@ -3,9 +3,9 @@ Redirecting stderr to build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rub
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Jan 23 2013 13:29:14
-gem5 started Jan 23 2013 14:07:36
-gem5 executing on ribera.cs.wisc.edu
+gem5 compiled Sep 24 2013 03:08:53
+gem5 started Sep 28 2013 03:05:49
+gem5 executing on zizzer
 command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA/tests/opt/quick/se/60.rubytest/alpha/linux/rubytest-ruby
 Global frequency set at 1000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
diff --git a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
index c503a22e4..34979640b 100644
--- a/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
+++ b/tests/quick/se/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt
@@ -4,9 +4,9 @@ sim_seconds                                  0.000222                       # Nu
 sim_ticks                                      221941                       # Number of ticks simulated
 final_tick                                     221941                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
 sim_freq                                   1000000000                       # Frequency of simulated ticks
-host_tick_rate                                2220183                       # Simulator tick rate (ticks/s)
-host_mem_usage                                 168784                       # Number of bytes of host memory used
-host_seconds                                     0.10                       # Real time elapsed on the host
+host_tick_rate                                2784815                       # Simulator tick rate (ticks/s)
+host_mem_usage                                 121880                       # Number of bytes of host memory used
+host_seconds                                     0.08                       # Real time elapsed on the host
 system.ruby.l1_cntrl0.cacheMemory.demand_hits           38                       # Number of cache demand hits
 system.ruby.l1_cntrl0.cacheMemory.demand_misses          917                       # Number of cache demand misses
 system.ruby.l1_cntrl0.cacheMemory.demand_accesses          955                       # Number of cache demand accesses
@@ -54,6 +54,14 @@ system.ruby.network.routers2.msg_bytes.Control::2         7328
 system.ruby.network.routers2.msg_bytes.Data::2        65808                      
 system.ruby.network.routers2.msg_bytes.Response_Data::4        65952                      
 system.ruby.network.routers2.msg_bytes.Writeback_Control::3         7304                      
+system.ruby.network.msg_count.Control            2748                      
+system.ruby.network.msg_count.Data               2742                      
+system.ruby.network.msg_count.Response_Data         2748                      
+system.ruby.network.msg_count.Writeback_Control         2739                      
+system.ruby.network.msg_byte.Control            21984                      
+system.ruby.network.msg_byte.Data              197424                      
+system.ruby.network.msg_byte.Response_Data       197856                      
+system.ruby.network.msg_byte.Writeback_Control        21912                      
 system.ruby.network.routers0.throttle0.link_utilization     2.062936                      
 system.ruby.network.routers0.throttle0.msg_count.Response_Data::4          916                      
 system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3          913                      
@@ -99,14 +107,6 @@ system.ruby.l1_cntrl0.M.Replacement               914      0.00%      0.00%
 system.ruby.l1_cntrl0.MI.Writeback_Ack            912      0.00%      0.00%
 system.ruby.l1_cntrl0.IS.Data                      98      0.00%      0.00%
 system.ruby.l1_cntrl0.IM.Data                     818      0.00%      0.00%
-system.ruby.network.msg_count.Control            2748                      
-system.ruby.network.msg_count.Data               2742                      
-system.ruby.network.msg_count.Response_Data         2748                      
-system.ruby.network.msg_count.Writeback_Control         2739                      
-system.ruby.network.msg_byte.Control            21984                      
-system.ruby.network.msg_byte.Data              197424                      
-system.ruby.network.msg_byte.Response_Data       197856                      
-system.ruby.network.msg_byte.Writeback_Control        21912                      
 system.ruby.dir_cntrl0.GETX                       916      0.00%      0.00%
 system.ruby.dir_cntrl0.PUTX                       914      0.00%      0.00%
 system.ruby.dir_cntrl0.Memory_Data                916      0.00%      0.00%
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini
new file mode 100644
index 000000000..61b6eb32e
--- /dev/null
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/config.ini
@@ -0,0 +1,116 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu membus monitor physmem
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.clk_domain]
+type=SrcClockDomain
+children=voltage_domain
+clock=1000
+voltage_domain=system.clk_domain.voltage_domain
+
+[system.clk_domain.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
+[system.cpu]
+type=TrafficGen
+clk_domain=system.clk_domain
+config_file=tests/quick/se/70.tgen/tgen-simple-dram.cfg
+elastic_req=false
+system=system
+port=system.monitor.slave
+
+[system.membus]
+type=NoncoherentBus
+clk_domain=system.clk_domain
+header_cycles=1
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.monitor.master system.system_port
+
+[system.monitor]
+type=CommMonitor
+bandwidth_bins=20
+burst_length_bins=20
+clk_domain=system.clk_domain
+disable_addr_dists=true
+disable_bandwidth_hists=false
+disable_burst_length_hists=false
+disable_itt_dists=false
+disable_latency_hists=false
+disable_outstanding_hists=false
+disable_transaction_hists=false
+itt_bins=20
+itt_max_bin=100000
+latency_bins=20
+outstanding_bins=20
+read_addr_mask=18446744073709551615
+sample_period=1000000000
+trace_file=
+transaction_bins=20
+write_addr_mask=18446744073709551615
+master=system.membus.slave[0]
+slave=system.cpu.port
+
+[system.physmem]
+type=SimpleDRAM
+activation_limit=4
+addr_mapping=RaBaChCo
+banks_per_rank=8
+burst_length=8
+channels=1
+clk_domain=system.clk_domain
+conf_table_reported=true
+device_bus_width=8
+device_rowbuffer_size=1024
+devices_per_rank=8
+in_addr_map=true
+mem_sched_policy=frfcfs
+null=false
+page_policy=open
+range=0:134217727
+ranks_per_channel=2
+read_buffer_size=32
+static_backend_latency=10000
+static_frontend_latency=10000
+tBURST=5000
+tCL=13750
+tRCD=13750
+tREFI=7800000
+tRFC=300000
+tRP=13750
+tWTR=7500
+tXAW=40000
+write_buffer_size=32
+write_thresh_perc=70
+port=system.membus.master[0]
+
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr
index cfdf73ce9..e69de29bb 100755
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simerr
@@ -1 +0,0 @@
-hack: be nice to actually delete the event here
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
index d1faa751a..2426a6cee 100755
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-dram/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simout
+Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug  6 2012 15:52:45
-gem5 started Aug  6 2012 15:56:03
-gem5 executing on 61f1f4j
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-dram
+gem5 compiled Sep 22 2013 05:53:51
+gem5 started Sep 22 2013 05:53:54
+gem5 executing on zizzer
+command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-dram
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
-Exiting @ tick 300940000 because Done
+Exiting @ tick 100000000000 because simulate() limit reached
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
new file mode 100644
index 000000000..27a6fb9af
--- /dev/null
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/config.ini
@@ -0,0 +1,95 @@
+[root]
+type=Root
+children=system
+full_system=false
+time_sync_enable=false
+time_sync_period=100000000000
+time_sync_spin_threshold=100000000
+
+[system]
+type=System
+children=clk_domain cpu membus monitor physmem
+boot_osflags=a
+cache_line_size=64
+clk_domain=system.clk_domain
+init_param=0
+kernel=
+load_addr_mask=1099511627775
+mem_mode=timing
+mem_ranges=
+memories=system.physmem
+num_work_ids=16
+readfile=
+symbolfile=
+work_begin_ckpt_count=0
+work_begin_cpu_id_exit=-1
+work_begin_exit_count=0
+work_cpus_ckpt_count=0
+work_end_ckpt_count=0
+work_end_exit_count=0
+work_item_id=-1
+system_port=system.membus.slave[1]
+
+[system.clk_domain]
+type=SrcClockDomain
+children=voltage_domain
+clock=1000
+voltage_domain=system.clk_domain.voltage_domain
+
+[system.clk_domain.voltage_domain]
+type=VoltageDomain
+voltage=1.000000
+
+[system.cpu]
+type=TrafficGen
+clk_domain=system.clk_domain
+config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg
+elastic_req=false
+system=system
+port=system.monitor.slave
+
+[system.membus]
+type=NoncoherentBus
+clk_domain=system.clk_domain
+header_cycles=1
+use_default_range=false
+width=16
+master=system.physmem.port
+slave=system.monitor.master system.system_port
+
+[system.monitor]
+type=CommMonitor
+bandwidth_bins=20
+burst_length_bins=20
+clk_domain=system.clk_domain
+disable_addr_dists=true
+disable_bandwidth_hists=false
+disable_burst_length_hists=false
+disable_itt_dists=false
+disable_latency_hists=false
+disable_outstanding_hists=false
+disable_transaction_hists=false
+itt_bins=20
+itt_max_bin=100000
+latency_bins=20
+outstanding_bins=20
+read_addr_mask=18446744073709551615
+sample_period=1000000000
+trace_file=monitor.ptrc.gz
+transaction_bins=20
+write_addr_mask=18446744073709551615
+master=system.membus.slave[0]
+slave=system.cpu.port
+
+[system.physmem]
+type=SimpleMemory
+bandwidth=73.000000
+clk_domain=system.clk_domain
+conf_table_reported=true
+in_addr_map=true
+latency=30000
+latency_var=0
+null=false
+range=0:134217727
+port=system.membus.master[0]
+
diff --git a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
index 727a89c99..efa3fa542 100755
--- a/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
+++ b/tests/quick/se/70.tgen/ref/null/none/tgen-simple-mem/simout
@@ -1,10 +1,12 @@
+Redirecting stdout to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simout
+Redirecting stderr to build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem/simerr
 gem5 Simulator System.  http://gem5.org
 gem5 is copyrighted software; use the --copyright option for details.
 
-gem5 compiled Aug 25 2012 13:56:00
-gem5 started Aug 25 2012 13:58:17
-gem5 executing on Andreas-MacBook-Pro.local
-command line: build/ARM/gem5.opt -d build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem -re tests/run.py build/ARM/tests/opt/quick/se/70.tgen/arm/linux/tgen-simple-mem
+gem5 compiled Sep 22 2013 05:53:51
+gem5 started Sep 22 2013 05:53:54
+gem5 executing on zizzer
+command line: build/NULL/gem5.opt -d build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem -re tests/run.py build/NULL/tests/opt/quick/se/70.tgen/null/none/tgen-simple-mem
 Global frequency set at 1000000000000 ticks per second
 info: Entering event queue @ 0.  Starting simulation...
 Exiting @ tick 100000000000 because simulate() limit reached